Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	16414004	1			T1	12		T2	69		T3	68
all_values[1]	16414004	1			T1	12		T2	69		T3	68
all_values[2]	16414004	1			T1	12		T2	69		T3	68

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

611108

1

T1

12

T2

19

T3

6

auto[1]

48630904

1

T1

24

T2

188

T3

198

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49013964

1

T1

36

T2

192

T3

192

auto[1]

228048

1

T2

15

T3

12

T4

15

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	209140	1			T1	12		T2	9		T12	1
all_values[0]	auto[0]	auto[1]	1343	1			T2	4		T13	2		T15	2
all_values[0]	auto[1]	auto[0]	16128848	1			T2	55		T3	64		T4	327
all_values[0]	auto[1]	auto[1]	74673	1			T2	1		T3	4		T4	5
all_values[1]	auto[0]	auto[0]	223117	1			T2	4		T3	5		T4	224
all_values[1]	auto[0]	auto[1]	992	1			T2	2		T3	1		T4	3
all_values[1]	auto[1]	auto[0]	16114871	1			T1	12		T2	60		T3	59
all_values[1]	auto[1]	auto[1]	75024	1			T2	3		T3	3		T4	2
all_values[2]	auto[0]	auto[0]	175477	1			T12	5		T5	19		T77	2
all_values[2]	auto[0]	auto[1]	1039	1			T77	1		T60	5		T80	5
all_values[2]	auto[1]	auto[0]	16162511	1			T1	12		T2	64		T3	64
all_values[2]	auto[1]	auto[1]	74977	1			T2	5		T3	4		T4	5