Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
59684 |
1 |
|
|
T1 |
2 |
|
T2 |
6 |
|
T3 |
2 |
auto[1] |
54926 |
1 |
|
|
T3 |
4 |
|
T4 |
4 |
|
T12 |
62 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
28441 |
1 |
|
|
T3 |
2 |
|
T4 |
2 |
|
T12 |
13 |
lower_val |
28523 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T12 |
16 |
zero_val |
881 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
57354 |
1 |
|
|
T1 |
2 |
|
T2 |
4 |
|
T3 |
4 |
lower_val |
57252 |
1 |
|
|
T2 |
2 |
|
T3 |
2 |
|
T4 |
2 |
zero_val |
4 |
1 |
|
|
T164 |
2 |
|
T165 |
2 |
|
- |
- |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
2 |
16 |
88.89 |
2 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
7364 |
1 |
|
|
T16 |
18 |
|
T21 |
1 |
|
T77 |
37 |
higher_val |
higher_val |
auto[1] |
6730 |
1 |
|
|
T3 |
1 |
|
T4 |
2 |
|
T12 |
3 |
higher_val |
lower_val |
auto[0] |
7419 |
1 |
|
|
T13 |
3 |
|
T16 |
22 |
|
T5 |
1 |
higher_val |
lower_val |
auto[1] |
6926 |
1 |
|
|
T3 |
1 |
|
T12 |
10 |
|
T21 |
21 |
higher_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T164 |
1 |
|
- |
- |
|
- |
- |
higher_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T165 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
7458 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T12 |
1 |
lower_val |
higher_val |
auto[1] |
6830 |
1 |
|
|
T3 |
1 |
|
T12 |
4 |
|
T21 |
22 |
lower_val |
lower_val |
auto[0] |
7372 |
1 |
|
|
T16 |
18 |
|
T77 |
45 |
|
T60 |
32 |
lower_val |
lower_val |
auto[1] |
6861 |
1 |
|
|
T12 |
11 |
|
T21 |
24 |
|
T79 |
29 |
lower_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T164 |
1 |
|
- |
- |
|
- |
- |
lower_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T165 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
339 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
higher_val |
auto[1] |
102 |
1 |
|
|
T85 |
1 |
|
T133 |
1 |
|
T32 |
3 |
zero_val |
lower_val |
auto[0] |
353 |
1 |
|
|
T4 |
1 |
|
T13 |
1 |
|
T5 |
1 |
zero_val |
lower_val |
auto[1] |
87 |
1 |
|
|
T85 |
1 |
|
T133 |
1 |
|
T40 |
1 |