Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6408064 |
1 |
|
|
T2 |
24 |
|
T3 |
24 |
|
T4 |
516 |
auto[1] |
9819620 |
1 |
|
|
T2 |
150 |
|
T3 |
150 |
|
T4 |
668 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
16193523 |
1 |
|
|
T2 |
174 |
|
T3 |
174 |
|
T4 |
1182 |
triple_byte_access |
11407 |
1 |
|
|
T4 |
1 |
|
T60 |
33 |
|
T83 |
23 |
halfword_access |
11404 |
1 |
|
|
T60 |
35 |
|
T83 |
26 |
|
T22 |
7 |
byte_access |
11350 |
1 |
|
|
T4 |
1 |
|
T60 |
39 |
|
T83 |
27 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
6373903 |
1 |
|
|
T2 |
24 |
|
T3 |
24 |
|
T4 |
514 |
auto[0] |
triple_byte_access |
11407 |
1 |
|
|
T4 |
1 |
|
T60 |
33 |
|
T83 |
23 |
auto[0] |
halfword_access |
11404 |
1 |
|
|
T60 |
35 |
|
T83 |
26 |
|
T22 |
7 |
auto[0] |
byte_access |
11350 |
1 |
|
|
T4 |
1 |
|
T60 |
39 |
|
T83 |
27 |
auto[1] |
word_access |
9819620 |
1 |
|
|
T2 |
150 |
|
T3 |
150 |
|
T4 |
668 |