Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.35 95.87 92.30 100.00 68.60 94.08 98.87 96.72


Total test records in report: 882
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html
T761 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.2780092372 Sep 18 08:55:57 PM UTC 24 Sep 18 08:56:21 PM UTC 24 971832514 ps
T762 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.3967603580 Sep 18 08:56:17 PM UTC 24 Sep 18 08:56:22 PM UTC 24 548831210 ps
T763 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.1580969123 Sep 18 08:56:09 PM UTC 24 Sep 18 08:56:22 PM UTC 24 489358790 ps
T764 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3524544298 Sep 18 08:56:20 PM UTC 24 Sep 18 08:56:23 PM UTC 24 41745412 ps
T765 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.548673850 Sep 18 08:56:20 PM UTC 24 Sep 18 08:56:23 PM UTC 24 45358305 ps
T766 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.3587833697 Sep 18 08:56:10 PM UTC 24 Sep 18 08:56:23 PM UTC 24 588428468 ps
T767 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.1583425365 Sep 18 08:56:18 PM UTC 24 Sep 18 08:56:23 PM UTC 24 53533962 ps
T768 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3373158514 Sep 18 08:56:19 PM UTC 24 Sep 18 08:56:23 PM UTC 24 259145127 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.3499345345 Sep 18 08:56:16 PM UTC 24 Sep 18 08:56:23 PM UTC 24 193569533 ps
T769 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.129994468 Sep 18 08:56:21 PM UTC 24 Sep 18 08:56:24 PM UTC 24 60728538 ps
T770 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.870484797 Sep 18 08:56:22 PM UTC 24 Sep 18 08:56:25 PM UTC 24 25418982 ps
T771 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.4173829750 Sep 18 08:56:22 PM UTC 24 Sep 18 08:56:25 PM UTC 24 155239520 ps
T772 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.481552105 Sep 18 08:56:24 PM UTC 24 Sep 18 08:56:26 PM UTC 24 19843920 ps
T773 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.3441287004 Sep 18 08:56:22 PM UTC 24 Sep 18 08:56:26 PM UTC 24 89949609 ps
T774 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.3492795912 Sep 18 08:56:24 PM UTC 24 Sep 18 08:56:26 PM UTC 24 35184870 ps
T775 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.3115064479 Sep 18 08:56:24 PM UTC 24 Sep 18 08:56:27 PM UTC 24 69029249 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.4025989726 Sep 18 08:56:21 PM UTC 24 Sep 18 08:56:27 PM UTC 24 1487437967 ps
T776 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.2693227513 Sep 18 08:56:24 PM UTC 24 Sep 18 08:56:27 PM UTC 24 286948754 ps
T777 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.1999812539 Sep 18 08:56:24 PM UTC 24 Sep 18 08:56:27 PM UTC 24 60168844 ps
T778 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.939291205 Sep 18 08:56:24 PM UTC 24 Sep 18 08:56:28 PM UTC 24 136386086 ps
T779 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.2412664451 Sep 18 08:56:25 PM UTC 24 Sep 18 08:56:28 PM UTC 24 164458055 ps
T780 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.2102497241 Sep 18 08:56:43 PM UTC 24 Sep 18 08:56:46 PM UTC 24 71101945 ps
T781 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2388439813 Sep 18 08:56:25 PM UTC 24 Sep 18 08:56:29 PM UTC 24 205950385 ps
T782 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.2672764214 Sep 18 08:56:26 PM UTC 24 Sep 18 08:56:29 PM UTC 24 359528984 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.3679787199 Sep 18 08:56:27 PM UTC 24 Sep 18 08:56:29 PM UTC 24 15338559 ps
T783 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.766638945 Sep 18 08:56:27 PM UTC 24 Sep 18 08:56:29 PM UTC 24 77046602 ps
T784 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.1271953121 Sep 18 08:56:27 PM UTC 24 Sep 18 08:56:30 PM UTC 24 33435991 ps
T785 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.3459462638 Sep 18 08:56:26 PM UTC 24 Sep 18 08:56:30 PM UTC 24 171116338 ps
T786 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.4559005 Sep 18 08:56:27 PM UTC 24 Sep 18 08:56:30 PM UTC 24 195472905 ps
T787 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.1563265204 Sep 18 08:56:26 PM UTC 24 Sep 18 08:56:30 PM UTC 24 183933444 ps
T788 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1062884144 Sep 18 08:56:27 PM UTC 24 Sep 18 08:56:30 PM UTC 24 102396082 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.1834456129 Sep 18 08:56:24 PM UTC 24 Sep 18 08:56:31 PM UTC 24 494242592 ps
T789 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1308382409 Sep 18 08:56:27 PM UTC 24 Sep 18 08:56:31 PM UTC 24 89433443 ps
T790 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.658182514 Sep 18 08:56:29 PM UTC 24 Sep 18 08:56:31 PM UTC 24 12131559 ps
T791 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.3207686402 Sep 18 08:56:29 PM UTC 24 Sep 18 08:56:32 PM UTC 24 58274186 ps
T792 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.4263420799 Sep 18 08:56:29 PM UTC 24 Sep 18 08:56:32 PM UTC 24 82676434 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.170518187 Sep 18 08:56:31 PM UTC 24 Sep 18 08:56:33 PM UTC 24 25072549 ps
T793 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.2669263281 Sep 18 08:56:31 PM UTC 24 Sep 18 08:56:33 PM UTC 24 61628098 ps
T794 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2357409797 Sep 18 08:56:31 PM UTC 24 Sep 18 08:56:34 PM UTC 24 64634775 ps
T795 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.3426720256 Sep 18 08:56:31 PM UTC 24 Sep 18 08:56:34 PM UTC 24 71309036 ps
T796 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.1014344463 Sep 18 08:56:32 PM UTC 24 Sep 18 08:56:35 PM UTC 24 46448705 ps
T797 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.515316518 Sep 18 08:56:31 PM UTC 24 Sep 18 08:56:35 PM UTC 24 458508731 ps
T798 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.1706967493 Sep 18 08:56:31 PM UTC 24 Sep 18 08:56:35 PM UTC 24 113139450 ps
T799 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.3217776754 Sep 18 08:56:31 PM UTC 24 Sep 18 08:56:36 PM UTC 24 352951429 ps
T800 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2509023521 Sep 18 08:56:43 PM UTC 24 Sep 18 08:56:46 PM UTC 24 193795382 ps
T801 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.4221679978 Sep 18 08:56:32 PM UTC 24 Sep 18 08:56:36 PM UTC 24 61239252 ps
T802 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.263137613 Sep 18 08:56:32 PM UTC 24 Sep 18 08:56:36 PM UTC 24 31992172 ps
T803 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.3328351146 Sep 18 08:56:29 PM UTC 24 Sep 18 08:56:36 PM UTC 24 483702300 ps
T804 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.2785081512 Sep 18 08:56:34 PM UTC 24 Sep 18 08:56:36 PM UTC 24 55712216 ps
T805 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.2248980044 Sep 18 08:56:34 PM UTC 24 Sep 18 08:56:36 PM UTC 24 45694951 ps
T806 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.3024681977 Sep 18 08:56:33 PM UTC 24 Sep 18 08:56:36 PM UTC 24 84614986 ps
T807 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.3711242233 Sep 18 08:56:29 PM UTC 24 Sep 18 08:56:37 PM UTC 24 1005886695 ps
T808 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.406325789 Sep 18 08:56:33 PM UTC 24 Sep 18 08:56:37 PM UTC 24 122776823 ps
T809 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.760843824 Sep 18 08:56:34 PM UTC 24 Sep 18 08:56:37 PM UTC 24 107697508 ps
T810 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.2678657575 Sep 18 08:56:33 PM UTC 24 Sep 18 08:56:38 PM UTC 24 112649791 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.2083571403 Sep 18 08:56:36 PM UTC 24 Sep 18 08:56:38 PM UTC 24 15591156 ps
T811 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.3415825664 Sep 18 08:56:36 PM UTC 24 Sep 18 08:56:39 PM UTC 24 74859708 ps
T812 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.715459068 Sep 18 08:56:38 PM UTC 24 Sep 18 08:56:40 PM UTC 24 41953627 ps
T813 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.4237012536 Sep 18 08:56:36 PM UTC 24 Sep 18 08:56:40 PM UTC 24 72471283 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.409659668 Sep 18 08:56:38 PM UTC 24 Sep 18 08:56:40 PM UTC 24 42288231 ps
T814 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.337692445 Sep 18 08:56:38 PM UTC 24 Sep 18 08:56:41 PM UTC 24 126608470 ps
T815 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.922929746 Sep 18 08:56:36 PM UTC 24 Sep 18 08:56:41 PM UTC 24 100399281 ps
T816 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.2838712541 Sep 18 08:56:38 PM UTC 24 Sep 18 08:56:41 PM UTC 24 27341019 ps
T817 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.3179008697 Sep 18 08:56:36 PM UTC 24 Sep 18 08:56:41 PM UTC 24 141259554 ps
T818 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.3566075401 Sep 18 08:56:38 PM UTC 24 Sep 18 08:56:41 PM UTC 24 90582692 ps
T819 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.1957503351 Sep 18 08:56:38 PM UTC 24 Sep 18 08:56:41 PM UTC 24 30786782 ps
T820 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1746414721 Sep 18 08:56:38 PM UTC 24 Sep 18 08:56:41 PM UTC 24 49312575 ps
T821 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.2215447211 Sep 18 08:56:38 PM UTC 24 Sep 18 08:56:42 PM UTC 24 95188953 ps
T822 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.3287086332 Sep 18 08:56:38 PM UTC 24 Sep 18 08:56:42 PM UTC 24 185769337 ps
T823 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.2072765179 Sep 18 08:56:40 PM UTC 24 Sep 18 08:56:43 PM UTC 24 31471619 ps
T824 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.2263670977 Sep 18 08:56:40 PM UTC 24 Sep 18 08:56:43 PM UTC 24 39198093 ps
T825 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.3083727953 Sep 18 08:56:38 PM UTC 24 Sep 18 08:56:43 PM UTC 24 219289114 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.3223025536 Sep 18 08:56:36 PM UTC 24 Sep 18 08:56:44 PM UTC 24 475822000 ps
T826 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.2969261756 Sep 18 08:56:42 PM UTC 24 Sep 18 08:56:44 PM UTC 24 13175982 ps
T827 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.3587864599 Sep 18 08:56:42 PM UTC 24 Sep 18 08:56:44 PM UTC 24 54866592 ps
T828 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.3111844681 Sep 18 08:56:40 PM UTC 24 Sep 18 08:56:44 PM UTC 24 340424508 ps
T829 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2797932903 Sep 18 08:56:42 PM UTC 24 Sep 18 08:56:44 PM UTC 24 139625772 ps
T830 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.563612953 Sep 18 08:56:42 PM UTC 24 Sep 18 08:56:44 PM UTC 24 153062629 ps
T831 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2171296014 Sep 18 08:56:42 PM UTC 24 Sep 18 08:56:45 PM UTC 24 421161035 ps
T832 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.1566406003 Sep 18 08:56:43 PM UTC 24 Sep 18 08:56:46 PM UTC 24 50890388 ps
T833 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.1592792971 Sep 18 08:56:42 PM UTC 24 Sep 18 08:56:46 PM UTC 24 227090886 ps
T834 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.3164900091 Sep 18 08:56:43 PM UTC 24 Sep 18 08:56:46 PM UTC 24 15491881 ps
T835 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.2196632090 Sep 18 08:56:43 PM UTC 24 Sep 18 08:56:47 PM UTC 24 72168448 ps
T836 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.3691469986 Sep 18 08:56:45 PM UTC 24 Sep 18 08:56:48 PM UTC 24 26246436 ps
T837 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.1288850756 Sep 18 08:56:46 PM UTC 24 Sep 18 08:56:48 PM UTC 24 38979287 ps
T838 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3222004817 Sep 18 08:56:46 PM UTC 24 Sep 18 08:56:48 PM UTC 24 114443109 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.1650541850 Sep 18 08:56:42 PM UTC 24 Sep 18 08:56:48 PM UTC 24 237950067 ps
T839 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.574195577 Sep 18 08:56:46 PM UTC 24 Sep 18 08:56:48 PM UTC 24 32880248 ps
T840 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3079724951 Sep 18 08:56:45 PM UTC 24 Sep 18 08:56:49 PM UTC 24 100488864 ps
T841 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.2629414404 Sep 18 08:56:45 PM UTC 24 Sep 18 08:56:49 PM UTC 24 175096236 ps
T842 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.1095917983 Sep 18 08:56:46 PM UTC 24 Sep 18 08:56:49 PM UTC 24 128812655 ps
T843 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.577935671 Sep 18 08:56:46 PM UTC 24 Sep 18 08:56:49 PM UTC 24 94661035 ps
T844 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.644083566 Sep 18 08:56:46 PM UTC 24 Sep 18 08:56:49 PM UTC 24 173189204 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.3860479494 Sep 18 08:56:43 PM UTC 24 Sep 18 08:56:49 PM UTC 24 585617260 ps
T845 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.2300821371 Sep 18 08:56:48 PM UTC 24 Sep 18 08:56:50 PM UTC 24 24002206 ps
T846 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.1763198561 Sep 18 08:56:48 PM UTC 24 Sep 18 08:56:50 PM UTC 24 37837357 ps
T847 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.401494635 Sep 18 08:56:47 PM UTC 24 Sep 18 08:56:51 PM UTC 24 169978140 ps
T848 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.2143305905 Sep 18 08:56:47 PM UTC 24 Sep 18 08:56:51 PM UTC 24 33133930 ps
T849 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.4247086265 Sep 18 08:56:49 PM UTC 24 Sep 18 08:56:51 PM UTC 24 72659741 ps
T850 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.3365516110 Sep 18 08:56:49 PM UTC 24 Sep 18 08:56:51 PM UTC 24 79044705 ps
T851 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.4043161853 Sep 18 08:56:49 PM UTC 24 Sep 18 08:56:51 PM UTC 24 19756782 ps
T852 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.3675423430 Sep 18 08:56:49 PM UTC 24 Sep 18 08:56:51 PM UTC 24 18203081 ps
T853 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.338290904 Sep 18 08:56:46 PM UTC 24 Sep 18 08:56:52 PM UTC 24 991866358 ps
T854 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.16992852 Sep 18 08:56:49 PM UTC 24 Sep 18 08:56:52 PM UTC 24 202057298 ps
T855 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1020492824 Sep 18 08:56:49 PM UTC 24 Sep 18 08:56:52 PM UTC 24 90698697 ps
T856 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.3653079649 Sep 18 08:56:51 PM UTC 24 Sep 18 08:56:53 PM UTC 24 71968814 ps
T857 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.3624635875 Sep 18 08:56:51 PM UTC 24 Sep 18 08:56:53 PM UTC 24 17542287 ps
T858 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.2355883766 Sep 18 08:56:51 PM UTC 24 Sep 18 08:56:53 PM UTC 24 58601111 ps
T859 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.4157123767 Sep 18 08:56:51 PM UTC 24 Sep 18 08:56:53 PM UTC 24 48289846 ps
T860 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.315601130 Sep 18 08:56:51 PM UTC 24 Sep 18 08:56:53 PM UTC 24 19505448 ps
T861 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.2734473715 Sep 18 08:56:47 PM UTC 24 Sep 18 08:56:53 PM UTC 24 371224921 ps
T862 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.982340388 Sep 18 08:56:51 PM UTC 24 Sep 18 08:56:53 PM UTC 24 24881828 ps
T863 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.482985622 Sep 18 08:56:51 PM UTC 24 Sep 18 08:56:53 PM UTC 24 17173574 ps
T864 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.4165911240 Sep 18 08:56:51 PM UTC 24 Sep 18 08:56:54 PM UTC 24 12131148 ps
T865 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.3050215822 Sep 18 08:56:51 PM UTC 24 Sep 18 08:56:54 PM UTC 24 42427167 ps
T866 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.1799870780 Sep 18 08:56:54 PM UTC 24 Sep 18 08:56:56 PM UTC 24 11718384 ps
T867 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.2176486814 Sep 18 08:56:54 PM UTC 24 Sep 18 08:56:56 PM UTC 24 30329152 ps
T868 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.3093334559 Sep 18 08:56:54 PM UTC 24 Sep 18 08:56:56 PM UTC 24 107203938 ps
T869 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.3031146502 Sep 18 08:56:54 PM UTC 24 Sep 18 08:56:57 PM UTC 24 22115170 ps
T870 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.636548625 Sep 18 08:56:54 PM UTC 24 Sep 18 08:56:57 PM UTC 24 54385073 ps
T871 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.2562364301 Sep 18 08:56:54 PM UTC 24 Sep 18 08:56:57 PM UTC 24 49056512 ps
T872 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.1545288718 Sep 18 08:56:54 PM UTC 24 Sep 18 08:56:57 PM UTC 24 151029076 ps
T873 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.2694892379 Sep 18 08:56:54 PM UTC 24 Sep 18 08:56:57 PM UTC 24 17167137 ps
T874 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.1213083849 Sep 18 08:56:54 PM UTC 24 Sep 18 08:56:57 PM UTC 24 33523571 ps
T875 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.905616868 Sep 18 08:56:54 PM UTC 24 Sep 18 08:56:57 PM UTC 24 41289724 ps
T876 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.94817024 Sep 18 08:56:54 PM UTC 24 Sep 18 08:56:57 PM UTC 24 24939200 ps
T877 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.259445394 Sep 18 08:56:54 PM UTC 24 Sep 18 08:56:57 PM UTC 24 21237584 ps
T878 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.3003476904 Sep 18 08:56:55 PM UTC 24 Sep 18 08:56:57 PM UTC 24 32853569 ps
T879 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.460538288 Sep 18 08:56:54 PM UTC 24 Sep 18 08:56:57 PM UTC 24 28897956 ps
T880 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.349639573 Sep 18 08:56:55 PM UTC 24 Sep 18 08:56:58 PM UTC 24 72163359 ps
T881 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.447913803 Sep 18 08:56:54 PM UTC 24 Sep 18 08:56:58 PM UTC 24 25245394 ps
T882 /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.3401906732 Sep 18 08:56:55 PM UTC 24 Sep 18 08:56:58 PM UTC 24 19193520 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_ready_error.1126257236
Short name T12
Test name
Test status
Simulation time 731195838 ps
CPU time 9.09 seconds
Started Sep 18 07:59:58 PM UTC 24
Finished Sep 18 08:00:09 PM UTC 24
Peak memory 231612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126257236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.1126257236 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/0.kmac_sideload.2697399822
Short name T4
Test name
Test status
Simulation time 77944717 ps
CPU time 5.68 seconds
Started Sep 18 07:59:57 PM UTC 24
Finished Sep 18 08:00:03 PM UTC 24
Peak memory 231480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697399822 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.2697399822 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_intg_err.2103907715
Short name T119
Test name
Test status
Simulation time 251862096 ps
CPU time 4.18 seconds
Started Sep 18 08:55:46 PM UTC 24
Finished Sep 18 08:55:51 PM UTC 24
Peak memory 229696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103907715 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.2103907715 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/0.kmac_lc_escalation.175572634
Short name T1
Test name
Test status
Simulation time 56007548 ps
CPU time 1.37 seconds
Started Sep 18 07:59:58 PM UTC 24
Finished Sep 18 08:00:01 PM UTC 24
Peak memory 228828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175572634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.175572634 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/5.kmac_stress_all_with_rand_reset.1140332401
Short name T40
Test name
Test status
Simulation time 7886140433 ps
CPU time 47.99 seconds
Started Sep 18 08:06:18 PM UTC 24
Finished Sep 18 08:07:07 PM UTC 24
Peak memory 244940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres
s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1140332401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all_
with_rand_reset.1140332401 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/3.kmac_sec_cm.3916419632
Short name T56
Test name
Test status
Simulation time 18323746629 ps
CPU time 48.12 seconds
Started Sep 18 08:03:08 PM UTC 24
Finished Sep 18 08:03:57 PM UTC 24
Peak memory 278772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916419632 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.3916419632 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/2.kmac_key_error.2090205869
Short name T20
Test name
Test status
Simulation time 2660080899 ps
CPU time 7.62 seconds
Started Sep 18 08:01:26 PM UTC 24
Finished Sep 18 08:01:35 PM UTC 24
Peak memory 227656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090205869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.2090205869 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/0.kmac_app_with_partial_data.627504435
Short name T22
Test name
Test status
Simulation time 2888337237 ps
CPU time 76.99 seconds
Started Sep 18 07:59:58 PM UTC 24
Finished Sep 18 08:01:17 PM UTC 24
Peak memory 252656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627504435 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.627504435 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/1.kmac_error.3822853859
Short name T27
Test name
Test status
Simulation time 113036648961 ps
CPU time 400.54 seconds
Started Sep 18 08:00:07 PM UTC 24
Finished Sep 18 08:06:54 PM UTC 24
Peak memory 600820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822853859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.3822853859 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/22.kmac_lc_escalation.851050947
Short name T99
Test name
Test status
Simulation time 169551311 ps
CPU time 1.43 seconds
Started Sep 18 08:24:46 PM UTC 24
Finished Sep 18 08:24:48 PM UTC 24
Peak memory 226376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851050947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.851050947 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/22.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors.1170196288
Short name T101
Test name
Test status
Simulation time 84651015 ps
CPU time 1.93 seconds
Started Sep 18 08:55:24 PM UTC 24
Finished Sep 18 08:55:28 PM UTC 24
Peak memory 229284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170196288 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors.1170196288 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/34.kmac_lc_escalation.880082674
Short name T100
Test name
Test status
Simulation time 780173488 ps
CPU time 13.81 seconds
Started Sep 18 08:38:59 PM UTC 24
Finished Sep 18 08:39:14 PM UTC 24
Peak memory 244484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880082674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.880082674 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/34.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_intr_test.1098251335
Short name T169
Test name
Test status
Simulation time 20229988 ps
CPU time 1.25 seconds
Started Sep 18 08:56:16 PM UTC 24
Finished Sep 18 08:56:18 PM UTC 24
Peak memory 218752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098251335 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.1098251335 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/6.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/0.kmac_smoke.1019715671
Short name T60
Test name
Test status
Simulation time 4837976937 ps
CPU time 62.87 seconds
Started Sep 18 07:59:56 PM UTC 24
Finished Sep 18 08:01:01 PM UTC 24
Peak memory 234544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019715671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.1019715671 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/28.kmac_lc_escalation.4242933522
Short name T67
Test name
Test status
Simulation time 160662265 ps
CPU time 2.04 seconds
Started Sep 18 08:31:48 PM UTC 24
Finished Sep 18 08:31:51 PM UTC 24
Peak memory 227656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242933522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.4242933522 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/28.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/20.kmac_lc_escalation.988047206
Short name T98
Test name
Test status
Simulation time 545226796 ps
CPU time 20 seconds
Started Sep 18 08:23:03 PM UTC 24
Finished Sep 18 08:23:24 PM UTC 24
Peak memory 244740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988047206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.988047206 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/20.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/2.kmac_burst_write.934646360
Short name T50
Test name
Test status
Simulation time 7175284201 ps
CPU time 365.44 seconds
Started Sep 18 08:00:28 PM UTC 24
Finished Sep 18 08:06:39 PM UTC 24
Peak memory 240420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934646360 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.934646360 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/1.kmac_mubi.1835467975
Short name T37
Test name
Test status
Simulation time 1708782164 ps
CPU time 86.25 seconds
Started Sep 18 08:00:07 PM UTC 24
Finished Sep 18 08:01:36 PM UTC 24
Peak memory 265204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835467975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.1835467975 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors.1717242367
Short name T102
Test name
Test status
Simulation time 103064336 ps
CPU time 1.4 seconds
Started Sep 18 08:55:42 PM UTC 24
Finished Sep 18 08:55:45 PM UTC 24
Peak memory 228620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717242367 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors.1717242367 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_128.989498512
Short name T164
Test name
Test status
Simulation time 2232000068 ps
CPU time 174.19 seconds
Started Sep 18 07:59:57 PM UTC 24
Finished Sep 18 08:02:54 PM UTC 24
Peak memory 285404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989498512 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.98949851
2 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_partial_access.149342764
Short name T136
Test name
Test status
Simulation time 18360689 ps
CPU time 1.76 seconds
Started Sep 18 08:55:54 PM UTC 24
Finished Sep 18 08:55:56 PM UTC 24
Peak memory 228680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149342764 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial_access.149342764 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/0.kmac_alert_test.1870092223
Short name T19
Test name
Test status
Simulation time 46772795 ps
CPU time 1.05 seconds
Started Sep 18 08:00:00 PM UTC 24
Finished Sep 18 08:00:08 PM UTC 24
Peak memory 216436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870092223 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.1870092223 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.1834456129
Short name T182
Test name
Test status
Simulation time 494242592 ps
CPU time 5.74 seconds
Started Sep 18 08:56:24 PM UTC 24
Finished Sep 18 08:56:31 PM UTC 24
Peak memory 229456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834456129 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.1834456129 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/9.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.3566075401
Short name T818
Test name
Test status
Simulation time 90582692 ps
CPU time 1.71 seconds
Started Sep 18 08:56:38 PM UTC 24
Finished Sep 18 08:56:41 PM UTC 24
Peak memory 228236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566075401 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors_with_csr_rw
.3566075401 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.3675423430
Short name T852
Test name
Test status
Simulation time 18203081 ps
CPU time 1.13 seconds
Started Sep 18 08:56:49 PM UTC 24
Finished Sep 18 08:56:51 PM UTC 24
Peak memory 218688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675423430 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.3675423430 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/23.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/9.kmac_error.3773544653
Short name T160
Test name
Test status
Simulation time 7496459472 ps
CPU time 309.03 seconds
Started Sep 18 08:11:12 PM UTC 24
Finished Sep 18 08:16:25 PM UTC 24
Peak memory 371744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773544653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.3773544653 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/9.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/10.kmac_stress_all.3642153637
Short name T437
Test name
Test status
Simulation time 163902528720 ps
CPU time 1168.43 seconds
Started Sep 18 08:12:20 PM UTC 24
Finished Sep 18 08:32:03 PM UTC 24
Peak memory 689252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642153637 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.3642153637 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/10.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.3223025536
Short name T185
Test name
Test status
Simulation time 475822000 ps
CPU time 6.69 seconds
Started Sep 18 08:56:36 PM UTC 24
Finished Sep 18 08:56:44 PM UTC 24
Peak memory 229432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223025536 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.3223025536 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/14.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/45.kmac_sideload.4009491926
Short name T165
Test name
Test status
Simulation time 3965289621 ps
CPU time 333.6 seconds
Started Sep 18 08:50:28 PM UTC 24
Finished Sep 18 08:56:07 PM UTC 24
Peak memory 357216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009491926 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.4009491926 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/45.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_256.2376367042
Short name T77
Test name
Test status
Simulation time 13870324945 ps
CPU time 50.73 seconds
Started Sep 18 07:59:57 PM UTC 24
Finished Sep 18 08:00:49 PM UTC 24
Peak memory 250928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376367042 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.2376367042
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/4.kmac_app_with_partial_data.276649926
Short name T217
Test name
Test status
Simulation time 60918351669 ps
CPU time 279.02 seconds
Started Sep 18 08:04:12 PM UTC 24
Finished Sep 18 08:08:55 PM UTC 24
Peak memory 432888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276649926 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.276649926 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_hw_reset.1809086978
Short name T122
Test name
Test status
Simulation time 106428011 ps
CPU time 1.7 seconds
Started Sep 18 08:55:32 PM UTC 24
Finished Sep 18 08:55:35 PM UTC 24
Peak memory 218700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809086978 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.1809086978 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.2950350917
Short name T103
Test name
Test status
Simulation time 121447499 ps
CPU time 1.95 seconds
Started Sep 18 08:55:42 PM UTC 24
Finished Sep 18 08:55:45 PM UTC 24
Peak memory 228552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950350917 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors_with_csr_rw.
2950350917 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/0.kmac_mubi.3222382156
Short name T33
Test name
Test status
Simulation time 17883257777 ps
CPU time 260.84 seconds
Started Sep 18 07:59:58 PM UTC 24
Finished Sep 18 08:04:23 PM UTC 24
Peak memory 330880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222382156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.3222382156 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_aliasing.3521053483
Short name T724
Test name
Test status
Simulation time 3795871132 ps
CPU time 15.21 seconds
Started Sep 18 08:55:36 PM UTC 24
Finished Sep 18 08:55:53 PM UTC 24
Peak memory 229632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521053483 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.3521053483 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_bit_bash.3986984066
Short name T729
Test name
Test status
Simulation time 5081298211 ps
CPU time 20.82 seconds
Started Sep 18 08:55:36 PM UTC 24
Finished Sep 18 08:55:58 PM UTC 24
Peak memory 219220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986984066 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.3986984066 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.28269926
Short name T125
Test name
Test status
Simulation time 84184896 ps
CPU time 3.37 seconds
Started Sep 18 08:55:39 PM UTC 24
Finished Sep 18 08:55:44 PM UTC 24
Peak memory 231828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=28269926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_me
m_rw_with_rand_reset.28269926 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_rw.1633864689
Short name T144
Test name
Test status
Simulation time 101099713 ps
CPU time 1.77 seconds
Started Sep 18 08:55:34 PM UTC 24
Finished Sep 18 08:55:37 PM UTC 24
Peak memory 218704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633864689 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.1633864689 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_intr_test.3847133879
Short name T121
Test name
Test status
Simulation time 26917942 ps
CPU time 1.07 seconds
Started Sep 18 08:55:30 PM UTC 24
Finished Sep 18 08:55:32 PM UTC 24
Peak memory 218744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847133879 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.3847133879 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_partial_access.3299629937
Short name T134
Test name
Test status
Simulation time 51802949 ps
CPU time 1.82 seconds
Started Sep 18 08:55:28 PM UTC 24
Finished Sep 18 08:55:31 PM UTC 24
Peak memory 228736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299629937 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partial_access.3299629937 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_walk.1938987983
Short name T721
Test name
Test status
Simulation time 12449241 ps
CPU time 1.14 seconds
Started Sep 18 08:55:26 PM UTC 24
Finished Sep 18 08:55:28 PM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938987983 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.1938987983 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_same_csr_outstanding.1187210171
Short name T145
Test name
Test status
Simulation time 235609811 ps
CPU time 2.54 seconds
Started Sep 18 08:55:38 PM UTC 24
Finished Sep 18 08:55:42 PM UTC 24
Peak memory 229524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187210171 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_outstanding.1187210171 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_errors.1500842834
Short name T124
Test name
Test status
Simulation time 173309267 ps
CPU time 3.89 seconds
Started Sep 18 08:55:30 PM UTC 24
Finished Sep 18 08:55:35 PM UTC 24
Peak memory 229576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500842834 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.1500842834 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_intg_err.1981423744
Short name T118
Test name
Test status
Simulation time 1418100280 ps
CPU time 5.57 seconds
Started Sep 18 08:55:30 PM UTC 24
Finished Sep 18 08:55:37 PM UTC 24
Peak memory 229520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981423744 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.1981423744 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_aliasing.1458031952
Short name T727
Test name
Test status
Simulation time 1326842564 ps
CPU time 5.52 seconds
Started Sep 18 08:55:50 PM UTC 24
Finished Sep 18 08:55:57 PM UTC 24
Peak memory 219172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458031952 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.1458031952 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_bit_bash.1271497704
Short name T733
Test name
Test status
Simulation time 491152856 ps
CPU time 13.72 seconds
Started Sep 18 08:55:48 PM UTC 24
Finished Sep 18 08:56:03 PM UTC 24
Peak memory 219156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271497704 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.1271497704 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_hw_reset.1923407070
Short name T723
Test name
Test status
Simulation time 200212340 ps
CPU time 1.36 seconds
Started Sep 18 08:55:47 PM UTC 24
Finished Sep 18 08:55:49 PM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923407070 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.1923407070 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.285631068
Short name T127
Test name
Test status
Simulation time 34621569 ps
CPU time 2.51 seconds
Started Sep 18 08:55:51 PM UTC 24
Finished Sep 18 08:55:55 PM UTC 24
Peak memory 229776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=285631068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_m
em_rw_with_rand_reset.285631068 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_rw.1964644579
Short name T146
Test name
Test status
Simulation time 321251525 ps
CPU time 1.81 seconds
Started Sep 18 08:55:48 PM UTC 24
Finished Sep 18 08:55:51 PM UTC 24
Peak memory 218704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964644579 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.1964644579 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_intr_test.2418797349
Short name T123
Test name
Test status
Simulation time 38431385 ps
CPU time 1.13 seconds
Started Sep 18 08:55:47 PM UTC 24
Finished Sep 18 08:55:49 PM UTC 24
Peak memory 218812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418797349 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.2418797349 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_partial_access.1544606703
Short name T135
Test name
Test status
Simulation time 25985777 ps
CPU time 1.76 seconds
Started Sep 18 08:55:45 PM UTC 24
Finished Sep 18 08:55:47 PM UTC 24
Peak memory 228740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544606703 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial_access.1544606703 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_walk.949313914
Short name T722
Test name
Test status
Simulation time 39529560 ps
CPU time 1.09 seconds
Started Sep 18 08:55:44 PM UTC 24
Finished Sep 18 08:55:46 PM UTC 24
Peak memory 218860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949313914 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.949313914 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_same_csr_outstanding.366840921
Short name T725
Test name
Test status
Simulation time 39529846 ps
CPU time 3.01 seconds
Started Sep 18 08:55:50 PM UTC 24
Finished Sep 18 08:55:54 PM UTC 24
Peak memory 229776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366840921 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_outstanding.366840921 +enable_m
asking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_errors.4028091643
Short name T126
Test name
Test status
Simulation time 282513361 ps
CPU time 5.8 seconds
Started Sep 18 08:55:46 PM UTC 24
Finished Sep 18 08:55:53 PM UTC 24
Peak memory 229568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028091643 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.4028091643 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1062884144
Short name T788
Test name
Test status
Simulation time 102396082 ps
CPU time 2.06 seconds
Started Sep 18 08:56:27 PM UTC 24
Finished Sep 18 08:56:30 PM UTC 24
Peak memory 229464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1062884144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr
_mem_rw_with_rand_reset.1062884144 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.766638945
Short name T783
Test name
Test status
Simulation time 77046602 ps
CPU time 1.23 seconds
Started Sep 18 08:56:27 PM UTC 24
Finished Sep 18 08:56:29 PM UTC 24
Peak memory 218552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766638945 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.766638945 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/10.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.3679787199
Short name T174
Test name
Test status
Simulation time 15338559 ps
CPU time 1.26 seconds
Started Sep 18 08:56:27 PM UTC 24
Finished Sep 18 08:56:29 PM UTC 24
Peak memory 218508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679787199 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.3679787199 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/10.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1308382409
Short name T789
Test name
Test status
Simulation time 89433443 ps
CPU time 2.71 seconds
Started Sep 18 08:56:27 PM UTC 24
Finished Sep 18 08:56:31 PM UTC 24
Peak memory 229456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308382409 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_csr_outstanding.1308382409 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/10.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.2412664451
Short name T779
Test name
Test status
Simulation time 164458055 ps
CPU time 1.71 seconds
Started Sep 18 08:56:25 PM UTC 24
Finished Sep 18 08:56:28 PM UTC 24
Peak memory 228580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412664451 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors.2412664451 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/10.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.1563265204
Short name T787
Test name
Test status
Simulation time 183933444 ps
CPU time 3.65 seconds
Started Sep 18 08:56:26 PM UTC 24
Finished Sep 18 08:56:30 PM UTC 24
Peak memory 229864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563265204 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors_with_csr_rw
.1563265204 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.2672764214
Short name T782
Test name
Test status
Simulation time 359528984 ps
CPU time 2.63 seconds
Started Sep 18 08:56:26 PM UTC 24
Finished Sep 18 08:56:29 PM UTC 24
Peak memory 229652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672764214 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.2672764214 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/10.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.3459462638
Short name T785
Test name
Test status
Simulation time 171116338 ps
CPU time 3.31 seconds
Started Sep 18 08:56:26 PM UTC 24
Finished Sep 18 08:56:30 PM UTC 24
Peak memory 229528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459462638 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.3459462638 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/10.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.3426720256
Short name T795
Test name
Test status
Simulation time 71309036 ps
CPU time 2.06 seconds
Started Sep 18 08:56:31 PM UTC 24
Finished Sep 18 08:56:34 PM UTC 24
Peak memory 229516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3426720256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr
_mem_rw_with_rand_reset.3426720256 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.3207686402
Short name T791
Test name
Test status
Simulation time 58274186 ps
CPU time 1.49 seconds
Started Sep 18 08:56:29 PM UTC 24
Finished Sep 18 08:56:32 PM UTC 24
Peak memory 218704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207686402 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.3207686402 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/11.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.658182514
Short name T790
Test name
Test status
Simulation time 12131559 ps
CPU time 1.13 seconds
Started Sep 18 08:56:29 PM UTC 24
Finished Sep 18 08:56:31 PM UTC 24
Peak memory 218740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658182514 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.658182514 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/11.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.4263420799
Short name T792
Test name
Test status
Simulation time 82676434 ps
CPU time 2.22 seconds
Started Sep 18 08:56:29 PM UTC 24
Finished Sep 18 08:56:32 PM UTC 24
Peak memory 229456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263420799 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr_outstanding.4263420799 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/11.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.1271953121
Short name T784
Test name
Test status
Simulation time 33435991 ps
CPU time 1.44 seconds
Started Sep 18 08:56:27 PM UTC 24
Finished Sep 18 08:56:30 PM UTC 24
Peak memory 228620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271953121 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors.1271953121 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/11.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.4559005
Short name T786
Test name
Test status
Simulation time 195472905 ps
CPU time 1.75 seconds
Started Sep 18 08:56:27 PM UTC 24
Finished Sep 18 08:56:30 PM UTC 24
Peak memory 228620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4559005 -assert
nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors_with_csr_rw.45
59005 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.3711242233
Short name T807
Test name
Test status
Simulation time 1005886695 ps
CPU time 6.48 seconds
Started Sep 18 08:56:29 PM UTC 24
Finished Sep 18 08:56:37 PM UTC 24
Peak memory 229596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711242233 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.3711242233 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/11.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.3328351146
Short name T803
Test name
Test status
Simulation time 483702300 ps
CPU time 6.12 seconds
Started Sep 18 08:56:29 PM UTC 24
Finished Sep 18 08:56:36 PM UTC 24
Peak memory 229772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328351146 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.3328351146 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/11.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.263137613
Short name T802
Test name
Test status
Simulation time 31992172 ps
CPU time 2.56 seconds
Started Sep 18 08:56:32 PM UTC 24
Finished Sep 18 08:56:36 PM UTC 24
Peak memory 229768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=263137613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_
mem_rw_with_rand_reset.263137613 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.2669263281
Short name T793
Test name
Test status
Simulation time 61628098 ps
CPU time 1.51 seconds
Started Sep 18 08:56:31 PM UTC 24
Finished Sep 18 08:56:33 PM UTC 24
Peak memory 218692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669263281 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.2669263281 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/12.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.170518187
Short name T175
Test name
Test status
Simulation time 25072549 ps
CPU time 1.06 seconds
Started Sep 18 08:56:31 PM UTC 24
Finished Sep 18 08:56:33 PM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170518187 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.170518187 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/12.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.1014344463
Short name T796
Test name
Test status
Simulation time 46448705 ps
CPU time 1.51 seconds
Started Sep 18 08:56:32 PM UTC 24
Finished Sep 18 08:56:35 PM UTC 24
Peak memory 228808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014344463 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr_outstanding.1014344463 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/12.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2357409797
Short name T794
Test name
Test status
Simulation time 64634775 ps
CPU time 1.86 seconds
Started Sep 18 08:56:31 PM UTC 24
Finished Sep 18 08:56:34 PM UTC 24
Peak memory 218380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357409797 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors.2357409797 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/12.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.1706967493
Short name T798
Test name
Test status
Simulation time 113139450 ps
CPU time 3.13 seconds
Started Sep 18 08:56:31 PM UTC 24
Finished Sep 18 08:56:35 PM UTC 24
Peak memory 229864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706967493 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors_with_csr_rw
.1706967493 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.3217776754
Short name T799
Test name
Test status
Simulation time 352951429 ps
CPU time 3.73 seconds
Started Sep 18 08:56:31 PM UTC 24
Finished Sep 18 08:56:36 PM UTC 24
Peak memory 229588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217776754 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.3217776754 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/12.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.515316518
Short name T797
Test name
Test status
Simulation time 458508731 ps
CPU time 2.92 seconds
Started Sep 18 08:56:31 PM UTC 24
Finished Sep 18 08:56:35 PM UTC 24
Peak memory 219276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515316518 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.515316518 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/12.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.4237012536
Short name T813
Test name
Test status
Simulation time 72471283 ps
CPU time 3.63 seconds
Started Sep 18 08:56:36 PM UTC 24
Finished Sep 18 08:56:40 PM UTC 24
Peak memory 231820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4237012536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr
_mem_rw_with_rand_reset.4237012536 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.2248980044
Short name T805
Test name
Test status
Simulation time 45694951 ps
CPU time 1.36 seconds
Started Sep 18 08:56:34 PM UTC 24
Finished Sep 18 08:56:36 PM UTC 24
Peak memory 218692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248980044 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.2248980044 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/13.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.2785081512
Short name T804
Test name
Test status
Simulation time 55712216 ps
CPU time 1.21 seconds
Started Sep 18 08:56:34 PM UTC 24
Finished Sep 18 08:56:36 PM UTC 24
Peak memory 218688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785081512 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.2785081512 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/13.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.760843824
Short name T809
Test name
Test status
Simulation time 107697508 ps
CPU time 2.19 seconds
Started Sep 18 08:56:34 PM UTC 24
Finished Sep 18 08:56:37 PM UTC 24
Peak memory 229452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760843824 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr_outstanding.760843824 +enable_
masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/13.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.4221679978
Short name T801
Test name
Test status
Simulation time 61239252 ps
CPU time 2.29 seconds
Started Sep 18 08:56:32 PM UTC 24
Finished Sep 18 08:56:36 PM UTC 24
Peak memory 230124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221679978 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors.4221679978 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/13.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.3024681977
Short name T806
Test name
Test status
Simulation time 84614986 ps
CPU time 2.9 seconds
Started Sep 18 08:56:33 PM UTC 24
Finished Sep 18 08:56:36 PM UTC 24
Peak memory 229840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024681977 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors_with_csr_rw
.3024681977 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.2678657575
Short name T810
Test name
Test status
Simulation time 112649791 ps
CPU time 4.12 seconds
Started Sep 18 08:56:33 PM UTC 24
Finished Sep 18 08:56:38 PM UTC 24
Peak memory 229572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678657575 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.2678657575 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/13.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.406325789
Short name T808
Test name
Test status
Simulation time 122776823 ps
CPU time 2.84 seconds
Started Sep 18 08:56:33 PM UTC 24
Finished Sep 18 08:56:37 PM UTC 24
Peak memory 229476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406325789 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.406325789 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/13.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.1957503351
Short name T819
Test name
Test status
Simulation time 30786782 ps
CPU time 2.08 seconds
Started Sep 18 08:56:38 PM UTC 24
Finished Sep 18 08:56:41 PM UTC 24
Peak memory 231820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1957503351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr
_mem_rw_with_rand_reset.1957503351 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.715459068
Short name T812
Test name
Test status
Simulation time 41953627 ps
CPU time 1.25 seconds
Started Sep 18 08:56:38 PM UTC 24
Finished Sep 18 08:56:40 PM UTC 24
Peak memory 218728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715459068 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.715459068 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/14.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.2083571403
Short name T176
Test name
Test status
Simulation time 15591156 ps
CPU time 1.15 seconds
Started Sep 18 08:56:36 PM UTC 24
Finished Sep 18 08:56:38 PM UTC 24
Peak memory 218808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083571403 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.2083571403 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/14.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.2215447211
Short name T821
Test name
Test status
Simulation time 95188953 ps
CPU time 2.95 seconds
Started Sep 18 08:56:38 PM UTC 24
Finished Sep 18 08:56:42 PM UTC 24
Peak memory 229500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215447211 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr_outstanding.2215447211 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/14.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.3415825664
Short name T811
Test name
Test status
Simulation time 74859708 ps
CPU time 1.85 seconds
Started Sep 18 08:56:36 PM UTC 24
Finished Sep 18 08:56:39 PM UTC 24
Peak memory 228620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415825664 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors.3415825664 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/14.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.922929746
Short name T815
Test name
Test status
Simulation time 100399281 ps
CPU time 3.83 seconds
Started Sep 18 08:56:36 PM UTC 24
Finished Sep 18 08:56:41 PM UTC 24
Peak memory 230072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922929746 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors_with_csr_rw.
922929746 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.3179008697
Short name T817
Test name
Test status
Simulation time 141259554 ps
CPU time 3.94 seconds
Started Sep 18 08:56:36 PM UTC 24
Finished Sep 18 08:56:41 PM UTC 24
Peak memory 229588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179008697 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.3179008697 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/14.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.3111844681
Short name T828
Test name
Test status
Simulation time 340424508 ps
CPU time 3.15 seconds
Started Sep 18 08:56:40 PM UTC 24
Finished Sep 18 08:56:44 PM UTC 24
Peak memory 231564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3111844681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr
_mem_rw_with_rand_reset.3111844681 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.2838712541
Short name T816
Test name
Test status
Simulation time 27341019 ps
CPU time 1.4 seconds
Started Sep 18 08:56:38 PM UTC 24
Finished Sep 18 08:56:41 PM UTC 24
Peak memory 218692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838712541 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.2838712541 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/15.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.409659668
Short name T172
Test name
Test status
Simulation time 42288231 ps
CPU time 1.2 seconds
Started Sep 18 08:56:38 PM UTC 24
Finished Sep 18 08:56:40 PM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409659668 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.409659668 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/15.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1746414721
Short name T820
Test name
Test status
Simulation time 49312575 ps
CPU time 1.99 seconds
Started Sep 18 08:56:38 PM UTC 24
Finished Sep 18 08:56:41 PM UTC 24
Peak memory 228744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746414721 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr_outstanding.1746414721 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/15.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.337692445
Short name T814
Test name
Test status
Simulation time 126608470 ps
CPU time 1.62 seconds
Started Sep 18 08:56:38 PM UTC 24
Finished Sep 18 08:56:41 PM UTC 24
Peak memory 228620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337692445 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors.337692445 +enable_maskin
g=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/15.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.3083727953
Short name T825
Test name
Test status
Simulation time 219289114 ps
CPU time 4.1 seconds
Started Sep 18 08:56:38 PM UTC 24
Finished Sep 18 08:56:43 PM UTC 24
Peak memory 229588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083727953 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.3083727953 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/15.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.3287086332
Short name T822
Test name
Test status
Simulation time 185769337 ps
CPU time 3.2 seconds
Started Sep 18 08:56:38 PM UTC 24
Finished Sep 18 08:56:42 PM UTC 24
Peak memory 218868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287086332 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.3287086332 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/15.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2797932903
Short name T829
Test name
Test status
Simulation time 139625772 ps
CPU time 1.62 seconds
Started Sep 18 08:56:42 PM UTC 24
Finished Sep 18 08:56:44 PM UTC 24
Peak memory 228676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2797932903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr
_mem_rw_with_rand_reset.2797932903 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.2969261756
Short name T826
Test name
Test status
Simulation time 13175982 ps
CPU time 1.17 seconds
Started Sep 18 08:56:42 PM UTC 24
Finished Sep 18 08:56:44 PM UTC 24
Peak memory 218692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969261756 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.2969261756 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/16.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.3587864599
Short name T827
Test name
Test status
Simulation time 54866592 ps
CPU time 1.24 seconds
Started Sep 18 08:56:42 PM UTC 24
Finished Sep 18 08:56:44 PM UTC 24
Peak memory 218636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587864599 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.3587864599 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/16.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.563612953
Short name T830
Test name
Test status
Simulation time 153062629 ps
CPU time 1.73 seconds
Started Sep 18 08:56:42 PM UTC 24
Finished Sep 18 08:56:44 PM UTC 24
Peak memory 228744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563612953 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr_outstanding.563612953 +enable_
masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/16.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.2072765179
Short name T823
Test name
Test status
Simulation time 31471619 ps
CPU time 1.75 seconds
Started Sep 18 08:56:40 PM UTC 24
Finished Sep 18 08:56:43 PM UTC 24
Peak memory 228556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072765179 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors.2072765179 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/16.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.2263670977
Short name T824
Test name
Test status
Simulation time 39198093 ps
CPU time 2.21 seconds
Started Sep 18 08:56:40 PM UTC 24
Finished Sep 18 08:56:43 PM UTC 24
Peak memory 236052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263670977 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors_with_csr_rw
.2263670977 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.1592792971
Short name T833
Test name
Test status
Simulation time 227090886 ps
CPU time 3.19 seconds
Started Sep 18 08:56:42 PM UTC 24
Finished Sep 18 08:56:46 PM UTC 24
Peak memory 229588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592792971 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.1592792971 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/16.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.1650541850
Short name T183
Test name
Test status
Simulation time 237950067 ps
CPU time 5.72 seconds
Started Sep 18 08:56:42 PM UTC 24
Finished Sep 18 08:56:48 PM UTC 24
Peak memory 229492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650541850 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.1650541850 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/16.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.2629414404
Short name T841
Test name
Test status
Simulation time 175096236 ps
CPU time 2.37 seconds
Started Sep 18 08:56:45 PM UTC 24
Finished Sep 18 08:56:49 PM UTC 24
Peak memory 229580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2629414404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr
_mem_rw_with_rand_reset.2629414404 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.3164900091
Short name T834
Test name
Test status
Simulation time 15491881 ps
CPU time 1.4 seconds
Started Sep 18 08:56:43 PM UTC 24
Finished Sep 18 08:56:46 PM UTC 24
Peak memory 218692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164900091 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.3164900091 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/17.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.1566406003
Short name T832
Test name
Test status
Simulation time 50890388 ps
CPU time 1.24 seconds
Started Sep 18 08:56:43 PM UTC 24
Finished Sep 18 08:56:46 PM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566406003 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.1566406003 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/17.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2509023521
Short name T800
Test name
Test status
Simulation time 193795382 ps
CPU time 2.08 seconds
Started Sep 18 08:56:43 PM UTC 24
Finished Sep 18 08:56:46 PM UTC 24
Peak memory 229500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509023521 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr_outstanding.2509023521 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/17.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2171296014
Short name T831
Test name
Test status
Simulation time 421161035 ps
CPU time 1.73 seconds
Started Sep 18 08:56:42 PM UTC 24
Finished Sep 18 08:56:45 PM UTC 24
Peak memory 228556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171296014 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors.2171296014 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/17.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.2102497241
Short name T780
Test name
Test status
Simulation time 71101945 ps
CPU time 1.86 seconds
Started Sep 18 08:56:43 PM UTC 24
Finished Sep 18 08:56:46 PM UTC 24
Peak memory 228308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102497241 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors_with_csr_rw
.2102497241 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.2196632090
Short name T835
Test name
Test status
Simulation time 72168448 ps
CPU time 3.09 seconds
Started Sep 18 08:56:43 PM UTC 24
Finished Sep 18 08:56:47 PM UTC 24
Peak memory 229828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196632090 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.2196632090 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/17.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.3860479494
Short name T186
Test name
Test status
Simulation time 585617260 ps
CPU time 5.06 seconds
Started Sep 18 08:56:43 PM UTC 24
Finished Sep 18 08:56:49 PM UTC 24
Peak memory 229212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860479494 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.3860479494 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/17.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.577935671
Short name T843
Test name
Test status
Simulation time 94661035 ps
CPU time 2.3 seconds
Started Sep 18 08:56:46 PM UTC 24
Finished Sep 18 08:56:49 PM UTC 24
Peak memory 229456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=577935671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_
mem_rw_with_rand_reset.577935671 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.574195577
Short name T839
Test name
Test status
Simulation time 32880248 ps
CPU time 1.58 seconds
Started Sep 18 08:56:46 PM UTC 24
Finished Sep 18 08:56:48 PM UTC 24
Peak memory 218720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574195577 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.574195577 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/18.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.1288850756
Short name T837
Test name
Test status
Simulation time 38979287 ps
CPU time 1.16 seconds
Started Sep 18 08:56:46 PM UTC 24
Finished Sep 18 08:56:48 PM UTC 24
Peak memory 218688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288850756 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.1288850756 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/18.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.644083566
Short name T844
Test name
Test status
Simulation time 173189204 ps
CPU time 2.59 seconds
Started Sep 18 08:56:46 PM UTC 24
Finished Sep 18 08:56:49 PM UTC 24
Peak memory 229452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644083566 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr_outstanding.644083566 +enable_
masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/18.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.3691469986
Short name T836
Test name
Test status
Simulation time 26246436 ps
CPU time 1.32 seconds
Started Sep 18 08:56:45 PM UTC 24
Finished Sep 18 08:56:48 PM UTC 24
Peak memory 228620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691469986 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors.3691469986 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/18.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3079724951
Short name T840
Test name
Test status
Simulation time 100488864 ps
CPU time 2.07 seconds
Started Sep 18 08:56:45 PM UTC 24
Finished Sep 18 08:56:49 PM UTC 24
Peak memory 229528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079724951 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors_with_csr_rw
.3079724951 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.1095917983
Short name T842
Test name
Test status
Simulation time 128812655 ps
CPU time 2.5 seconds
Started Sep 18 08:56:46 PM UTC 24
Finished Sep 18 08:56:49 PM UTC 24
Peak memory 229652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095917983 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.1095917983 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/18.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.338290904
Short name T853
Test name
Test status
Simulation time 991866358 ps
CPU time 5.03 seconds
Started Sep 18 08:56:46 PM UTC 24
Finished Sep 18 08:56:52 PM UTC 24
Peak memory 229768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338290904 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.338290904 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/18.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.16992852
Short name T854
Test name
Test status
Simulation time 202057298 ps
CPU time 1.74 seconds
Started Sep 18 08:56:49 PM UTC 24
Finished Sep 18 08:56:52 PM UTC 24
Peak memory 228616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=16992852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_m
em_rw_with_rand_reset.16992852 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.1763198561
Short name T846
Test name
Test status
Simulation time 37837357 ps
CPU time 1.23 seconds
Started Sep 18 08:56:48 PM UTC 24
Finished Sep 18 08:56:50 PM UTC 24
Peak memory 218692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763198561 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.1763198561 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/19.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.2300821371
Short name T845
Test name
Test status
Simulation time 24002206 ps
CPU time 1.11 seconds
Started Sep 18 08:56:48 PM UTC 24
Finished Sep 18 08:56:50 PM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300821371 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.2300821371 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/19.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1020492824
Short name T855
Test name
Test status
Simulation time 90698697 ps
CPU time 1.87 seconds
Started Sep 18 08:56:49 PM UTC 24
Finished Sep 18 08:56:52 PM UTC 24
Peak memory 228788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020492824 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr_outstanding.1020492824 +enabl
e_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/19.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3222004817
Short name T838
Test name
Test status
Simulation time 114443109 ps
CPU time 1.41 seconds
Started Sep 18 08:56:46 PM UTC 24
Finished Sep 18 08:56:48 PM UTC 24
Peak memory 228620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222004817 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors.3222004817 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/19.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.401494635
Short name T847
Test name
Test status
Simulation time 169978140 ps
CPU time 2.33 seconds
Started Sep 18 08:56:47 PM UTC 24
Finished Sep 18 08:56:51 PM UTC 24
Peak memory 229800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401494635 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors_with_csr_rw.
401494635 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.2143305905
Short name T848
Test name
Test status
Simulation time 33133930 ps
CPU time 2.3 seconds
Started Sep 18 08:56:47 PM UTC 24
Finished Sep 18 08:56:51 PM UTC 24
Peak memory 229924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143305905 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.2143305905 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/19.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.2734473715
Short name T861
Test name
Test status
Simulation time 371224921 ps
CPU time 4.91 seconds
Started Sep 18 08:56:47 PM UTC 24
Finished Sep 18 08:56:53 PM UTC 24
Peak memory 219212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734473715 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.2734473715 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/19.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_aliasing.2348075759
Short name T739
Test name
Test status
Simulation time 463380539 ps
CPU time 7.4 seconds
Started Sep 18 08:55:58 PM UTC 24
Finished Sep 18 08:56:07 PM UTC 24
Peak memory 219152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348075759 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.2348075759 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.2780092372
Short name T761
Test name
Test status
Simulation time 971832514 ps
CPU time 23.16 seconds
Started Sep 18 08:55:57 PM UTC 24
Finished Sep 18 08:56:21 PM UTC 24
Peak memory 219156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780092372 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.2780092372 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_hw_reset.3372865836
Short name T728
Test name
Test status
Simulation time 27173854 ps
CPU time 1.28 seconds
Started Sep 18 08:55:56 PM UTC 24
Finished Sep 18 08:55:58 PM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372865836 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.3372865836 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.2702857137
Short name T155
Test name
Test status
Simulation time 90353858 ps
CPU time 3.06 seconds
Started Sep 18 08:55:59 PM UTC 24
Finished Sep 18 08:56:03 PM UTC 24
Peak memory 231560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2702857137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_
mem_rw_with_rand_reset.2702857137 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_rw.1319077445
Short name T730
Test name
Test status
Simulation time 65659683 ps
CPU time 1.3 seconds
Started Sep 18 08:55:57 PM UTC 24
Finished Sep 18 08:55:59 PM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319077445 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.1319077445 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_intr_test.3713059852
Short name T166
Test name
Test status
Simulation time 16184231 ps
CPU time 1.06 seconds
Started Sep 18 08:55:55 PM UTC 24
Finished Sep 18 08:55:57 PM UTC 24
Peak memory 218812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713059852 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.3713059852 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_walk.33795942
Short name T726
Test name
Test status
Simulation time 12558660 ps
CPU time 1.11 seconds
Started Sep 18 08:55:54 PM UTC 24
Finished Sep 18 08:55:56 PM UTC 24
Peak memory 218808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33795942 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.33795942 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_same_csr_outstanding.2337896580
Short name T147
Test name
Test status
Simulation time 102701696 ps
CPU time 2 seconds
Started Sep 18 08:55:58 PM UTC 24
Finished Sep 18 08:56:01 PM UTC 24
Peak memory 228792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337896580 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_outstanding.2337896580 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors.1286927259
Short name T111
Test name
Test status
Simulation time 46858208 ps
CPU time 1.75 seconds
Started Sep 18 08:55:51 PM UTC 24
Finished Sep 18 08:55:54 PM UTC 24
Peak memory 228620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286927259 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors.1286927259 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.12840231
Short name T112
Test name
Test status
Simulation time 123300929 ps
CPU time 3.53 seconds
Started Sep 18 08:55:54 PM UTC 24
Finished Sep 18 08:55:58 PM UTC 24
Peak memory 229884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12840231 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors_with_csr_rw.12
840231 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_errors.725744675
Short name T128
Test name
Test status
Simulation time 254252362 ps
CPU time 3.92 seconds
Started Sep 18 08:55:54 PM UTC 24
Finished Sep 18 08:55:59 PM UTC 24
Peak memory 229668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725744675 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.725744675 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_intg_err.1606585009
Short name T120
Test name
Test status
Simulation time 182704688 ps
CPU time 5.73 seconds
Started Sep 18 08:55:55 PM UTC 24
Finished Sep 18 08:56:02 PM UTC 24
Peak memory 229520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606585009 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.1606585009 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.4247086265
Short name T849
Test name
Test status
Simulation time 72659741 ps
CPU time 1.07 seconds
Started Sep 18 08:56:49 PM UTC 24
Finished Sep 18 08:56:51 PM UTC 24
Peak memory 218688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247086265 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.4247086265 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/20.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.4043161853
Short name T851
Test name
Test status
Simulation time 19756782 ps
CPU time 1.2 seconds
Started Sep 18 08:56:49 PM UTC 24
Finished Sep 18 08:56:51 PM UTC 24
Peak memory 218688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043161853 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.4043161853 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/21.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.3365516110
Short name T850
Test name
Test status
Simulation time 79044705 ps
CPU time 1.06 seconds
Started Sep 18 08:56:49 PM UTC 24
Finished Sep 18 08:56:51 PM UTC 24
Peak memory 218688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365516110 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.3365516110 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/22.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.2355883766
Short name T858
Test name
Test status
Simulation time 58601111 ps
CPU time 1.08 seconds
Started Sep 18 08:56:51 PM UTC 24
Finished Sep 18 08:56:53 PM UTC 24
Peak memory 218688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355883766 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.2355883766 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/24.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.3624635875
Short name T857
Test name
Test status
Simulation time 17542287 ps
CPU time 0.93 seconds
Started Sep 18 08:56:51 PM UTC 24
Finished Sep 18 08:56:53 PM UTC 24
Peak memory 218688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624635875 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.3624635875 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/25.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.3653079649
Short name T856
Test name
Test status
Simulation time 71968814 ps
CPU time 0.9 seconds
Started Sep 18 08:56:51 PM UTC 24
Finished Sep 18 08:56:53 PM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653079649 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.3653079649 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/26.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.4157123767
Short name T859
Test name
Test status
Simulation time 48289846 ps
CPU time 1.02 seconds
Started Sep 18 08:56:51 PM UTC 24
Finished Sep 18 08:56:53 PM UTC 24
Peak memory 218688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157123767 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.4157123767 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/27.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.315601130
Short name T860
Test name
Test status
Simulation time 19505448 ps
CPU time 0.98 seconds
Started Sep 18 08:56:51 PM UTC 24
Finished Sep 18 08:56:53 PM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315601130 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.315601130 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/28.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.3050215822
Short name T865
Test name
Test status
Simulation time 42427167 ps
CPU time 1.16 seconds
Started Sep 18 08:56:51 PM UTC 24
Finished Sep 18 08:56:54 PM UTC 24
Peak memory 218688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050215822 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.3050215822 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/29.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.3793617668
Short name T743
Test name
Test status
Simulation time 155291029 ps
CPU time 4.01 seconds
Started Sep 18 08:56:04 PM UTC 24
Finished Sep 18 08:56:09 PM UTC 24
Peak memory 219344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793617668 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.3793617668 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.4125868398
Short name T749
Test name
Test status
Simulation time 2702891343 ps
CPU time 9.27 seconds
Started Sep 18 08:56:04 PM UTC 24
Finished Sep 18 08:56:15 PM UTC 24
Peak memory 219220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125868398 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.4125868398 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_hw_reset.4104941694
Short name T736
Test name
Test status
Simulation time 380872330 ps
CPU time 1.72 seconds
Started Sep 18 08:56:03 PM UTC 24
Finished Sep 18 08:56:06 PM UTC 24
Peak memory 228680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104941694 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.4104941694 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.170375258
Short name T742
Test name
Test status
Simulation time 182992426 ps
CPU time 2.35 seconds
Started Sep 18 08:56:05 PM UTC 24
Finished Sep 18 08:56:09 PM UTC 24
Peak memory 229472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=170375258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_m
em_rw_with_rand_reset.170375258 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_rw.3362693416
Short name T735
Test name
Test status
Simulation time 16370326 ps
CPU time 1.66 seconds
Started Sep 18 08:56:03 PM UTC 24
Finished Sep 18 08:56:06 PM UTC 24
Peak memory 218756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362693416 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.3362693416 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_intr_test.1511770031
Short name T167
Test name
Test status
Simulation time 21345326 ps
CPU time 1.17 seconds
Started Sep 18 08:56:03 PM UTC 24
Finished Sep 18 08:56:05 PM UTC 24
Peak memory 218672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511770031 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.1511770031 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_partial_access.3092523481
Short name T137
Test name
Test status
Simulation time 62736863 ps
CPU time 2.25 seconds
Started Sep 18 08:56:01 PM UTC 24
Finished Sep 18 08:56:04 PM UTC 24
Peak memory 229392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092523481 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial_access.3092523481 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_walk.2027395459
Short name T731
Test name
Test status
Simulation time 39475904 ps
CPU time 1.13 seconds
Started Sep 18 08:56:00 PM UTC 24
Finished Sep 18 08:56:02 PM UTC 24
Peak memory 218868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027395459 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.2027395459 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_same_csr_outstanding.2656876703
Short name T740
Test name
Test status
Simulation time 48864367 ps
CPU time 2.13 seconds
Started Sep 18 08:56:05 PM UTC 24
Finished Sep 18 08:56:08 PM UTC 24
Peak memory 229404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656876703 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_outstanding.2656876703 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors.3097456481
Short name T732
Test name
Test status
Simulation time 32954028 ps
CPU time 1.47 seconds
Started Sep 18 08:55:59 PM UTC 24
Finished Sep 18 08:56:02 PM UTC 24
Peak memory 218444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097456481 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors.3097456481 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.2714165732
Short name T104
Test name
Test status
Simulation time 604446167 ps
CPU time 3.91 seconds
Started Sep 18 08:55:59 PM UTC 24
Finished Sep 18 08:56:04 PM UTC 24
Peak memory 230120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714165732 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors_with_csr_rw.
2714165732 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_errors.2669717659
Short name T737
Test name
Test status
Simulation time 77559235 ps
CPU time 3.07 seconds
Started Sep 18 08:56:02 PM UTC 24
Finished Sep 18 08:56:06 PM UTC 24
Peak memory 229888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669717659 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.2669717659 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_intg_err.1225865789
Short name T738
Test name
Test status
Simulation time 210909695 ps
CPU time 3.07 seconds
Started Sep 18 08:56:02 PM UTC 24
Finished Sep 18 08:56:06 PM UTC 24
Peak memory 229456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225865789 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.1225865789 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.4165911240
Short name T864
Test name
Test status
Simulation time 12131148 ps
CPU time 1.09 seconds
Started Sep 18 08:56:51 PM UTC 24
Finished Sep 18 08:56:54 PM UTC 24
Peak memory 218624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165911240 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.4165911240 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/30.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.982340388
Short name T862
Test name
Test status
Simulation time 24881828 ps
CPU time 0.99 seconds
Started Sep 18 08:56:51 PM UTC 24
Finished Sep 18 08:56:53 PM UTC 24
Peak memory 218596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982340388 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.982340388 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/31.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.482985622
Short name T863
Test name
Test status
Simulation time 17173574 ps
CPU time 0.94 seconds
Started Sep 18 08:56:51 PM UTC 24
Finished Sep 18 08:56:53 PM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482985622 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.482985622 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/32.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.3093334559
Short name T868
Test name
Test status
Simulation time 107203938 ps
CPU time 1.16 seconds
Started Sep 18 08:56:54 PM UTC 24
Finished Sep 18 08:56:56 PM UTC 24
Peak memory 218688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093334559 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.3093334559 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/33.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.2562364301
Short name T871
Test name
Test status
Simulation time 49056512 ps
CPU time 1.11 seconds
Started Sep 18 08:56:54 PM UTC 24
Finished Sep 18 08:56:57 PM UTC 24
Peak memory 218424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562364301 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.2562364301 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/34.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.1799870780
Short name T866
Test name
Test status
Simulation time 11718384 ps
CPU time 0.8 seconds
Started Sep 18 08:56:54 PM UTC 24
Finished Sep 18 08:56:56 PM UTC 24
Peak memory 218344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799870780 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.1799870780 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/35.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.2176486814
Short name T867
Test name
Test status
Simulation time 30329152 ps
CPU time 0.99 seconds
Started Sep 18 08:56:54 PM UTC 24
Finished Sep 18 08:56:56 PM UTC 24
Peak memory 218688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176486814 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.2176486814 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/36.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.905616868
Short name T875
Test name
Test status
Simulation time 41289724 ps
CPU time 1.09 seconds
Started Sep 18 08:56:54 PM UTC 24
Finished Sep 18 08:56:57 PM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905616868 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.905616868 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/37.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.3031146502
Short name T869
Test name
Test status
Simulation time 22115170 ps
CPU time 1.08 seconds
Started Sep 18 08:56:54 PM UTC 24
Finished Sep 18 08:56:57 PM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031146502 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.3031146502 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/38.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.636548625
Short name T870
Test name
Test status
Simulation time 54385073 ps
CPU time 1.1 seconds
Started Sep 18 08:56:54 PM UTC 24
Finished Sep 18 08:56:57 PM UTC 24
Peak memory 218808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636548625 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.636548625 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/39.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.3587833697
Short name T766
Test name
Test status
Simulation time 588428468 ps
CPU time 11.27 seconds
Started Sep 18 08:56:10 PM UTC 24
Finished Sep 18 08:56:23 PM UTC 24
Peak memory 229392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587833697 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.3587833697 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.1580969123
Short name T763
Test name
Test status
Simulation time 489358790 ps
CPU time 11.85 seconds
Started Sep 18 08:56:09 PM UTC 24
Finished Sep 18 08:56:22 PM UTC 24
Peak memory 219156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580969123 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.1580969123 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_hw_reset.2496426631
Short name T745
Test name
Test status
Simulation time 59204926 ps
CPU time 1.41 seconds
Started Sep 18 08:56:09 PM UTC 24
Finished Sep 18 08:56:12 PM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496426631 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.2496426631 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.1751187012
Short name T748
Test name
Test status
Simulation time 288769132 ps
CPU time 2.55 seconds
Started Sep 18 08:56:10 PM UTC 24
Finished Sep 18 08:56:14 PM UTC 24
Peak memory 229512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1751187012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_
mem_rw_with_rand_reset.1751187012 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_rw.658180796
Short name T746
Test name
Test status
Simulation time 18505304 ps
CPU time 1.39 seconds
Started Sep 18 08:56:09 PM UTC 24
Finished Sep 18 08:56:12 PM UTC 24
Peak memory 218756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658180796 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.658180796 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_intr_test.3893418824
Short name T168
Test name
Test status
Simulation time 11941330 ps
CPU time 1.18 seconds
Started Sep 18 08:56:08 PM UTC 24
Finished Sep 18 08:56:10 PM UTC 24
Peak memory 218812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893418824 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.3893418824 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_partial_access.1391455115
Short name T138
Test name
Test status
Simulation time 76794610 ps
CPU time 2.23 seconds
Started Sep 18 08:56:07 PM UTC 24
Finished Sep 18 08:56:10 PM UTC 24
Peak memory 229392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391455115 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial_access.1391455115 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_walk.3800179379
Short name T741
Test name
Test status
Simulation time 27771254 ps
CPU time 1.08 seconds
Started Sep 18 08:56:07 PM UTC 24
Finished Sep 18 08:56:09 PM UTC 24
Peak memory 218868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800179379 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.3800179379 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_same_csr_outstanding.1707997667
Short name T747
Test name
Test status
Simulation time 31700175 ps
CPU time 2.12 seconds
Started Sep 18 08:56:10 PM UTC 24
Finished Sep 18 08:56:14 PM UTC 24
Peak memory 229504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707997667 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_outstanding.1707997667 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors.661885555
Short name T106
Test name
Test status
Simulation time 72408638 ps
CPU time 1.6 seconds
Started Sep 18 08:56:07 PM UTC 24
Finished Sep 18 08:56:09 PM UTC 24
Peak memory 228620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661885555 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors.661885555 +enable_masking
=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.630566544
Short name T105
Test name
Test status
Simulation time 58119672 ps
CPU time 2.58 seconds
Started Sep 18 08:56:07 PM UTC 24
Finished Sep 18 08:56:10 PM UTC 24
Peak memory 229804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630566544 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors_with_csr_rw.6
30566544 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_errors.293044389
Short name T744
Test name
Test status
Simulation time 167475549 ps
CPU time 3.83 seconds
Started Sep 18 08:56:07 PM UTC 24
Finished Sep 18 08:56:12 PM UTC 24
Peak memory 229668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293044389 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.293044389 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_intg_err.94638427
Short name T179
Test name
Test status
Simulation time 431045962 ps
CPU time 3.97 seconds
Started Sep 18 08:56:08 PM UTC 24
Finished Sep 18 08:56:13 PM UTC 24
Peak memory 229472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94638427 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.94638427 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.1545288718
Short name T872
Test name
Test status
Simulation time 151029076 ps
CPU time 1.02 seconds
Started Sep 18 08:56:54 PM UTC 24
Finished Sep 18 08:56:57 PM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545288718 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.1545288718 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/40.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.259445394
Short name T877
Test name
Test status
Simulation time 21237584 ps
CPU time 1.06 seconds
Started Sep 18 08:56:54 PM UTC 24
Finished Sep 18 08:56:57 PM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259445394 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.259445394 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/41.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.94817024
Short name T876
Test name
Test status
Simulation time 24939200 ps
CPU time 0.94 seconds
Started Sep 18 08:56:54 PM UTC 24
Finished Sep 18 08:56:57 PM UTC 24
Peak memory 218824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94817024 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.94817024 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/42.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.1213083849
Short name T874
Test name
Test status
Simulation time 33523571 ps
CPU time 0.93 seconds
Started Sep 18 08:56:54 PM UTC 24
Finished Sep 18 08:56:57 PM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213083849 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.1213083849 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/43.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.2694892379
Short name T873
Test name
Test status
Simulation time 17167137 ps
CPU time 0.86 seconds
Started Sep 18 08:56:54 PM UTC 24
Finished Sep 18 08:56:57 PM UTC 24
Peak memory 218808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694892379 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.2694892379 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/44.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.447913803
Short name T881
Test name
Test status
Simulation time 25245394 ps
CPU time 1.14 seconds
Started Sep 18 08:56:54 PM UTC 24
Finished Sep 18 08:56:58 PM UTC 24
Peak memory 218808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447913803 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.447913803 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/45.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.460538288
Short name T879
Test name
Test status
Simulation time 28897956 ps
CPU time 0.84 seconds
Started Sep 18 08:56:54 PM UTC 24
Finished Sep 18 08:56:57 PM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460538288 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.460538288 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/46.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.3003476904
Short name T878
Test name
Test status
Simulation time 32853569 ps
CPU time 0.77 seconds
Started Sep 18 08:56:55 PM UTC 24
Finished Sep 18 08:56:57 PM UTC 24
Peak memory 218688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003476904 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.3003476904 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/47.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.3401906732
Short name T882
Test name
Test status
Simulation time 19193520 ps
CPU time 1.07 seconds
Started Sep 18 08:56:55 PM UTC 24
Finished Sep 18 08:56:58 PM UTC 24
Peak memory 218688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401906732 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.3401906732 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/48.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.349639573
Short name T880
Test name
Test status
Simulation time 72163359 ps
CPU time 0.77 seconds
Started Sep 18 08:56:55 PM UTC 24
Finished Sep 18 08:56:58 PM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349639573 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.349639573 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/49.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.2515727010
Short name T751
Test name
Test status
Simulation time 22565099 ps
CPU time 1.78 seconds
Started Sep 18 08:56:13 PM UTC 24
Finished Sep 18 08:56:16 PM UTC 24
Peak memory 228676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2515727010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_
mem_rw_with_rand_reset.2515727010 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_rw.2357535634
Short name T750
Test name
Test status
Simulation time 29924283 ps
CPU time 1.71 seconds
Started Sep 18 08:56:13 PM UTC 24
Finished Sep 18 08:56:16 PM UTC 24
Peak memory 228740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357535634 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.2357535634 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/5.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_intr_test.646673487
Short name T170
Test name
Test status
Simulation time 39049823 ps
CPU time 1.02 seconds
Started Sep 18 08:56:13 PM UTC 24
Finished Sep 18 08:56:15 PM UTC 24
Peak memory 218816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646673487 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.646673487 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/5.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_same_csr_outstanding.3152916114
Short name T753
Test name
Test status
Simulation time 137402751 ps
CPU time 2.2 seconds
Started Sep 18 08:56:13 PM UTC 24
Finished Sep 18 08:56:16 PM UTC 24
Peak memory 229464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152916114 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_outstanding.3152916114 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/5.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors.3613631631
Short name T109
Test name
Test status
Simulation time 19345135 ps
CPU time 1.18 seconds
Started Sep 18 08:56:12 PM UTC 24
Finished Sep 18 08:56:14 PM UTC 24
Peak memory 218444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613631631 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors.3613631631 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1647600986
Short name T110
Test name
Test status
Simulation time 184041602 ps
CPU time 2.19 seconds
Started Sep 18 08:56:12 PM UTC 24
Finished Sep 18 08:56:15 PM UTC 24
Peak memory 229532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647600986 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors_with_csr_rw.
1647600986 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_errors.1168267385
Short name T752
Test name
Test status
Simulation time 79908919 ps
CPU time 3.15 seconds
Started Sep 18 08:56:12 PM UTC 24
Finished Sep 18 08:56:16 PM UTC 24
Peak memory 229844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168267385 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.1168267385 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/5.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.786577179
Short name T184
Test name
Test status
Simulation time 201944061 ps
CPU time 4.96 seconds
Started Sep 18 08:56:12 PM UTC 24
Finished Sep 18 08:56:18 PM UTC 24
Peak memory 231824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786577179 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.786577179 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/5.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.94988553
Short name T759
Test name
Test status
Simulation time 73767964 ps
CPU time 2.59 seconds
Started Sep 18 08:56:17 PM UTC 24
Finished Sep 18 08:56:21 PM UTC 24
Peak memory 229524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=94988553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_me
m_rw_with_rand_reset.94988553 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_rw.1938407667
Short name T755
Test name
Test status
Simulation time 38105512 ps
CPU time 1.26 seconds
Started Sep 18 08:56:16 PM UTC 24
Finished Sep 18 08:56:18 PM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938407667 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.1938407667 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/6.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_same_csr_outstanding.2880858298
Short name T756
Test name
Test status
Simulation time 57469303 ps
CPU time 2.16 seconds
Started Sep 18 08:56:16 PM UTC 24
Finished Sep 18 08:56:19 PM UTC 24
Peak memory 229760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880858298 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr_outstanding.2880858298 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/6.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors.1227717960
Short name T108
Test name
Test status
Simulation time 39434130 ps
CPU time 1.77 seconds
Started Sep 18 08:56:14 PM UTC 24
Finished Sep 18 08:56:17 PM UTC 24
Peak memory 228544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227717960 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors.1227717960 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.1890888297
Short name T754
Test name
Test status
Simulation time 117740777 ps
CPU time 2.62 seconds
Started Sep 18 08:56:14 PM UTC 24
Finished Sep 18 08:56:18 PM UTC 24
Peak memory 236644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890888297 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors_with_csr_rw.
1890888297 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_errors.301246369
Short name T757
Test name
Test status
Simulation time 125844355 ps
CPU time 4.44 seconds
Started Sep 18 08:56:14 PM UTC 24
Finished Sep 18 08:56:20 PM UTC 24
Peak memory 229588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301246369 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.301246369 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/6.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.3499345345
Short name T180
Test name
Test status
Simulation time 193569533 ps
CPU time 6.64 seconds
Started Sep 18 08:56:16 PM UTC 24
Finished Sep 18 08:56:23 PM UTC 24
Peak memory 229456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499345345 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.3499345345 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/6.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3524544298
Short name T764
Test name
Test status
Simulation time 41745412 ps
CPU time 2.08 seconds
Started Sep 18 08:56:20 PM UTC 24
Finished Sep 18 08:56:23 PM UTC 24
Peak memory 229768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3524544298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_
mem_rw_with_rand_reset.3524544298 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.22492944
Short name T760
Test name
Test status
Simulation time 42125989 ps
CPU time 1.31 seconds
Started Sep 18 08:56:18 PM UTC 24
Finished Sep 18 08:56:21 PM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22492944 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.22492944 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/7.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_intr_test.305200648
Short name T171
Test name
Test status
Simulation time 30313284 ps
CPU time 0.94 seconds
Started Sep 18 08:56:18 PM UTC 24
Finished Sep 18 08:56:20 PM UTC 24
Peak memory 218876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305200648 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.305200648 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/7.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3373158514
Short name T768
Test name
Test status
Simulation time 259145127 ps
CPU time 2.42 seconds
Started Sep 18 08:56:19 PM UTC 24
Finished Sep 18 08:56:23 PM UTC 24
Peak memory 229456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373158514 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_outstanding.3373158514 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/7.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2904432719
Short name T107
Test name
Test status
Simulation time 14457561 ps
CPU time 1.25 seconds
Started Sep 18 08:56:17 PM UTC 24
Finished Sep 18 08:56:19 PM UTC 24
Peak memory 218444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904432719 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors.2904432719 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.2080103706
Short name T758
Test name
Test status
Simulation time 57648007 ps
CPU time 2.43 seconds
Started Sep 18 08:56:17 PM UTC 24
Finished Sep 18 08:56:21 PM UTC 24
Peak memory 229820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080103706 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors_with_csr_rw.
2080103706 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.3967603580
Short name T762
Test name
Test status
Simulation time 548831210 ps
CPU time 3.57 seconds
Started Sep 18 08:56:17 PM UTC 24
Finished Sep 18 08:56:22 PM UTC 24
Peak memory 229844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967603580 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.3967603580 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/7.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.1583425365
Short name T767
Test name
Test status
Simulation time 53533962 ps
CPU time 3.53 seconds
Started Sep 18 08:56:18 PM UTC 24
Finished Sep 18 08:56:23 PM UTC 24
Peak memory 219236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583425365 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.1583425365 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/7.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.4173829750
Short name T771
Test name
Test status
Simulation time 155239520 ps
CPU time 2.25 seconds
Started Sep 18 08:56:22 PM UTC 24
Finished Sep 18 08:56:25 PM UTC 24
Peak memory 229768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4173829750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_
mem_rw_with_rand_reset.4173829750 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.870484797
Short name T770
Test name
Test status
Simulation time 25418982 ps
CPU time 1.47 seconds
Started Sep 18 08:56:22 PM UTC 24
Finished Sep 18 08:56:25 PM UTC 24
Peak memory 218756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870484797 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.870484797 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/8.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.2810761139
Short name T173
Test name
Test status
Simulation time 16027985 ps
CPU time 1.16 seconds
Started Sep 18 08:56:22 PM UTC 24
Finished Sep 18 08:56:24 PM UTC 24
Peak memory 218752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810761139 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.2810761139 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/8.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.3441287004
Short name T773
Test name
Test status
Simulation time 89949609 ps
CPU time 3 seconds
Started Sep 18 08:56:22 PM UTC 24
Finished Sep 18 08:56:26 PM UTC 24
Peak memory 229756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441287004 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_outstanding.3441287004 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/8.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.548673850
Short name T765
Test name
Test status
Simulation time 45358305 ps
CPU time 2.12 seconds
Started Sep 18 08:56:20 PM UTC 24
Finished Sep 18 08:56:23 PM UTC 24
Peak memory 229804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548673850 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors.548673850 +enable_masking
=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/8.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.129994468
Short name T769
Test name
Test status
Simulation time 60728538 ps
CPU time 2.32 seconds
Started Sep 18 08:56:21 PM UTC 24
Finished Sep 18 08:56:24 PM UTC 24
Peak memory 229548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129994468 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors_with_csr_rw.1
29994468 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.2190031777
Short name T734
Test name
Test status
Simulation time 195566958 ps
CPU time 2.49 seconds
Started Sep 18 08:56:21 PM UTC 24
Finished Sep 18 08:56:24 PM UTC 24
Peak memory 229924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190031777 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.2190031777 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/8.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.4025989726
Short name T181
Test name
Test status
Simulation time 1487437967 ps
CPU time 4.85 seconds
Started Sep 18 08:56:21 PM UTC 24
Finished Sep 18 08:56:27 PM UTC 24
Peak memory 229476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025989726 -assert nopostproc +UV
M_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.4025989726 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/8.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2388439813
Short name T781
Test name
Test status
Simulation time 205950385 ps
CPU time 2.59 seconds
Started Sep 18 08:56:25 PM UTC 24
Finished Sep 18 08:56:29 PM UTC 24
Peak memory 229452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2388439813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_
mem_rw_with_rand_reset.2388439813 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.3492795912
Short name T774
Test name
Test status
Simulation time 35184870 ps
CPU time 1.36 seconds
Started Sep 18 08:56:24 PM UTC 24
Finished Sep 18 08:56:26 PM UTC 24
Peak memory 218748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492795912 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.3492795912 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/9.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.481552105
Short name T772
Test name
Test status
Simulation time 19843920 ps
CPU time 1.13 seconds
Started Sep 18 08:56:24 PM UTC 24
Finished Sep 18 08:56:26 PM UTC 24
Peak memory 218816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481552105 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.481552105 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/9.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.1999812539
Short name T777
Test name
Test status
Simulation time 60168844 ps
CPU time 2 seconds
Started Sep 18 08:56:24 PM UTC 24
Finished Sep 18 08:56:27 PM UTC 24
Peak memory 228748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999812539 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_outstanding.1999812539 +enable
_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/9.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.3115064479
Short name T775
Test name
Test status
Simulation time 69029249 ps
CPU time 1.84 seconds
Started Sep 18 08:56:24 PM UTC 24
Finished Sep 18 08:56:27 PM UTC 24
Peak memory 228620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115064479 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors.3115064479 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/9.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.2693227513
Short name T776
Test name
Test status
Simulation time 286948754 ps
CPU time 2.05 seconds
Started Sep 18 08:56:24 PM UTC 24
Finished Sep 18 08:56:27 PM UTC 24
Peak memory 229944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693227513 -ass
ert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors_with_csr_rw.
2693227513 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.939291205
Short name T778
Test name
Test status
Simulation time 136386086 ps
CPU time 3.01 seconds
Started Sep 18 08:56:24 PM UTC 24
Finished Sep 18 08:56:28 PM UTC 24
Peak memory 229588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939291205 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.939291205 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/9.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/0.kmac_app.1650211746
Short name T39
Test name
Test status
Simulation time 66622297135 ps
CPU time 322.6 seconds
Started Sep 18 07:59:58 PM UTC 24
Finished Sep 18 08:05:25 PM UTC 24
Peak memory 504600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650211746 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.1650211746 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/0.kmac_burst_write.1471992172
Short name T143
Test name
Test status
Simulation time 130568518540 ps
CPU time 1025.3 seconds
Started Sep 18 07:59:57 PM UTC 24
Finished Sep 18 08:17:14 PM UTC 24
Peak memory 269108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471992172 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.1471992172 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/0.kmac_edn_timeout_error.172008539
Short name T18
Test name
Test status
Simulation time 233357171 ps
CPU time 15.51 seconds
Started Sep 18 07:59:58 PM UTC 24
Finished Sep 18 08:00:15 PM UTC 24
Peak memory 234148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172008539 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.172008539 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_mode_error.1557043542
Short name T28
Test name
Test status
Simulation time 3845178329 ps
CPU time 15.53 seconds
Started Sep 18 07:59:58 PM UTC 24
Finished Sep 18 08:00:22 PM UTC 24
Peak memory 233540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557043542 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.1557043542 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/0.kmac_entropy_refresh.3975178969
Short name T209
Test name
Test status
Simulation time 73562470973 ps
CPU time 421.81 seconds
Started Sep 18 07:59:58 PM UTC 24
Finished Sep 18 08:07:06 PM UTC 24
Peak memory 500828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975178969 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.3975178969 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/0.kmac_error.1179269774
Short name T26
Test name
Test status
Simulation time 57497548291 ps
CPU time 387.8 seconds
Started Sep 18 07:59:58 PM UTC 24
Finished Sep 18 08:06:32 PM UTC 24
Peak memory 514804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179269774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.1179269774 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/0.kmac_key_error.2527316134
Short name T14
Test name
Test status
Simulation time 12741941539 ps
CPU time 10.92 seconds
Started Sep 18 07:59:58 PM UTC 24
Finished Sep 18 08:00:10 PM UTC 24
Peak memory 227332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527316134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.2527316134 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/0.kmac_long_msg_and_output.644114570
Short name T187
Test name
Test status
Simulation time 4559140466 ps
CPU time 375.96 seconds
Started Sep 18 07:59:57 PM UTC 24
Finished Sep 18 08:06:18 PM UTC 24
Peak memory 471792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644114570 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_and_output.644114570 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/0.kmac_sec_cm.3329241880
Short name T10
Test name
Test status
Simulation time 12143770331 ps
CPU time 80.72 seconds
Started Sep 18 07:59:59 PM UTC 24
Finished Sep 18 08:01:29 PM UTC 24
Peak memory 278728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329241880 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.3329241880 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/0.kmac_stress_all.2104613796
Short name T133
Test name
Test status
Simulation time 13241287335 ps
CPU time 200.58 seconds
Started Sep 18 07:59:58 PM UTC 24
Finished Sep 18 08:03:22 PM UTC 24
Peak memory 508760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104613796 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.2104613796 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac.2164028234
Short name T3
Test name
Test status
Simulation time 214340992 ps
CPU time 2.43 seconds
Started Sep 18 07:59:58 PM UTC 24
Finished Sep 18 08:00:01 PM UTC 24
Peak memory 229756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164028234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac.2164028234 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac_xof.1577347519
Short name T2
Test name
Test status
Simulation time 99092468 ps
CPU time 2.04 seconds
Started Sep 18 07:59:58 PM UTC 24
Finished Sep 18 08:00:01 PM UTC 24
Peak memory 227504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577347519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.1577347519 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_224.2486574201
Short name T491
Test name
Test status
Simulation time 241756067964 ps
CPU time 2280.92 seconds
Started Sep 18 07:59:57 PM UTC 24
Finished Sep 18 08:38:24 PM UTC 24
Peak memory 3117436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486574201 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.2486574201
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_384.480531972
Short name T417
Test name
Test status
Simulation time 233810012845 ps
CPU time 1824.31 seconds
Started Sep 18 07:59:57 PM UTC 24
Finished Sep 18 08:30:42 PM UTC 24
Peak memory 2380380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480531972 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.480531972 +
enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_512.2214084170
Short name T16
Test name
Test status
Simulation time 274614850 ps
CPU time 13.22 seconds
Started Sep 18 07:59:57 PM UTC 24
Finished Sep 18 08:00:11 PM UTC 24
Peak memory 229416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214084170 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.2214084170
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_256.2325914734
Short name T360
Test name
Test status
Simulation time 33606599676 ps
CPU time 1420.05 seconds
Started Sep 18 07:59:57 PM UTC 24
Finished Sep 18 08:23:53 PM UTC 24
Peak memory 1116828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325914734 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.2325914
734 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/1.kmac_alert_test.1943041370
Short name T46
Test name
Test status
Simulation time 23039259 ps
CPU time 1.16 seconds
Started Sep 18 08:00:16 PM UTC 24
Finished Sep 18 08:00:18 PM UTC 24
Peak memory 216508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943041370 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.1943041370 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/1.kmac_app.810187243
Short name T48
Test name
Test status
Simulation time 10694272774 ps
CPU time 135.92 seconds
Started Sep 18 08:00:02 PM UTC 24
Finished Sep 18 08:02:24 PM UTC 24
Peak memory 293552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810187243 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.810187243 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/1.kmac_app_with_partial_data.1059413780
Short name T24
Test name
Test status
Simulation time 177722733911 ps
CPU time 353.98 seconds
Started Sep 18 08:00:07 PM UTC 24
Finished Sep 18 08:06:06 PM UTC 24
Peak memory 445236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059413780 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.1059413780 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/1.kmac_burst_write.685050562
Short name T96
Test name
Test status
Simulation time 11758360397 ps
CPU time 82.06 seconds
Started Sep 18 08:00:00 PM UTC 24
Finished Sep 18 08:01:29 PM UTC 24
Peak memory 234360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685050562 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.685050562 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/1.kmac_edn_timeout_error.3251882251
Short name T30
Test name
Test status
Simulation time 1871436680 ps
CPU time 53.67 seconds
Started Sep 18 08:00:10 PM UTC 24
Finished Sep 18 08:01:05 PM UTC 24
Peak memory 233900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251882251 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.3251882251 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_mode_error.3548281556
Short name T29
Test name
Test status
Simulation time 469016365 ps
CPU time 40.92 seconds
Started Sep 18 08:00:10 PM UTC 24
Finished Sep 18 08:00:52 PM UTC 24
Peak memory 233868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548281556 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.3548281556 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_ready_error.3489130278
Short name T21
Test name
Test status
Simulation time 14676428943 ps
CPU time 35.39 seconds
Started Sep 18 08:00:12 PM UTC 24
Finished Sep 18 08:00:49 PM UTC 24
Peak memory 234288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489130278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.3489130278 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/1.kmac_entropy_refresh.1660732674
Short name T23
Test name
Test status
Simulation time 11959547784 ps
CPU time 274.36 seconds
Started Sep 18 08:00:07 PM UTC 24
Finished Sep 18 08:04:46 PM UTC 24
Peak memory 443228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660732674 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.1660732674 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/1.kmac_key_error.3753569709
Short name T17
Test name
Test status
Simulation time 6575589080 ps
CPU time 4.06 seconds
Started Sep 18 08:00:08 PM UTC 24
Finished Sep 18 08:00:14 PM UTC 24
Peak memory 227300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753569709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.3753569709 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/1.kmac_lc_escalation.3742515772
Short name T5
Test name
Test status
Simulation time 41049971 ps
CPU time 2.05 seconds
Started Sep 18 08:00:12 PM UTC 24
Finished Sep 18 08:00:15 PM UTC 24
Peak memory 227656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742515772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.3742515772 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/1.kmac_long_msg_and_output.358175108
Short name T374
Test name
Test status
Simulation time 15484471278 ps
CPU time 1469.26 seconds
Started Sep 18 08:00:00 PM UTC 24
Finished Sep 18 08:24:52 PM UTC 24
Peak memory 1155836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358175108 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_and_output.358175108 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/1.kmac_sec_cm.3661554004
Short name T6
Test name
Test status
Simulation time 22474254183 ps
CPU time 50.94 seconds
Started Sep 18 08:00:16 PM UTC 24
Finished Sep 18 08:01:09 PM UTC 24
Peak memory 272388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661554004 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.3661554004 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/1.kmac_sideload.2962778798
Short name T36
Test name
Test status
Simulation time 51371230978 ps
CPU time 419.14 seconds
Started Sep 18 08:00:00 PM UTC 24
Finished Sep 18 08:07:12 PM UTC 24
Peak memory 574272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962778798 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.2962778798 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/1.kmac_smoke.601794632
Short name T83
Test name
Test status
Simulation time 5351044378 ps
CPU time 67.54 seconds
Started Sep 18 08:00:00 PM UTC 24
Finished Sep 18 08:01:15 PM UTC 24
Peak memory 234300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601794632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.601794632 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/1.kmac_stress_all.2978607188
Short name T225
Test name
Test status
Simulation time 19926949235 ps
CPU time 607.14 seconds
Started Sep 18 08:00:12 PM UTC 24
Finished Sep 18 08:10:27 PM UTC 24
Peak memory 883488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978607188 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.2978607188 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac.2002546588
Short name T13
Test name
Test status
Simulation time 58282748 ps
CPU time 2.18 seconds
Started Sep 18 08:00:01 PM UTC 24
Finished Sep 18 08:00:09 PM UTC 24
Peak memory 229472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002546588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac.2002546588 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac_xof.3615744446
Short name T15
Test name
Test status
Simulation time 261860961 ps
CPU time 3.79 seconds
Started Sep 18 08:00:02 PM UTC 24
Finished Sep 18 08:00:11 PM UTC 24
Peak memory 229536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615744446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.3615744446 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_224.3133947548
Short name T394
Test name
Test status
Simulation time 34600289687 ps
CPU time 1633.54 seconds
Started Sep 18 08:00:00 PM UTC 24
Finished Sep 18 08:27:37 PM UTC 24
Peak memory 1159836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133947548 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.3133947548
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_256.1025509093
Short name T489
Test name
Test status
Simulation time 237382637023 ps
CPU time 2259.71 seconds
Started Sep 18 08:00:00 PM UTC 24
Finished Sep 18 08:38:14 PM UTC 24
Peak memory 3074664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025509093 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.1025509093
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_384.3748315502
Short name T305
Test name
Test status
Simulation time 52842755818 ps
CPU time 1109.2 seconds
Started Sep 18 08:00:00 PM UTC 24
Finished Sep 18 08:18:47 PM UTC 24
Peak memory 907932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748315502 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.3748315502
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_512.1950400891
Short name T324
Test name
Test status
Simulation time 97196284301 ps
CPU time 1239.04 seconds
Started Sep 18 08:00:00 PM UTC 24
Finished Sep 18 08:21:00 PM UTC 24
Peak memory 1715100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950400891 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.1950400891
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_128.1603738802
Short name T190
Test name
Test status
Simulation time 52480032358 ps
CPU time 223.86 seconds
Started Sep 18 08:00:01 PM UTC 24
Finished Sep 18 08:03:53 PM UTC 24
Peak memory 279284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603738802 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.1603738
802 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_256.2088401340
Short name T91
Test name
Test status
Simulation time 2418668886 ps
CPU time 122.27 seconds
Started Sep 18 08:00:01 PM UTC 24
Finished Sep 18 08:02:11 PM UTC 24
Peak memory 262896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088401340 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.2088401
340 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/10.kmac_alert_test.93244022
Short name T247
Test name
Test status
Simulation time 13221201 ps
CPU time 1.22 seconds
Started Sep 18 08:12:23 PM UTC 24
Finished Sep 18 08:12:25 PM UTC 24
Peak memory 216452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93244022 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.93244022 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/10.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/10.kmac_app.1347951590
Short name T243
Test name
Test status
Simulation time 1772665451 ps
CPU time 19.48 seconds
Started Sep 18 08:11:57 PM UTC 24
Finished Sep 18 08:12:18 PM UTC 24
Peak memory 234160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347951590 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.1347951590 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/10.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/10.kmac_burst_write.3376327085
Short name T51
Test name
Test status
Simulation time 5036369064 ps
CPU time 262.58 seconds
Started Sep 18 08:11:57 PM UTC 24
Finished Sep 18 08:16:24 PM UTC 24
Peak memory 238648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376327085 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.3376327085 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/10.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/10.kmac_edn_timeout_error.1096481247
Short name T248
Test name
Test status
Simulation time 1032111599 ps
CPU time 25.39 seconds
Started Sep 18 08:12:12 PM UTC 24
Finished Sep 18 08:12:38 PM UTC 24
Peak memory 246184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096481247 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.1096481247 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/10.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/10.kmac_entropy_mode_error.67160420
Short name T210
Test name
Test status
Simulation time 8803934001 ps
CPU time 47.39 seconds
Started Sep 18 08:12:19 PM UTC 24
Finished Sep 18 08:13:08 PM UTC 24
Peak memory 234144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67160420 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.67160420 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/10.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/10.kmac_entropy_refresh.2529214605
Short name T274
Test name
Test status
Simulation time 13294815422 ps
CPU time 199.04 seconds
Started Sep 18 08:11:58 PM UTC 24
Finished Sep 18 08:15:20 PM UTC 24
Peak memory 310040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529214605 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.2529214605 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/10.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/10.kmac_error.2373122758
Short name T268
Test name
Test status
Simulation time 24089193562 ps
CPU time 145.88 seconds
Started Sep 18 08:11:59 PM UTC 24
Finished Sep 18 08:14:28 PM UTC 24
Peak memory 363580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373122758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.2373122758 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/10.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/10.kmac_key_error.229092358
Short name T245
Test name
Test status
Simulation time 1069158210 ps
CPU time 10.96 seconds
Started Sep 18 08:12:06 PM UTC 24
Finished Sep 18 08:12:19 PM UTC 24
Peak memory 227280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229092358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.229092358 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/10.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/10.kmac_lc_escalation.3851161544
Short name T246
Test name
Test status
Simulation time 65510686 ps
CPU time 1.99 seconds
Started Sep 18 08:12:19 PM UTC 24
Finished Sep 18 08:12:22 PM UTC 24
Peak memory 226388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851161544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.3851161544 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/10.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/10.kmac_long_msg_and_output.4235541140
Short name T286
Test name
Test status
Simulation time 7722148952 ps
CPU time 277.65 seconds
Started Sep 18 08:11:55 PM UTC 24
Finished Sep 18 08:16:37 PM UTC 24
Peak memory 586548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235541140 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_and_output.4235541140 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/10.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/10.kmac_sideload.2442472959
Short name T272
Test name
Test status
Simulation time 5248564171 ps
CPU time 194.8 seconds
Started Sep 18 08:11:55 PM UTC 24
Finished Sep 18 08:15:13 PM UTC 24
Peak memory 318308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442472959 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.2442472959 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/10.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/10.kmac_smoke.3095786590
Short name T244
Test name
Test status
Simulation time 582907223 ps
CPU time 23.09 seconds
Started Sep 18 08:11:54 PM UTC 24
Finished Sep 18 08:12:18 PM UTC 24
Peak memory 231860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095786590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.3095786590 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/10.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/11.kmac_alert_test.2465182327
Short name T255
Test name
Test status
Simulation time 49654350 ps
CPU time 1.23 seconds
Started Sep 18 08:13:28 PM UTC 24
Finished Sep 18 08:13:30 PM UTC 24
Peak memory 216388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465182327 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.2465182327 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/11.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/11.kmac_app.1422071988
Short name T279
Test name
Test status
Simulation time 28604779236 ps
CPU time 162.04 seconds
Started Sep 18 08:12:57 PM UTC 24
Finished Sep 18 08:15:43 PM UTC 24
Peak memory 353324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422071988 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.1422071988 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/11.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/11.kmac_burst_write.2076012464
Short name T52
Test name
Test status
Simulation time 6003737944 ps
CPU time 328.98 seconds
Started Sep 18 08:12:56 PM UTC 24
Finished Sep 18 08:18:30 PM UTC 24
Peak memory 238388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076012464 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.2076012464 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/11.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/11.kmac_edn_timeout_error.505936068
Short name T258
Test name
Test status
Simulation time 823968516 ps
CPU time 34.94 seconds
Started Sep 18 08:13:09 PM UTC 24
Finished Sep 18 08:13:45 PM UTC 24
Peak memory 233896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505936068 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.505936068 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/11.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/11.kmac_entropy_mode_error.3936901515
Short name T254
Test name
Test status
Simulation time 11485726981 ps
CPU time 15.89 seconds
Started Sep 18 08:13:10 PM UTC 24
Finished Sep 18 08:13:27 PM UTC 24
Peak memory 233508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936901515 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.3936901515 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/11.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/11.kmac_entropy_refresh.2979122305
Short name T304
Test name
Test status
Simulation time 72396399963 ps
CPU time 336.81 seconds
Started Sep 18 08:12:59 PM UTC 24
Finished Sep 18 08:18:41 PM UTC 24
Peak memory 480052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979122305 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.2979122305 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/11.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/11.kmac_error.2042140475
Short name T256
Test name
Test status
Simulation time 8516487453 ps
CPU time 35.52 seconds
Started Sep 18 08:13:00 PM UTC 24
Finished Sep 18 08:13:37 PM UTC 24
Peak memory 267068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042140475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.2042140475 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/11.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/11.kmac_key_error.1019891118
Short name T252
Test name
Test status
Simulation time 987713728 ps
CPU time 3.73 seconds
Started Sep 18 08:13:05 PM UTC 24
Finished Sep 18 08:13:09 PM UTC 24
Peak memory 227304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019891118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.1019891118 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/11.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/11.kmac_lc_escalation.1361485209
Short name T64
Test name
Test status
Simulation time 1174039501 ps
CPU time 9.64 seconds
Started Sep 18 08:13:14 PM UTC 24
Finished Sep 18 08:13:25 PM UTC 24
Peak memory 244508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361485209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.1361485209 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/11.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/11.kmac_long_msg_and_output.1071469354
Short name T483
Test name
Test status
Simulation time 39658076547 ps
CPU time 1477.76 seconds
Started Sep 18 08:12:39 PM UTC 24
Finished Sep 18 08:37:35 PM UTC 24
Peak memory 2095932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071469354 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_and_output.1071469354 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/11.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/11.kmac_sideload.1410380357
Short name T270
Test name
Test status
Simulation time 4945617208 ps
CPU time 116.07 seconds
Started Sep 18 08:12:42 PM UTC 24
Finished Sep 18 08:14:41 PM UTC 24
Peak memory 275180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410380357 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.1410380357 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/11.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/11.kmac_smoke.577116194
Short name T251
Test name
Test status
Simulation time 5774491042 ps
CPU time 36.66 seconds
Started Sep 18 08:12:26 PM UTC 24
Finished Sep 18 08:13:04 PM UTC 24
Peak memory 233808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577116194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.577116194 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/11.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/11.kmac_stress_all.1392938875
Short name T695
Test name
Test status
Simulation time 77625403304 ps
CPU time 2933.2 seconds
Started Sep 18 08:13:26 PM UTC 24
Finished Sep 18 09:02:53 PM UTC 24
Peak memory 2610432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392938875 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.1392938875 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/11.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/12.kmac_alert_test.2270063026
Short name T267
Test name
Test status
Simulation time 73248707 ps
CPU time 1.34 seconds
Started Sep 18 08:14:17 PM UTC 24
Finished Sep 18 08:14:20 PM UTC 24
Peak memory 216388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270063026 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.2270063026 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/12.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/12.kmac_app.2581380153
Short name T291
Test name
Test status
Simulation time 6602938808 ps
CPU time 200.09 seconds
Started Sep 18 08:13:46 PM UTC 24
Finished Sep 18 08:17:10 PM UTC 24
Peak memory 301808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581380153 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.2581380153 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/12.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/12.kmac_burst_write.1193476576
Short name T362
Test name
Test status
Simulation time 6986107341 ps
CPU time 614.96 seconds
Started Sep 18 08:13:38 PM UTC 24
Finished Sep 18 08:24:01 PM UTC 24
Peak memory 248668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193476576 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.1193476576 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/12.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/12.kmac_edn_timeout_error.2852047510
Short name T266
Test name
Test status
Simulation time 1257262398 ps
CPU time 15.54 seconds
Started Sep 18 08:14:00 PM UTC 24
Finished Sep 18 08:14:16 PM UTC 24
Peak memory 233900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852047510 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.2852047510 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/12.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/12.kmac_entropy_mode_error.2498086187
Short name T269
Test name
Test status
Simulation time 824064789 ps
CPU time 21.18 seconds
Started Sep 18 08:14:11 PM UTC 24
Finished Sep 18 08:14:33 PM UTC 24
Peak memory 233936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498086187 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.2498086187 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/12.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/12.kmac_entropy_refresh.704408053
Short name T300
Test name
Test status
Simulation time 35396477499 ps
CPU time 256.71 seconds
Started Sep 18 08:13:50 PM UTC 24
Finished Sep 18 08:18:11 PM UTC 24
Peak memory 390220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704408053 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.704408053 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/12.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/12.kmac_error.3307223735
Short name T277
Test name
Test status
Simulation time 3086909924 ps
CPU time 96.19 seconds
Started Sep 18 08:13:56 PM UTC 24
Finished Sep 18 08:15:34 PM UTC 24
Peak memory 289604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307223735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.3307223735 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/12.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/12.kmac_key_error.3599473711
Short name T263
Test name
Test status
Simulation time 2023976169 ps
CPU time 10.7 seconds
Started Sep 18 08:13:58 PM UTC 24
Finished Sep 18 08:14:10 PM UTC 24
Peak memory 227172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599473711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.3599473711 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/12.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/12.kmac_lc_escalation.179208880
Short name T265
Test name
Test status
Simulation time 150038804 ps
CPU time 2.98 seconds
Started Sep 18 08:14:11 PM UTC 24
Finished Sep 18 08:14:15 PM UTC 24
Peak memory 229556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179208880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.179208880 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/12.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/12.kmac_long_msg_and_output.2194448974
Short name T302
Test name
Test status
Simulation time 10886152523 ps
CPU time 285.51 seconds
Started Sep 18 08:13:35 PM UTC 24
Finished Sep 18 08:18:25 PM UTC 24
Peak memory 386048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194448974 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_and_output.2194448974 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/12.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/12.kmac_sideload.1143877608
Short name T316
Test name
Test status
Simulation time 9332693867 ps
CPU time 362.09 seconds
Started Sep 18 08:13:37 PM UTC 24
Finished Sep 18 08:19:45 PM UTC 24
Peak memory 492340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143877608 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.1143877608 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/12.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/12.kmac_smoke.3422343445
Short name T261
Test name
Test status
Simulation time 709861352 ps
CPU time 24.56 seconds
Started Sep 18 08:13:31 PM UTC 24
Finished Sep 18 08:13:57 PM UTC 24
Peak memory 231536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422343445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.3422343445 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/12.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/12.kmac_stress_all.74683519
Short name T500
Test name
Test status
Simulation time 89050959959 ps
CPU time 1487.59 seconds
Started Sep 18 08:14:16 PM UTC 24
Finished Sep 18 08:39:21 PM UTC 24
Peak memory 1068364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74683519 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.74683519 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/12.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/13.kmac_alert_test.3157484955
Short name T280
Test name
Test status
Simulation time 47558374 ps
CPU time 1.19 seconds
Started Sep 18 08:15:43 PM UTC 24
Finished Sep 18 08:15:45 PM UTC 24
Peak memory 216388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157484955 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.3157484955 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/13.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/13.kmac_app.2431032065
Short name T276
Test name
Test status
Simulation time 10468707466 ps
CPU time 32.84 seconds
Started Sep 18 08:14:59 PM UTC 24
Finished Sep 18 08:15:33 PM UTC 24
Peak memory 240792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431032065 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.2431032065 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/13.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/13.kmac_burst_write.3287833933
Short name T387
Test name
Test status
Simulation time 24398229135 ps
CPU time 716.81 seconds
Started Sep 18 08:14:41 PM UTC 24
Finished Sep 18 08:26:47 PM UTC 24
Peak memory 258868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287833933 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.3287833933 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/13.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/13.kmac_edn_timeout_error.1621734102
Short name T278
Test name
Test status
Simulation time 182259534 ps
CPU time 9.2 seconds
Started Sep 18 08:15:25 PM UTC 24
Finished Sep 18 08:15:35 PM UTC 24
Peak memory 231324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621734102 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.1621734102 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/13.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/13.kmac_entropy_mode_error.3763586703
Short name T284
Test name
Test status
Simulation time 14335700583 ps
CPU time 51.85 seconds
Started Sep 18 08:15:34 PM UTC 24
Finished Sep 18 08:16:27 PM UTC 24
Peak memory 234000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763586703 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.3763586703 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/13.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/13.kmac_entropy_refresh.2536416084
Short name T313
Test name
Test status
Simulation time 43202068148 ps
CPU time 221 seconds
Started Sep 18 08:15:14 PM UTC 24
Finished Sep 18 08:18:58 PM UTC 24
Peak memory 402164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536416084 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.2536416084 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/13.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/13.kmac_error.4062211096
Short name T288
Test name
Test status
Simulation time 26855106914 ps
CPU time 97.91 seconds
Started Sep 18 08:15:18 PM UTC 24
Finished Sep 18 08:16:58 PM UTC 24
Peak memory 310048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062211096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.4062211096 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/13.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/13.kmac_key_error.96854784
Short name T275
Test name
Test status
Simulation time 153799412 ps
CPU time 2.56 seconds
Started Sep 18 08:15:21 PM UTC 24
Finished Sep 18 08:15:24 PM UTC 24
Peak memory 226964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96854784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.96854784 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/13.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/13.kmac_lc_escalation.3945784184
Short name T8
Test name
Test status
Simulation time 872650517 ps
CPU time 41.17 seconds
Started Sep 18 08:15:35 PM UTC 24
Finished Sep 18 08:16:18 PM UTC 24
Peak memory 250556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945784184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.3945784184 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/13.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/13.kmac_long_msg_and_output.714407762
Short name T440
Test name
Test status
Simulation time 267911735251 ps
CPU time 1069.54 seconds
Started Sep 18 08:14:28 PM UTC 24
Finished Sep 18 08:32:31 PM UTC 24
Peak memory 1510196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714407762 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_and_output.714407762 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/13.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/13.kmac_sideload.502974147
Short name T335
Test name
Test status
Simulation time 33061294749 ps
CPU time 434.63 seconds
Started Sep 18 08:14:34 PM UTC 24
Finished Sep 18 08:21:55 PM UTC 24
Peak memory 621364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502974147 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.502974147 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/13.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/13.kmac_smoke.2727812318
Short name T273
Test name
Test status
Simulation time 3653207068 ps
CPU time 54.02 seconds
Started Sep 18 08:14:21 PM UTC 24
Finished Sep 18 08:15:17 PM UTC 24
Peak memory 234240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727812318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.2727812318 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/13.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/13.kmac_stress_all.1103335251
Short name T441
Test name
Test status
Simulation time 60735112735 ps
CPU time 1011.15 seconds
Started Sep 18 08:15:36 PM UTC 24
Finished Sep 18 08:32:39 PM UTC 24
Peak memory 691320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103335251 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.1103335251 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/13.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/14.kmac_alert_test.1561215523
Short name T289
Test name
Test status
Simulation time 16024347 ps
CPU time 1.24 seconds
Started Sep 18 08:16:58 PM UTC 24
Finished Sep 18 08:17:01 PM UTC 24
Peak memory 216388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561215523 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.1561215523 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/14.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/14.kmac_app.2391889219
Short name T311
Test name
Test status
Simulation time 10686248439 ps
CPU time 155.6 seconds
Started Sep 18 08:16:19 PM UTC 24
Finished Sep 18 08:18:57 PM UTC 24
Peak memory 340784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391889219 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.2391889219 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/14.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/14.kmac_burst_write.987181601
Short name T349
Test name
Test status
Simulation time 14299755077 ps
CPU time 403.88 seconds
Started Sep 18 08:16:10 PM UTC 24
Finished Sep 18 08:22:59 PM UTC 24
Peak memory 250596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987181601 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.987181601 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/14.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/14.kmac_edn_timeout_error.3577066109
Short name T292
Test name
Test status
Simulation time 656001131 ps
CPU time 41.46 seconds
Started Sep 18 08:16:37 PM UTC 24
Finished Sep 18 08:17:20 PM UTC 24
Peak memory 234152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577066109 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.3577066109 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/14.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/14.kmac_entropy_mode_error.3591718097
Short name T293
Test name
Test status
Simulation time 6020881782 ps
CPU time 51.46 seconds
Started Sep 18 08:16:37 PM UTC 24
Finished Sep 18 08:17:30 PM UTC 24
Peak memory 244204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591718097 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.3591718097 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/14.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/14.kmac_entropy_refresh.2554317011
Short name T290
Test name
Test status
Simulation time 7534420866 ps
CPU time 42.92 seconds
Started Sep 18 08:16:25 PM UTC 24
Finished Sep 18 08:17:10 PM UTC 24
Peak memory 254944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554317011 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.2554317011 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/14.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/14.kmac_error.2132702142
Short name T296
Test name
Test status
Simulation time 2338939961 ps
CPU time 71.28 seconds
Started Sep 18 08:16:26 PM UTC 24
Finished Sep 18 08:17:39 PM UTC 24
Peak memory 297980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132702142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.2132702142 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/14.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/14.kmac_key_error.871044042
Short name T287
Test name
Test status
Simulation time 4831814843 ps
CPU time 10.07 seconds
Started Sep 18 08:16:28 PM UTC 24
Finished Sep 18 08:16:39 PM UTC 24
Peak memory 227564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871044042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.871044042 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/14.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/14.kmac_lc_escalation.3691503067
Short name T70
Test name
Test status
Simulation time 51195700 ps
CPU time 2 seconds
Started Sep 18 08:16:40 PM UTC 24
Finished Sep 18 08:16:43 PM UTC 24
Peak memory 226384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691503067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.3691503067 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/14.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/14.kmac_long_msg_and_output.435101237
Short name T535
Test name
Test status
Simulation time 304858511210 ps
CPU time 1570.28 seconds
Started Sep 18 08:15:49 PM UTC 24
Finished Sep 18 08:42:17 PM UTC 24
Peak memory 2079672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435101237 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_and_output.435101237 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/14.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/14.kmac_sideload.1283720344
Short name T351
Test name
Test status
Simulation time 16141322893 ps
CPU time 417 seconds
Started Sep 18 08:16:05 PM UTC 24
Finished Sep 18 08:23:07 PM UTC 24
Peak memory 561972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283720344 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.1283720344 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/14.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/14.kmac_smoke.2578001249
Short name T283
Test name
Test status
Simulation time 2900350223 ps
CPU time 21.26 seconds
Started Sep 18 08:15:46 PM UTC 24
Finished Sep 18 08:16:09 PM UTC 24
Peak memory 233976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578001249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.2578001249 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/14.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/14.kmac_stress_all.4067036873
Short name T384
Test name
Test status
Simulation time 6768235656 ps
CPU time 563.33 seconds
Started Sep 18 08:16:44 PM UTC 24
Finished Sep 18 08:26:15 PM UTC 24
Peak memory 494820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067036873 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.4067036873 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/14.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/15.kmac_alert_test.4073255950
Short name T298
Test name
Test status
Simulation time 81134433 ps
CPU time 1.35 seconds
Started Sep 18 08:17:50 PM UTC 24
Finished Sep 18 08:17:52 PM UTC 24
Peak memory 216388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073255950 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.4073255950 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/15.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/15.kmac_app.1840617326
Short name T326
Test name
Test status
Simulation time 4199482796 ps
CPU time 244.81 seconds
Started Sep 18 08:17:15 PM UTC 24
Finished Sep 18 08:21:24 PM UTC 24
Peak memory 328628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840617326 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.1840617326 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/15.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/15.kmac_burst_write.100457129
Short name T422
Test name
Test status
Simulation time 26050359343 ps
CPU time 816.82 seconds
Started Sep 18 08:17:11 PM UTC 24
Finished Sep 18 08:30:58 PM UTC 24
Peak memory 262872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100457129 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.100457129 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/15.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/15.kmac_edn_timeout_error.2157872011
Short name T297
Test name
Test status
Simulation time 206232303 ps
CPU time 16.73 seconds
Started Sep 18 08:17:31 PM UTC 24
Finished Sep 18 08:17:49 PM UTC 24
Peak memory 233600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157872011 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.2157872011 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/15.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/15.kmac_entropy_mode_error.1720115687
Short name T299
Test name
Test status
Simulation time 779002754 ps
CPU time 18.06 seconds
Started Sep 18 08:17:38 PM UTC 24
Finished Sep 18 08:17:58 PM UTC 24
Peak memory 231308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720115687 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.1720115687 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/15.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/15.kmac_entropy_refresh.3850650069
Short name T310
Test name
Test status
Simulation time 15169733994 ps
CPU time 92.04 seconds
Started Sep 18 08:17:21 PM UTC 24
Finished Sep 18 08:18:55 PM UTC 24
Peak memory 271076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850650069 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.3850650069 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/15.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/15.kmac_error.3993937125
Short name T339
Test name
Test status
Simulation time 13297154546 ps
CPU time 295.29 seconds
Started Sep 18 08:17:23 PM UTC 24
Finished Sep 18 08:22:23 PM UTC 24
Peak memory 342880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993937125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.3993937125 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/15.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/15.kmac_key_error.3948857231
Short name T295
Test name
Test status
Simulation time 2355640118 ps
CPU time 5.71 seconds
Started Sep 18 08:17:31 PM UTC 24
Finished Sep 18 08:17:38 PM UTC 24
Peak memory 227332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948857231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.3948857231 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/15.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/15.kmac_lc_escalation.1599187051
Short name T65
Test name
Test status
Simulation time 711389337 ps
CPU time 6.82 seconds
Started Sep 18 08:17:40 PM UTC 24
Finished Sep 18 08:17:48 PM UTC 24
Peak memory 233968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599187051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.1599187051 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/15.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/15.kmac_long_msg_and_output.1595975685
Short name T397
Test name
Test status
Simulation time 6938956955 ps
CPU time 640.74 seconds
Started Sep 18 08:17:08 PM UTC 24
Finished Sep 18 08:27:57 PM UTC 24
Peak memory 658228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595975685 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_and_output.1595975685 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/15.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/15.kmac_sideload.3936788546
Short name T367
Test name
Test status
Simulation time 18452878378 ps
CPU time 437.98 seconds
Started Sep 18 08:17:11 PM UTC 24
Finished Sep 18 08:24:35 PM UTC 24
Peak memory 598764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936788546 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.3936788546 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/15.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/15.kmac_smoke.2002128451
Short name T294
Test name
Test status
Simulation time 2185947204 ps
CPU time 27.67 seconds
Started Sep 18 08:17:02 PM UTC 24
Finished Sep 18 08:17:31 PM UTC 24
Peak memory 231732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002128451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.2002128451 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/15.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/15.kmac_stress_all.458426268
Short name T177
Test name
Test status
Simulation time 3205274711 ps
CPU time 183.83 seconds
Started Sep 18 08:17:50 PM UTC 24
Finished Sep 18 08:20:56 PM UTC 24
Peak memory 273268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458426268 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.458426268 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/15.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/16.kmac_alert_test.2031178652
Short name T312
Test name
Test status
Simulation time 30208315 ps
CPU time 1.25 seconds
Started Sep 18 08:18:56 PM UTC 24
Finished Sep 18 08:18:58 PM UTC 24
Peak memory 216316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031178652 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.2031178652 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/16.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/16.kmac_app.3921252
Short name T325
Test name
Test status
Simulation time 4620263682 ps
CPU time 152.14 seconds
Started Sep 18 08:18:26 PM UTC 24
Finished Sep 18 08:21:01 PM UTC 24
Peak memory 324420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921252 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.3921252 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/16.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/16.kmac_burst_write.729382455
Short name T399
Test name
Test status
Simulation time 16381741742 ps
CPU time 582.39 seconds
Started Sep 18 08:18:13 PM UTC 24
Finished Sep 18 08:28:03 PM UTC 24
Peak memory 254820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729382455 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.729382455 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/16.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/16.kmac_edn_timeout_error.4236220158
Short name T314
Test name
Test status
Simulation time 1325953691 ps
CPU time 9.69 seconds
Started Sep 18 08:18:48 PM UTC 24
Finished Sep 18 08:18:59 PM UTC 24
Peak memory 233864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236220158 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.4236220158 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/16.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/16.kmac_entropy_mode_error.3857086303
Short name T315
Test name
Test status
Simulation time 1893196822 ps
CPU time 19.02 seconds
Started Sep 18 08:18:51 PM UTC 24
Finished Sep 18 08:19:11 PM UTC 24
Peak memory 233416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857086303 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.3857086303 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/16.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/16.kmac_entropy_refresh.2796166907
Short name T358
Test name
Test status
Simulation time 15510407179 ps
CPU time 296.15 seconds
Started Sep 18 08:18:27 PM UTC 24
Finished Sep 18 08:23:27 PM UTC 24
Peak memory 486520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796166907 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.2796166907 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/16.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/16.kmac_error.1680861331
Short name T338
Test name
Test status
Simulation time 5357728962 ps
CPU time 220.69 seconds
Started Sep 18 08:18:31 PM UTC 24
Finished Sep 18 08:22:16 PM UTC 24
Peak memory 326496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680861331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.1680861331 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/16.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/16.kmac_key_error.1061570104
Short name T308
Test name
Test status
Simulation time 1988792743 ps
CPU time 7.76 seconds
Started Sep 18 08:18:42 PM UTC 24
Finished Sep 18 08:18:51 PM UTC 24
Peak memory 227176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061570104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.1061570104 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/16.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/16.kmac_lc_escalation.1632082194
Short name T309
Test name
Test status
Simulation time 40790118 ps
CPU time 2.07 seconds
Started Sep 18 08:18:52 PM UTC 24
Finished Sep 18 08:18:55 PM UTC 24
Peak memory 227300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632082194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.1632082194 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/16.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/16.kmac_long_msg_and_output.4082597599
Short name T632
Test name
Test status
Simulation time 331361543374 ps
CPU time 2069.5 seconds
Started Sep 18 08:17:59 PM UTC 24
Finished Sep 18 08:52:53 PM UTC 24
Peak memory 2607900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082597599 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_and_output.4082597599 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/16.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/16.kmac_sideload.4241826107
Short name T354
Test name
Test status
Simulation time 22220259192 ps
CPU time 296.6 seconds
Started Sep 18 08:18:12 PM UTC 24
Finished Sep 18 08:23:13 PM UTC 24
Peak memory 361504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241826107 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.4241826107 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/16.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/16.kmac_smoke.1123268028
Short name T307
Test name
Test status
Simulation time 16109502127 ps
CPU time 56.61 seconds
Started Sep 18 08:17:53 PM UTC 24
Finished Sep 18 08:18:51 PM UTC 24
Peak memory 234296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123268028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.1123268028 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/16.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/16.kmac_stress_all.492108402
Short name T577
Test name
Test status
Simulation time 90404616631 ps
CPU time 1688.35 seconds
Started Sep 18 08:18:52 PM UTC 24
Finished Sep 18 08:47:20 PM UTC 24
Peak memory 889592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492108402 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.492108402 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/16.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/17.kmac_alert_test.830300580
Short name T321
Test name
Test status
Simulation time 29214534 ps
CPU time 1.23 seconds
Started Sep 18 08:20:29 PM UTC 24
Finished Sep 18 08:20:31 PM UTC 24
Peak memory 216508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830300580 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.830300580 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/17.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/17.kmac_app.1789299512
Short name T157
Test name
Test status
Simulation time 9055116539 ps
CPU time 179.54 seconds
Started Sep 18 08:19:00 PM UTC 24
Finished Sep 18 08:22:03 PM UTC 24
Peak memory 398120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789299512 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.1789299512 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/17.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/17.kmac_burst_write.584593483
Short name T329
Test name
Test status
Simulation time 6073681202 ps
CPU time 147.15 seconds
Started Sep 18 08:18:59 PM UTC 24
Finished Sep 18 08:21:29 PM UTC 24
Peak memory 234296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584593483 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.584593483 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/17.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/17.kmac_edn_timeout_error.3004103843
Short name T320
Test name
Test status
Simulation time 4904584492 ps
CPU time 17.78 seconds
Started Sep 18 08:20:09 PM UTC 24
Finished Sep 18 08:20:28 PM UTC 24
Peak memory 233504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004103843 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.3004103843 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/17.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/17.kmac_entropy_mode_error.4089133886
Short name T323
Test name
Test status
Simulation time 1714735543 ps
CPU time 41.48 seconds
Started Sep 18 08:20:12 PM UTC 24
Finished Sep 18 08:20:55 PM UTC 24
Peak memory 233940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089133886 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.4089133886 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/17.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/17.kmac_entropy_refresh.3975232187
Short name T322
Test name
Test status
Simulation time 4749349854 ps
CPU time 83.69 seconds
Started Sep 18 08:19:12 PM UTC 24
Finished Sep 18 08:20:38 PM UTC 24
Peak memory 277272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975232187 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.3975232187 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/17.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/17.kmac_error.2095174222
Short name T318
Test name
Test status
Simulation time 956176203 ps
CPU time 20.44 seconds
Started Sep 18 08:19:45 PM UTC 24
Finished Sep 18 08:20:07 PM UTC 24
Peak memory 246500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095174222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.2095174222 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/17.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/17.kmac_lc_escalation.3912726163
Short name T9
Test name
Test status
Simulation time 91086280 ps
CPU time 1.84 seconds
Started Sep 18 08:20:13 PM UTC 24
Finished Sep 18 08:20:16 PM UTC 24
Peak memory 226388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912726163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.3912726163 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/17.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/17.kmac_long_msg_and_output.1179453403
Short name T480
Test name
Test status
Simulation time 11157782181 ps
CPU time 1070.62 seconds
Started Sep 18 08:18:58 PM UTC 24
Finished Sep 18 08:37:02 PM UTC 24
Peak memory 879420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179453403 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_and_output.1179453403 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/17.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/17.kmac_sideload.2132216901
Short name T328
Test name
Test status
Simulation time 1914942832 ps
CPU time 146.34 seconds
Started Sep 18 08:18:59 PM UTC 24
Finished Sep 18 08:21:28 PM UTC 24
Peak memory 289408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132216901 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.2132216901 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/17.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/17.kmac_smoke.2374988552
Short name T317
Test name
Test status
Simulation time 15669330567 ps
CPU time 60.58 seconds
Started Sep 18 08:18:56 PM UTC 24
Finished Sep 18 08:19:58 PM UTC 24
Peak memory 234060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374988552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.2374988552 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/17.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/17.kmac_stress_all.3087930905
Short name T346
Test name
Test status
Simulation time 25761604818 ps
CPU time 152.96 seconds
Started Sep 18 08:20:17 PM UTC 24
Finished Sep 18 08:22:53 PM UTC 24
Peak memory 328536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087930905 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.3087930905 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/17.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/18.kmac_alert_test.1543401817
Short name T333
Test name
Test status
Simulation time 110711784 ps
CPU time 1.29 seconds
Started Sep 18 08:21:32 PM UTC 24
Finished Sep 18 08:21:35 PM UTC 24
Peak memory 216388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543401817 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.1543401817 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/18.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/18.kmac_app.1767298552
Short name T347
Test name
Test status
Simulation time 2236328375 ps
CPU time 110.63 seconds
Started Sep 18 08:21:00 PM UTC 24
Finished Sep 18 08:22:53 PM UTC 24
Peak memory 271092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767298552 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.1767298552 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/18.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/18.kmac_burst_write.3819025494
Short name T416
Test name
Test status
Simulation time 33038837058 ps
CPU time 575.4 seconds
Started Sep 18 08:20:57 PM UTC 24
Finished Sep 18 08:30:40 PM UTC 24
Peak memory 254688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819025494 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.3819025494 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/18.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/18.kmac_edn_timeout_error.2978619301
Short name T334
Test name
Test status
Simulation time 1001341447 ps
CPU time 26.16 seconds
Started Sep 18 08:21:27 PM UTC 24
Finished Sep 18 08:21:54 PM UTC 24
Peak memory 234192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978619301 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.2978619301 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/18.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/18.kmac_entropy_mode_error.2877474960
Short name T337
Test name
Test status
Simulation time 4290623970 ps
CPU time 31.9 seconds
Started Sep 18 08:21:29 PM UTC 24
Finished Sep 18 08:22:03 PM UTC 24
Peak memory 233964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877474960 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.2877474960 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/18.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/18.kmac_entropy_refresh.1056473727
Short name T378
Test name
Test status
Simulation time 26526337773 ps
CPU time 276.14 seconds
Started Sep 18 08:21:02 PM UTC 24
Finished Sep 18 08:25:42 PM UTC 24
Peak memory 328760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056473727 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.1056473727 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/18.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/18.kmac_error.2982622284
Short name T342
Test name
Test status
Simulation time 901286911 ps
CPU time 75.28 seconds
Started Sep 18 08:21:19 PM UTC 24
Finished Sep 18 08:22:36 PM UTC 24
Peak memory 277112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982622284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.2982622284 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/18.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/18.kmac_key_error.2360837604
Short name T331
Test name
Test status
Simulation time 757062782 ps
CPU time 5.01 seconds
Started Sep 18 08:21:25 PM UTC 24
Finished Sep 18 08:21:31 PM UTC 24
Peak memory 227232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360837604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.2360837604 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/18.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/18.kmac_lc_escalation.2062731363
Short name T332
Test name
Test status
Simulation time 124692778 ps
CPU time 2.4 seconds
Started Sep 18 08:21:30 PM UTC 24
Finished Sep 18 08:21:34 PM UTC 24
Peak memory 227356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062731363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.2062731363 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/18.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/18.kmac_long_msg_and_output.3258903923
Short name T569
Test name
Test status
Simulation time 15060413050 ps
CPU time 1546.09 seconds
Started Sep 18 08:20:39 PM UTC 24
Finished Sep 18 08:46:44 PM UTC 24
Peak memory 1207096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258903923 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_and_output.3258903923 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/18.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/18.kmac_sideload.631610798
Short name T383
Test name
Test status
Simulation time 13944965069 ps
CPU time 304.14 seconds
Started Sep 18 08:20:55 PM UTC 24
Finished Sep 18 08:26:04 PM UTC 24
Peak memory 352992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631610798 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.631610798 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/18.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/18.kmac_smoke.2177534453
Short name T327
Test name
Test status
Simulation time 3160623196 ps
CPU time 52.7 seconds
Started Sep 18 08:20:32 PM UTC 24
Finished Sep 18 08:21:26 PM UTC 24
Peak memory 233712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177534453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.2177534453 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/18.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/18.kmac_stress_all.1314344513
Short name T593
Test name
Test status
Simulation time 74558612186 ps
CPU time 1630.01 seconds
Started Sep 18 08:21:31 PM UTC 24
Finished Sep 18 08:49:01 PM UTC 24
Peak memory 697436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314344513 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.1314344513 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/18.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/19.kmac_alert_test.89797936
Short name T343
Test name
Test status
Simulation time 16092294 ps
CPU time 1.25 seconds
Started Sep 18 08:22:37 PM UTC 24
Finished Sep 18 08:22:40 PM UTC 24
Peak memory 216452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89797936 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.89797936 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/19.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/19.kmac_app.2622160302
Short name T388
Test name
Test status
Simulation time 11089521532 ps
CPU time 290.96 seconds
Started Sep 18 08:21:59 PM UTC 24
Finished Sep 18 08:26:54 PM UTC 24
Peak memory 426764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622160302 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.2622160302 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/19.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/19.kmac_burst_write.1005100881
Short name T435
Test name
Test status
Simulation time 58311539423 ps
CPU time 591.8 seconds
Started Sep 18 08:21:55 PM UTC 24
Finished Sep 18 08:31:55 PM UTC 24
Peak memory 246524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005100881 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.1005100881 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/19.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/19.kmac_edn_timeout_error.3181889142
Short name T352
Test name
Test status
Simulation time 5433315180 ps
CPU time 30.51 seconds
Started Sep 18 08:22:36 PM UTC 24
Finished Sep 18 08:23:08 PM UTC 24
Peak memory 234284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181889142 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.3181889142 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/19.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/19.kmac_entropy_mode_error.1196624030
Short name T348
Test name
Test status
Simulation time 11462750639 ps
CPU time 18.91 seconds
Started Sep 18 08:22:36 PM UTC 24
Finished Sep 18 08:22:56 PM UTC 24
Peak memory 233964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196624030 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.1196624030 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/19.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/19.kmac_entropy_refresh.452592670
Short name T369
Test name
Test status
Simulation time 20209613693 ps
CPU time 152.24 seconds
Started Sep 18 08:22:04 PM UTC 24
Finished Sep 18 08:24:39 PM UTC 24
Peak memory 291452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452592670 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.452592670 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/19.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/19.kmac_error.728686893
Short name T375
Test name
Test status
Simulation time 2601953826 ps
CPU time 176.09 seconds
Started Sep 18 08:22:04 PM UTC 24
Finished Sep 18 08:25:03 PM UTC 24
Peak memory 326180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728686893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.728686893 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/19.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/19.kmac_key_error.681938795
Short name T340
Test name
Test status
Simulation time 975845202 ps
CPU time 9.98 seconds
Started Sep 18 08:22:17 PM UTC 24
Finished Sep 18 08:22:28 PM UTC 24
Peak memory 227436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681938795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.681938795 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/19.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/19.kmac_lc_escalation.1485398102
Short name T344
Test name
Test status
Simulation time 36517211 ps
CPU time 1.89 seconds
Started Sep 18 08:22:37 PM UTC 24
Finished Sep 18 08:22:40 PM UTC 24
Peak memory 226388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485398102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.1485398102 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/19.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/19.kmac_long_msg_and_output.2956242626
Short name T675
Test name
Test status
Simulation time 50577432247 ps
CPU time 2086.17 seconds
Started Sep 18 08:21:35 PM UTC 24
Finished Sep 18 08:56:48 PM UTC 24
Peak memory 2605916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956242626 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_and_output.2956242626 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/19.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/19.kmac_sideload.331758957
Short name T345
Test name
Test status
Simulation time 2674651277 ps
CPU time 50.02 seconds
Started Sep 18 08:21:55 PM UTC 24
Finished Sep 18 08:22:47 PM UTC 24
Peak memory 250672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331758957 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.331758957 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/19.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/19.kmac_smoke.333417679
Short name T341
Test name
Test status
Simulation time 980781826 ps
CPU time 59.07 seconds
Started Sep 18 08:21:34 PM UTC 24
Finished Sep 18 08:22:36 PM UTC 24
Peak memory 233940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333417679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.333417679 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/19.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/19.kmac_stress_all.3127288085
Short name T490
Test name
Test status
Simulation time 12569506946 ps
CPU time 926.22 seconds
Started Sep 18 08:22:37 PM UTC 24
Finished Sep 18 08:38:14 PM UTC 24
Peak memory 496756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127288085 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.3127288085 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/19.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/2.kmac_alert_test.2027599265
Short name T58
Test name
Test status
Simulation time 29611636 ps
CPU time 1.25 seconds
Started Sep 18 08:01:31 PM UTC 24
Finished Sep 18 08:01:33 PM UTC 24
Peak memory 216508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027599265 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.2027599265 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/2.kmac_app.2427319835
Short name T117
Test name
Test status
Simulation time 19698442631 ps
CPU time 308.62 seconds
Started Sep 18 08:01:10 PM UTC 24
Finished Sep 18 08:06:23 PM UTC 24
Peak memory 492468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427319835 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.2427319835 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/2.kmac_app_with_partial_data.4099959362
Short name T62
Test name
Test status
Simulation time 1638250750 ps
CPU time 7.35 seconds
Started Sep 18 08:01:14 PM UTC 24
Finished Sep 18 08:01:22 PM UTC 24
Peak memory 231640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099959362 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.4099959362 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/2.kmac_edn_timeout_error.2867409462
Short name T93
Test name
Test status
Simulation time 1120969814 ps
CPU time 49.96 seconds
Started Sep 18 08:01:27 PM UTC 24
Finished Sep 18 08:02:19 PM UTC 24
Peak memory 233880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867409462 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.2867409462 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_mode_error.3442113302
Short name T97
Test name
Test status
Simulation time 108736793 ps
CPU time 6.05 seconds
Started Sep 18 08:01:27 PM UTC 24
Finished Sep 18 08:01:35 PM UTC 24
Peak memory 229300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442113302 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.3442113302 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_ready_error.3992377720
Short name T47
Test name
Test status
Simulation time 12487250652 ps
CPU time 48.33 seconds
Started Sep 18 08:01:28 PM UTC 24
Finished Sep 18 08:02:18 PM UTC 24
Peak memory 234132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992377720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.3992377720 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/2.kmac_entropy_refresh.1520463006
Short name T57
Test name
Test status
Simulation time 44098833124 ps
CPU time 289.44 seconds
Started Sep 18 08:01:26 PM UTC 24
Finished Sep 18 08:06:20 PM UTC 24
Peak memory 435288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520463006 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.1520463006 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/2.kmac_error.2936744942
Short name T25
Test name
Test status
Simulation time 17709830512 ps
CPU time 258.39 seconds
Started Sep 18 08:01:26 PM UTC 24
Finished Sep 18 08:05:49 PM UTC 24
Peak memory 465912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936744942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.2936744942 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/2.kmac_lc_escalation.1244348460
Short name T45
Test name
Test status
Simulation time 95202482 ps
CPU time 1.73 seconds
Started Sep 18 08:01:28 PM UTC 24
Finished Sep 18 08:01:31 PM UTC 24
Peak memory 226448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244348460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.1244348460 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/2.kmac_long_msg_and_output.855344823
Short name T357
Test name
Test status
Simulation time 43726165109 ps
CPU time 1369.52 seconds
Started Sep 18 08:00:19 PM UTC 24
Finished Sep 18 08:23:25 PM UTC 24
Peak memory 1995612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855344823 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_and_output.855344823 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/2.kmac_mubi.1676547092
Short name T63
Test name
Test status
Simulation time 32529492891 ps
CPU time 189.24 seconds
Started Sep 18 08:01:26 PM UTC 24
Finished Sep 18 08:04:39 PM UTC 24
Peak memory 359532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676547092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.1676547092 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/2.kmac_sec_cm.3734124299
Short name T11
Test name
Test status
Simulation time 9035406095 ps
CPU time 48.29 seconds
Started Sep 18 08:01:30 PM UTC 24
Finished Sep 18 08:02:20 PM UTC 24
Peak memory 278728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734124299 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.3734124299 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/2.kmac_sideload.55565495
Short name T31
Test name
Test status
Simulation time 5735106924 ps
CPU time 236.16 seconds
Started Sep 18 08:00:22 PM UTC 24
Finished Sep 18 08:04:22 PM UTC 24
Peak memory 318304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55565495 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.55565495 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/2.kmac_smoke.42086531
Short name T84
Test name
Test status
Simulation time 958946183 ps
CPU time 59.98 seconds
Started Sep 18 08:00:19 PM UTC 24
Finished Sep 18 08:01:21 PM UTC 24
Peak memory 233620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42086531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.42086531 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/2.kmac_stress_all.4087098194
Short name T621
Test name
Test status
Simulation time 969551736090 ps
CPU time 2949.26 seconds
Started Sep 18 08:01:28 PM UTC 24
Finished Sep 18 08:51:10 PM UTC 24
Peak memory 1401960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087098194 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.4087098194 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/2.kmac_stress_all_with_rand_reset.1137909081
Short name T32
Test name
Test status
Simulation time 3001380451 ps
CPU time 225.84 seconds
Started Sep 18 08:01:28 PM UTC 24
Finished Sep 18 08:05:18 PM UTC 24
Peak memory 294016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres
s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1137909081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all_
with_rand_reset.1137909081 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac.831255829
Short name T81
Test name
Test status
Simulation time 83939561 ps
CPU time 3.61 seconds
Started Sep 18 08:01:09 PM UTC 24
Finished Sep 18 08:01:14 PM UTC 24
Peak memory 229488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831255829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_ve
ctors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac.831255829 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac_xof.2122018099
Short name T80
Test name
Test status
Simulation time 159072803 ps
CPU time 3.34 seconds
Started Sep 18 08:01:10 PM UTC 24
Finished Sep 18 08:01:14 PM UTC 24
Peak memory 229744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122018099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.2122018099 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_224.158945830
Short name T79
Test name
Test status
Simulation time 636528858 ps
CPU time 42.01 seconds
Started Sep 18 08:00:30 PM UTC 24
Finished Sep 18 08:01:13 PM UTC 24
Peak memory 234364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158945830 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.158945830 +
enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_256.4116229485
Short name T411
Test name
Test status
Simulation time 66977274494 ps
CPU time 1723.38 seconds
Started Sep 18 08:00:50 PM UTC 24
Finished Sep 18 08:29:55 PM UTC 24
Peak memory 1133532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116229485 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.4116229485
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_384.1066666793
Short name T85
Test name
Test status
Simulation time 2754843506 ps
CPU time 32.2 seconds
Started Sep 18 08:00:50 PM UTC 24
Finished Sep 18 08:01:24 PM UTC 24
Peak memory 233876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066666793 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.1066666793
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_512.2233033049
Short name T82
Test name
Test status
Simulation time 721691470 ps
CPU time 20.76 seconds
Started Sep 18 08:00:53 PM UTC 24
Finished Sep 18 08:01:15 PM UTC 24
Peak memory 234288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233033049 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.2233033049
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_128.2020003238
Short name T544
Test name
Test status
Simulation time 145386902239 ps
CPU time 2553.55 seconds
Started Sep 18 08:00:53 PM UTC 24
Finished Sep 18 08:43:55 PM UTC 24
Peak memory 3642112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020003238 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.2020003
238 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_256.2821631939
Short name T228
Test name
Test status
Simulation time 93319427207 ps
CPU time 580 seconds
Started Sep 18 08:01:08 PM UTC 24
Finished Sep 18 08:10:57 PM UTC 24
Peak memory 361120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821631939 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.2821631
939 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/20.kmac_alert_test.4206356670
Short name T353
Test name
Test status
Simulation time 215934780 ps
CPU time 1.29 seconds
Started Sep 18 08:23:09 PM UTC 24
Finished Sep 18 08:23:11 PM UTC 24
Peak memory 216388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206356670 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.4206356670 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/20.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/20.kmac_app.2739719754
Short name T415
Test name
Test status
Simulation time 14302519334 ps
CPU time 427.05 seconds
Started Sep 18 08:22:54 PM UTC 24
Finished Sep 18 08:30:06 PM UTC 24
Peak memory 607028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739719754 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.2739719754 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/20.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/20.kmac_burst_write.312818925
Short name T484
Test name
Test status
Simulation time 23814714365 ps
CPU time 886.09 seconds
Started Sep 18 08:22:49 PM UTC 24
Finished Sep 18 08:37:45 PM UTC 24
Peak memory 264960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312818925 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.312818925 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/20.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/20.kmac_entropy_refresh.1094319467
Short name T158
Test name
Test status
Simulation time 16023576530 ps
CPU time 165.35 seconds
Started Sep 18 08:22:55 PM UTC 24
Finished Sep 18 08:25:43 PM UTC 24
Peak memory 285468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094319467 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.1094319467 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/20.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/20.kmac_error.287598062
Short name T356
Test name
Test status
Simulation time 992077961 ps
CPU time 24.71 seconds
Started Sep 18 08:22:57 PM UTC 24
Finished Sep 18 08:23:23 PM UTC 24
Peak memory 244344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287598062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.287598062 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/20.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/20.kmac_key_error.4188256710
Short name T355
Test name
Test status
Simulation time 3995932023 ps
CPU time 19.89 seconds
Started Sep 18 08:23:00 PM UTC 24
Finished Sep 18 08:23:21 PM UTC 24
Peak memory 227620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188256710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.4188256710 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/20.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/20.kmac_long_msg_and_output.2866567262
Short name T669
Test name
Test status
Simulation time 117586999546 ps
CPU time 1986.33 seconds
Started Sep 18 08:22:40 PM UTC 24
Finished Sep 18 08:56:10 PM UTC 24
Peak memory 2491164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866567262 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_and_output.2866567262 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/20.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/20.kmac_sideload.970945548
Short name T386
Test name
Test status
Simulation time 45989165997 ps
CPU time 240.55 seconds
Started Sep 18 08:22:40 PM UTC 24
Finished Sep 18 08:26:45 PM UTC 24
Peak memory 420600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970945548 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.970945548 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/20.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/20.kmac_smoke.3205114981
Short name T350
Test name
Test status
Simulation time 755786555 ps
CPU time 23.29 seconds
Started Sep 18 08:22:37 PM UTC 24
Finished Sep 18 08:23:02 PM UTC 24
Peak memory 231604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205114981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.3205114981 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/20.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/20.kmac_stress_all.3403500856
Short name T513
Test name
Test status
Simulation time 42360963718 ps
CPU time 1042.86 seconds
Started Sep 18 08:23:08 PM UTC 24
Finished Sep 18 08:40:43 PM UTC 24
Peak memory 1283204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403500856 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.3403500856 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/20.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/21.kmac_alert_test.890151794
Short name T363
Test name
Test status
Simulation time 22978501 ps
CPU time 1.19 seconds
Started Sep 18 08:24:02 PM UTC 24
Finished Sep 18 08:24:04 PM UTC 24
Peak memory 216508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890151794 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.890151794 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/21.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/21.kmac_app.374584271
Short name T368
Test name
Test status
Simulation time 2270581369 ps
CPU time 68.42 seconds
Started Sep 18 08:23:25 PM UTC 24
Finished Sep 18 08:24:36 PM UTC 24
Peak memory 273180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374584271 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.374584271 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/21.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/21.kmac_burst_write.85457748
Short name T525
Test name
Test status
Simulation time 109629913797 ps
CPU time 1074.02 seconds
Started Sep 18 08:23:23 PM UTC 24
Finished Sep 18 08:41:31 PM UTC 24
Peak memory 265012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85457748 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.85457748 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/21.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/21.kmac_entropy_refresh.3346803137
Short name T370
Test name
Test status
Simulation time 18444415150 ps
CPU time 76.78 seconds
Started Sep 18 08:23:27 PM UTC 24
Finished Sep 18 08:24:45 PM UTC 24
Peak memory 279612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346803137 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.3346803137 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/21.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/21.kmac_error.3115340538
Short name T412
Test name
Test status
Simulation time 187850450075 ps
CPU time 387.55 seconds
Started Sep 18 08:23:29 PM UTC 24
Finished Sep 18 08:30:02 PM UTC 24
Peak memory 592696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115340538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.3115340538 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/21.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/21.kmac_key_error.882422803
Short name T364
Test name
Test status
Simulation time 6530981509 ps
CPU time 18.93 seconds
Started Sep 18 08:23:47 PM UTC 24
Finished Sep 18 08:24:07 PM UTC 24
Peak memory 227408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882422803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.882422803 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/21.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/21.kmac_lc_escalation.706888041
Short name T361
Test name
Test status
Simulation time 160599772 ps
CPU time 2.34 seconds
Started Sep 18 08:23:54 PM UTC 24
Finished Sep 18 08:23:57 PM UTC 24
Peak memory 227712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706888041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.706888041 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/21.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/21.kmac_long_msg_and_output.247361995
Short name T438
Test name
Test status
Simulation time 66351701030 ps
CPU time 540.09 seconds
Started Sep 18 08:23:14 PM UTC 24
Finished Sep 18 08:32:21 PM UTC 24
Peak memory 982088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247361995 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_and_output.247361995 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/21.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/21.kmac_sideload.694696846
Short name T398
Test name
Test status
Simulation time 21901119682 ps
CPU time 271.84 seconds
Started Sep 18 08:23:22 PM UTC 24
Finished Sep 18 08:27:59 PM UTC 24
Peak memory 336948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694696846 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.694696846 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/21.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/21.kmac_smoke.811479506
Short name T359
Test name
Test status
Simulation time 490332585 ps
CPU time 32.12 seconds
Started Sep 18 08:23:12 PM UTC 24
Finished Sep 18 08:23:46 PM UTC 24
Peak memory 231892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811479506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.811479506 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/21.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/21.kmac_stress_all.2802771578
Short name T427
Test name
Test status
Simulation time 62363666894 ps
CPU time 427.71 seconds
Started Sep 18 08:23:58 PM UTC 24
Finished Sep 18 08:31:11 PM UTC 24
Peak memory 660220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802771578 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.2802771578 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/21.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/22.kmac_alert_test.3863933018
Short name T372
Test name
Test status
Simulation time 33794967 ps
CPU time 1.16 seconds
Started Sep 18 08:24:49 PM UTC 24
Finished Sep 18 08:24:51 PM UTC 24
Peak memory 216360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863933018 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.3863933018 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/22.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/22.kmac_app.817726369
Short name T373
Test name
Test status
Simulation time 1818469829 ps
CPU time 24.76 seconds
Started Sep 18 08:24:25 PM UTC 24
Finished Sep 18 08:24:51 PM UTC 24
Peak memory 236128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817726369 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.817726369 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/22.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/22.kmac_burst_write.2726683486
Short name T461
Test name
Test status
Simulation time 64605285683 ps
CPU time 600 seconds
Started Sep 18 08:24:19 PM UTC 24
Finished Sep 18 08:34:27 PM UTC 24
Peak memory 254752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726683486 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.2726683486 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/22.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/22.kmac_entropy_refresh.2700210811
Short name T421
Test name
Test status
Simulation time 71684104613 ps
CPU time 376.83 seconds
Started Sep 18 08:24:36 PM UTC 24
Finished Sep 18 08:30:58 PM UTC 24
Peak memory 492256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700210811 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.2700210811 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/22.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/22.kmac_error.3661089580
Short name T396
Test name
Test status
Simulation time 16684871098 ps
CPU time 192.35 seconds
Started Sep 18 08:24:37 PM UTC 24
Finished Sep 18 08:27:52 PM UTC 24
Peak memory 416612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661089580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.3661089580 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/22.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/22.kmac_key_error.2182198213
Short name T371
Test name
Test status
Simulation time 742531405 ps
CPU time 6.7 seconds
Started Sep 18 08:24:40 PM UTC 24
Finished Sep 18 08:24:48 PM UTC 24
Peak memory 227496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182198213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.2182198213 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/22.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/22.kmac_long_msg_and_output.185070998
Short name T716
Test name
Test status
Simulation time 88264573464 ps
CPU time 3572.77 seconds
Started Sep 18 08:24:08 PM UTC 24
Finished Sep 18 09:24:20 PM UTC 24
Peak memory 4186996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185070998 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_and_output.185070998 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/22.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/22.kmac_sideload.2556661358
Short name T408
Test name
Test status
Simulation time 66605405145 ps
CPU time 294.15 seconds
Started Sep 18 08:24:18 PM UTC 24
Finished Sep 18 08:29:17 PM UTC 24
Peak memory 484156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556661358 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.2556661358 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/22.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/22.kmac_smoke.505557158
Short name T366
Test name
Test status
Simulation time 320124824 ps
CPU time 17.85 seconds
Started Sep 18 08:24:05 PM UTC 24
Finished Sep 18 08:24:24 PM UTC 24
Peak memory 229484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505557158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.505557158 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/22.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/22.kmac_stress_all.3229995133
Short name T586
Test name
Test status
Simulation time 77257260613 ps
CPU time 1351.23 seconds
Started Sep 18 08:24:49 PM UTC 24
Finished Sep 18 08:47:36 PM UTC 24
Peak memory 1573912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229995133 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.3229995133 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/22.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/23.kmac_alert_test.3355527409
Short name T382
Test name
Test status
Simulation time 47568387 ps
CPU time 1.38 seconds
Started Sep 18 08:25:51 PM UTC 24
Finished Sep 18 08:25:53 PM UTC 24
Peak memory 216388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355527409 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.3355527409 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/23.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/23.kmac_app.2062213618
Short name T406
Test name
Test status
Simulation time 8515495857 ps
CPU time 240.33 seconds
Started Sep 18 08:25:08 PM UTC 24
Finished Sep 18 08:29:13 PM UTC 24
Peak memory 305936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062213618 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.2062213618 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/23.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/23.kmac_burst_write.4276369164
Short name T178
Test name
Test status
Simulation time 29533332944 ps
CPU time 610.61 seconds
Started Sep 18 08:25:03 PM UTC 24
Finished Sep 18 08:35:23 PM UTC 24
Peak memory 248608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276369164 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.4276369164 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/23.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/23.kmac_entropy_refresh.3158871390
Short name T391
Test name
Test status
Simulation time 2833731597 ps
CPU time 102.39 seconds
Started Sep 18 08:25:28 PM UTC 24
Finished Sep 18 08:27:13 PM UTC 24
Peak memory 265056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158871390 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.3158871390 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/23.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/23.kmac_error.2604909699
Short name T389
Test name
Test status
Simulation time 4576720169 ps
CPU time 79.92 seconds
Started Sep 18 08:25:43 PM UTC 24
Finished Sep 18 08:27:04 PM UTC 24
Peak memory 283444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604909699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.2604909699 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/23.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/23.kmac_key_error.2465893281
Short name T381
Test name
Test status
Simulation time 2176274113 ps
CPU time 5.87 seconds
Started Sep 18 08:25:44 PM UTC 24
Finished Sep 18 08:25:51 PM UTC 24
Peak memory 227396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465893281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.2465893281 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/23.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/23.kmac_lc_escalation.542470984
Short name T380
Test name
Test status
Simulation time 159457491 ps
CPU time 2.16 seconds
Started Sep 18 08:25:46 PM UTC 24
Finished Sep 18 08:25:49 PM UTC 24
Peak memory 227312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542470984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.542470984 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/23.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/23.kmac_long_msg_and_output.2328546644
Short name T704
Test name
Test status
Simulation time 83142801783 ps
CPU time 2505.56 seconds
Started Sep 18 08:24:53 PM UTC 24
Finished Sep 18 09:07:07 PM UTC 24
Peak memory 3027776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328546644 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_and_output.2328546644 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/23.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/23.kmac_sideload.360847103
Short name T376
Test name
Test status
Simulation time 693070318 ps
CPU time 12.93 seconds
Started Sep 18 08:24:53 PM UTC 24
Finished Sep 18 08:25:07 PM UTC 24
Peak memory 234164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360847103 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.360847103 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/23.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/23.kmac_smoke.1665883283
Short name T379
Test name
Test status
Simulation time 3291074341 ps
CPU time 51.17 seconds
Started Sep 18 08:24:52 PM UTC 24
Finished Sep 18 08:25:45 PM UTC 24
Peak memory 233812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665883283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.1665883283 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/23.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/23.kmac_stress_all.2517555981
Short name T560
Test name
Test status
Simulation time 150107009771 ps
CPU time 1162.8 seconds
Started Sep 18 08:25:50 PM UTC 24
Finished Sep 18 08:45:27 PM UTC 24
Peak memory 1336444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517555981 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.2517555981 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/23.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/24.kmac_alert_test.2235181470
Short name T393
Test name
Test status
Simulation time 122032826 ps
CPU time 1.22 seconds
Started Sep 18 08:27:15 PM UTC 24
Finished Sep 18 08:27:17 PM UTC 24
Peak memory 216388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235181470 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.2235181470 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/24.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/24.kmac_app.99757237
Short name T410
Test name
Test status
Simulation time 16959056914 ps
CPU time 180.04 seconds
Started Sep 18 08:26:45 PM UTC 24
Finished Sep 18 08:29:49 PM UTC 24
Peak memory 301816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99757237 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.99757237 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/24.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/24.kmac_burst_write.977517204
Short name T448
Test name
Test status
Simulation time 15739772722 ps
CPU time 384.55 seconds
Started Sep 18 08:26:25 PM UTC 24
Finished Sep 18 08:32:55 PM UTC 24
Peak memory 240420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977517204 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.977517204 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/24.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/24.kmac_entropy_refresh.2654121052
Short name T400
Test name
Test status
Simulation time 4646067067 ps
CPU time 89.09 seconds
Started Sep 18 08:26:49 PM UTC 24
Finished Sep 18 08:28:20 PM UTC 24
Peak memory 256856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654121052 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.2654121052 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/24.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/24.kmac_error.3929995902
Short name T433
Test name
Test status
Simulation time 10383480904 ps
CPU time 291.57 seconds
Started Sep 18 08:26:55 PM UTC 24
Finished Sep 18 08:31:51 PM UTC 24
Peak memory 508732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929995902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.3929995902 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/24.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/24.kmac_key_error.1076762685
Short name T390
Test name
Test status
Simulation time 311617637 ps
CPU time 4 seconds
Started Sep 18 08:27:05 PM UTC 24
Finished Sep 18 08:27:10 PM UTC 24
Peak memory 227228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076762685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.1076762685 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/24.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/24.kmac_lc_escalation.1888637735
Short name T392
Test name
Test status
Simulation time 36728474 ps
CPU time 1.95 seconds
Started Sep 18 08:27:11 PM UTC 24
Finished Sep 18 08:27:14 PM UTC 24
Peak memory 226388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888637735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.1888637735 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/24.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/24.kmac_long_msg_and_output.2346394489
Short name T692
Test name
Test status
Simulation time 23039842255 ps
CPU time 2156.27 seconds
Started Sep 18 08:26:05 PM UTC 24
Finished Sep 18 09:02:26 PM UTC 24
Peak memory 1626904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346394489 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_and_output.2346394489 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/24.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/24.kmac_sideload.3925457747
Short name T409
Test name
Test status
Simulation time 6489665146 ps
CPU time 201.64 seconds
Started Sep 18 08:26:16 PM UTC 24
Finished Sep 18 08:29:41 PM UTC 24
Peak memory 320308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925457747 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.3925457747 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/24.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/24.kmac_smoke.2454964090
Short name T385
Test name
Test status
Simulation time 5572012009 ps
CPU time 28.87 seconds
Started Sep 18 08:25:54 PM UTC 24
Finished Sep 18 08:26:24 PM UTC 24
Peak memory 234172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454964090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.2454964090 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/24.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/24.kmac_stress_all.2042951035
Short name T616
Test name
Test status
Simulation time 208442969020 ps
CPU time 1408.91 seconds
Started Sep 18 08:27:14 PM UTC 24
Finished Sep 18 08:51:00 PM UTC 24
Peak memory 988308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042951035 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.2042951035 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/24.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/25.kmac_alert_test.3024811075
Short name T403
Test name
Test status
Simulation time 88334003 ps
CPU time 1.29 seconds
Started Sep 18 08:28:38 PM UTC 24
Finished Sep 18 08:28:41 PM UTC 24
Peak memory 216388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024811075 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.3024811075 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/25.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/25.kmac_app.1668646159
Short name T425
Test name
Test status
Simulation time 29603950838 ps
CPU time 185.65 seconds
Started Sep 18 08:27:57 PM UTC 24
Finished Sep 18 08:31:06 PM UTC 24
Peak memory 359412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668646159 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.1668646159 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/25.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/25.kmac_burst_write.1711095676
Short name T407
Test name
Test status
Simulation time 3717427491 ps
CPU time 77.64 seconds
Started Sep 18 08:27:53 PM UTC 24
Finished Sep 18 08:29:13 PM UTC 24
Peak memory 244532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711095676 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.1711095676 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/25.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/25.kmac_entropy_refresh.3419971074
Short name T450
Test name
Test status
Simulation time 10662959441 ps
CPU time 298.45 seconds
Started Sep 18 08:28:00 PM UTC 24
Finished Sep 18 08:33:02 PM UTC 24
Peak memory 334648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419971074 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.3419971074 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/25.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/25.kmac_error.2463735132
Short name T429
Test name
Test status
Simulation time 9824286163 ps
CPU time 197.09 seconds
Started Sep 18 08:28:04 PM UTC 24
Finished Sep 18 08:31:24 PM UTC 24
Peak memory 316212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463735132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.2463735132 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/25.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/25.kmac_key_error.3150562040
Short name T401
Test name
Test status
Simulation time 5575372781 ps
CPU time 7.22 seconds
Started Sep 18 08:28:21 PM UTC 24
Finished Sep 18 08:28:29 PM UTC 24
Peak memory 227404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150562040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.3150562040 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/25.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/25.kmac_lc_escalation.478871973
Short name T402
Test name
Test status
Simulation time 153696709 ps
CPU time 1.79 seconds
Started Sep 18 08:28:34 PM UTC 24
Finished Sep 18 08:28:37 PM UTC 24
Peak memory 226336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478871973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.478871973 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/25.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/25.kmac_long_msg_and_output.2002737787
Short name T482
Test name
Test status
Simulation time 24294791217 ps
CPU time 577.41 seconds
Started Sep 18 08:27:38 PM UTC 24
Finished Sep 18 08:37:24 PM UTC 24
Peak memory 586748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002737787 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_and_output.2002737787 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/25.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/25.kmac_sideload.3535024777
Short name T405
Test name
Test status
Simulation time 5255345511 ps
CPU time 75.26 seconds
Started Sep 18 08:27:48 PM UTC 24
Finished Sep 18 08:29:05 PM UTC 24
Peak memory 295652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535024777 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.3535024777 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/25.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/25.kmac_smoke.625903001
Short name T395
Test name
Test status
Simulation time 3914330596 ps
CPU time 27.42 seconds
Started Sep 18 08:27:18 PM UTC 24
Finished Sep 18 08:27:47 PM UTC 24
Peak memory 233712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625903001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.625903001 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/25.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/25.kmac_stress_all.3636770077
Short name T449
Test name
Test status
Simulation time 85710909322 ps
CPU time 261.8 seconds
Started Sep 18 08:28:35 PM UTC 24
Finished Sep 18 08:33:01 PM UTC 24
Peak memory 316612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636770077 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.3636770077 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/25.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/26.kmac_alert_test.3411455058
Short name T414
Test name
Test status
Simulation time 16094772 ps
CPU time 1.22 seconds
Started Sep 18 08:30:02 PM UTC 24
Finished Sep 18 08:30:05 PM UTC 24
Peak memory 216388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411455058 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.3411455058 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/26.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/26.kmac_app.2168813414
Short name T431
Test name
Test status
Simulation time 17577732333 ps
CPU time 138.67 seconds
Started Sep 18 08:29:14 PM UTC 24
Finished Sep 18 08:31:35 PM UTC 24
Peak memory 322396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168813414 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.2168813414 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/26.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/26.kmac_burst_write.62615171
Short name T428
Test name
Test status
Simulation time 3368343582 ps
CPU time 118.24 seconds
Started Sep 18 08:29:14 PM UTC 24
Finished Sep 18 08:31:14 PM UTC 24
Peak memory 234284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62615171 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.62615171 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/26.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/26.kmac_entropy_refresh.1315248141
Short name T453
Test name
Test status
Simulation time 101672116564 ps
CPU time 259.33 seconds
Started Sep 18 08:29:18 PM UTC 24
Finished Sep 18 08:33:41 PM UTC 24
Peak memory 316152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315248141 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.1315248141 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/26.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/26.kmac_error.4256339739
Short name T41
Test name
Test status
Simulation time 12271130442 ps
CPU time 357.34 seconds
Started Sep 18 08:29:42 PM UTC 24
Finished Sep 18 08:35:44 PM UTC 24
Peak memory 570108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256339739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.4256339739 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/26.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/26.kmac_key_error.4025788121
Short name T413
Test name
Test status
Simulation time 1182930505 ps
CPU time 11.87 seconds
Started Sep 18 08:29:50 PM UTC 24
Finished Sep 18 08:30:03 PM UTC 24
Peak memory 227208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025788121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.4025788121 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/26.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/26.kmac_lc_escalation.2817604100
Short name T66
Test name
Test status
Simulation time 137668179 ps
CPU time 4.35 seconds
Started Sep 18 08:29:55 PM UTC 24
Finished Sep 18 08:30:01 PM UTC 24
Peak memory 231704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817604100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.2817604100 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/26.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/26.kmac_long_msg_and_output.4284503242
Short name T462
Test name
Test status
Simulation time 8061538558 ps
CPU time 371.35 seconds
Started Sep 18 08:28:55 PM UTC 24
Finished Sep 18 08:35:12 PM UTC 24
Peak memory 482140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284503242 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_and_output.4284503242 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/26.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/26.kmac_sideload.1423012373
Short name T420
Test name
Test status
Simulation time 1215283581 ps
CPU time 107.42 seconds
Started Sep 18 08:29:07 PM UTC 24
Finished Sep 18 08:30:56 PM UTC 24
Peak memory 265084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423012373 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.1423012373 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/26.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/26.kmac_smoke.4233925159
Short name T404
Test name
Test status
Simulation time 431210940 ps
CPU time 11.59 seconds
Started Sep 18 08:28:41 PM UTC 24
Finished Sep 18 08:28:55 PM UTC 24
Peak memory 229496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233925159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.4233925159 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/26.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/26.kmac_stress_all.209722166
Short name T605
Test name
Test status
Simulation time 69242721177 ps
CPU time 1199.29 seconds
Started Sep 18 08:30:01 PM UTC 24
Finished Sep 18 08:50:15 PM UTC 24
Peak memory 1043628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209722166 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.209722166 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/26.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/27.kmac_alert_test.3260689231
Short name T424
Test name
Test status
Simulation time 22545183 ps
CPU time 1.24 seconds
Started Sep 18 08:31:02 PM UTC 24
Finished Sep 18 08:31:05 PM UTC 24
Peak memory 216388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260689231 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.3260689231 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/27.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/27.kmac_app.2452484227
Short name T460
Test name
Test status
Simulation time 9405658165 ps
CPU time 217.94 seconds
Started Sep 18 08:30:43 PM UTC 24
Finished Sep 18 08:34:24 PM UTC 24
Peak memory 418612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452484227 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.2452484227 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/27.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/27.kmac_burst_write.1122305838
Short name T419
Test name
Test status
Simulation time 59144363 ps
CPU time 6.77 seconds
Started Sep 18 08:30:42 PM UTC 24
Finished Sep 18 08:30:50 PM UTC 24
Peak memory 227364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122305838 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.1122305838 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/27.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/27.kmac_entropy_refresh.3542745261
Short name T436
Test name
Test status
Simulation time 1078901411 ps
CPU time 69.72 seconds
Started Sep 18 08:30:49 PM UTC 24
Finished Sep 18 08:32:01 PM UTC 24
Peak memory 248440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542745261 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.3542745261 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/27.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/27.kmac_error.3853240022
Short name T446
Test name
Test status
Simulation time 17382611154 ps
CPU time 117.14 seconds
Started Sep 18 08:30:51 PM UTC 24
Finished Sep 18 08:32:50 PM UTC 24
Peak memory 361308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853240022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.3853240022 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/27.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/27.kmac_key_error.3944865472
Short name T426
Test name
Test status
Simulation time 2363722082 ps
CPU time 11.8 seconds
Started Sep 18 08:30:57 PM UTC 24
Finished Sep 18 08:31:10 PM UTC 24
Peak memory 227304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944865472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.3944865472 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/27.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/27.kmac_lc_escalation.3447817133
Short name T423
Test name
Test status
Simulation time 153869496 ps
CPU time 1.9 seconds
Started Sep 18 08:30:58 PM UTC 24
Finished Sep 18 08:31:01 PM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447817133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.3447817133 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/27.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/27.kmac_long_msg_and_output.347751895
Short name T630
Test name
Test status
Simulation time 50381697278 ps
CPU time 1327.75 seconds
Started Sep 18 08:30:05 PM UTC 24
Finished Sep 18 08:52:28 PM UTC 24
Peak memory 2057312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347751895 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_and_output.347751895 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/27.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/27.kmac_sideload.2361527073
Short name T492
Test name
Test status
Simulation time 20880475039 ps
CPU time 493.74 seconds
Started Sep 18 08:30:08 PM UTC 24
Finished Sep 18 08:38:28 PM UTC 24
Peak memory 670692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361527073 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.2361527073 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/27.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/27.kmac_smoke.2630658330
Short name T418
Test name
Test status
Simulation time 6428443633 ps
CPU time 42.78 seconds
Started Sep 18 08:30:03 PM UTC 24
Finished Sep 18 08:30:48 PM UTC 24
Peak memory 234268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630658330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.2630658330 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/27.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/27.kmac_stress_all.1182965570
Short name T527
Test name
Test status
Simulation time 40722019549 ps
CPU time 634.79 seconds
Started Sep 18 08:30:59 PM UTC 24
Finished Sep 18 08:41:42 PM UTC 24
Peak memory 380292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182965570 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.1182965570 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/27.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/28.kmac_alert_test.3641886093
Short name T434
Test name
Test status
Simulation time 44254796 ps
CPU time 1.19 seconds
Started Sep 18 08:31:52 PM UTC 24
Finished Sep 18 08:31:54 PM UTC 24
Peak memory 216388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641886093 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.3641886093 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/28.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/28.kmac_app.619411179
Short name T451
Test name
Test status
Simulation time 7332615445 ps
CPU time 122.28 seconds
Started Sep 18 08:31:15 PM UTC 24
Finished Sep 18 08:33:20 PM UTC 24
Peak memory 312096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619411179 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.619411179 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/28.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/28.kmac_burst_write.528597258
Short name T459
Test name
Test status
Simulation time 4882182555 ps
CPU time 172.88 seconds
Started Sep 18 08:31:13 PM UTC 24
Finished Sep 18 08:34:08 PM UTC 24
Peak memory 236280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528597258 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.528597258 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/28.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/28.kmac_entropy_refresh.4107649259
Short name T485
Test name
Test status
Simulation time 57583908156 ps
CPU time 381.63 seconds
Started Sep 18 08:31:25 PM UTC 24
Finished Sep 18 08:37:52 PM UTC 24
Peak memory 531476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107649259 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.4107649259 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/28.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/28.kmac_error.1060339618
Short name T481
Test name
Test status
Simulation time 27682617892 ps
CPU time 347.92 seconds
Started Sep 18 08:31:25 PM UTC 24
Finished Sep 18 08:37:18 PM UTC 24
Peak memory 367356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060339618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.1060339618 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/28.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/28.kmac_key_error.1543159218
Short name T432
Test name
Test status
Simulation time 1075284876 ps
CPU time 10.14 seconds
Started Sep 18 08:31:36 PM UTC 24
Finished Sep 18 08:31:47 PM UTC 24
Peak memory 227276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543159218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.1543159218 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/28.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/28.kmac_long_msg_and_output.3983668105
Short name T526
Test name
Test status
Simulation time 77829896113 ps
CPU time 617.5 seconds
Started Sep 18 08:31:08 PM UTC 24
Finished Sep 18 08:41:33 PM UTC 24
Peak memory 990012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983668105 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_and_output.3983668105 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/28.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/28.kmac_sideload.167134706
Short name T469
Test name
Test status
Simulation time 2996804817 ps
CPU time 254.36 seconds
Started Sep 18 08:31:11 PM UTC 24
Finished Sep 18 08:35:29 PM UTC 24
Peak memory 326460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167134706 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.167134706 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/28.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/28.kmac_smoke.189530333
Short name T430
Test name
Test status
Simulation time 546846948 ps
CPU time 17.73 seconds
Started Sep 18 08:31:05 PM UTC 24
Finished Sep 18 08:31:24 PM UTC 24
Peak memory 229524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189530333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.189530333 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/28.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/28.kmac_stress_all.1219868567
Short name T611
Test name
Test status
Simulation time 132221205644 ps
CPU time 1124.45 seconds
Started Sep 18 08:31:52 PM UTC 24
Finished Sep 18 08:50:51 PM UTC 24
Peak memory 1168800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219868567 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.1219868567 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/28.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/29.kmac_alert_test.1522715449
Short name T447
Test name
Test status
Simulation time 14787951 ps
CPU time 1.15 seconds
Started Sep 18 08:32:49 PM UTC 24
Finished Sep 18 08:32:52 PM UTC 24
Peak memory 216388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522715449 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.1522715449 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/29.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/29.kmac_app.1703020805
Short name T455
Test name
Test status
Simulation time 7773475794 ps
CPU time 89.97 seconds
Started Sep 18 08:32:22 PM UTC 24
Finished Sep 18 08:33:54 PM UTC 24
Peak memory 299768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703020805 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.1703020805 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/29.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/29.kmac_burst_write.119201063
Short name T493
Test name
Test status
Simulation time 4724773584 ps
CPU time 389.41 seconds
Started Sep 18 08:32:04 PM UTC 24
Finished Sep 18 08:38:38 PM UTC 24
Peak memory 242432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119201063 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.119201063 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/29.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/29.kmac_entropy_refresh.244863486
Short name T465
Test name
Test status
Simulation time 20004217520 ps
CPU time 170.1 seconds
Started Sep 18 08:32:27 PM UTC 24
Finished Sep 18 08:35:20 PM UTC 24
Peak memory 289636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244863486 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.244863486 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/29.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/29.kmac_error.3294965991
Short name T458
Test name
Test status
Simulation time 959081924 ps
CPU time 87.17 seconds
Started Sep 18 08:32:32 PM UTC 24
Finished Sep 18 08:34:01 PM UTC 24
Peak memory 279164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294965991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.3294965991 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/29.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/29.kmac_key_error.135216360
Short name T445
Test name
Test status
Simulation time 2676358541 ps
CPU time 6.89 seconds
Started Sep 18 08:32:40 PM UTC 24
Finished Sep 18 08:32:48 PM UTC 24
Peak memory 227432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135216360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.135216360 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/29.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/29.kmac_lc_escalation.550121347
Short name T443
Test name
Test status
Simulation time 262027254 ps
CPU time 1.86 seconds
Started Sep 18 08:32:42 PM UTC 24
Finished Sep 18 08:32:45 PM UTC 24
Peak memory 226336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550121347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.550121347 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/29.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/29.kmac_long_msg_and_output.966273189
Short name T717
Test name
Test status
Simulation time 343127102467 ps
CPU time 3461.16 seconds
Started Sep 18 08:31:57 PM UTC 24
Finished Sep 18 09:30:15 PM UTC 24
Peak memory 4219812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966273189 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_and_output.966273189 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/29.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/29.kmac_sideload.772782496
Short name T439
Test name
Test status
Simulation time 2964728674 ps
CPU time 22.76 seconds
Started Sep 18 08:32:02 PM UTC 24
Finished Sep 18 08:32:26 PM UTC 24
Peak memory 236340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772782496 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.772782496 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/29.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/29.kmac_smoke.115265119
Short name T442
Test name
Test status
Simulation time 6606636349 ps
CPU time 43.43 seconds
Started Sep 18 08:31:55 PM UTC 24
Finished Sep 18 08:32:41 PM UTC 24
Peak memory 234268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115265119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.115265119 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/29.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/29.kmac_stress_all.140586588
Short name T705
Test name
Test status
Simulation time 59467693710 ps
CPU time 2080.14 seconds
Started Sep 18 08:32:46 PM UTC 24
Finished Sep 18 09:07:51 PM UTC 24
Peak memory 1348804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140586588 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.140586588 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/29.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/3.kmac_alert_test.1040254765
Short name T193
Test name
Test status
Simulation time 16582104 ps
CPU time 1.21 seconds
Started Sep 18 08:03:14 PM UTC 24
Finished Sep 18 08:03:17 PM UTC 24
Peak memory 216508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040254765 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.1040254765 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/3.kmac_app.3292473594
Short name T206
Test name
Test status
Simulation time 37947713241 ps
CPU time 251.81 seconds
Started Sep 18 08:02:20 PM UTC 24
Finished Sep 18 08:06:36 PM UTC 24
Peak memory 310324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292473594 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.3292473594 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/3.kmac_app_with_partial_data.1708935669
Short name T61
Test name
Test status
Simulation time 1827913253 ps
CPU time 48.07 seconds
Started Sep 18 08:02:23 PM UTC 24
Finished Sep 18 08:03:13 PM UTC 24
Peak memory 265148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708935669 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.1708935669 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/3.kmac_burst_write.2222515284
Short name T139
Test name
Test status
Simulation time 5798270036 ps
CPU time 217.15 seconds
Started Sep 18 08:01:36 PM UTC 24
Finished Sep 18 08:05:17 PM UTC 24
Peak memory 238072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222515284 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.2222515284 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/3.kmac_edn_timeout_error.1732211293
Short name T194
Test name
Test status
Simulation time 4500606962 ps
CPU time 37.35 seconds
Started Sep 18 08:02:40 PM UTC 24
Finished Sep 18 08:03:19 PM UTC 24
Peak memory 233964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732211293 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.1732211293 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_mode_error.3731286513
Short name T132
Test name
Test status
Simulation time 4312269847 ps
CPU time 29.43 seconds
Started Sep 18 08:02:50 PM UTC 24
Finished Sep 18 08:03:21 PM UTC 24
Peak memory 234216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731286513 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.3731286513 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_ready_error.2969432378
Short name T116
Test name
Test status
Simulation time 14076591154 ps
CPU time 24.11 seconds
Started Sep 18 08:02:59 PM UTC 24
Finished Sep 18 08:03:24 PM UTC 24
Peak memory 231580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969432378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.2969432378 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/3.kmac_entropy_refresh.1042555260
Short name T115
Test name
Test status
Simulation time 164331892989 ps
CPU time 305.8 seconds
Started Sep 18 08:02:24 PM UTC 24
Finished Sep 18 08:07:35 PM UTC 24
Peak memory 447456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042555260 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.1042555260 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/3.kmac_error.2636640107
Short name T54
Test name
Test status
Simulation time 1422064399 ps
CPU time 112.08 seconds
Started Sep 18 08:02:27 PM UTC 24
Finished Sep 18 08:04:21 PM UTC 24
Peak memory 281400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636640107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.2636640107 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/3.kmac_key_error.2378195012
Short name T49
Test name
Test status
Simulation time 736329102 ps
CPU time 8.72 seconds
Started Sep 18 08:02:39 PM UTC 24
Finished Sep 18 08:02:49 PM UTC 24
Peak memory 227232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378195012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.2378195012 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/3.kmac_lc_escalation.3162634151
Short name T43
Test name
Test status
Simulation time 2023104827 ps
CPU time 6.34 seconds
Started Sep 18 08:02:59 PM UTC 24
Finished Sep 18 08:03:07 PM UTC 24
Peak memory 231584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162634151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.3162634151 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/3.kmac_long_msg_and_output.1677710064
Short name T538
Test name
Test status
Simulation time 23113572993 ps
CPU time 2462.53 seconds
Started Sep 18 08:01:34 PM UTC 24
Finished Sep 18 08:43:05 PM UTC 24
Peak memory 1686296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677710064 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_and_output.1677710064 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/3.kmac_mubi.3619573623
Short name T38
Test name
Test status
Simulation time 6382736464 ps
CPU time 60.58 seconds
Started Sep 18 08:02:25 PM UTC 24
Finished Sep 18 08:03:28 PM UTC 24
Peak memory 265340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619573623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.3619573623 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/3.kmac_sideload.1785780506
Short name T152
Test name
Test status
Simulation time 17483344130 ps
CPU time 358.18 seconds
Started Sep 18 08:01:36 PM UTC 24
Finished Sep 18 08:07:39 PM UTC 24
Peak memory 379792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785780506 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.1785780506 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/3.kmac_smoke.350915152
Short name T90
Test name
Test status
Simulation time 2886359283 ps
CPU time 31.74 seconds
Started Sep 18 08:01:32 PM UTC 24
Finished Sep 18 08:02:05 PM UTC 24
Peak memory 233712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350915152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.350915152 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/3.kmac_stress_all.487989004
Short name T301
Test name
Test status
Simulation time 31891900980 ps
CPU time 898.43 seconds
Started Sep 18 08:03:02 PM UTC 24
Finished Sep 18 08:18:12 PM UTC 24
Peak memory 1231668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487989004 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.487989004 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac.4134061417
Short name T94
Test name
Test status
Simulation time 31590896 ps
CPU time 2.79 seconds
Started Sep 18 08:02:19 PM UTC 24
Finished Sep 18 08:02:23 PM UTC 24
Peak memory 227708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134061417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac.4134061417 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac_xof.2328886404
Short name T95
Test name
Test status
Simulation time 107750298 ps
CPU time 2.62 seconds
Started Sep 18 08:02:20 PM UTC 24
Finished Sep 18 08:02:24 PM UTC 24
Peak memory 227800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328886404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac_xof.2328886404 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_224.336617700
Short name T188
Test name
Test status
Simulation time 3205009510 ps
CPU time 47.83 seconds
Started Sep 18 08:01:36 PM UTC 24
Finished Sep 18 08:02:26 PM UTC 24
Peak memory 234168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336617700 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.336617700 +
enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_256.27108811
Short name T502
Test name
Test status
Simulation time 202692687015 ps
CPU time 2239.61 seconds
Started Sep 18 08:01:42 PM UTC 24
Finished Sep 18 08:39:27 PM UTC 24
Peak memory 3043948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27108811 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.27108811 +en
able_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_384.1582850634
Short name T92
Test name
Test status
Simulation time 436713218 ps
CPU time 32.82 seconds
Started Sep 18 08:01:42 PM UTC 24
Finished Sep 18 08:02:16 PM UTC 24
Peak memory 233872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582850634 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.1582850634
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_512.800548704
Short name T336
Test name
Test status
Simulation time 32543144306 ps
CPU time 1178.45 seconds
Started Sep 18 08:02:06 PM UTC 24
Finished Sep 18 08:21:58 PM UTC 24
Peak memory 1766376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800548704 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.800548704 +
enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_128.1692301573
Short name T607
Test name
Test status
Simulation time 246568930340 ps
CPU time 2873.1 seconds
Started Sep 18 08:02:11 PM UTC 24
Finished Sep 18 08:50:35 PM UTC 24
Peak memory 3619496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692301573 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.1692301
573 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_256.3132622907
Short name T223
Test name
Test status
Simulation time 57180348889 ps
CPU time 468.35 seconds
Started Sep 18 08:02:17 PM UTC 24
Finished Sep 18 08:10:12 PM UTC 24
Peak memory 359068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132622907 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.3132622
907 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/30.kmac_alert_test.2996948172
Short name T457
Test name
Test status
Simulation time 37257378 ps
CPU time 1.17 seconds
Started Sep 18 08:33:57 PM UTC 24
Finished Sep 18 08:34:00 PM UTC 24
Peak memory 216388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996948172 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.2996948172 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/30.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/30.kmac_app.2393193801
Short name T495
Test name
Test status
Simulation time 17371923389 ps
CPU time 343.75 seconds
Started Sep 18 08:33:04 PM UTC 24
Finished Sep 18 08:38:52 PM UTC 24
Peak memory 553780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393193801 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.2393193801 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/30.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/30.kmac_burst_write.4037341287
Short name T533
Test name
Test status
Simulation time 55764891584 ps
CPU time 536.69 seconds
Started Sep 18 08:33:03 PM UTC 24
Finished Sep 18 08:42:07 PM UTC 24
Peak memory 252664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037341287 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.4037341287 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/30.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/30.kmac_entropy_refresh.898783299
Short name T463
Test name
Test status
Simulation time 19460321546 ps
CPU time 112.67 seconds
Started Sep 18 08:33:21 PM UTC 24
Finished Sep 18 08:35:16 PM UTC 24
Peak memory 303968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898783299 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.898783299 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/30.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/30.kmac_error.1258736340
Short name T470
Test name
Test status
Simulation time 1611385069 ps
CPU time 118.96 seconds
Started Sep 18 08:33:37 PM UTC 24
Finished Sep 18 08:35:38 PM UTC 24
Peak memory 285664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258736340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.1258736340 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/30.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/30.kmac_key_error.2657057909
Short name T454
Test name
Test status
Simulation time 3289914306 ps
CPU time 9.32 seconds
Started Sep 18 08:33:42 PM UTC 24
Finished Sep 18 08:33:53 PM UTC 24
Peak memory 227332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657057909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.2657057909 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/30.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/30.kmac_lc_escalation.1619671956
Short name T456
Test name
Test status
Simulation time 44573491 ps
CPU time 1.98 seconds
Started Sep 18 08:33:53 PM UTC 24
Finished Sep 18 08:33:56 PM UTC 24
Peak memory 226420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619671956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.1619671956 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/30.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/30.kmac_long_msg_and_output.486321978
Short name T714
Test name
Test status
Simulation time 189945395819 ps
CPU time 3020.24 seconds
Started Sep 18 08:32:52 PM UTC 24
Finished Sep 18 09:23:47 PM UTC 24
Peak memory 3648488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486321978 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_and_output.486321978 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/30.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/30.kmac_sideload.3000987432
Short name T496
Test name
Test status
Simulation time 15982124441 ps
CPU time 352.33 seconds
Started Sep 18 08:32:57 PM UTC 24
Finished Sep 18 08:38:54 PM UTC 24
Peak memory 369664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000987432 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.3000987432 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/30.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/30.kmac_smoke.3445738350
Short name T452
Test name
Test status
Simulation time 1436171134 ps
CPU time 42.82 seconds
Started Sep 18 08:32:51 PM UTC 24
Finished Sep 18 08:33:36 PM UTC 24
Peak memory 233652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445738350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.3445738350 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/30.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/30.kmac_stress_all.1298687258
Short name T686
Test name
Test status
Simulation time 121225850273 ps
CPU time 1459.82 seconds
Started Sep 18 08:33:55 PM UTC 24
Finished Sep 18 08:58:33 PM UTC 24
Peak memory 1539424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298687258 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.1298687258 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/30.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/31.kmac_alert_test.209911690
Short name T468
Test name
Test status
Simulation time 16946857 ps
CPU time 1.16 seconds
Started Sep 18 08:35:25 PM UTC 24
Finished Sep 18 08:35:27 PM UTC 24
Peak memory 216508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209911690 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.209911690 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/31.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/31.kmac_app.3997887723
Short name T475
Test name
Test status
Simulation time 4722887746 ps
CPU time 95.02 seconds
Started Sep 18 08:34:28 PM UTC 24
Finished Sep 18 08:36:05 PM UTC 24
Peak memory 326708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997887723 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.3997887723 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/31.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/31.kmac_burst_write.817921356
Short name T471
Test name
Test status
Simulation time 807790843 ps
CPU time 71.36 seconds
Started Sep 18 08:34:26 PM UTC 24
Finished Sep 18 08:35:39 PM UTC 24
Peak memory 234172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817921356 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.817921356 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/31.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/31.kmac_entropy_refresh.4262677996
Short name T473
Test name
Test status
Simulation time 7906080565 ps
CPU time 38.59 seconds
Started Sep 18 08:35:13 PM UTC 24
Finished Sep 18 08:35:53 PM UTC 24
Peak memory 258864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262677996 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.4262677996 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/31.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/31.kmac_error.1022170762
Short name T509
Test name
Test status
Simulation time 13172692151 ps
CPU time 288.37 seconds
Started Sep 18 08:35:16 PM UTC 24
Finished Sep 18 08:40:09 PM UTC 24
Peak memory 334592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022170762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.1022170762 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/31.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/31.kmac_key_error.4265243712
Short name T467
Test name
Test status
Simulation time 1665882743 ps
CPU time 4.78 seconds
Started Sep 18 08:35:21 PM UTC 24
Finished Sep 18 08:35:26 PM UTC 24
Peak memory 227172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265243712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.4265243712 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/31.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/31.kmac_lc_escalation.1180119975
Short name T466
Test name
Test status
Simulation time 48529303 ps
CPU time 2.55 seconds
Started Sep 18 08:35:21 PM UTC 24
Finished Sep 18 08:35:24 PM UTC 24
Peak memory 229604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180119975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.1180119975 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/31.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/31.kmac_long_msg_and_output.795413049
Short name T610
Test name
Test status
Simulation time 107007824208 ps
CPU time 995.16 seconds
Started Sep 18 08:34:03 PM UTC 24
Finished Sep 18 08:50:49 PM UTC 24
Peak memory 1587964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795413049 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_and_output.795413049 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/31.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/31.kmac_sideload.345145286
Short name T514
Test name
Test status
Simulation time 12933171146 ps
CPU time 391.36 seconds
Started Sep 18 08:34:10 PM UTC 24
Finished Sep 18 08:40:47 PM UTC 24
Peak memory 492592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345145286 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.345145286 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/31.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/31.kmac_smoke.1001996733
Short name T464
Test name
Test status
Simulation time 9467589220 ps
CPU time 77.12 seconds
Started Sep 18 08:34:00 PM UTC 24
Finished Sep 18 08:35:19 PM UTC 24
Peak memory 234336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001996733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.1001996733 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/31.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/31.kmac_stress_all.2180525459
Short name T521
Test name
Test status
Simulation time 11185000838 ps
CPU time 335.32 seconds
Started Sep 18 08:35:24 PM UTC 24
Finished Sep 18 08:41:04 PM UTC 24
Peak memory 645940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180525459 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.2180525459 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/31.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/32.kmac_alert_test.3581946106
Short name T478
Test name
Test status
Simulation time 19222291 ps
CPU time 1.08 seconds
Started Sep 18 08:36:07 PM UTC 24
Finished Sep 18 08:36:09 PM UTC 24
Peak memory 216388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581946106 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.3581946106 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/32.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/32.kmac_app.754451227
Short name T472
Test name
Test status
Simulation time 223000887 ps
CPU time 4 seconds
Started Sep 18 08:35:40 PM UTC 24
Finished Sep 18 08:35:45 PM UTC 24
Peak memory 229784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754451227 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.754451227 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/32.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/32.kmac_burst_write.454646074
Short name T516
Test name
Test status
Simulation time 18958928014 ps
CPU time 305.11 seconds
Started Sep 18 08:35:39 PM UTC 24
Finished Sep 18 08:40:48 PM UTC 24
Peak memory 244476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454646074 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.454646074 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/32.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/32.kmac_entropy_refresh.1340462141
Short name T503
Test name
Test status
Simulation time 9997691767 ps
CPU time 233.68 seconds
Started Sep 18 08:35:45 PM UTC 24
Finished Sep 18 08:39:42 PM UTC 24
Peak memory 451376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340462141 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.1340462141 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/32.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/32.kmac_error.2726396549
Short name T534
Test name
Test status
Simulation time 4371537494 ps
CPU time 376.16 seconds
Started Sep 18 08:35:46 PM UTC 24
Finished Sep 18 08:42:08 PM UTC 24
Peak memory 389944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726396549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.2726396549 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/32.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/32.kmac_key_error.619281106
Short name T474
Test name
Test status
Simulation time 2319321199 ps
CPU time 6.72 seconds
Started Sep 18 08:35:54 PM UTC 24
Finished Sep 18 08:36:02 PM UTC 24
Peak memory 227664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619281106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.619281106 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/32.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/32.kmac_lc_escalation.2477344196
Short name T477
Test name
Test status
Simulation time 56370819 ps
CPU time 1.88 seconds
Started Sep 18 08:36:04 PM UTC 24
Finished Sep 18 08:36:07 PM UTC 24
Peak memory 226428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477344196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.2477344196 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/32.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/32.kmac_long_msg_and_output.2699292615
Short name T701
Test name
Test status
Simulation time 181365205628 ps
CPU time 1816.29 seconds
Started Sep 18 08:35:28 PM UTC 24
Finished Sep 18 09:06:06 PM UTC 24
Peak memory 2265944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699292615 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_and_output.2699292615 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/32.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/32.kmac_sideload.1704674914
Short name T528
Test name
Test status
Simulation time 12631506018 ps
CPU time 371.61 seconds
Started Sep 18 08:35:30 PM UTC 24
Finished Sep 18 08:41:47 PM UTC 24
Peak memory 566112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704674914 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.1704674914 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/32.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/32.kmac_smoke.3106416970
Short name T476
Test name
Test status
Simulation time 5017829101 ps
CPU time 37.46 seconds
Started Sep 18 08:35:27 PM UTC 24
Finished Sep 18 08:36:06 PM UTC 24
Peak memory 233784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106416970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.3106416970 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/32.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/32.kmac_stress_all.1681108942
Short name T681
Test name
Test status
Simulation time 116882880680 ps
CPU time 1295.84 seconds
Started Sep 18 08:36:06 PM UTC 24
Finished Sep 18 08:57:58 PM UTC 24
Peak memory 974048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681108942 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.1681108942 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/32.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/33.kmac_alert_test.370164182
Short name T488
Test name
Test status
Simulation time 36136531 ps
CPU time 1.23 seconds
Started Sep 18 08:38:09 PM UTC 24
Finished Sep 18 08:38:11 PM UTC 24
Peak memory 216508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370164182 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.370164182 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/33.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/33.kmac_app.2962897334
Short name T444
Test name
Test status
Simulation time 14756169794 ps
CPU time 119.16 seconds
Started Sep 18 08:37:18 PM UTC 24
Finished Sep 18 08:39:20 PM UTC 24
Peak memory 322356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962897334 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.2962897334 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/33.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/33.kmac_burst_write.1755527898
Short name T585
Test name
Test status
Simulation time 110783318356 ps
CPU time 620.29 seconds
Started Sep 18 08:37:02 PM UTC 24
Finished Sep 18 08:47:31 PM UTC 24
Peak memory 254720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755527898 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.1755527898 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/33.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/33.kmac_entropy_refresh.1068841960
Short name T512
Test name
Test status
Simulation time 36420402911 ps
CPU time 169.06 seconds
Started Sep 18 08:37:25 PM UTC 24
Finished Sep 18 08:40:17 PM UTC 24
Peak memory 357208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068841960 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.1068841960 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/33.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/33.kmac_error.3978178574
Short name T506
Test name
Test status
Simulation time 9720026320 ps
CPU time 137.51 seconds
Started Sep 18 08:37:36 PM UTC 24
Finished Sep 18 08:39:56 PM UTC 24
Peak memory 365304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978178574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.3978178574 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/33.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/33.kmac_key_error.2070113336
Short name T486
Test name
Test status
Simulation time 1117702273 ps
CPU time 10.43 seconds
Started Sep 18 08:37:47 PM UTC 24
Finished Sep 18 08:37:58 PM UTC 24
Peak memory 227596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070113336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.2070113336 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/33.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/33.kmac_lc_escalation.2245994755
Short name T487
Test name
Test status
Simulation time 485318889 ps
CPU time 14.57 seconds
Started Sep 18 08:37:53 PM UTC 24
Finished Sep 18 08:38:09 PM UTC 24
Peak memory 244664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245994755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.2245994755 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/33.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/33.kmac_long_msg_and_output.1087286312
Short name T708
Test name
Test status
Simulation time 158758048818 ps
CPU time 2404.11 seconds
Started Sep 18 08:36:10 PM UTC 24
Finished Sep 18 09:16:42 PM UTC 24
Peak memory 1703008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087286312 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_and_output.1087286312 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/33.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/33.kmac_sideload.236370917
Short name T497
Test name
Test status
Simulation time 4149362790 ps
CPU time 118.42 seconds
Started Sep 18 08:36:55 PM UTC 24
Finished Sep 18 08:38:56 PM UTC 24
Peak memory 328436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236370917 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.236370917 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/33.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/33.kmac_smoke.2646040360
Short name T479
Test name
Test status
Simulation time 2073588785 ps
CPU time 44.47 seconds
Started Sep 18 08:36:08 PM UTC 24
Finished Sep 18 08:36:54 PM UTC 24
Peak memory 234420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646040360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.2646040360 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/33.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/33.kmac_stress_all.1768872441
Short name T524
Test name
Test status
Simulation time 14278717948 ps
CPU time 191.34 seconds
Started Sep 18 08:37:59 PM UTC 24
Finished Sep 18 08:41:14 PM UTC 24
Peak memory 283772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768872441 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.1768872441 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/33.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/34.kmac_alert_test.2210100167
Short name T498
Test name
Test status
Simulation time 41790450 ps
CPU time 1.13 seconds
Started Sep 18 08:38:59 PM UTC 24
Finished Sep 18 08:39:01 PM UTC 24
Peak memory 216388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210100167 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.2210100167 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/34.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/34.kmac_app.1278271143
Short name T523
Test name
Test status
Simulation time 13550601696 ps
CPU time 159.23 seconds
Started Sep 18 08:38:30 PM UTC 24
Finished Sep 18 08:41:11 PM UTC 24
Peak memory 383772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278271143 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.1278271143 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/34.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/34.kmac_burst_write.3180571986
Short name T575
Test name
Test status
Simulation time 19788346237 ps
CPU time 515.21 seconds
Started Sep 18 08:38:25 PM UTC 24
Finished Sep 18 08:47:07 PM UTC 24
Peak memory 246516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180571986 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.3180571986 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/34.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/34.kmac_entropy_refresh.931809111
Short name T582
Test name
Test status
Simulation time 24371951676 ps
CPU time 521.84 seconds
Started Sep 18 08:38:40 PM UTC 24
Finished Sep 18 08:47:29 PM UTC 24
Peak memory 582496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931809111 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.931809111 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/34.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/34.kmac_error.4210488007
Short name T519
Test name
Test status
Simulation time 1247706341 ps
CPU time 115.98 seconds
Started Sep 18 08:38:58 PM UTC 24
Finished Sep 18 08:40:56 PM UTC 24
Peak memory 279228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210488007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.4210488007 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/34.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/34.kmac_key_error.666009848
Short name T501
Test name
Test status
Simulation time 12053063211 ps
CPU time 22.67 seconds
Started Sep 18 08:38:59 PM UTC 24
Finished Sep 18 08:39:23 PM UTC 24
Peak memory 227380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666009848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.666009848 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/34.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/34.kmac_long_msg_and_output.2930787640
Short name T706
Test name
Test status
Simulation time 23748483398 ps
CPU time 2017.51 seconds
Started Sep 18 08:38:15 PM UTC 24
Finished Sep 18 09:12:16 PM UTC 24
Peak memory 1653852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930787640 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_and_output.2930787640 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/34.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/34.kmac_sideload.933663385
Short name T532
Test name
Test status
Simulation time 42399715077 ps
CPU time 222.17 seconds
Started Sep 18 08:38:15 PM UTC 24
Finished Sep 18 08:42:01 PM UTC 24
Peak memory 422644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933663385 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.933663385 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/34.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/34.kmac_smoke.543948587
Short name T494
Test name
Test status
Simulation time 5451835430 ps
CPU time 35.52 seconds
Started Sep 18 08:38:12 PM UTC 24
Finished Sep 18 08:38:49 PM UTC 24
Peak memory 233684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543948587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.543948587 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/34.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/34.kmac_stress_all.505131357
Short name T712
Test name
Test status
Simulation time 88235413126 ps
CPU time 2448 seconds
Started Sep 18 08:38:59 PM UTC 24
Finished Sep 18 09:20:15 PM UTC 24
Peak memory 1654236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505131357 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.505131357 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/34.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/35.kmac_alert_test.3974066080
Short name T507
Test name
Test status
Simulation time 124032942 ps
CPU time 1.3 seconds
Started Sep 18 08:39:57 PM UTC 24
Finished Sep 18 08:40:00 PM UTC 24
Peak memory 216388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974066080 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.3974066080 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/35.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/35.kmac_app.4266061795
Short name T504
Test name
Test status
Simulation time 1385924610 ps
CPU time 19.01 seconds
Started Sep 18 08:39:22 PM UTC 24
Finished Sep 18 08:39:43 PM UTC 24
Peak memory 234132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266061795 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.4266061795 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/35.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/35.kmac_burst_write.3698807052
Short name T627
Test name
Test status
Simulation time 77651905450 ps
CPU time 761.31 seconds
Started Sep 18 08:39:21 PM UTC 24
Finished Sep 18 08:52:12 PM UTC 24
Peak memory 250712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698807052 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.3698807052 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/35.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/35.kmac_entropy_refresh.1962625333
Short name T547
Test name
Test status
Simulation time 11915156554 ps
CPU time 279.44 seconds
Started Sep 18 08:39:24 PM UTC 24
Finished Sep 18 08:44:07 PM UTC 24
Peak memory 328700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962625333 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.1962625333 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/35.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/35.kmac_error.3576493295
Short name T537
Test name
Test status
Simulation time 7444063393 ps
CPU time 182.49 seconds
Started Sep 18 08:39:29 PM UTC 24
Finished Sep 18 08:42:34 PM UTC 24
Peak memory 390204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576493295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.3576493295 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/35.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/35.kmac_key_error.2139387640
Short name T505
Test name
Test status
Simulation time 5656467029 ps
CPU time 9.28 seconds
Started Sep 18 08:39:44 PM UTC 24
Finished Sep 18 08:39:54 PM UTC 24
Peak memory 227660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139387640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.2139387640 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/35.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/35.kmac_lc_escalation.1638980732
Short name T508
Test name
Test status
Simulation time 366819628 ps
CPU time 17.82 seconds
Started Sep 18 08:39:44 PM UTC 24
Finished Sep 18 08:40:03 PM UTC 24
Peak memory 244724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638980732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.1638980732 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/35.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/35.kmac_long_msg_and_output.3393623375
Short name T715
Test name
Test status
Simulation time 283518004580 ps
CPU time 2654.09 seconds
Started Sep 18 08:39:15 PM UTC 24
Finished Sep 18 09:23:58 PM UTC 24
Peak memory 3369816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393623375 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_and_output.3393623375 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/35.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/35.kmac_sideload.4089188716
Short name T558
Test name
Test status
Simulation time 22514269793 ps
CPU time 348.8 seconds
Started Sep 18 08:39:18 PM UTC 24
Finished Sep 18 08:45:12 PM UTC 24
Peak memory 549632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089188716 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.4089188716 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/35.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/35.kmac_smoke.1600499777
Short name T510
Test name
Test status
Simulation time 1038310099 ps
CPU time 65.56 seconds
Started Sep 18 08:39:02 PM UTC 24
Finished Sep 18 08:40:09 PM UTC 24
Peak memory 233656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600499777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.1600499777 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/35.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/35.kmac_stress_all.2128726365
Short name T592
Test name
Test status
Simulation time 30324477364 ps
CPU time 536.64 seconds
Started Sep 18 08:39:55 PM UTC 24
Finished Sep 18 08:48:59 PM UTC 24
Peak memory 332920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128726365 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.2128726365 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/35.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/36.kmac_alert_test.1267380720
Short name T518
Test name
Test status
Simulation time 108051957 ps
CPU time 1.22 seconds
Started Sep 18 08:40:53 PM UTC 24
Finished Sep 18 08:40:55 PM UTC 24
Peak memory 216388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267380720 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.1267380720 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/36.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/36.kmac_app.1123221218
Short name T578
Test name
Test status
Simulation time 15701418075 ps
CPU time 418.8 seconds
Started Sep 18 08:40:16 PM UTC 24
Finished Sep 18 08:47:21 PM UTC 24
Peak memory 516852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123221218 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.1123221218 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/36.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/36.kmac_burst_write.892078807
Short name T522
Test name
Test status
Simulation time 6595702618 ps
CPU time 55.04 seconds
Started Sep 18 08:40:10 PM UTC 24
Finished Sep 18 08:41:07 PM UTC 24
Peak memory 234292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892078807 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.892078807 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/36.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/36.kmac_entropy_refresh.240284644
Short name T555
Test name
Test status
Simulation time 7614464223 ps
CPU time 273.7 seconds
Started Sep 18 08:40:18 PM UTC 24
Finished Sep 18 08:44:55 PM UTC 24
Peak memory 361276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240284644 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.240284644 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/36.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/36.kmac_error.2713979087
Short name T541
Test name
Test status
Simulation time 9512506257 ps
CPU time 160 seconds
Started Sep 18 08:40:44 PM UTC 24
Finished Sep 18 08:43:27 PM UTC 24
Peak memory 316124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713979087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.2713979087 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/36.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/36.kmac_key_error.745296998
Short name T520
Test name
Test status
Simulation time 3225877825 ps
CPU time 7.9 seconds
Started Sep 18 08:40:48 PM UTC 24
Finished Sep 18 08:40:57 PM UTC 24
Peak memory 227368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745296998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.745296998 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/36.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/36.kmac_lc_escalation.2733092843
Short name T517
Test name
Test status
Simulation time 34159115 ps
CPU time 1.9 seconds
Started Sep 18 08:40:49 PM UTC 24
Finished Sep 18 08:40:52 PM UTC 24
Peak memory 226384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733092843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.2733092843 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/36.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/36.kmac_long_msg_and_output.680020521
Short name T671
Test name
Test status
Simulation time 10283009228 ps
CPU time 955.68 seconds
Started Sep 18 08:40:04 PM UTC 24
Finished Sep 18 08:56:12 PM UTC 24
Peak memory 840472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680020521 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_and_output.680020521 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/36.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/36.kmac_sideload.1459915684
Short name T553
Test name
Test status
Simulation time 15396422336 ps
CPU time 254.7 seconds
Started Sep 18 08:40:10 PM UTC 24
Finished Sep 18 08:44:29 PM UTC 24
Peak memory 330748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459915684 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.1459915684 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/36.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/36.kmac_smoke.907986719
Short name T511
Test name
Test status
Simulation time 585788278 ps
CPU time 13.64 seconds
Started Sep 18 08:40:00 PM UTC 24
Finished Sep 18 08:40:15 PM UTC 24
Peak memory 231596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907986719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.907986719 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/36.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/36.kmac_stress_all.2533229399
Short name T698
Test name
Test status
Simulation time 47378617732 ps
CPU time 1466.55 seconds
Started Sep 18 08:40:49 PM UTC 24
Finished Sep 18 09:05:32 PM UTC 24
Peak memory 1491808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533229399 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.2533229399 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/36.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/37.kmac_alert_test.1314247082
Short name T539
Test name
Test status
Simulation time 14204542 ps
CPU time 1.22 seconds
Started Sep 18 08:42:07 PM UTC 24
Finished Sep 18 08:43:18 PM UTC 24
Peak memory 216456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314247082 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.1314247082 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/37.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/37.kmac_app.3166523219
Short name T536
Test name
Test status
Simulation time 1421346064 ps
CPU time 78.04 seconds
Started Sep 18 08:41:08 PM UTC 24
Finished Sep 18 08:42:28 PM UTC 24
Peak memory 263132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166523219 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.3166523219 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/37.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/37.kmac_burst_write.951750135
Short name T634
Test name
Test status
Simulation time 20892429200 ps
CPU time 705.04 seconds
Started Sep 18 08:41:05 PM UTC 24
Finished Sep 18 08:52:58 PM UTC 24
Peak memory 258844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951750135 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.951750135 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/37.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/37.kmac_entropy_refresh.3016342557
Short name T567
Test name
Test status
Simulation time 12068237932 ps
CPU time 323.63 seconds
Started Sep 18 08:41:13 PM UTC 24
Finished Sep 18 08:46:41 PM UTC 24
Peak memory 453428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016342557 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.3016342557 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/37.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/37.kmac_error.1604501483
Short name T42
Test name
Test status
Simulation time 32230899283 ps
CPU time 129.98 seconds
Started Sep 18 08:41:15 PM UTC 24
Finished Sep 18 08:43:27 PM UTC 24
Peak memory 345188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604501483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.1604501483 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/37.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/37.kmac_key_error.730201270
Short name T529
Test name
Test status
Simulation time 1567261243 ps
CPU time 14.32 seconds
Started Sep 18 08:41:32 PM UTC 24
Finished Sep 18 08:41:47 PM UTC 24
Peak memory 227536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730201270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.730201270 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/37.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/37.kmac_lc_escalation.1849595864
Short name T530
Test name
Test status
Simulation time 2516226421 ps
CPU time 20.01 seconds
Started Sep 18 08:41:34 PM UTC 24
Finished Sep 18 08:41:56 PM UTC 24
Peak memory 246684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849595864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.1849595864 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/37.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/37.kmac_long_msg_and_output.664256421
Short name T713
Test name
Test status
Simulation time 236837771302 ps
CPU time 2492.35 seconds
Started Sep 18 08:40:57 PM UTC 24
Finished Sep 18 09:22:59 PM UTC 24
Peak memory 2997052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664256421 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_and_output.664256421 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/37.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/37.kmac_sideload.1082070480
Short name T576
Test name
Test status
Simulation time 77384868463 ps
CPU time 365.9 seconds
Started Sep 18 08:40:57 PM UTC 24
Finished Sep 18 08:47:08 PM UTC 24
Peak memory 555776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082070480 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.1082070480 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/37.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/37.kmac_smoke.548443363
Short name T531
Test name
Test status
Simulation time 5219150327 ps
CPU time 60.47 seconds
Started Sep 18 08:40:56 PM UTC 24
Finished Sep 18 08:41:58 PM UTC 24
Peak memory 234208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548443363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.548443363 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/37.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/37.kmac_stress_all.202822244
Short name T566
Test name
Test status
Simulation time 8057820923 ps
CPU time 182.59 seconds
Started Sep 18 08:42:03 PM UTC 24
Finished Sep 18 08:46:20 PM UTC 24
Peak memory 327084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202822244 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.202822244 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/37.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/38.kmac_alert_test.792528698
Short name T540
Test name
Test status
Simulation time 63285411 ps
CPU time 1.31 seconds
Started Sep 18 08:43:19 PM UTC 24
Finished Sep 18 08:43:21 PM UTC 24
Peak memory 216508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792528698 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.792528698 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/38.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/38.kmac_app.4174250897
Short name T549
Test name
Test status
Simulation time 11687379730 ps
CPU time 55.99 seconds
Started Sep 18 08:42:28 PM UTC 24
Finished Sep 18 08:44:15 PM UTC 24
Peak memory 277276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174250897 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.4174250897 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/38.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/38.kmac_burst_write.3683399272
Short name T542
Test name
Test status
Simulation time 557879560 ps
CPU time 11.92 seconds
Started Sep 18 08:42:22 PM UTC 24
Finished Sep 18 08:43:28 PM UTC 24
Peak memory 231544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683399272 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.3683399272 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/38.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/38.kmac_entropy_refresh.1281566202
Short name T572
Test name
Test status
Simulation time 14559712834 ps
CPU time 207.95 seconds
Started Sep 18 08:42:29 PM UTC 24
Finished Sep 18 08:46:49 PM UTC 24
Peak memory 308060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281566202 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.1281566202 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/38.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/38.kmac_error.3718338542
Short name T556
Test name
Test status
Simulation time 4472283826 ps
CPU time 105.03 seconds
Started Sep 18 08:42:38 PM UTC 24
Finished Sep 18 08:45:04 PM UTC 24
Peak memory 330536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718338542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.3718338542 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/38.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/38.kmac_key_error.2236178023
Short name T543
Test name
Test status
Simulation time 966599248 ps
CPU time 10.22 seconds
Started Sep 18 08:42:48 PM UTC 24
Finished Sep 18 08:43:29 PM UTC 24
Peak memory 227272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236178023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.2236178023 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/38.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/38.kmac_lc_escalation.325440730
Short name T68
Test name
Test status
Simulation time 226270354 ps
CPU time 1.47 seconds
Started Sep 18 08:42:55 PM UTC 24
Finished Sep 18 08:43:20 PM UTC 24
Peak memory 226372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325440730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.325440730 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/38.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/38.kmac_long_msg_and_output.3025116368
Short name T693
Test name
Test status
Simulation time 43136430276 ps
CPU time 1138.23 seconds
Started Sep 18 08:42:17 PM UTC 24
Finished Sep 18 09:02:30 PM UTC 24
Peak memory 1754236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025116368 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_and_output.3025116368 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/38.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/38.kmac_sideload.1262760259
Short name T563
Test name
Test status
Simulation time 7670813863 ps
CPU time 138.83 seconds
Started Sep 18 08:42:19 PM UTC 24
Finished Sep 18 08:45:39 PM UTC 24
Peak memory 326392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262760259 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.1262760259 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/38.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/38.kmac_smoke.2804208082
Short name T545
Test name
Test status
Simulation time 7163845578 ps
CPU time 42.82 seconds
Started Sep 18 08:42:08 PM UTC 24
Finished Sep 18 08:44:02 PM UTC 24
Peak memory 234240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804208082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.2804208082 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/38.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/38.kmac_stress_all.1408724515
Short name T702
Test name
Test status
Simulation time 94066345072 ps
CPU time 1359.71 seconds
Started Sep 18 08:43:05 PM UTC 24
Finished Sep 18 09:06:14 PM UTC 24
Peak memory 1262656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408724515 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.1408724515 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/38.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/39.kmac_alert_test.830655026
Short name T551
Test name
Test status
Simulation time 38585241 ps
CPU time 1.18 seconds
Started Sep 18 08:44:13 PM UTC 24
Finished Sep 18 08:44:16 PM UTC 24
Peak memory 216508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830655026 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.830655026 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/39.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/39.kmac_app.3168347418
Short name T552
Test name
Test status
Simulation time 3020909987 ps
CPU time 47.28 seconds
Started Sep 18 08:43:29 PM UTC 24
Finished Sep 18 08:44:18 PM UTC 24
Peak memory 260900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168347418 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.3168347418 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/39.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/39.kmac_burst_write.1239515140
Short name T596
Test name
Test status
Simulation time 18073894870 ps
CPU time 336.2 seconds
Started Sep 18 08:43:28 PM UTC 24
Finished Sep 18 08:49:09 PM UTC 24
Peak memory 240432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239515140 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.1239515140 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/39.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/39.kmac_entropy_refresh.1525065010
Short name T565
Test name
Test status
Simulation time 11059864693 ps
CPU time 155.82 seconds
Started Sep 18 08:43:30 PM UTC 24
Finished Sep 18 08:46:09 PM UTC 24
Peak memory 361272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525065010 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.1525065010 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/39.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/39.kmac_error.3812098785
Short name T561
Test name
Test status
Simulation time 4432887725 ps
CPU time 91.32 seconds
Started Sep 18 08:43:56 PM UTC 24
Finished Sep 18 08:45:29 PM UTC 24
Peak memory 283704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812098785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.3812098785 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/39.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/39.kmac_key_error.2856644261
Short name T548
Test name
Test status
Simulation time 2790019082 ps
CPU time 8.65 seconds
Started Sep 18 08:44:03 PM UTC 24
Finished Sep 18 08:44:13 PM UTC 24
Peak memory 227560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856644261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.2856644261 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/39.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/39.kmac_lc_escalation.1161973368
Short name T550
Test name
Test status
Simulation time 416379994 ps
CPU time 9.46 seconds
Started Sep 18 08:44:04 PM UTC 24
Finished Sep 18 08:44:15 PM UTC 24
Peak memory 244468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161973368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.1161973368 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/39.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/39.kmac_long_msg_and_output.3520108971
Short name T710
Test name
Test status
Simulation time 23228371410 ps
CPU time 2051.92 seconds
Started Sep 18 08:43:22 PM UTC 24
Finished Sep 18 09:17:56 PM UTC 24
Peak memory 1708856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520108971 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_and_output.3520108971 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/39.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/39.kmac_sideload.3039372663
Short name T629
Test name
Test status
Simulation time 21133272772 ps
CPU time 529.96 seconds
Started Sep 18 08:43:28 PM UTC 24
Finished Sep 18 08:52:25 PM UTC 24
Peak memory 668576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039372663 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.3039372663 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/39.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/39.kmac_smoke.169275319
Short name T546
Test name
Test status
Simulation time 1517134733 ps
CPU time 41.76 seconds
Started Sep 18 08:43:21 PM UTC 24
Finished Sep 18 08:44:04 PM UTC 24
Peak memory 234080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169275319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.169275319 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/39.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/39.kmac_stress_all.3128968627
Short name T659
Test name
Test status
Simulation time 109093651434 ps
CPU time 653.17 seconds
Started Sep 18 08:44:07 PM UTC 24
Finished Sep 18 08:55:08 PM UTC 24
Peak memory 887624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128968627 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.3128968627 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/39.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/4.kmac_alert_test.530612023
Short name T203
Test name
Test status
Simulation time 20381869 ps
CPU time 1.2 seconds
Started Sep 18 08:04:46 PM UTC 24
Finished Sep 18 08:04:49 PM UTC 24
Peak memory 216452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530612023 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.530612023 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/4.kmac_app.1379911002
Short name T212
Test name
Test status
Simulation time 9636980259 ps
CPU time 216.7 seconds
Started Sep 18 08:04:09 PM UTC 24
Finished Sep 18 08:07:49 PM UTC 24
Peak memory 430900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379911002 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.1379911002 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/4.kmac_burst_write.178684875
Short name T330
Test name
Test status
Simulation time 138731488298 ps
CPU time 1073.76 seconds
Started Sep 18 08:03:23 PM UTC 24
Finished Sep 18 08:21:30 PM UTC 24
Peak memory 267072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178684875 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.178684875 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/4.kmac_edn_timeout_error.3634922574
Short name T201
Test name
Test status
Simulation time 110854854 ps
CPU time 8.72 seconds
Started Sep 18 08:04:23 PM UTC 24
Finished Sep 18 08:04:33 PM UTC 24
Peak memory 231396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634922574 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.3634922574 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_mode_error.3980910438
Short name T204
Test name
Test status
Simulation time 5174859631 ps
CPU time 31.25 seconds
Started Sep 18 08:04:25 PM UTC 24
Finished Sep 18 08:04:57 PM UTC 24
Peak memory 234188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980910438 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.3980910438 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_ready_error.3020888538
Short name T202
Test name
Test status
Simulation time 484230379 ps
CPU time 8.11 seconds
Started Sep 18 08:04:30 PM UTC 24
Finished Sep 18 08:04:39 PM UTC 24
Peak memory 229588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020888538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.3020888538 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/4.kmac_entropy_refresh.1990077841
Short name T114
Test name
Test status
Simulation time 31122609295 ps
CPU time 154.68 seconds
Started Sep 18 08:04:14 PM UTC 24
Finished Sep 18 08:06:52 PM UTC 24
Peak memory 314356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990077841 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.1990077841 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/4.kmac_error.3561994724
Short name T55
Test name
Test status
Simulation time 2066431044 ps
CPU time 28.24 seconds
Started Sep 18 08:04:21 PM UTC 24
Finished Sep 18 08:04:51 PM UTC 24
Peak memory 250464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561994724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.3561994724 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/4.kmac_key_error.3791576413
Short name T71
Test name
Test status
Simulation time 920053408 ps
CPU time 5.74 seconds
Started Sep 18 08:04:22 PM UTC 24
Finished Sep 18 08:04:29 PM UTC 24
Peak memory 227232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791576413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.3791576413 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/4.kmac_lc_escalation.3244605353
Short name T44
Test name
Test status
Simulation time 66499786 ps
CPU time 1.72 seconds
Started Sep 18 08:04:44 PM UTC 24
Finished Sep 18 08:04:47 PM UTC 24
Peak memory 226448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244605353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.3244605353 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/4.kmac_long_msg_and_output.4121978799
Short name T151
Test name
Test status
Simulation time 14283476606 ps
CPU time 251.34 seconds
Started Sep 18 08:03:20 PM UTC 24
Finished Sep 18 08:07:36 PM UTC 24
Peak memory 412460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121978799 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and_output.4121978799 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/4.kmac_mubi.3447126973
Short name T35
Test name
Test status
Simulation time 5764111314 ps
CPU time 112.9 seconds
Started Sep 18 08:04:21 PM UTC 24
Finished Sep 18 08:06:17 PM UTC 24
Peak memory 279680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447126973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.3447126973 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/4.kmac_sec_cm.252693293
Short name T78
Test name
Test status
Simulation time 35415164312 ps
CPU time 113.67 seconds
Started Sep 18 08:04:45 PM UTC 24
Finished Sep 18 08:06:41 PM UTC 24
Peak memory 282840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252693293 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.252693293 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/4.kmac_sideload.2283658188
Short name T200
Test name
Test status
Simulation time 6297486928 ps
CPU time 57.24 seconds
Started Sep 18 08:03:22 PM UTC 24
Finished Sep 18 08:04:21 PM UTC 24
Peak memory 260864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283658188 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.2283658188 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/4.kmac_smoke.3903518028
Short name T191
Test name
Test status
Simulation time 135442229 ps
CPU time 9.83 seconds
Started Sep 18 08:03:18 PM UTC 24
Finished Sep 18 08:03:29 PM UTC 24
Peak memory 229588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903518028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.3903518028 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/4.kmac_stress_all.75588555
Short name T88
Test name
Test status
Simulation time 56422823373 ps
CPU time 339.08 seconds
Started Sep 18 08:04:45 PM UTC 24
Finished Sep 18 08:10:29 PM UTC 24
Peak memory 386172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75588555 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.75588555 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac.1831054635
Short name T196
Test name
Test status
Simulation time 265592314 ps
CPU time 3.39 seconds
Started Sep 18 08:04:04 PM UTC 24
Finished Sep 18 08:04:08 PM UTC 24
Peak memory 229536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831054635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac.1831054635 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac_xof.1982646633
Short name T197
Test name
Test status
Simulation time 191318101 ps
CPU time 3.61 seconds
Started Sep 18 08:04:07 PM UTC 24
Finished Sep 18 08:04:12 PM UTC 24
Peak memory 229552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982646633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_v
ectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac_xof.1982646633 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_224.2182078025
Short name T199
Test name
Test status
Simulation time 5317691305 ps
CPU time 53.47 seconds
Started Sep 18 08:03:25 PM UTC 24
Finished Sep 18 08:04:20 PM UTC 24
Peak memory 256692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182078025 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.2182078025
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_256.1951212906
Short name T198
Test name
Test status
Simulation time 3385920741 ps
CPU time 42.57 seconds
Started Sep 18 08:03:29 PM UTC 24
Finished Sep 18 08:04:13 PM UTC 24
Peak memory 234200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951212906 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.1951212906
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_384.500835279
Short name T195
Test name
Test status
Simulation time 4758311695 ps
CPU time 35.37 seconds
Started Sep 18 08:03:29 PM UTC 24
Finished Sep 18 08:04:06 PM UTC 24
Peak memory 238264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500835279 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.500835279 +
enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_512.3978034882
Short name T281
Test name
Test status
Simulation time 18452659025 ps
CPU time 730.12 seconds
Started Sep 18 08:03:29 PM UTC 24
Finished Sep 18 08:15:48 PM UTC 24
Peak memory 697048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978034882 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.3978034882
+enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_128.939320502
Short name T219
Test name
Test status
Simulation time 28541614856 ps
CPU time 321.08 seconds
Started Sep 18 08:03:54 PM UTC 24
Finished Sep 18 08:09:20 PM UTC 24
Peak memory 279216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939320502 -assert nop
ostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.93932050
2 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_256.2104921280
Short name T619
Test name
Test status
Simulation time 343795257229 ps
CPU time 2795.76 seconds
Started Sep 18 08:03:58 PM UTC 24
Finished Sep 18 08:51:06 PM UTC 24
Peak memory 2966180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104921280 -assert no
postproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.2104921
280 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/4.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/40.kmac_alert_test.3468950828
Short name T562
Test name
Test status
Simulation time 29642741 ps
CPU time 1.24 seconds
Started Sep 18 08:45:27 PM UTC 24
Finished Sep 18 08:45:30 PM UTC 24
Peak memory 216388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468950828 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.3468950828 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/40.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/40.kmac_app.1523914156
Short name T579
Test name
Test status
Simulation time 32947027299 ps
CPU time 170.49 seconds
Started Sep 18 08:44:30 PM UTC 24
Finished Sep 18 08:47:23 PM UTC 24
Peak memory 355060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523914156 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.1523914156 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/40.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/40.kmac_burst_write.3225620289
Short name T574
Test name
Test status
Simulation time 7119737457 ps
CPU time 156.4 seconds
Started Sep 18 08:44:19 PM UTC 24
Finished Sep 18 08:46:58 PM UTC 24
Peak memory 244732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225620289 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.3225620289 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/40.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/40.kmac_entropy_refresh.4105880115
Short name T595
Test name
Test status
Simulation time 34939446710 ps
CPU time 263.18 seconds
Started Sep 18 08:44:37 PM UTC 24
Finished Sep 18 08:49:05 PM UTC 24
Peak memory 433116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105880115 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.4105880115 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/40.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/40.kmac_error.843834653
Short name T608
Test name
Test status
Simulation time 18481668527 ps
CPU time 347.45 seconds
Started Sep 18 08:44:56 PM UTC 24
Finished Sep 18 08:50:49 PM UTC 24
Peak memory 379740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843834653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.843834653 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/40.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/40.kmac_key_error.1475443040
Short name T557
Test name
Test status
Simulation time 461605389 ps
CPU time 5.25 seconds
Started Sep 18 08:45:04 PM UTC 24
Finished Sep 18 08:45:10 PM UTC 24
Peak memory 227172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475443040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.1475443040 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/40.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/40.kmac_lc_escalation.2539272501
Short name T559
Test name
Test status
Simulation time 2343450811 ps
CPU time 14.24 seconds
Started Sep 18 08:45:11 PM UTC 24
Finished Sep 18 08:45:27 PM UTC 24
Peak memory 244600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539272501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.2539272501 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/40.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/40.kmac_long_msg_and_output.584982094
Short name T684
Test name
Test status
Simulation time 59515984256 ps
CPU time 831.48 seconds
Started Sep 18 08:44:16 PM UTC 24
Finished Sep 18 08:58:17 PM UTC 24
Peak memory 1176380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584982094 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_and_output.584982094 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/40.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/40.kmac_sideload.2980711259
Short name T597
Test name
Test status
Simulation time 106136661438 ps
CPU time 301.46 seconds
Started Sep 18 08:44:17 PM UTC 24
Finished Sep 18 08:49:23 PM UTC 24
Peak memory 439452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980711259 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.2980711259 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/40.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/40.kmac_smoke.3738486460
Short name T554
Test name
Test status
Simulation time 686260109 ps
CPU time 19.62 seconds
Started Sep 18 08:44:16 PM UTC 24
Finished Sep 18 08:44:36 PM UTC 24
Peak memory 231604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738486460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.3738486460 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/40.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/40.kmac_stress_all.2215214211
Short name T665
Test name
Test status
Simulation time 29117771716 ps
CPU time 626.42 seconds
Started Sep 18 08:45:12 PM UTC 24
Finished Sep 18 08:55:47 PM UTC 24
Peak memory 496804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215214211 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.2215214211 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/40.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/41.kmac_alert_test.2510645750
Short name T571
Test name
Test status
Simulation time 18374635 ps
CPU time 1.16 seconds
Started Sep 18 08:46:46 PM UTC 24
Finished Sep 18 08:46:48 PM UTC 24
Peak memory 216388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510645750 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.2510645750 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/41.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/41.kmac_app.1047152879
Short name T609
Test name
Test status
Simulation time 23632501037 ps
CPU time 281.17 seconds
Started Sep 18 08:46:04 PM UTC 24
Finished Sep 18 08:50:49 PM UTC 24
Peak memory 500788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047152879 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.1047152879 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/41.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/41.kmac_burst_write.2637912845
Short name T641
Test name
Test status
Simulation time 12685372193 ps
CPU time 460.24 seconds
Started Sep 18 08:45:41 PM UTC 24
Finished Sep 18 08:53:27 PM UTC 24
Peak memory 250656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637912845 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.2637912845 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/41.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/41.kmac_entropy_refresh.237736968
Short name T588
Test name
Test status
Simulation time 46414697427 ps
CPU time 123.58 seconds
Started Sep 18 08:46:10 PM UTC 24
Finished Sep 18 08:48:16 PM UTC 24
Peak memory 330496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237736968 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.237736968 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/41.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/41.kmac_error.3788916958
Short name T589
Test name
Test status
Simulation time 11614303242 ps
CPU time 119.04 seconds
Started Sep 18 08:46:21 PM UTC 24
Finished Sep 18 08:48:23 PM UTC 24
Peak memory 349024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788916958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.3788916958 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/41.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/41.kmac_key_error.1289651724
Short name T573
Test name
Test status
Simulation time 789920530 ps
CPU time 8.79 seconds
Started Sep 18 08:46:42 PM UTC 24
Finished Sep 18 08:46:52 PM UTC 24
Peak memory 227272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289651724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.1289651724 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/41.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/41.kmac_lc_escalation.1659492514
Short name T570
Test name
Test status
Simulation time 94692752 ps
CPU time 1.39 seconds
Started Sep 18 08:46:42 PM UTC 24
Finished Sep 18 08:46:45 PM UTC 24
Peak memory 226388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659492514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.1659492514 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/41.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/41.kmac_long_msg_and_output.429087124
Short name T648
Test name
Test status
Simulation time 16314396552 ps
CPU time 504.51 seconds
Started Sep 18 08:45:31 PM UTC 24
Finished Sep 18 08:54:02 PM UTC 24
Peak memory 840500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429087124 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_and_output.429087124 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/41.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/41.kmac_sideload.537048203
Short name T664
Test name
Test status
Simulation time 260310758592 ps
CPU time 607.67 seconds
Started Sep 18 08:45:31 PM UTC 24
Finished Sep 18 08:55:46 PM UTC 24
Peak memory 643832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537048203 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.537048203 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/41.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/41.kmac_smoke.1154830281
Short name T564
Test name
Test status
Simulation time 2783574697 ps
CPU time 33.38 seconds
Started Sep 18 08:45:29 PM UTC 24
Finished Sep 18 08:46:03 PM UTC 24
Peak memory 234076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154830281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.1154830281 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/41.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/41.kmac_stress_all.3714586711
Short name T688
Test name
Test status
Simulation time 34648168726 ps
CPU time 781.21 seconds
Started Sep 18 08:46:45 PM UTC 24
Finished Sep 18 08:59:56 PM UTC 24
Peak memory 627784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714586711 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.3714586711 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/41.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/42.kmac_alert_test.3463244825
Short name T584
Test name
Test status
Simulation time 38866550 ps
CPU time 1.19 seconds
Started Sep 18 08:47:29 PM UTC 24
Finished Sep 18 08:47:31 PM UTC 24
Peak memory 216388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463244825 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.3463244825 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/42.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/42.kmac_app.925732013
Short name T636
Test name
Test status
Simulation time 20069643345 ps
CPU time 349.74 seconds
Started Sep 18 08:47:08 PM UTC 24
Finished Sep 18 08:53:04 PM UTC 24
Peak memory 539704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925732013 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.925732013 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/42.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/42.kmac_burst_write.2525057452
Short name T679
Test name
Test status
Simulation time 18491592745 ps
CPU time 619.62 seconds
Started Sep 18 08:46:59 PM UTC 24
Finished Sep 18 08:57:27 PM UTC 24
Peak memory 252728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525057452 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.2525057452 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/42.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/42.kmac_entropy_refresh.2862924835
Short name T603
Test name
Test status
Simulation time 9401545161 ps
CPU time 174.42 seconds
Started Sep 18 08:47:09 PM UTC 24
Finished Sep 18 08:50:07 PM UTC 24
Peak memory 373560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862924835 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.2862924835 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/42.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/42.kmac_error.653842315
Short name T653
Test name
Test status
Simulation time 13213875273 ps
CPU time 419.57 seconds
Started Sep 18 08:47:21 PM UTC 24
Finished Sep 18 08:54:27 PM UTC 24
Peak memory 606968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653842315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.653842315 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/42.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/42.kmac_key_error.3422237797
Short name T580
Test name
Test status
Simulation time 464989070 ps
CPU time 2.19 seconds
Started Sep 18 08:47:23 PM UTC 24
Finished Sep 18 08:47:26 PM UTC 24
Peak memory 226960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422237797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.3422237797 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/42.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/42.kmac_lc_escalation.3798044689
Short name T581
Test name
Test status
Simulation time 169202572 ps
CPU time 2.08 seconds
Started Sep 18 08:47:25 PM UTC 24
Finished Sep 18 08:47:28 PM UTC 24
Peak memory 227564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798044689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.3798044689 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/42.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/42.kmac_long_msg_and_output.4083500450
Short name T718
Test name
Test status
Simulation time 82936440979 ps
CPU time 2805.06 seconds
Started Sep 18 08:46:50 PM UTC 24
Finished Sep 18 09:34:06 PM UTC 24
Peak memory 3507168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083500450 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_and_output.4083500450 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/42.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/42.kmac_sideload.398283597
Short name T633
Test name
Test status
Simulation time 4772416854 ps
CPU time 358.18 seconds
Started Sep 18 08:46:53 PM UTC 24
Finished Sep 18 08:52:57 PM UTC 24
Peak memory 392028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398283597 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.398283597 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/42.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/42.kmac_smoke.753311412
Short name T583
Test name
Test status
Simulation time 650054771 ps
CPU time 40.38 seconds
Started Sep 18 08:46:49 PM UTC 24
Finished Sep 18 08:47:31 PM UTC 24
Peak memory 231892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753311412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.753311412 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/42.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/42.kmac_stress_all.3361028369
Short name T709
Test name
Test status
Simulation time 84087633462 ps
CPU time 1782.19 seconds
Started Sep 18 08:47:27 PM UTC 24
Finished Sep 18 09:17:28 PM UTC 24
Peak memory 1280796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361028369 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.3361028369 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/42.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/43.kmac_alert_test.425916031
Short name T594
Test name
Test status
Simulation time 113446864 ps
CPU time 1.29 seconds
Started Sep 18 08:49:00 PM UTC 24
Finished Sep 18 08:49:02 PM UTC 24
Peak memory 216508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425916031 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.425916031 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/43.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/43.kmac_app.4072518053
Short name T599
Test name
Test status
Simulation time 2629138955 ps
CPU time 122.94 seconds
Started Sep 18 08:47:37 PM UTC 24
Finished Sep 18 08:49:43 PM UTC 24
Peak memory 271148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072518053 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.4072518053 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/43.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/43.kmac_burst_write.3482649564
Short name T668
Test name
Test status
Simulation time 54009999010 ps
CPU time 501.79 seconds
Started Sep 18 08:47:32 PM UTC 24
Finished Sep 18 08:56:00 PM UTC 24
Peak memory 248620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482649564 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.3482649564 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/43.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/43.kmac_entropy_refresh.3826469762
Short name T650
Test name
Test status
Simulation time 16764421247 ps
CPU time 360.92 seconds
Started Sep 18 08:48:09 PM UTC 24
Finished Sep 18 08:54:16 PM UTC 24
Peak memory 502496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826469762 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.3826469762 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/43.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/43.kmac_error.423905544
Short name T631
Test name
Test status
Simulation time 13168738174 ps
CPU time 258.09 seconds
Started Sep 18 08:48:17 PM UTC 24
Finished Sep 18 08:52:39 PM UTC 24
Peak memory 338744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423905544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.423905544 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/43.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/43.kmac_key_error.2367321800
Short name T590
Test name
Test status
Simulation time 1912110663 ps
CPU time 8.68 seconds
Started Sep 18 08:48:24 PM UTC 24
Finished Sep 18 08:48:33 PM UTC 24
Peak memory 227280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367321800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.2367321800 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/43.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/43.kmac_lc_escalation.912230592
Short name T591
Test name
Test status
Simulation time 168291355 ps
CPU time 2.53 seconds
Started Sep 18 08:48:35 PM UTC 24
Finished Sep 18 08:48:38 PM UTC 24
Peak memory 227632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912230592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.912230592 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/43.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/43.kmac_long_msg_and_output.1876838833
Short name T711
Test name
Test status
Simulation time 19987943876 ps
CPU time 1878.77 seconds
Started Sep 18 08:47:32 PM UTC 24
Finished Sep 18 09:19:12 PM UTC 24
Peak memory 1405696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876838833 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_and_output.1876838833 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/43.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/43.kmac_sideload.2758684811
Short name T651
Test name
Test status
Simulation time 21071175315 ps
CPU time 407.73 seconds
Started Sep 18 08:47:32 PM UTC 24
Finished Sep 18 08:54:25 PM UTC 24
Peak memory 654132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758684811 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.2758684811 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/43.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/43.kmac_smoke.3971840276
Short name T587
Test name
Test status
Simulation time 4842429821 ps
CPU time 36.82 seconds
Started Sep 18 08:47:30 PM UTC 24
Finished Sep 18 08:48:08 PM UTC 24
Peak memory 233984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971840276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.3971840276 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/43.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/43.kmac_stress_all.3745842261
Short name T690
Test name
Test status
Simulation time 39729772400 ps
CPU time 684.74 seconds
Started Sep 18 08:48:39 PM UTC 24
Finished Sep 18 09:00:12 PM UTC 24
Peak memory 545924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745842261 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.3745842261 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/43.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/44.kmac_alert_test.3697825082
Short name T604
Test name
Test status
Simulation time 78695427 ps
CPU time 1.24 seconds
Started Sep 18 08:50:08 PM UTC 24
Finished Sep 18 08:50:10 PM UTC 24
Peak memory 216388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697825082 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.3697825082 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/44.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/44.kmac_app.79176983
Short name T606
Test name
Test status
Simulation time 2002503476 ps
CPU time 62.07 seconds
Started Sep 18 08:49:23 PM UTC 24
Finished Sep 18 08:50:27 PM UTC 24
Peak memory 269280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79176983 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.79176983 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/44.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/44.kmac_burst_write.2313400911
Short name T694
Test name
Test status
Simulation time 51536648270 ps
CPU time 791.7 seconds
Started Sep 18 08:49:09 PM UTC 24
Finished Sep 18 09:02:31 PM UTC 24
Peak memory 258812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313400911 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.2313400911 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/44.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/44.kmac_entropy_refresh.4184213751
Short name T612
Test name
Test status
Simulation time 3051699638 ps
CPU time 84.33 seconds
Started Sep 18 08:49:26 PM UTC 24
Finished Sep 18 08:50:53 PM UTC 24
Peak memory 277496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184213751 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.4184213751 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/44.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/44.kmac_error.2807771648
Short name T676
Test name
Test status
Simulation time 20290486357 ps
CPU time 421.39 seconds
Started Sep 18 08:49:44 PM UTC 24
Finished Sep 18 08:56:51 PM UTC 24
Peak memory 387936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807771648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.2807771648 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/44.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/44.kmac_key_error.1459057009
Short name T601
Test name
Test status
Simulation time 446751466 ps
CPU time 5.11 seconds
Started Sep 18 08:49:44 PM UTC 24
Finished Sep 18 08:49:50 PM UTC 24
Peak memory 227176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459057009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.1459057009 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/44.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/44.kmac_lc_escalation.2687360670
Short name T602
Test name
Test status
Simulation time 58716951 ps
CPU time 2.22 seconds
Started Sep 18 08:49:51 PM UTC 24
Finished Sep 18 08:49:54 PM UTC 24
Peak memory 227300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687360670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.2687360670 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/44.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/44.kmac_long_msg_and_output.741350252
Short name T707
Test name
Test status
Simulation time 35111173212 ps
CPU time 1619.73 seconds
Started Sep 18 08:49:03 PM UTC 24
Finished Sep 18 09:16:21 PM UTC 24
Peak memory 1334272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741350252 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_and_output.741350252 +enable_mask
ing=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/44.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/44.kmac_sideload.1706101430
Short name T598
Test name
Test status
Simulation time 203750410 ps
CPU time 17.96 seconds
Started Sep 18 08:49:06 PM UTC 24
Finished Sep 18 08:49:26 PM UTC 24
Peak memory 234172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706101430 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.1706101430 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/44.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/44.kmac_smoke.392444847
Short name T600
Test name
Test status
Simulation time 5595875286 ps
CPU time 39.08 seconds
Started Sep 18 08:49:02 PM UTC 24
Finished Sep 18 08:49:43 PM UTC 24
Peak memory 234128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392444847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.392444847 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/44.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/44.kmac_stress_all.1705258725
Short name T640
Test name
Test status
Simulation time 13917368753 ps
CPU time 188.92 seconds
Started Sep 18 08:49:55 PM UTC 24
Finished Sep 18 08:53:07 PM UTC 24
Peak memory 474168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705258725 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.1705258725 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/44.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/45.kmac_alert_test.247512115
Short name T615
Test name
Test status
Simulation time 20739099 ps
CPU time 1.31 seconds
Started Sep 18 08:50:57 PM UTC 24
Finished Sep 18 08:50:59 PM UTC 24
Peak memory 216508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247512115 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.247512115 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/45.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/45.kmac_app.1187037828
Short name T656
Test name
Test status
Simulation time 44153261396 ps
CPU time 249.33 seconds
Started Sep 18 08:50:49 PM UTC 24
Finished Sep 18 08:55:03 PM UTC 24
Peak memory 434992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187037828 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.1187037828 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/45.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/45.kmac_burst_write.1522703844
Short name T687
Test name
Test status
Simulation time 58870935470 ps
CPU time 543.96 seconds
Started Sep 18 08:50:35 PM UTC 24
Finished Sep 18 08:59:46 PM UTC 24
Peak memory 252704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522703844 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.1522703844 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/45.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/45.kmac_entropy_refresh.1006472013
Short name T620
Test name
Test status
Simulation time 2356105807 ps
CPU time 16.06 seconds
Started Sep 18 08:50:51 PM UTC 24
Finished Sep 18 08:51:08 PM UTC 24
Peak memory 244476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006472013 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.1006472013 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/45.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/45.kmac_error.1013039168
Short name T655
Test name
Test status
Simulation time 7669549479 ps
CPU time 232.82 seconds
Started Sep 18 08:50:51 PM UTC 24
Finished Sep 18 08:54:47 PM UTC 24
Peak memory 430876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013039168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.1013039168 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/45.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/45.kmac_key_error.604110341
Short name T618
Test name
Test status
Simulation time 1790176419 ps
CPU time 12.49 seconds
Started Sep 18 08:50:52 PM UTC 24
Finished Sep 18 08:51:05 PM UTC 24
Peak memory 227176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604110341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.604110341 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/45.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/45.kmac_lc_escalation.1491288175
Short name T614
Test name
Test status
Simulation time 74859095 ps
CPU time 1.75 seconds
Started Sep 18 08:50:54 PM UTC 24
Finished Sep 18 08:50:57 PM UTC 24
Peak memory 226424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491288175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.1491288175 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/45.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/45.kmac_long_msg_and_output.3958464450
Short name T680
Test name
Test status
Simulation time 10282288521 ps
CPU time 433.88 seconds
Started Sep 18 08:50:16 PM UTC 24
Finished Sep 18 08:57:35 PM UTC 24
Peak memory 560120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958464450 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_and_output.3958464450 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/45.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/45.kmac_smoke.867337126
Short name T617
Test name
Test status
Simulation time 2873518905 ps
CPU time 50.11 seconds
Started Sep 18 08:50:11 PM UTC 24
Finished Sep 18 08:51:03 PM UTC 24
Peak memory 234328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867337126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.867337126 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/45.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/45.kmac_stress_all.355741750
Short name T691
Test name
Test status
Simulation time 66283142473 ps
CPU time 662.59 seconds
Started Sep 18 08:50:55 PM UTC 24
Finished Sep 18 09:02:06 PM UTC 24
Peak memory 382016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355741750 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.355741750 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/45.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/46.kmac_alert_test.7048753
Short name T626
Test name
Test status
Simulation time 33416387 ps
CPU time 1.18 seconds
Started Sep 18 08:51:41 PM UTC 24
Finished Sep 18 08:51:43 PM UTC 24
Peak memory 216396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7048753 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.7048753 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/46.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/46.kmac_app.3154848452
Short name T637
Test name
Test status
Simulation time 3409186190 ps
CPU time 115.18 seconds
Started Sep 18 08:51:06 PM UTC 24
Finished Sep 18 08:53:04 PM UTC 24
Peak memory 267316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154848452 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.3154848452 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/46.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/46.kmac_burst_write.1144020173
Short name T696
Test name
Test status
Simulation time 44843600590 ps
CPU time 756.12 seconds
Started Sep 18 08:51:06 PM UTC 24
Finished Sep 18 09:03:53 PM UTC 24
Peak memory 256816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144020173 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.1144020173 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/46.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/46.kmac_entropy_refresh.3301624693
Short name T662
Test name
Test status
Simulation time 44299226428 ps
CPU time 254.26 seconds
Started Sep 18 08:51:09 PM UTC 24
Finished Sep 18 08:55:27 PM UTC 24
Peak memory 430944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301624693 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.3301624693 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/46.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/46.kmac_error.983555949
Short name T622
Test name
Test status
Simulation time 376736722 ps
CPU time 9.11 seconds
Started Sep 18 08:51:11 PM UTC 24
Finished Sep 18 08:51:21 PM UTC 24
Peak memory 234108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983555949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.983555949 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/46.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/46.kmac_key_error.138448803
Short name T623
Test name
Test status
Simulation time 606521305 ps
CPU time 3.79 seconds
Started Sep 18 08:51:22 PM UTC 24
Finished Sep 18 08:51:27 PM UTC 24
Peak memory 227176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138448803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.138448803 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/46.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/46.kmac_lc_escalation.2382563342
Short name T624
Test name
Test status
Simulation time 96966720 ps
CPU time 2.02 seconds
Started Sep 18 08:51:28 PM UTC 24
Finished Sep 18 08:51:31 PM UTC 24
Peak memory 227628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382563342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.2382563342 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/46.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/46.kmac_long_msg_and_output.1707319178
Short name T667
Test name
Test status
Simulation time 3089566272 ps
CPU time 287.17 seconds
Started Sep 18 08:51:01 PM UTC 24
Finished Sep 18 08:55:53 PM UTC 24
Peak memory 432892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707319178 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_and_output.1707319178 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/46.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/46.kmac_sideload.824137212
Short name T643
Test name
Test status
Simulation time 3702894743 ps
CPU time 150.71 seconds
Started Sep 18 08:51:04 PM UTC 24
Finished Sep 18 08:53:38 PM UTC 24
Peak memory 296028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824137212 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.824137212 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/46.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/46.kmac_smoke.362184427
Short name T625
Test name
Test status
Simulation time 3103616770 ps
CPU time 38.47 seconds
Started Sep 18 08:51:00 PM UTC 24
Finished Sep 18 08:51:40 PM UTC 24
Peak memory 233768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362184427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.362184427 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/46.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/46.kmac_stress_all.3237784738
Short name T699
Test name
Test status
Simulation time 65831361436 ps
CPU time 840.6 seconds
Started Sep 18 08:51:32 PM UTC 24
Finished Sep 18 09:05:43 PM UTC 24
Peak memory 1266428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237784738 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.3237784738 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/46.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/47.kmac_alert_test.715926467
Short name T639
Test name
Test status
Simulation time 34106455 ps
CPU time 1.32 seconds
Started Sep 18 08:53:04 PM UTC 24
Finished Sep 18 08:53:07 PM UTC 24
Peak memory 216508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715926467 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.715926467 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/47.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/47.kmac_app.1328979870
Short name T683
Test name
Test status
Simulation time 13555370825 ps
CPU time 332.52 seconds
Started Sep 18 08:52:30 PM UTC 24
Finished Sep 18 08:58:07 PM UTC 24
Peak memory 500572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328979870 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.1328979870 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/47.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/47.kmac_burst_write.1704599090
Short name T685
Test name
Test status
Simulation time 33871856923 ps
CPU time 350.33 seconds
Started Sep 18 08:52:26 PM UTC 24
Finished Sep 18 08:58:21 PM UTC 24
Peak memory 246584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704599090 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.1704599090 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/47.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/47.kmac_entropy_refresh.3243921151
Short name T663
Test name
Test status
Simulation time 10318859102 ps
CPU time 179.25 seconds
Started Sep 18 08:52:40 PM UTC 24
Finished Sep 18 08:55:42 PM UTC 24
Peak memory 297756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243921151 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.3243921151 +enable_masking=0 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/47.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/47.kmac_error.2310352909
Short name T642
Test name
Test status
Simulation time 1330626271 ps
CPU time 36.79 seconds
Started Sep 18 08:52:54 PM UTC 24
Finished Sep 18 08:53:32 PM UTC 24
Peak memory 260768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310352909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.2310352909 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/47.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/47.kmac_key_error.3958550480
Short name T638
Test name
Test status
Simulation time 805437438 ps
CPU time 7.39 seconds
Started Sep 18 08:52:57 PM UTC 24
Finished Sep 18 08:53:06 PM UTC 24
Peak memory 227204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958550480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.3958550480 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/47.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/47.kmac_lc_escalation.1395609165
Short name T635
Test name
Test status
Simulation time 47250724 ps
CPU time 1.69 seconds
Started Sep 18 08:52:59 PM UTC 24
Finished Sep 18 08:53:02 PM UTC 24
Peak memory 226388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395609165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.1395609165 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/47.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/47.kmac_long_msg_and_output.1785649787
Short name T670
Test name
Test status
Simulation time 2742827496 ps
CPU time 233.89 seconds
Started Sep 18 08:52:13 PM UTC 24
Finished Sep 18 08:56:11 PM UTC 24
Peak memory 375776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785649787 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_and_output.1785649787 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/47.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/47.kmac_sideload.1566373094
Short name T644
Test name
Test status
Simulation time 8394261299 ps
CPU time 78.27 seconds
Started Sep 18 08:52:18 PM UTC 24
Finished Sep 18 08:53:39 PM UTC 24
Peak memory 287484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566373094 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.1566373094 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/47.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/47.kmac_smoke.836197520
Short name T628
Test name
Test status
Simulation time 3849904932 ps
CPU time 31.3 seconds
Started Sep 18 08:51:44 PM UTC 24
Finished Sep 18 08:52:17 PM UTC 24
Peak memory 233944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836197520 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.836197520 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/47.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/47.kmac_stress_all.2747899797
Short name T682
Test name
Test status
Simulation time 16563384056 ps
CPU time 297.65 seconds
Started Sep 18 08:53:02 PM UTC 24
Finished Sep 18 08:58:04 PM UTC 24
Peak memory 281664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747899797 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.2747899797 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/47.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/48.kmac_alert_test.3299574413
Short name T649
Test name
Test status
Simulation time 207995105 ps
CPU time 1.28 seconds
Started Sep 18 08:54:01 PM UTC 24
Finished Sep 18 08:54:04 PM UTC 24
Peak memory 216388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299574413 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.3299574413 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/48.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/48.kmac_app.871398986
Short name T654
Test name
Test status
Simulation time 2847698168 ps
CPU time 66.34 seconds
Started Sep 18 08:53:28 PM UTC 24
Finished Sep 18 08:54:36 PM UTC 24
Peak memory 273396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871398986 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.871398986 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/48.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/48.kmac_burst_write.3111404567
Short name T700
Test name
Test status
Simulation time 114882949173 ps
CPU time 752.56 seconds
Started Sep 18 08:53:08 PM UTC 24
Finished Sep 18 09:05:50 PM UTC 24
Peak memory 261152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111404567 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.3111404567 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/48.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/48.kmac_entropy_refresh.921141477
Short name T673
Test name
Test status
Simulation time 8306052354 ps
CPU time 177.57 seconds
Started Sep 18 08:53:33 PM UTC 24
Finished Sep 18 08:56:34 PM UTC 24
Peak memory 330560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921141477 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.921141477 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/48.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/48.kmac_error.1590659387
Short name T666
Test name
Test status
Simulation time 10619111033 ps
CPU time 131.21 seconds
Started Sep 18 08:53:39 PM UTC 24
Finished Sep 18 08:55:53 PM UTC 24
Peak memory 341048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590659387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.1590659387 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/48.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/48.kmac_key_error.3952846565
Short name T646
Test name
Test status
Simulation time 67194493 ps
CPU time 1.73 seconds
Started Sep 18 08:53:40 PM UTC 24
Finished Sep 18 08:53:43 PM UTC 24
Peak memory 226372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952846565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.3952846565 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/48.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/48.kmac_lc_escalation.979679609
Short name T647
Test name
Test status
Simulation time 647108581 ps
CPU time 18.38 seconds
Started Sep 18 08:53:41 PM UTC 24
Finished Sep 18 08:54:01 PM UTC 24
Peak memory 234500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979679609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.979679609 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/48.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/48.kmac_long_msg_and_output.3363483277
Short name T719
Test name
Test status
Simulation time 107984260674 ps
CPU time 2809.77 seconds
Started Sep 18 08:53:06 PM UTC 24
Finished Sep 18 09:40:28 PM UTC 24
Peak memory 1897364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363483277 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_and_output.3363483277 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/48.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/48.kmac_sideload.2010453488
Short name T678
Test name
Test status
Simulation time 9964825410 ps
CPU time 255.35 seconds
Started Sep 18 08:53:08 PM UTC 24
Finished Sep 18 08:57:27 PM UTC 24
Peak memory 471864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010453488 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.2010453488 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/48.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/48.kmac_smoke.3163677536
Short name T645
Test name
Test status
Simulation time 1872567211 ps
CPU time 33.16 seconds
Started Sep 18 08:53:05 PM UTC 24
Finished Sep 18 08:53:40 PM UTC 24
Peak memory 231572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163677536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.3163677536 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/48.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/48.kmac_stress_all.2592795560
Short name T674
Test name
Test status
Simulation time 4400070182 ps
CPU time 176.28 seconds
Started Sep 18 08:53:43 PM UTC 24
Finished Sep 18 08:56:43 PM UTC 24
Peak memory 265336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592795560 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.2592795560 +enable_masking=0
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/48.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/49.kmac_alert_test.1239080635
Short name T660
Test name
Test status
Simulation time 18258655 ps
CPU time 1.27 seconds
Started Sep 18 08:55:08 PM UTC 24
Finished Sep 18 08:55:10 PM UTC 24
Peak memory 216388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239080635 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.1239080635 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/49.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/49.kmac_app.4094465485
Short name T661
Test name
Test status
Simulation time 4514391512 ps
CPU time 49.24 seconds
Started Sep 18 08:54:27 PM UTC 24
Finished Sep 18 08:55:18 PM UTC 24
Peak memory 250608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094465485 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.4094465485 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/49.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/49.kmac_burst_write.338037259
Short name T697
Test name
Test status
Simulation time 23137714495 ps
CPU time 631.46 seconds
Started Sep 18 08:54:26 PM UTC 24
Finished Sep 18 09:05:06 PM UTC 24
Peak memory 246524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338037259 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.338037259 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/49.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/49.kmac_entropy_refresh.305776356
Short name T689
Test name
Test status
Simulation time 16763967435 ps
CPU time 329.96 seconds
Started Sep 18 08:54:28 PM UTC 24
Finished Sep 18 09:00:03 PM UTC 24
Peak memory 514880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305776356 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.305776356 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/49.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/49.kmac_error.3953652090
Short name T672
Test name
Test status
Simulation time 5227741662 ps
CPU time 105.83 seconds
Started Sep 18 08:54:37 PM UTC 24
Finished Sep 18 08:56:25 PM UTC 24
Peak memory 283388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953652090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.3953652090 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/49.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/49.kmac_key_error.4123587319
Short name T657
Test name
Test status
Simulation time 1807057478 ps
CPU time 16 seconds
Started Sep 18 08:54:48 PM UTC 24
Finished Sep 18 08:55:05 PM UTC 24
Peak memory 227448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123587319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.4123587319 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/49.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/49.kmac_lc_escalation.3836468912
Short name T658
Test name
Test status
Simulation time 131243204 ps
CPU time 1.73 seconds
Started Sep 18 08:55:03 PM UTC 24
Finished Sep 18 08:55:06 PM UTC 24
Peak memory 226364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836468912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.3836468912 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/49.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/49.kmac_long_msg_and_output.3655200945
Short name T720
Test name
Test status
Simulation time 114252201339 ps
CPU time 3424.59 seconds
Started Sep 18 08:54:05 PM UTC 24
Finished Sep 18 09:51:47 PM UTC 24
Peak memory 3959708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655200945 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_and_output.3655200945 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/49.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/49.kmac_sideload.2389258662
Short name T677
Test name
Test status
Simulation time 5925818088 ps
CPU time 158.04 seconds
Started Sep 18 08:54:17 PM UTC 24
Finished Sep 18 08:56:58 PM UTC 24
Peak memory 342832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389258662 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.2389258662 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/49.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/49.kmac_smoke.2723992659
Short name T652
Test name
Test status
Simulation time 305663415 ps
CPU time 21.31 seconds
Started Sep 18 08:54:03 PM UTC 24
Finished Sep 18 08:54:26 PM UTC 24
Peak memory 231580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723992659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.2723992659 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/49.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/49.kmac_stress_all.946735727
Short name T703
Test name
Test status
Simulation time 74220624853 ps
CPU time 701.96 seconds
Started Sep 18 08:55:06 PM UTC 24
Finished Sep 18 09:06:57 PM UTC 24
Peak memory 1233964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946735727 -assert nopos
tproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.946735727 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/49.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/5.kmac_alert_test.326488766
Short name T205
Test name
Test status
Simulation time 35788214 ps
CPU time 1.18 seconds
Started Sep 18 08:06:19 PM UTC 24
Finished Sep 18 08:06:21 PM UTC 24
Peak memory 216452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326488766 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.326488766 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/5.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/5.kmac_app.348446098
Short name T34
Test name
Test status
Simulation time 4796834859 ps
CPU time 96.05 seconds
Started Sep 18 08:05:18 PM UTC 24
Finished Sep 18 08:06:56 PM UTC 24
Peak memory 308320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348446098 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.348446098 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/5.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/5.kmac_app_with_partial_data.4027113208
Short name T230
Test name
Test status
Simulation time 19349195568 ps
CPU time 344.97 seconds
Started Sep 18 08:05:19 PM UTC 24
Finished Sep 18 08:11:08 PM UTC 24
Peak memory 539488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027113208 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.4027113208 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/5.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/5.kmac_burst_write.1431210523
Short name T53
Test name
Test status
Simulation time 35582090348 ps
CPU time 966.51 seconds
Started Sep 18 08:04:59 PM UTC 24
Finished Sep 18 08:21:18 PM UTC 24
Peak memory 252672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431210523 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.1431210523 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/5.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/5.kmac_edn_timeout_error.3423702650
Short name T131
Test name
Test status
Simulation time 496451205 ps
CPU time 9.45 seconds
Started Sep 18 08:05:53 PM UTC 24
Finished Sep 18 08:06:04 PM UTC 24
Peak memory 233320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423702650 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.3423702650 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/5.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_mode_error.4294518861
Short name T207
Test name
Test status
Simulation time 1878619689 ps
CPU time 52.07 seconds
Started Sep 18 08:06:04 PM UTC 24
Finished Sep 18 08:06:58 PM UTC 24
Peak memory 233872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294518861 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.4294518861 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/5.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_ready_error.3218905581
Short name T208
Test name
Test status
Simulation time 4951207432 ps
CPU time 54.17 seconds
Started Sep 18 08:06:06 PM UTC 24
Finished Sep 18 08:07:01 PM UTC 24
Peak memory 234396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218905581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.3218905581 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/5.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/5.kmac_entropy_refresh.3668014288
Short name T113
Test name
Test status
Simulation time 1548826570 ps
CPU time 63.1 seconds
Started Sep 18 08:05:26 PM UTC 24
Finished Sep 18 08:06:31 PM UTC 24
Peak memory 256728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668014288 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.3668014288 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/5.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/5.kmac_error.3346781299
Short name T163
Test name
Test status
Simulation time 2465149286 ps
CPU time 187.77 seconds
Started Sep 18 08:05:42 PM UTC 24
Finished Sep 18 08:08:53 PM UTC 24
Peak memory 326448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346781299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.3346781299 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/5.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/5.kmac_key_error.2406146566
Short name T72
Test name
Test status
Simulation time 1268782595 ps
CPU time 13.81 seconds
Started Sep 18 08:05:49 PM UTC 24
Finished Sep 18 08:06:04 PM UTC 24
Peak memory 227172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406146566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.2406146566 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/5.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/5.kmac_lc_escalation.2825769135
Short name T69
Test name
Test status
Simulation time 101034413 ps
CPU time 1.65 seconds
Started Sep 18 08:06:08 PM UTC 24
Finished Sep 18 08:06:10 PM UTC 24
Peak memory 226488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825769135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.2825769135 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/5.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/5.kmac_long_msg_and_output.1847182408
Short name T499
Test name
Test status
Simulation time 62486401307 ps
CPU time 2042.11 seconds
Started Sep 18 08:04:51 PM UTC 24
Finished Sep 18 08:39:17 PM UTC 24
Peak memory 2466676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847182408 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and_output.1847182408 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/5.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/5.kmac_mubi.3435372840
Short name T86
Test name
Test status
Simulation time 622029437 ps
CPU time 8.74 seconds
Started Sep 18 08:05:32 PM UTC 24
Finished Sep 18 08:05:42 PM UTC 24
Peak memory 234432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435372840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.3435372840 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/5.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/5.kmac_sideload.3787305644
Short name T129
Test name
Test status
Simulation time 780043733 ps
CPU time 38.54 seconds
Started Sep 18 08:04:52 PM UTC 24
Finished Sep 18 08:05:32 PM UTC 24
Peak memory 244612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787305644 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.3787305644 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/5.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/5.kmac_smoke.148307904
Short name T130
Test name
Test status
Simulation time 3640076109 ps
CPU time 62.84 seconds
Started Sep 18 08:04:47 PM UTC 24
Finished Sep 18 08:05:53 PM UTC 24
Peak memory 233784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148307904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.148307904 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/5.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/5.kmac_stress_all.3191499082
Short name T365
Test name
Test status
Simulation time 35242918394 ps
CPU time 1070.21 seconds
Started Sep 18 08:06:11 PM UTC 24
Finished Sep 18 08:24:14 PM UTC 24
Peak memory 1379060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191499082 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.3191499082 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/5.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/6.kmac_alert_test.596626349
Short name T148
Test name
Test status
Simulation time 27501554 ps
CPU time 1 seconds
Started Sep 18 08:07:08 PM UTC 24
Finished Sep 18 08:07:10 PM UTC 24
Peak memory 216452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596626349 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.596626349 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/6.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/6.kmac_app.616963154
Short name T222
Test name
Test status
Simulation time 40173167788 ps
CPU time 211.28 seconds
Started Sep 18 08:06:33 PM UTC 24
Finished Sep 18 08:10:08 PM UTC 24
Peak memory 402272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616963154 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.616963154 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/6.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/6.kmac_app_with_partial_data.3857200095
Short name T229
Test name
Test status
Simulation time 17427561178 ps
CPU time 263.08 seconds
Started Sep 18 08:06:37 PM UTC 24
Finished Sep 18 08:11:04 PM UTC 24
Peak memory 343072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857200095 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.3857200095 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/6.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/6.kmac_burst_write.3387860103
Short name T319
Test name
Test status
Simulation time 22660708621 ps
CPU time 808.13 seconds
Started Sep 18 08:06:32 PM UTC 24
Finished Sep 18 08:20:11 PM UTC 24
Peak memory 267004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387860103 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.3387860103 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/6.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/6.kmac_edn_timeout_error.2775918876
Short name T153
Test name
Test status
Simulation time 1544595972 ps
CPU time 42.88 seconds
Started Sep 18 08:06:57 PM UTC 24
Finished Sep 18 08:07:42 PM UTC 24
Peak memory 233880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775918876 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.2775918876 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/6.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_mode_error.3611557007
Short name T211
Test name
Test status
Simulation time 13636115542 ps
CPU time 47.97 seconds
Started Sep 18 08:06:59 PM UTC 24
Finished Sep 18 08:07:49 PM UTC 24
Peak memory 234252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611557007 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.3611557007 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/6.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_ready_error.3127820487
Short name T150
Test name
Test status
Simulation time 3499611597 ps
CPU time 27.96 seconds
Started Sep 18 08:07:03 PM UTC 24
Finished Sep 18 08:07:33 PM UTC 24
Peak memory 234236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127820487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.3127820487 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/6.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/6.kmac_entropy_refresh.1945937856
Short name T233
Test name
Test status
Simulation time 29495024334 ps
CPU time 286.27 seconds
Started Sep 18 08:06:41 PM UTC 24
Finished Sep 18 08:11:31 PM UTC 24
Peak memory 344884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945937856 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.1945937856 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/6.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/6.kmac_error.3925178778
Short name T162
Test name
Test status
Simulation time 47790800284 ps
CPU time 357.49 seconds
Started Sep 18 08:06:53 PM UTC 24
Finished Sep 18 08:12:56 PM UTC 24
Peak memory 541432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925178778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.3925178778 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/6.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/6.kmac_key_error.1155632402
Short name T73
Test name
Test status
Simulation time 919765232 ps
CPU time 6.22 seconds
Started Sep 18 08:06:55 PM UTC 24
Finished Sep 18 08:07:02 PM UTC 24
Peak memory 227464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155632402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.1155632402 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/6.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/6.kmac_lc_escalation.66139084
Short name T140
Test name
Test status
Simulation time 26009674 ps
CPU time 2.32 seconds
Started Sep 18 08:07:03 PM UTC 24
Finished Sep 18 08:07:07 PM UTC 24
Peak memory 229352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66139084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.66139084 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/6.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/6.kmac_long_msg_and_output.980666455
Short name T613
Test name
Test status
Simulation time 276379443836 ps
CPU time 2641.97 seconds
Started Sep 18 08:06:22 PM UTC 24
Finished Sep 18 08:50:54 PM UTC 24
Peak memory 3378008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980666455 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_and_output.980666455 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/6.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/6.kmac_mubi.1549381065
Short name T159
Test name
Test status
Simulation time 69709890532 ps
CPU time 369.64 seconds
Started Sep 18 08:06:43 PM UTC 24
Finished Sep 18 08:12:58 PM UTC 24
Peak memory 523384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549381065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.1549381065 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/6.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/6.kmac_sideload.3352773698
Short name T264
Test name
Test status
Simulation time 12192433057 ps
CPU time 459.08 seconds
Started Sep 18 08:06:24 PM UTC 24
Finished Sep 18 08:14:10 PM UTC 24
Peak memory 559872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352773698 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.3352773698 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/6.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/6.kmac_smoke.1132759530
Short name T149
Test name
Test status
Simulation time 1719266448 ps
CPU time 55.62 seconds
Started Sep 18 08:06:21 PM UTC 24
Finished Sep 18 08:07:18 PM UTC 24
Peak memory 233900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132759530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.1132759530 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/6.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/6.kmac_stress_all.3491644115
Short name T141
Test name
Test status
Simulation time 14588918906 ps
CPU time 381.97 seconds
Started Sep 18 08:07:08 PM UTC 24
Finished Sep 18 08:13:35 PM UTC 24
Peak memory 365688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491644115 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.3491644115 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/6.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/6.kmac_stress_all_with_rand_reset.1944115365
Short name T59
Test name
Test status
Simulation time 2480070505 ps
CPU time 60.34 seconds
Started Sep 18 08:07:08 PM UTC 24
Finished Sep 18 08:08:10 PM UTC 24
Peak memory 261244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres
s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1944115365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all_
with_rand_reset.1944115365 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/7.kmac_alert_test.344337117
Short name T216
Test name
Test status
Simulation time 50397676 ps
CPU time 1.19 seconds
Started Sep 18 08:07:59 PM UTC 24
Finished Sep 18 08:08:01 PM UTC 24
Peak memory 216452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344337117 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.344337117 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/7.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/7.kmac_app.1383464768
Short name T236
Test name
Test status
Simulation time 4888778466 ps
CPU time 264.89 seconds
Started Sep 18 08:07:19 PM UTC 24
Finished Sep 18 08:11:48 PM UTC 24
Peak memory 340784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383464768 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.1383464768 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/7.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/7.kmac_app_with_partial_data.2691859142
Short name T242
Test name
Test status
Simulation time 53002167105 ps
CPU time 273.82 seconds
Started Sep 18 08:07:33 PM UTC 24
Finished Sep 18 08:12:11 PM UTC 24
Peak memory 494384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691859142 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.2691859142 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/7.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/7.kmac_burst_write.3307798803
Short name T189
Test name
Test status
Simulation time 25594303517 ps
CPU time 595.56 seconds
Started Sep 18 08:07:18 PM UTC 24
Finished Sep 18 08:17:22 PM UTC 24
Peak memory 248576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307798803 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.3307798803 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/7.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/7.kmac_edn_timeout_error.177748592
Short name T214
Test name
Test status
Simulation time 70719138 ps
CPU time 7.37 seconds
Started Sep 18 08:07:47 PM UTC 24
Finished Sep 18 08:07:55 PM UTC 24
Peak memory 227236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177748592 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.177748592 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/7.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_mode_error.1812962820
Short name T215
Test name
Test status
Simulation time 108177499 ps
CPU time 9.97 seconds
Started Sep 18 08:07:50 PM UTC 24
Finished Sep 18 08:08:01 PM UTC 24
Peak memory 233668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812962820 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.1812962820 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/7.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_ready_error.1293445225
Short name T156
Test name
Test status
Simulation time 18357151815 ps
CPU time 42.21 seconds
Started Sep 18 08:07:50 PM UTC 24
Finished Sep 18 08:08:33 PM UTC 24
Peak memory 234488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293445225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.1293445225 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/7.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/7.kmac_entropy_refresh.3655981354
Short name T257
Test name
Test status
Simulation time 42879081058 ps
CPU time 357.46 seconds
Started Sep 18 08:07:35 PM UTC 24
Finished Sep 18 08:13:38 PM UTC 24
Peak memory 506696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655981354 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.3655981354 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/7.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/7.kmac_error.4207210041
Short name T161
Test name
Test status
Simulation time 26305416813 ps
CPU time 135.96 seconds
Started Sep 18 08:07:41 PM UTC 24
Finished Sep 18 08:09:59 PM UTC 24
Peak memory 332592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207210041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.4207210041 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/7.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/7.kmac_key_error.2853819981
Short name T74
Test name
Test status
Simulation time 941993050 ps
CPU time 10 seconds
Started Sep 18 08:07:43 PM UTC 24
Finished Sep 18 08:07:54 PM UTC 24
Peak memory 227172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853819981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.2853819981 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/7.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/7.kmac_lc_escalation.752102889
Short name T7
Test name
Test status
Simulation time 71230246 ps
CPU time 1.83 seconds
Started Sep 18 08:07:55 PM UTC 24
Finished Sep 18 08:07:58 PM UTC 24
Peak memory 226328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752102889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.752102889 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/7.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/7.kmac_long_msg_and_output.708722062
Short name T303
Test name
Test status
Simulation time 116952869799 ps
CPU time 665.65 seconds
Started Sep 18 08:07:12 PM UTC 24
Finished Sep 18 08:18:26 PM UTC 24
Peak memory 1094388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708722062 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_and_output.708722062 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/7.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/7.kmac_mubi.1186091071
Short name T89
Test name
Test status
Simulation time 21011974619 ps
CPU time 258.11 seconds
Started Sep 18 08:07:36 PM UTC 24
Finished Sep 18 08:11:58 PM UTC 24
Peak memory 447648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186091071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.1186091071 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/7.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/7.kmac_sideload.2231094058
Short name T213
Test name
Test status
Simulation time 1414780076 ps
CPU time 40.04 seconds
Started Sep 18 08:07:13 PM UTC 24
Finished Sep 18 08:07:55 PM UTC 24
Peak memory 252548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231094058 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.2231094058 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/7.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/7.kmac_smoke.1905965214
Short name T154
Test name
Test status
Simulation time 1113277967 ps
CPU time 34.54 seconds
Started Sep 18 08:07:10 PM UTC 24
Finished Sep 18 08:07:46 PM UTC 24
Peak memory 231532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905965214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.1905965214 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/7.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/7.kmac_stress_all.1527074166
Short name T253
Test name
Test status
Simulation time 60894845995 ps
CPU time 313.47 seconds
Started Sep 18 08:07:55 PM UTC 24
Finished Sep 18 08:13:13 PM UTC 24
Peak memory 480028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527074166 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.1527074166 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/7.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/7.kmac_stress_all_with_rand_reset.3797100123
Short name T87
Test name
Test status
Simulation time 7481054690 ps
CPU time 54.37 seconds
Started Sep 18 08:07:56 PM UTC 24
Finished Sep 18 08:08:52 PM UTC 24
Peak memory 261260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stres
s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3797100123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all_
with_rand_reset.3797100123 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/8.kmac_alert_test.1378311375
Short name T224
Test name
Test status
Simulation time 35874845 ps
CPU time 1.34 seconds
Started Sep 18 08:10:14 PM UTC 24
Finished Sep 18 08:10:16 PM UTC 24
Peak memory 216508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378311375 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.1378311375 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/8.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/8.kmac_app.2303658244
Short name T249
Test name
Test status
Simulation time 19843867558 ps
CPU time 224.64 seconds
Started Sep 18 08:08:53 PM UTC 24
Finished Sep 18 08:12:41 PM UTC 24
Peak memory 330480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303658244 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.2303658244 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/8.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/8.kmac_app_with_partial_data.2586066355
Short name T218
Test name
Test status
Simulation time 238310487 ps
CPU time 21.58 seconds
Started Sep 18 08:08:54 PM UTC 24
Finished Sep 18 08:09:17 PM UTC 24
Peak memory 244668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586066355 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.2586066355 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/8.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/8.kmac_burst_write.3431815078
Short name T377
Test name
Test status
Simulation time 126500709361 ps
CPU time 1000.98 seconds
Started Sep 18 08:08:35 PM UTC 24
Finished Sep 18 08:25:28 PM UTC 24
Peak memory 269312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431815078 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.3431815078 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/8.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/8.kmac_edn_timeout_error.2919821546
Short name T220
Test name
Test status
Simulation time 2115836728 ps
CPU time 32.03 seconds
Started Sep 18 08:09:21 PM UTC 24
Finished Sep 18 08:09:54 PM UTC 24
Peak memory 233836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919821546 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.2919821546 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/8.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_mode_error.2775666017
Short name T226
Test name
Test status
Simulation time 8280848222 ps
CPU time 64.16 seconds
Started Sep 18 08:09:27 PM UTC 24
Finished Sep 18 08:10:34 PM UTC 24
Peak memory 233996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775666017 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.2775666017 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/8.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_ready_error.1923912113
Short name T232
Test name
Test status
Simulation time 6355788554 ps
CPU time 86.75 seconds
Started Sep 18 08:09:55 PM UTC 24
Finished Sep 18 08:11:24 PM UTC 24
Peak memory 234236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923912113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.1923912113 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/8.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/8.kmac_entropy_refresh.4266815568
Short name T250
Test name
Test status
Simulation time 8998085744 ps
CPU time 237.18 seconds
Started Sep 18 08:08:56 PM UTC 24
Finished Sep 18 08:12:57 PM UTC 24
Peak memory 445180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266815568 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.4266815568 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/8.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/8.kmac_error.865804038
Short name T260
Test name
Test status
Simulation time 9961840464 ps
CPU time 275.53 seconds
Started Sep 18 08:09:15 PM UTC 24
Finished Sep 18 08:13:54 PM UTC 24
Peak memory 447488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865804038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.865804038 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/8.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/8.kmac_key_error.2289460374
Short name T75
Test name
Test status
Simulation time 1350674450 ps
CPU time 7.09 seconds
Started Sep 18 08:09:18 PM UTC 24
Finished Sep 18 08:09:26 PM UTC 24
Peak memory 227168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289460374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.2289460374 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/8.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/8.kmac_lc_escalation.3126095451
Short name T221
Test name
Test status
Simulation time 176524127 ps
CPU time 2.23 seconds
Started Sep 18 08:10:00 PM UTC 24
Finished Sep 18 08:10:04 PM UTC 24
Peak memory 227296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126095451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.3126095451 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/8.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/8.kmac_long_msg_and_output.2805418395
Short name T306
Test name
Test status
Simulation time 15189555731 ps
CPU time 639.1 seconds
Started Sep 18 08:08:02 PM UTC 24
Finished Sep 18 08:18:50 PM UTC 24
Peak memory 918328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805418395 -assert nopostproc +UVM
_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_and_output.2805418395 +enable_mas
king=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/8.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/8.kmac_mubi.3993503958
Short name T241
Test name
Test status
Simulation time 8071375549 ps
CPU time 167.53 seconds
Started Sep 18 08:09:15 PM UTC 24
Finished Sep 18 08:12:05 PM UTC 24
Peak memory 298244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993503958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.3993503958 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/8.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/8.kmac_sideload.2701955175
Short name T259
Test name
Test status
Simulation time 4274527920 ps
CPU time 334.31 seconds
Started Sep 18 08:08:10 PM UTC 24
Finished Sep 18 08:13:49 PM UTC 24
Peak memory 375604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701955175 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.2701955175 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/8.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/8.kmac_smoke.965310476
Short name T192
Test name
Test status
Simulation time 9962917796 ps
CPU time 58.88 seconds
Started Sep 18 08:08:02 PM UTC 24
Finished Sep 18 08:09:03 PM UTC 24
Peak memory 234316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965310476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.965310476 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/8.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/8.kmac_stress_all.3207331103
Short name T515
Test name
Test status
Simulation time 78732774649 ps
CPU time 1822.34 seconds
Started Sep 18 08:10:04 PM UTC 24
Finished Sep 18 08:40:48 PM UTC 24
Peak memory 1303980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207331103 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.3207331103 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/8.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/9.kmac_alert_test.4051274684
Short name T238
Test name
Test status
Simulation time 39496386 ps
CPU time 1.13 seconds
Started Sep 18 08:11:54 PM UTC 24
Finished Sep 18 08:11:56 PM UTC 24
Peak memory 216508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051274684 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.4051274684 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/9.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/9.kmac_app.994859160
Short name T285
Test name
Test status
Simulation time 4989687555 ps
CPU time 352.83 seconds
Started Sep 18 08:10:38 PM UTC 24
Finished Sep 18 08:16:36 PM UTC 24
Peak memory 349156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994859160 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.994859160 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/9.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/9.kmac_app_with_partial_data.1126267102
Short name T282
Test name
Test status
Simulation time 8575017714 ps
CPU time 301.69 seconds
Started Sep 18 08:10:57 PM UTC 24
Finished Sep 18 08:16:04 PM UTC 24
Peak memory 457784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126267102 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.1126267102 +enable_ma
sking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/9.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/9.kmac_burst_write.3287751056
Short name T142
Test name
Test status
Simulation time 19701691655 ps
CPU time 387.02 seconds
Started Sep 18 08:10:34 PM UTC 24
Finished Sep 18 08:17:07 PM UTC 24
Peak memory 244480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287751056 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.3287751056 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/9.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/9.kmac_edn_timeout_error.497043209
Short name T240
Test name
Test status
Simulation time 2256193561 ps
CPU time 33.4 seconds
Started Sep 18 08:11:23 PM UTC 24
Finished Sep 18 08:11:58 PM UTC 24
Peak memory 234072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497043209 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.497043209 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/9.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_mode_error.1724239032
Short name T237
Test name
Test status
Simulation time 331953859 ps
CPU time 25.09 seconds
Started Sep 18 08:11:25 PM UTC 24
Finished Sep 18 08:11:52 PM UTC 24
Peak memory 234212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724239032 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.1724239032 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/9.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_ready_error.1890722751
Short name T235
Test name
Test status
Simulation time 2947421730 ps
CPU time 12.95 seconds
Started Sep 18 08:11:31 PM UTC 24
Finished Sep 18 08:11:45 PM UTC 24
Peak memory 231920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890722751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_
unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.1890722751 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/9.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/9.kmac_entropy_refresh.2228253613
Short name T239
Test name
Test status
Simulation time 1970022423 ps
CPU time 43.91 seconds
Started Sep 18 08:11:11 PM UTC 24
Finished Sep 18 08:11:56 PM UTC 24
Peak memory 244436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228253613 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.2228253613 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/9.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/9.kmac_key_error.1359611873
Short name T76
Test name
Test status
Simulation time 3783255144 ps
CPU time 6.71 seconds
Started Sep 18 08:11:22 PM UTC 24
Finished Sep 18 08:11:30 PM UTC 24
Peak memory 227296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359611873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.1359611873 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/9.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/9.kmac_lc_escalation.563656359
Short name T234
Test name
Test status
Simulation time 149087391 ps
CPU time 1.76 seconds
Started Sep 18 08:11:32 PM UTC 24
Finished Sep 18 08:11:35 PM UTC 24
Peak memory 226328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563656359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TES
T_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmaske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.563656359 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/9.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/9.kmac_long_msg_and_output.324719702
Short name T271
Test name
Test status
Simulation time 12594125802 ps
CPU time 265.53 seconds
Started Sep 18 08:10:28 PM UTC 24
Finished Sep 18 08:14:57 PM UTC 24
Peak memory 393980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324719702 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and_output.324719702 +enable_maski
ng=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/9.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/9.kmac_mubi.1524613385
Short name T262
Test name
Test status
Simulation time 7894127712 ps
CPU time 163.63 seconds
Started Sep 18 08:11:12 PM UTC 24
Finished Sep 18 08:13:58 PM UTC 24
Peak memory 368000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524613385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.1524613385 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/9.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/9.kmac_sideload.3485810592
Short name T227
Test name
Test status
Simulation time 58872176 ps
CPU time 6.61 seconds
Started Sep 18 08:10:30 PM UTC 24
Finished Sep 18 08:10:38 PM UTC 24
Peak memory 231648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485810592 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.3485810592 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/9.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/9.kmac_smoke.2906276625
Short name T231
Test name
Test status
Simulation time 3754902618 ps
CPU time 61.01 seconds
Started Sep 18 08:10:17 PM UTC 24
Finished Sep 18 08:11:19 PM UTC 24
Peak memory 233968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906276625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TE
ST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.2906276625 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/9.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default/9.kmac_stress_all.1582729033
Short name T568
Test name
Test status
Simulation time 26643084538 ps
CPU time 2083.5 seconds
Started Sep 18 08:11:35 PM UTC 24
Finished Sep 18 08:46:42 PM UTC 24
Peak memory 803956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/rep
o/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582729033 -assert nopo
stproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.1582729033 +enable_masking=0 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/9.kmac_stress_all/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%