Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	18899930	1			T1	90		T2	71		T4	1
all_values[1]	18899930	1			T1	90		T2	71		T4	1
all_values[2]	18899930	1			T1	90		T2	71		T4	1

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

575311

1

T1

103

T2

15

T4

2

auto[1]

56124479

1

T1

167

T2

198

T4

1

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56486436

1

T1

255

T2

201

T4

3

auto[1]

213354

1

T1

15

T2

12

T14

12

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	196396	1			T1	9		T4	1		T16	1
all_values[0]	auto[0]	auto[1]	1388	1			T1	4		T17	6		T22	2
all_values[0]	auto[1]	auto[0]	18632416	1			T1	76		T2	67		T14	78
all_values[0]	auto[1]	auto[1]	69730	1			T1	1		T2	4		T14	4
all_values[1]	auto[0]	auto[0]	197362	1			T1	85		T21	348		T45	2
all_values[1]	auto[0]	auto[1]	1046	1			T1	5		T21	3		T45	1
all_values[1]	auto[1]	auto[0]	18631450	1			T2	67		T4	1		T14	78
all_values[1]	auto[1]	auto[1]	70072	1			T2	4		T14	4		T15	102
all_values[2]	auto[0]	auto[0]	178066	1			T2	13		T4	1		T14	5
all_values[2]	auto[0]	auto[1]	1053	1			T2	2		T14	1		T15	2
all_values[2]	auto[1]	auto[0]	18650746	1			T1	85		T2	54		T14	73
all_values[2]	auto[1]	auto[1]	70065	1			T1	5		T2	2		T14	3