Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55026 |
1 |
|
|
T1 |
6 |
|
T2 |
2 |
|
T4 |
2 |
auto[1] |
53582 |
1 |
|
|
T2 |
4 |
|
T17 |
4 |
|
T21 |
38 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
26845 |
1 |
|
|
T1 |
5 |
|
T14 |
2 |
|
T15 |
24 |
lower_val |
26890 |
1 |
|
|
T4 |
1 |
|
T14 |
1 |
|
T15 |
46 |
zero_val |
894 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
54146 |
1 |
|
|
T1 |
2 |
|
T2 |
4 |
|
T4 |
2 |
lower_val |
54454 |
1 |
|
|
T1 |
4 |
|
T2 |
2 |
|
T14 |
4 |
zero_val |
8 |
1 |
|
|
T152 |
2 |
|
T153 |
2 |
|
T154 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
4 |
14 |
77.78 |
4 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
[auto[1]] |
0 |
1 |
1 |
|
[lower_val] |
[zero_val] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
6638 |
1 |
|
|
T1 |
1 |
|
T15 |
11 |
|
T16 |
16 |
higher_val |
higher_val |
auto[1] |
6618 |
1 |
|
|
T21 |
4 |
|
T73 |
29 |
|
T25 |
5 |
higher_val |
lower_val |
auto[0] |
6833 |
1 |
|
|
T1 |
4 |
|
T14 |
2 |
|
T15 |
13 |
higher_val |
lower_val |
auto[1] |
6755 |
1 |
|
|
T17 |
2 |
|
T21 |
2 |
|
T73 |
27 |
higher_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T155 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
6751 |
1 |
|
|
T4 |
1 |
|
T15 |
21 |
|
T16 |
21 |
lower_val |
higher_val |
auto[1] |
6642 |
1 |
|
|
T21 |
11 |
|
T73 |
38 |
|
T25 |
4 |
lower_val |
lower_val |
auto[0] |
6817 |
1 |
|
|
T14 |
1 |
|
T15 |
25 |
|
T16 |
10 |
lower_val |
lower_val |
auto[1] |
6678 |
1 |
|
|
T21 |
4 |
|
T73 |
44 |
|
T25 |
14 |
lower_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T153 |
1 |
|
T154 |
1 |
|
- |
- |
zero_val |
higher_val |
auto[0] |
339 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
1 |
zero_val |
higher_val |
auto[1] |
94 |
1 |
|
|
T73 |
1 |
|
T78 |
1 |
|
T56 |
2 |
zero_val |
lower_val |
auto[0] |
361 |
1 |
|
|
T16 |
1 |
|
T18 |
1 |
|
T45 |
1 |
zero_val |
lower_val |
auto[1] |
100 |
1 |
|
|
T73 |
1 |
|
T156 |
2 |
|
T157 |
1 |