Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	16233649	1			T1	120		T2	86		T3	178
all_values[1]	16233649	1			T1	120		T2	86		T3	178
all_values[2]	16233649	1			T1	120		T2	86		T3	178

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

564276

1

T1

137

T2

6

T3

179

auto[1]

48136671

1

T1

223

T2

252

T3

355

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48475731

1

T1

345

T2

249

T3

528

auto[1]

225216

1

T1

15

T2

9

T3

6

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Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	185206	1			T1	60		T3	176		T12	11
all_values[0]	auto[0]	auto[1]	1398	1			T1	4		T3	2		T12	4
all_values[0]	auto[1]	auto[0]	15973371	1			T1	55		T2	83		T4	7
all_values[0]	auto[1]	auto[1]	73674	1			T1	1		T2	3		T12	1
all_values[1]	auto[0]	auto[0]	170773	1			T1	60		T18	1		T52	2
all_values[1]	auto[0]	auto[1]	917	1			T1	4		T52	1		T30	2
all_values[1]	auto[1]	auto[0]	15987804	1			T1	55		T2	83		T3	176
all_values[1]	auto[1]	auto[1]	74155	1			T1	1		T2	3		T3	2
all_values[2]	auto[0]	auto[0]	205011	1			T1	7		T2	5		T3	1
all_values[2]	auto[0]	auto[1]	971	1			T1	2		T2	1		T12	2
all_values[2]	auto[1]	auto[0]	15953566	1			T1	108		T2	78		T3	175
all_values[2]	auto[1]	auto[1]	74101	1			T1	3		T2	2		T3	2