Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
61284 |
1 |
|
|
T1 |
6 |
|
T2 |
2 |
|
T3 |
4 |
auto[1] |
51666 |
1 |
|
|
T2 |
4 |
|
T12 |
4 |
|
T14 |
4 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
28412 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T3 |
3 |
lower_val |
27539 |
1 |
|
|
T2 |
2 |
|
T4 |
1 |
|
T12 |
3 |
zero_val |
904 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
1 |
2 |
66.67 |
User Defined Bins for wait_timer_val
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
zero_val |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
56036 |
1 |
|
|
T1 |
4 |
|
T2 |
2 |
|
T3 |
2 |
lower_val |
56914 |
1 |
|
|
T1 |
2 |
|
T2 |
4 |
|
T3 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
6 |
12 |
66.67 |
6 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
* |
[zero_val] |
* |
-- |
-- |
6 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
7738 |
1 |
|
|
T1 |
2 |
|
T3 |
2 |
|
T13 |
29 |
higher_val |
higher_val |
auto[1] |
6430 |
1 |
|
|
T2 |
1 |
|
T14 |
1 |
|
T22 |
5 |
higher_val |
lower_val |
auto[0] |
7654 |
1 |
|
|
T3 |
1 |
|
T13 |
17 |
|
T5 |
1 |
higher_val |
lower_val |
auto[1] |
6590 |
1 |
|
|
T2 |
2 |
|
T14 |
2 |
|
T22 |
8 |
lower_val |
higher_val |
auto[0] |
7498 |
1 |
|
|
T4 |
1 |
|
T13 |
28 |
|
T16 |
17 |
lower_val |
higher_val |
auto[1] |
6189 |
1 |
|
|
T2 |
1 |
|
T22 |
2 |
|
T30 |
1 |
lower_val |
lower_val |
auto[0] |
7508 |
1 |
|
|
T2 |
1 |
|
T13 |
28 |
|
T16 |
14 |
lower_val |
lower_val |
auto[1] |
6344 |
1 |
|
|
T12 |
3 |
|
T22 |
6 |
|
T81 |
29 |
zero_val |
higher_val |
auto[0] |
340 |
1 |
|
|
T1 |
1 |
|
T4 |
1 |
|
T13 |
1 |
zero_val |
higher_val |
auto[1] |
95 |
1 |
|
|
T30 |
2 |
|
T156 |
1 |
|
T61 |
2 |
zero_val |
lower_val |
auto[0] |
372 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T12 |
1 |
zero_val |
lower_val |
auto[1] |
97 |
1 |
|
|
T30 |
1 |
|
T156 |
1 |
|
T157 |
2 |