Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	16233649	1			T1	120		T2	86		T3	178
all_pins[1]	16233649	1			T1	120		T2	86		T3	178
all_pins[2]	16233649	1			T1	120		T2	86		T3	178

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	48328038	1			T1	359		T2	255		T3	534
values[0x1]	372909	1			T1	1		T2	3		T12	1
transitions[0x0=>0x1]	371029	1			T1	1		T2	3		T12	1
transitions[0x1=>0x0]	371049	1			T1	1		T2	3		T12	1

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	16159975	1			T1	119		T2	83		T3	178
all_pins[0]	values[0x1]	73674	1			T1	1		T2	3		T12	1
all_pins[0]	transitions[0x0=>0x1]	73656	1			T1	1		T2	3		T12	1
all_pins[0]	transitions[0x1=>0x0]	69	1			T55	2		T144	6		T171	8
all_pins[1]	values[0x0]	16233562	1			T1	120		T2	86		T3	178
all_pins[1]	values[0x1]	87	1			T55	2		T144	6		T171	8
all_pins[1]	transitions[0x0=>0x1]	74	1			T55	2		T144	6		T171	8
all_pins[1]	transitions[0x1=>0x0]	299135	1			T38	4410		T39	3068		T58	101
all_pins[2]	values[0x0]	15934501	1			T1	120		T2	86		T3	178
all_pins[2]	values[0x1]	299148	1			T38	4410		T39	3068		T58	101
all_pins[2]	transitions[0x0=>0x1]	297299	1			T38	4379		T39	3048		T58	100
all_pins[2]	transitions[0x1=>0x0]	71845	1			T1	1		T2	3		T12	1