Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	16540114	1			T1	155		T2	71		T11	25
all_values[1]	16540114	1			T1	155		T2	71		T11	25
all_values[2]	16540114	1			T1	155		T2	71		T11	25

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

605848

1

T1

6

T11

2

T12

25

auto[1]

49014494

1

T1

459

T2

213

T11

73

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49395411

1

T1

456

T2

198

T11

75

auto[1]

224931

1

T1

9

T2

15

T12

426

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Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	200083	1			T11	2		T75	13		T37	260
all_values[0]	auto[0]	auto[1]	1285	1			T75	2		T37	2		T77	6
all_values[0]	auto[1]	auto[0]	16265054	1			T1	152		T2	66		T11	23
all_values[0]	auto[1]	auto[1]	73692	1			T1	3		T2	5		T12	142
all_values[1]	auto[0]	auto[0]	215913	1			T1	5		T12	22		T14	2
all_values[1]	auto[0]	auto[1]	964	1			T1	1		T12	3		T14	1
all_values[1]	auto[1]	auto[0]	16249224	1			T1	147		T2	66		T11	25
all_values[1]	auto[1]	auto[1]	74013	1			T1	2		T2	5		T12	139
all_values[2]	auto[0]	auto[0]	186667	1			T14	4		T16	5		T46	2
all_values[2]	auto[0]	auto[1]	936	1			T14	3		T16	1		T46	1
all_values[2]	auto[1]	auto[0]	16278470	1			T1	152		T2	66		T11	25
all_values[2]	auto[1]	auto[1]	74041	1			T1	3		T2	5		T12	142