Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56274 |
1 |
|
|
T1 |
2 |
|
T2 |
6 |
|
T3 |
2 |
auto[1] |
56844 |
1 |
|
|
T1 |
4 |
|
T16 |
4 |
|
T60 |
302 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
28158 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T11 |
18 |
lower_val |
28123 |
1 |
|
|
T2 |
1 |
|
T11 |
10 |
|
T12 |
40 |
zero_val |
894 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
1 |
2 |
66.67 |
User Defined Bins for wait_timer_val
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
zero_val |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
56764 |
1 |
|
|
T1 |
4 |
|
T2 |
4 |
|
T11 |
24 |
lower_val |
56354 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
6 |
12 |
66.67 |
6 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
* |
[zero_val] |
* |
-- |
-- |
6 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
6996 |
1 |
|
|
T2 |
1 |
|
T11 |
9 |
|
T12 |
25 |
higher_val |
higher_val |
auto[1] |
7196 |
1 |
|
|
T1 |
1 |
|
T16 |
1 |
|
T60 |
41 |
higher_val |
lower_val |
auto[0] |
6927 |
1 |
|
|
T2 |
1 |
|
T11 |
9 |
|
T12 |
23 |
higher_val |
lower_val |
auto[1] |
7039 |
1 |
|
|
T1 |
1 |
|
T60 |
35 |
|
T21 |
7 |
lower_val |
higher_val |
auto[0] |
7030 |
1 |
|
|
T2 |
1 |
|
T11 |
3 |
|
T12 |
19 |
lower_val |
higher_val |
auto[1] |
6972 |
1 |
|
|
T16 |
2 |
|
T60 |
31 |
|
T21 |
1 |
lower_val |
lower_val |
auto[0] |
6906 |
1 |
|
|
T11 |
7 |
|
T12 |
21 |
|
T14 |
37 |
lower_val |
lower_val |
auto[1] |
7215 |
1 |
|
|
T60 |
47 |
|
T21 |
4 |
|
T22 |
17 |
zero_val |
higher_val |
auto[0] |
368 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T11 |
1 |
zero_val |
higher_val |
auto[1] |
94 |
1 |
|
|
T85 |
1 |
|
T128 |
3 |
|
T80 |
1 |
zero_val |
lower_val |
auto[0] |
333 |
1 |
|
|
T3 |
1 |
|
T17 |
1 |
|
T46 |
1 |
zero_val |
lower_val |
auto[1] |
99 |
1 |
|
|
T158 |
2 |
|
T85 |
1 |
|
T35 |
1 |