Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	16540114	1			T1	155		T2	71		T11	25
all_pins[1]	16540114	1			T1	155		T2	71		T11	25
all_pins[2]	16540114	1			T1	155		T2	71		T11	25

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	49252617	1			T1	462		T2	208		T11	75
values[0x1]	367725	1			T1	3		T2	5		T12	142
transitions[0x0=>0x1]	365901	1			T1	3		T2	5		T12	142
transitions[0x1=>0x0]	365931	1			T1	3		T2	5		T12	142

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	16466422	1			T1	152		T2	66		T11	25
all_pins[0]	values[0x1]	73692	1			T1	3		T2	5		T12	142
all_pins[0]	transitions[0x0=>0x1]	73679	1			T1	3		T2	5		T12	142
all_pins[0]	transitions[0x1=>0x0]	48	1			T52	3		T181	4		T182	3
all_pins[1]	values[0x0]	16540053	1			T1	155		T2	71		T11	25
all_pins[1]	values[0x1]	61	1			T52	3		T181	4		T182	3
all_pins[1]	transitions[0x0=>0x1]	47	1			T52	3		T181	4		T182	3
all_pins[1]	transitions[0x1=>0x0]	293958	1			T31	7		T34	8892		T35	291
all_pins[2]	values[0x0]	16246142	1			T1	155		T2	71		T11	25
all_pins[2]	values[0x1]	293972	1			T31	7		T34	8892		T35	291
all_pins[2]	transitions[0x0=>0x1]	292175	1			T31	7		T34	8835		T35	290
all_pins[2]	transitions[0x1=>0x0]	71925	1			T1	3		T2	5		T12	142