Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6216523 |
1 |
|
|
T1 |
48 |
|
T2 |
24 |
|
T11 |
728 |
auto[1] |
9561120 |
1 |
|
|
T1 |
150 |
|
T2 |
150 |
|
T11 |
1640 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
15743968 |
1 |
|
|
T1 |
198 |
|
T2 |
174 |
|
T11 |
2368 |
triple_byte_access |
11314 |
1 |
|
|
T12 |
19 |
|
T60 |
39 |
|
T21 |
1 |
halfword_access |
11262 |
1 |
|
|
T12 |
21 |
|
T60 |
41 |
|
T21 |
5 |
byte_access |
11099 |
1 |
|
|
T12 |
21 |
|
T60 |
31 |
|
T21 |
5 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
6182848 |
1 |
|
|
T1 |
48 |
|
T2 |
24 |
|
T11 |
728 |
auto[0] |
triple_byte_access |
11314 |
1 |
|
|
T12 |
19 |
|
T60 |
39 |
|
T21 |
1 |
auto[0] |
halfword_access |
11262 |
1 |
|
|
T12 |
21 |
|
T60 |
41 |
|
T21 |
5 |
auto[0] |
byte_access |
11099 |
1 |
|
|
T12 |
21 |
|
T60 |
31 |
|
T21 |
5 |
auto[1] |
word_access |
9561120 |
1 |
|
|
T1 |
150 |
|
T2 |
150 |
|
T11 |
1640 |