Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 7 0 7 100.00
Crosses 12 0 12 100.00


Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_cg_cc 12 0 12 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
all_values[0] 17311231 1 T1 70 T2 68 T5 2
all_values[1] 17311231 1 T1 70 T2 68 T5 2
all_values[2] 17311231 1 T1 70 T2 68 T5 2


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 458628 1 T1 76 T2 24 T15 10
auto[1] 51475065 1 T1 134 T2 180 T5 6


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 51723750 1 T1 195 T2 189 T5 3
auto[1] 209943 1 T1 15 T2 15 T5 3


Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 12 0 12 100.00


Automatically Generated Cross Bins for intr_cg_cc

Bins
cp_intr   cp_intr_en   cp_intr_state   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
all_values[0] auto[0] auto[0] 113601 1 T2 8 T15 3 T19 212
all_values[0] auto[0] auto[1] 1173 1 T2 4 T15 4 T19 4
all_values[0] auto[1] auto[0] 17127649 1 T1 65 T2 55 T5 1
all_values[0] auto[1] auto[1] 68808 1 T1 5 T2 1 T5 1
all_values[1] auto[0] auto[0] 204692 1 T1 5 T2 4 T15 1
all_values[1] auto[0] auto[1] 917 1 T1 1 T2 2 T15 2
all_values[1] auto[1] auto[0] 17036558 1 T1 60 T2 59 T5 1
all_values[1] auto[1] auto[1] 69064 1 T1 4 T2 3 T5 1
all_values[2] auto[0] auto[0] 137339 1 T1 65 T2 4 T18 10
all_values[2] auto[0] auto[1] 906 1 T1 5 T2 2 T18 2
all_values[2] auto[1] auto[0] 17103911 1 T2 59 T5 1 T13 1
all_values[2] auto[1] auto[1] 69075 1 T2 3 T5 1 T13 1