Group : tb.dut.kmac_cov_if::cmd_process_cg
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Group : tb.dut.kmac_cov_if::cmd_process_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/kmac_cov_if.sv


Summary for Group tb.dut.kmac_cov_if::cmd_process_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 7 0 7 100.00


Variables for Group tb.dut.kmac_cov_if::cmd_process_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
kmac_keccak_state 2 0 2 100.00 100 1 1 0
kmac_msgfifo_empty 2 0 2 100.00 100 1 1 0
kmac_msgfifo_full 2 0 2 100.00 100 1 1 0
kmac_msgfifo_has_data 1 0 1 100.00 100 1 1 0


Summary for Variable kmac_keccak_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for kmac_keccak_state

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
inactive 104927 1 T1 7 T2 7 T3 1
active 5268 1 T5 7 T12 2 T13 13


Summary for Variable kmac_msgfifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for kmac_msgfifo_empty

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
not_empty 9822 1 T4 2 T5 20 T13 9
empty 100373 1 T1 7 T2 7 T3 1


Summary for Variable kmac_msgfifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for kmac_msgfifo_full

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
not_full 110041 1 T1 7 T2 7 T3 1
full 154 1 T21 2 T40 3 T41 2


Summary for Variable kmac_msgfifo_has_data

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for kmac_msgfifo_has_data

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
has_data 5432 1 T4 2 T5 16 T13 9