Design subhierarchy
dashboard | hierarchy | modlist | groups | tests | asserts

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NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_alert_tx[1].u_prim_alert_sender 100.00 100.00
intr_fifo_empty 86.94 90.00 77.78 80.00 100.00
intr_kmac_done 93.75 100.00 75.00 100.00 100.00
intr_kmac_err 93.75 100.00 75.00 100.00 100.00
kmac_csr_assert 100.00 100.00
sha3pad_assert_cov_if 100.00 100.00
tlul_assert_device 100.00 100.00
 u_app_intf 86.27 94.83 91.23 51.11 94.17 100.00
 u_errchk 94.04 97.22 96.67 80.00 96.30 100.00
 u_kmac_core 99.04 100.00 100.00 100.00 100.00 94.23 100.00
 u_msgfifo 97.75 100.00 95.00 100.00 93.75 100.00
 u_prim_lc_sync 100.00 100.00 100.00 100.00
 u_reg 98.99 99.19 97.03 100.00 98.72 100.00
 u_sha3 92.16 91.91 88.51 100.00 80.56 92.00 100.00
 u_sha3_done_sender 100.00 100.00 100.00 100.00
 u_state_regs 100.00 100.00 100.00 100.00
 u_staterd 89.88 89.88 81.09 88.54 100.00
 u_tlul_adapter_msgfifo 80.51 87.12 74.69 77.38 82.86