Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	101971626	1			T1	286		T2	306		T13	810
all_values[1]	101971626	1			T1	286		T2	306		T13	810
all_values[2]	101971626	1			T1	286		T2	306		T13	810

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

568182

1

T1

157

T2

111

T4

287

auto[1]

305346696

1

T1

701

T2

807

T13

2430

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

304369590

1

T1

822

T2

870

T13

2061

auto[1]

1545288

1

T1

36

T2

48

T13

369

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	243756	1			T2	89		T4	285		T15	325
all_values[0]	auto[0]	auto[1]	2279	1			T2	10		T4	2		T15	6
all_values[0]	auto[1]	auto[0]	101212774	1			T1	274		T2	201		T13	687
all_values[0]	auto[1]	auto[1]	512817	1			T1	12		T2	6		T13	123
all_values[1]	auto[0]	auto[0]	161188	1			T2	8		T15	299		T16	2
all_values[1]	auto[0]	auto[1]	1698	1			T2	4		T15	4		T17	3
all_values[1]	auto[1]	auto[0]	101295342	1			T1	274		T2	282		T13	687
all_values[1]	auto[1]	auto[1]	513398	1			T1	12		T2	12		T13	123
all_values[2]	auto[0]	auto[0]	157777	1			T1	147		T16	2		T17	14
all_values[2]	auto[0]	auto[1]	1484	1			T1	10		T17	2		T71	1
all_values[2]	auto[1]	auto[0]	101298753	1			T1	127		T2	290		T13	687
all_values[2]	auto[1]	auto[1]	513612	1			T1	2		T2	16		T13	123