Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
356374 |
1 |
|
|
T1 |
2 |
|
T2 |
18 |
|
T13 |
2 |
auto[1] |
344550 |
1 |
|
|
T1 |
16 |
|
T13 |
152 |
|
T4 |
16 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
176446 |
1 |
|
|
T1 |
4 |
|
T2 |
7 |
|
T13 |
38 |
lower_val |
172949 |
1 |
|
|
T1 |
1 |
|
T2 |
8 |
|
T13 |
37 |
zero_val |
1858 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T13 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
350520 |
1 |
|
|
T1 |
10 |
|
T2 |
8 |
|
T13 |
64 |
lower_val |
350398 |
1 |
|
|
T1 |
8 |
|
T2 |
10 |
|
T13 |
90 |
zero_val |
6 |
1 |
|
|
T148 |
2 |
|
T149 |
2 |
|
T150 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
2 |
16 |
88.89 |
2 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
44765 |
1 |
|
|
T2 |
3 |
|
T15 |
10 |
|
T16 |
29 |
higher_val |
higher_val |
auto[1] |
43625 |
1 |
|
|
T1 |
1 |
|
T13 |
15 |
|
T4 |
1 |
higher_val |
lower_val |
auto[0] |
44750 |
1 |
|
|
T2 |
4 |
|
T15 |
14 |
|
T16 |
23 |
higher_val |
lower_val |
auto[1] |
43304 |
1 |
|
|
T1 |
3 |
|
T13 |
23 |
|
T4 |
3 |
higher_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T149 |
1 |
|
- |
- |
|
- |
- |
higher_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T150 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
44022 |
1 |
|
|
T2 |
3 |
|
T13 |
1 |
|
T15 |
7 |
lower_val |
higher_val |
auto[1] |
42510 |
1 |
|
|
T1 |
1 |
|
T13 |
20 |
|
T17 |
34 |
lower_val |
lower_val |
auto[0] |
43784 |
1 |
|
|
T2 |
5 |
|
T15 |
12 |
|
T16 |
30 |
lower_val |
lower_val |
auto[1] |
42631 |
1 |
|
|
T13 |
16 |
|
T4 |
2 |
|
T17 |
44 |
lower_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T149 |
1 |
|
- |
- |
|
- |
- |
lower_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T150 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
699 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T13 |
1 |
zero_val |
higher_val |
auto[1] |
241 |
1 |
|
|
T33 |
1 |
|
T76 |
2 |
|
T151 |
1 |
zero_val |
lower_val |
auto[0] |
679 |
1 |
|
|
T16 |
1 |
|
T17 |
1 |
|
T21 |
1 |
zero_val |
lower_val |
auto[1] |
239 |
1 |
|
|
T33 |
1 |
|
T152 |
1 |
|
T76 |
1 |