Group : kmac_env_pkg::kmac_env_cov::entropy_timer_cg
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Summary for Group kmac_env_pkg::kmac_env_cov::entropy_timer_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 1 7 87.50
Crosses 18 6 12 66.67


Variables for Group kmac_env_pkg::kmac_env_cov::entropy_timer_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
entropy_edn_mode_enabled 2 0 2 100.00 100 1 1 2
prescaler_val 3 0 3 100.00 100 1 1 0
wait_timer_val 3 1 2 66.67 100 1 1 0


Crosses for Group kmac_env_pkg::kmac_env_cov::entropy_timer_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
entropy_timer_cross 18 6 12 66.67 100 1 1 0


Summary for Variable entropy_edn_mode_enabled

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for entropy_edn_mode_enabled

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 57110 1 T1 2 T2 2 T4 2
auto[1] 50448 1 T1 4 T2 4 T16 4



Summary for Variable prescaler_val

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for prescaler_val

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
higher_val 26727 1 T1 2 T2 2 T5 7
lower_val 26641 1 T1 2 T2 1 T5 4
zero_val 887 1 T1 1 T2 1 T4 1



Summary for Variable wait_timer_val

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 1 2 66.67


User Defined Bins for wait_timer_val

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
zero_val 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
higher_val 53494 1 T1 2 T2 2 T5 14
lower_val 54064 1 T1 4 T2 4 T4 2



Summary for Cross entropy_timer_cross

Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 18 6 12 66.67 6


Automatically Generated Cross Bins for entropy_timer_cross

Element holes
prescaler_valwait_timer_valentropy_edn_mode_enabledCOUNTAT LEASTNUMBERSTATUS
* [zero_val] * -- -- 6


Covered bins
prescaler_valwait_timer_valentropy_edn_mode_enabledCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
higher_val higher_val auto[0] 7013 1 T1 1 T5 3 T13 2
higher_val higher_val auto[1] 6314 1 T2 1 T53 36 T20 10
higher_val lower_val auto[0] 7083 1 T2 1 T5 4 T13 4
higher_val lower_val auto[1] 6317 1 T1 1 T53 30 T20 14
lower_val higher_val auto[0] 7027 1 T13 4 T15 18 T19 20
lower_val higher_val auto[1] 6174 1 T53 22 T20 13 T21 7
lower_val lower_val auto[0] 7186 1 T5 4 T13 6 T15 22
lower_val lower_val auto[1] 6254 1 T1 2 T2 1 T53 27
zero_val higher_val auto[0] 346 1 T1 1 T5 1 T15 1
zero_val higher_val auto[1] 88 1 T66 1 T138 1 T57 2
zero_val lower_val auto[0] 370 1 T2 1 T4 1 T13 1
zero_val lower_val auto[1] 83 1 T21 1 T66 4 T138 3

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