Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	17311231	1			T1	70		T2	68		T5	2
all_pins[1]	17311231	1			T1	70		T2	68		T5	2
all_pins[2]	17311231	1			T1	70		T2	68		T5	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	51577093	1			T1	205		T2	203		T5	4
values[0x1]	356600	1			T1	5		T2	1		T5	2
transitions[0x0=>0x1]	354823	1			T1	5		T2	1		T5	1
transitions[0x1=>0x0]	354878	1			T1	5		T2	1		T5	2

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	17242423	1			T1	65		T2	67		T5	1
all_pins[0]	values[0x1]	68808	1			T1	5		T2	1		T5	1
all_pins[0]	transitions[0x0=>0x1]	68797	1			T1	5		T2	1		T5	1
all_pins[0]	transitions[0x1=>0x0]	52	1			T169	6		T170	4		T171	4
all_pins[1]	values[0x0]	17311168	1			T1	70		T2	68		T5	2
all_pins[1]	values[0x1]	63	1			T169	6		T170	4		T171	4
all_pins[1]	transitions[0x0=>0x1]	51	1			T169	6		T170	4		T171	4
all_pins[1]	transitions[0x1=>0x0]	287717	1			T5	1		T13	1		T19	558
all_pins[2]	values[0x0]	17023502	1			T1	70		T2	68		T5	1
all_pins[2]	values[0x1]	287729	1			T5	1		T13	1		T19	558
all_pins[2]	transitions[0x0=>0x1]	285975	1			T19	558		T40	5526		T41	9169
all_pins[2]	transitions[0x1=>0x0]	67109	1			T1	5		T2	1		T5	1