Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	101971626	1			T1	286		T2	306		T13	810
all_pins[1]	101971626	1			T1	286		T2	306		T13	810
all_pins[2]	101971626	1			T1	286		T2	306		T13	810

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	305072256	1			T1	846		T2	912		T13	2307
values[0x1]	842622	1			T1	12		T2	6		T13	123
transitions[0x0=>0x1]	840600	1			T1	12		T2	6		T13	123
transitions[0x1=>0x0]	840627	1			T1	12		T2	6		T13	123

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	101458809	1			T1	274		T2	300		T13	687
all_pins[0]	values[0x1]	512817	1			T1	12		T2	6		T13	123
all_pins[0]	transitions[0x0=>0x1]	512799	1			T1	12		T2	6		T13	123
all_pins[0]	transitions[0x1=>0x0]	54	1			T158	3		T159	11		T160	5
all_pins[1]	values[0x0]	101971554	1			T1	286		T2	306		T13	810
all_pins[1]	values[0x1]	72	1			T158	3		T159	11		T160	5
all_pins[1]	transitions[0x0=>0x1]	63	1			T158	3		T159	11		T160	5
all_pins[1]	transitions[0x1=>0x0]	329724	1			T25	314		T33	18481		T26	843
all_pins[2]	values[0x0]	101641893	1			T1	286		T2	306		T13	810
all_pins[2]	values[0x1]	329733	1			T25	314		T33	18481		T26	843
all_pins[2]	transitions[0x0=>0x1]	327738	1			T25	314		T33	18349		T26	843
all_pins[2]	transitions[0x1=>0x0]	510849	1			T1	12		T2	6		T13	123