Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100130787	1			T1	59634		T2	4		T3	221747
all_pins[1]	100130787	1			T1	59634		T2	4		T3	221747
all_pins[2]	100130787	1			T1	59634		T2	4		T3	221747

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	299572715	1			T1	178261		T2	12		T3	664650
values[0x1]	819646	1			T1	641		T3	591		T4	21
transitions[0x0=>0x1]	817733	1			T1	639		T3	591		T4	21
transitions[0x1=>0x0]	817756	1			T1	639		T3	591		T4	21

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99623511	1			T1	59459		T2	4		T3	221156
all_pins[0]	values[0x1]	507276	1			T1	175		T3	591		T4	21
all_pins[0]	transitions[0x0=>0x1]	507262	1			T1	175		T3	591		T4	21
all_pins[0]	transitions[0x1=>0x0]	61	1			T44	4		T178	2		T179	6
all_pins[1]	values[0x0]	100130712	1			T1	59634		T2	4		T3	221747
all_pins[1]	values[0x1]	75	1			T44	4		T178	2		T179	6
all_pins[1]	transitions[0x0=>0x1]	53	1			T44	4		T178	2		T179	6
all_pins[1]	transitions[0x1=>0x0]	312273	1			T1	466		T24	5898		T28	144
all_pins[2]	values[0x0]	99818492	1			T1	59168		T2	4		T3	221747
all_pins[2]	values[0x1]	312295	1			T1	466		T24	5898		T28	144
all_pins[2]	transitions[0x0=>0x1]	310418	1			T1	464		T24	5866		T28	144
all_pins[2]	transitions[0x1=>0x0]	505422	1			T1	173		T3	591		T4	21