Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	703	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5913	1			T15	3		T21	5		T22	15
len_601_800	13522	1			T4	2		T15	15		T21	5
len_401_600	8814	1			T4	2		T15	13		T21	11
len_201_400	16666	1			T4	1		T15	6		T21	3
len_65_200	74209	1			T13	36		T4	1		T15	2
len_min_for_xof_require_squeeze	1013	1			T17	2		T84	1		T75	1
len_keccak_block_sizes[72]	771	1			T17	1		T76	1		T173	2
len_keccak_block_sizes[104]	749	1			T13	1		T30	1		T28	1
len_keccak_block_sizes[136]	764	1			T13	1		T171	2		T174	2
len_keccak_block_sizes[144]	304	1			T13	1		T17	2		T171	1
len_keccak_block_sizes[168]	298	1			T17	1		T22	1		T26	1
len_datapath_width	14060	1			T1	3		T2	3		T17	8
len_2_63	215437	1			T1	6		T2	6		T13	41
len_1	52	1			T17	2		T44	1		T175	1