LC_CTRL Simulation Results

Tuesday May 10 2022 08:05:09 UTC

GitHub Revision: `25be34391`
Foundry Revision: `25be34391`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3200075316

Test Results

Milestone	Name	Tests	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	20	20	100.00
		lc_ctrl_csr_aliasing	5	5	100.00
V1		TOTAL	105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	50	50	100.00
V2	lc_errors	lc_ctrl_errors	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	50	50	100.00
		lc_ctrl_prog_failure	50	50	100.00
		lc_ctrl_errors	50	50	100.00
		lc_ctrl_security_escalation	50	50	100.00
		lc_ctrl_jtag_state_failure	20	20	100.00
		lc_ctrl_jtag_prog_failure	20	20	100.00
		lc_ctrl_jtag_errors	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	20	20	100.00
		lc_ctrl_jtag_state_post_trans	20	20	100.00
		lc_ctrl_jtag_prog_failure	20	20	100.00
		lc_ctrl_jtag_errors	20	20	100.00
		lc_ctrl_jtag_access	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	10	10	100.00
		lc_ctrl_jtag_csr_rw	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	10	10	100.00
		lc_ctrl_jtag_alert_test	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	10	10	100.00
V2	stress_all	lc_ctrl_stress_all	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	5	5	100.00
		lc_ctrl_csr_rw	20	20	100.00
		lc_ctrl_csr_aliasing	5	5	100.00
		lc_ctrl_same_csr_outstanding	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	5	5	100.00
		lc_ctrl_csr_rw	20	20	100.00
		lc_ctrl_csr_aliasing	5	5	100.00
		lc_ctrl_same_csr_outstanding	20	20	100.00
V2		TOTAL	640	640	100.00
V2S	tl_intg_err	lc_ctrl_tl_intg_err	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	50	50	100.00
		lc_ctrl_sec_cm	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	50	50	100.00
		lc_ctrl_sec_cm	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	50	50	100.00
		lc_ctrl_sec_cm	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	50	50	100.00
		lc_ctrl_sec_cm	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	50	50	100.00
		lc_ctrl_sec_cm	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	50	50	100.00
		lc_ctrl_sec_cm	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	50	50	100.00
		lc_ctrl_sec_cm	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	50	50	100.00
		lc_ctrl_sec_cm	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	50	50	100.00
		lc_ctrl_jtag_state_post_trans	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	50	50	100.00
V2S		TOTAL	175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	9	50	18.00
V3		TOTAL	9	50	18.00
		TOTAL	929	970	95.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	25	25	25	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
85.65	89.21	58.77	98.24	71.21	93.55	97.51	91.07

Failure Buckets

UVM_ERROR (lc_ctrl_errors_vseq.sv:728) [lc_ctrl_lc_errors_vseq] Check failed state_error_act == state_error_exp (* [*] vs * [*]) has 3 failures:

Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

6.lc_ctrl_stress_all_with_rand_reset.3713557326
Line 13581, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/out/run.log

  UVM_ERROR @ 26005974398 ps: (lc_ctrl_errors_vseq.sv:728) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed state_error_act == state_error_exp (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 26005974398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.lc_ctrl_stress_all_with_rand_reset.303988696
Line 1650, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/15.lc_ctrl_stress_all_with_rand_reset/out/run.log

  UVM_ERROR @ 7219021757 ps: (lc_ctrl_errors_vseq.sv:728) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed state_error_act == state_error_exp (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 7219021757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (lc_ctrl_errors_vseq.sv:738) [lc_ctrl_lc_errors_vseq] Check failed transition_error_exp == transition_error_act (* [*] vs * [*]) has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 1.lc_ctrl_stress_all_with_rand_reset.2937206955
    Line 10818, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/out/run.log
```
  UVM_ERROR @ 12549282051 ps: (lc_ctrl_errors_vseq.sv:738) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed transition_error_exp == transition_error_act (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 12549282051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_errors_vseq.sv:734) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 7.lc_ctrl_stress_all_with_rand_reset.3701058471
    Line 7516, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/out/run.log
```
  UVM_ERROR @ 8825099824 ps: (lc_ctrl_errors_vseq.sv:734) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 8825099824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_scoreboard.sv:345) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: lc_ctrl_reg_block.lc_state has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 32.lc_ctrl_stress_all_with_rand_reset.614534339
    Line 16728, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/32.lc_ctrl_stress_all_with_rand_reset/out/run.log
```
  UVM_ERROR @ 14111072554 ps: (lc_ctrl_scoreboard.sv:345) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (762010326 [0x2d6b5ad6] vs 588826161 [0x2318c631]) reg name: lc_ctrl_reg_block.lc_state
  UVM_INFO @ 14111072554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```