d498f91d6d498f91d6| Milestone | Name | Tests | Passing | Total | Pass Rate |
|---|---|---|---|---|---|
| V1 | smoke | lc_ctrl_smoke | 46 | 50 | 92.00 |
| V1 | csr_hw_reset | lc_ctrl_csr_hw_reset | 5 | 5 | 100.00 |
| V1 | csr_rw | lc_ctrl_csr_rw | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | lc_ctrl_csr_bit_bash | 5 | 5 | 100.00 |
| V1 | csr_aliasing | lc_ctrl_csr_aliasing | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | lc_ctrl_csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | lc_ctrl_csr_rw | 20 | 20 | 100.00 |
| lc_ctrl_csr_aliasing | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 101 | 105 | 96.19 | |
| V2 | state_post_trans | lc_ctrl_state_post_trans | 49 | 50 | 98.00 |
| V2 | regwen_during_op | lc_ctrl_regwen_during_op | 10 | 10 | 100.00 |
| V2 | lc_prog_failure | lc_ctrl_prog_failure | 47 | 50 | 94.00 |
| V2 | lc_state_failure | lc_ctrl_state_failure | 46 | 50 | 92.00 |
| V2 | lc_errors | lc_ctrl_errors | 47 | 50 | 94.00 |
| V2 | security_escalation | lc_ctrl_state_failure | 46 | 50 | 92.00 |
| lc_ctrl_prog_failure | 47 | 50 | 94.00 | ||
| lc_ctrl_errors | 47 | 50 | 94.00 | ||
| lc_ctrl_security_escalation | 47 | 50 | 94.00 | ||
| lc_ctrl_jtag_state_failure | 20 | 20 | 100.00 | ||
| lc_ctrl_jtag_prog_failure | 20 | 20 | 100.00 | ||
| lc_ctrl_jtag_errors | 20 | 20 | 100.00 | ||
| V2 | jtag_access | lc_ctrl_jtag_smoke | 19 | 20 | 95.00 |
| lc_ctrl_jtag_state_post_trans | 20 | 20 | 100.00 | ||
| lc_ctrl_jtag_prog_failure | 20 | 20 | 100.00 | ||
| lc_ctrl_jtag_errors | 20 | 20 | 100.00 | ||
| lc_ctrl_jtag_access | 46 | 50 | 92.00 | ||
| lc_ctrl_jtag_regwen_during_op | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_csr_hw_reset | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_csr_rw | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_csr_bit_bash | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_csr_aliasing | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_same_csr_outstanding | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_csr_mem_rw_with_rand_reset | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_alert_test | 10 | 10 | 100.00 | ||
| V2 | jtag_priority | lc_ctrl_jtag_priority | 10 | 10 | 100.00 |
| V2 | stress_all | lc_ctrl_stress_all | 46 | 50 | 92.00 |
| V2 | alert_test | lc_ctrl_alert_test | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | lc_ctrl_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | lc_ctrl_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | lc_ctrl_csr_hw_reset | 5 | 5 | 100.00 |
| lc_ctrl_csr_rw | 20 | 20 | 100.00 | ||
| lc_ctrl_csr_aliasing | 5 | 5 | 100.00 | ||
| lc_ctrl_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | lc_ctrl_csr_hw_reset | 5 | 5 | 100.00 |
| lc_ctrl_csr_rw | 20 | 20 | 100.00 | ||
| lc_ctrl_csr_aliasing | 5 | 5 | 100.00 | ||
| lc_ctrl_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 617 | 640 | 96.41 | |
| V2S | tl_intg_err | lc_ctrl_tl_intg_err | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_integrity | lc_ctrl_tl_intg_err | 20 | 20 | 100.00 |
| V2S | sec_cm_transition_config_regwen | lc_ctrl_regwen_during_op | 10 | 10 | 100.00 |
| V2S | sec_cm_manuf_state_sparse | lc_ctrl_state_failure | 46 | 50 | 92.00 |
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_transition_ctr_sparse | lc_ctrl_state_failure | 46 | 50 | 92.00 |
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_manuf_state_bkgn_chk | lc_ctrl_state_failure | 46 | 50 | 92.00 |
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_transition_ctr_bkgn_chk | lc_ctrl_state_failure | 46 | 50 | 92.00 |
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_state_config_sparse | lc_ctrl_state_failure | 46 | 50 | 92.00 |
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_main_fsm_sparse | lc_ctrl_state_failure | 46 | 50 | 92.00 |
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_kmac_fsm_sparse | lc_ctrl_state_failure | 46 | 50 | 92.00 |
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_main_fsm_local_esc | lc_ctrl_state_failure | 46 | 50 | 92.00 |
| lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_main_fsm_global_esc | lc_ctrl_security_escalation | 47 | 50 | 94.00 |
| V2S | sec_cm_main_ctrl_flow_consistency | lc_ctrl_state_post_trans | 49 | 50 | 98.00 |
| lc_ctrl_jtag_state_post_trans | 20 | 20 | 100.00 | ||
| V2S | sec_cm_intersig_mubi | lc_ctrl_sec_mubi | 46 | 50 | 92.00 |
| V2S | sec_cm_token_valid_ctrl_mubi | lc_ctrl_sec_mubi | 46 | 50 | 92.00 |
| V2S | sec_cm_token_digest | lc_ctrl_sec_token_digest | 46 | 50 | 92.00 |
| V2S | sec_cm_token_mux_ctrl_redun | lc_ctrl_sec_token_mux | 45 | 50 | 90.00 |
| V2S | sec_cm_token_valid_mux_redun | lc_ctrl_sec_token_mux | 45 | 50 | 90.00 |
| V2S | TOTAL | 157 | 175 | 89.71 | |
| V3 | stress_all_with_rand_reset | lc_ctrl_stress_all_with_rand_reset | 7 | 50 | 14.00 |
| V3 | TOTAL | 7 | 50 | 14.00 | |
| TOTAL | 882 | 970 | 90.93 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 25 | 25 | 17 | 68.00 |
| V2S | 5 | 5 | 1 | 20.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 85.08 | 89.07 | 58.64 | 98.35 | 66.67 | 94.26 | 97.51 | 91.07 |
Exit reason: Error: User command failed Job returned non-zero exit code has 46 failures:
Test lc_ctrl_sec_cm has 1 failures.
0.lc_ctrl_sec_cm.1429591621
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_sec_cm/out/run.log
[make]: simulate
cd /workspace/0.lc_ctrl_sec_cm/out && /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429591621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.1429591621
Chronologic VCS simulator copyright 1991-2021
Contains Synopsys proprietary information.
Compiler version S-2021.09-SP2-1_Full64; Runtime version S-2021.09-SP2-1_Full64; May 18 02:15 2022
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:99: simulate] Error 255
Test lc_ctrl_sec_token_digest has 4 failures.
16.lc_ctrl_sec_token_digest.583142128
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/16.lc_ctrl_sec_token_digest/out/run.log
[make]: simulate
cd /workspace/16.lc_ctrl_sec_token_digest/out && /workspace/default/simv +create_jtag_riscv_map=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583142128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_digest.583142128
Chronologic VCS simulator copyright 1991-2021
Contains Synopsys proprietary information.
Compiler version S-2021.09-SP2-1_Full64; Runtime version S-2021.09-SP2-1_Full64; May 18 02:15 2022
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:99: simulate] Error 255
20.lc_ctrl_sec_token_digest.552061940
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/20.lc_ctrl_sec_token_digest/out/run.log
[make]: simulate
cd /workspace/20.lc_ctrl_sec_token_digest/out && /workspace/default/simv +create_jtag_riscv_map=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552061940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_digest.552061940
Chronologic VCS simulator copyright 1991-2021
Contains Synopsys proprietary information.
Compiler version S-2021.09-SP2-1_Full64; Runtime version S-2021.09-SP2-1_Full64; May 18 02:15 2022
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:99: simulate] Error 255
... and 2 more failures.
Test lc_ctrl_jtag_smoke has 1 failures.
17.lc_ctrl_jtag_smoke.441213444
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/17.lc_ctrl_jtag_smoke/out/run.log
[make]: simulate
cd /workspace/17.lc_ctrl_jtag_smoke/out && /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441213444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.441213444
Chronologic VCS simulator copyright 1991-2021
Contains Synopsys proprietary information.
Compiler version S-2021.09-SP2-1_Full64; Runtime version S-2021.09-SP2-1_Full64; May 18 02:15 2022
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:99: simulate] Error 255
Test lc_ctrl_sec_mubi has 4 failures.
17.lc_ctrl_sec_mubi.2999122649
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/17.lc_ctrl_sec_mubi/out/run.log
[make]: simulate
cd /workspace/17.lc_ctrl_sec_mubi/out && /workspace/default/simv +create_jtag_riscv_map=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999122649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.2999122649
Chronologic VCS simulator copyright 1991-2021
Contains Synopsys proprietary information.
Compiler version S-2021.09-SP2-1_Full64; Runtime version S-2021.09-SP2-1_Full64; May 18 02:15 2022
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:99: simulate] Error 255
21.lc_ctrl_sec_mubi.2061699949
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/21.lc_ctrl_sec_mubi/out/run.log
[make]: simulate
cd /workspace/21.lc_ctrl_sec_mubi/out && /workspace/default/simv +create_jtag_riscv_map=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061699949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.2061699949
Chronologic VCS simulator copyright 1991-2021
Contains Synopsys proprietary information.
Compiler version S-2021.09-SP2-1_Full64; Runtime version S-2021.09-SP2-1_Full64; May 18 02:15 2022
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:99: simulate] Error 255
... and 2 more failures.
Test lc_ctrl_sec_token_mux has 5 failures.
18.lc_ctrl_sec_token_mux.3493861882
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/18.lc_ctrl_sec_token_mux/out/run.log
[make]: simulate
cd /workspace/18.lc_ctrl_sec_token_mux/out && /workspace/default/simv +create_jtag_riscv_map=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493861882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.3493861882
Chronologic VCS simulator copyright 1991-2021
Contains Synopsys proprietary information.
Compiler version S-2021.09-SP2-1_Full64; Runtime version S-2021.09-SP2-1_Full64; May 18 02:15 2022
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:99: simulate] Error 255
22.lc_ctrl_sec_token_mux.641647780
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/22.lc_ctrl_sec_token_mux/out/run.log
[make]: simulate
cd /workspace/22.lc_ctrl_sec_token_mux/out && /workspace/default/simv +create_jtag_riscv_map=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW +prim_cdc_rand_delay_mode=disable -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641647780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.641647780
Chronologic VCS simulator copyright 1991-2021
Contains Synopsys proprietary information.
Compiler version S-2021.09-SP2-1_Full64; Runtime version S-2021.09-SP2-1_Full64; May 18 02:15 2022
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:99: simulate] Error 255
... and 3 more failures.
... and 9 more tests.
UVM_ERROR (lc_ctrl_fsm.sv:706) [ASSERT FAILED] SecCmCFILinear_A has 4 failures:
1.lc_ctrl_sec_cm.2377622281
Line 63, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_sec_cm/out/run.log
UVM_ERROR @ 1024475 ps: (lc_ctrl_fsm.sv:706) [ASSERT FAILED] SecCmCFILinear_A
UVM_INFO @ 1024475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.lc_ctrl_sec_cm.3090836791
Line 98, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_sec_cm/out/run.log
UVM_ERROR @ 10343246 ps: (lc_ctrl_fsm.sv:706) [ASSERT FAILED] SecCmCFILinear_A
UVM_INFO @ 10343246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (lc_ctrl_scoreboard.sv:345) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: lc_ctrl_reg_block.lc_state has 2 failures:
31.lc_ctrl_stress_all_with_rand_reset.1675952178
Line 4355, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/31.lc_ctrl_stress_all_with_rand_reset/out/run.log
UVM_ERROR @ 2505664529 ps: (lc_ctrl_scoreboard.sv:345) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (762010326 [0x2d6b5ad6] vs 34636833 [0x2108421]) reg name: lc_ctrl_reg_block.lc_state
UVM_INFO @ 2505664529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.lc_ctrl_stress_all_with_rand_reset.246048542
Line 8653, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/32.lc_ctrl_stress_all_with_rand_reset/out/run.log
UVM_ERROR @ 10712402510 ps: (lc_ctrl_scoreboard.sv:345) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (762010326 [0x2d6b5ad6] vs 277094664 [0x10842108]) reg name: lc_ctrl_reg_block.lc_state
UVM_INFO @ 10712402510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:734) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:
38.lc_ctrl_stress_all_with_rand_reset.1570220865
Line 25847, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/38.lc_ctrl_stress_all_with_rand_reset/out/run.log
UVM_ERROR @ 38431371722 ps: (lc_ctrl_errors_vseq.sv:734) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (1 [0x1] vs 0 [0x0])
UVM_INFO @ 38431371722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---