LC_CTRL Simulation Results

Tuesday May 23 2023 07:02:27 UTC

GitHub Revision: `83db9403d`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 1254715506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	9.300s	703.509us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.070s	20.045us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.100s	17.600us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.880s	88.133us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.220s	17.048us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.730s	22.978us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.100s	17.600us	20	20	100.00
		lc_ctrl_csr_aliasing	1.220s	17.048us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	13.450s	174.012us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	19.400s	319.258us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.950s	22.879us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.230s	625.910us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	1.028m	1.415ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	23.710s	1.969ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	1.028m	1.415ms	50	50	100.00
		lc_ctrl_prog_failure	6.230s	625.910us	50	50	100.00
		lc_ctrl_errors	23.710s	1.969ms	50	50	100.00
		lc_ctrl_security_escalation	16.140s	482.208us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.100m	3.610ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	23.610s	902.208us	20	20	100.00
		lc_ctrl_jtag_errors	1.129m	5.738ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	17.520s	712.837us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	40.100s	1.343ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	23.610s	902.208us	20	20	100.00
		lc_ctrl_jtag_errors	1.129m	5.738ms	20	20	100.00
		lc_ctrl_jtag_access	29.160s	1.422ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	27.690s	1.116ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.340s	269.901us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.610s	184.784us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	30.430s	2.685ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	29.840s	1.401ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.920s	42.665us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.170s	143.355us	9	10	90.00
		lc_ctrl_jtag_alert_test	3.760s	144.426us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	59.300s	2.681ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.280s	15.214us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	7.470m	31.319ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.400s	35.123us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.070s	2.567ms	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.070s	2.567ms	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.070s	20.045us	5	5	100.00
		lc_ctrl_csr_rw	1.100s	17.600us	20	20	100.00
		lc_ctrl_csr_aliasing	1.220s	17.048us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.060s	98.706us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.070s	20.045us	5	5	100.00
		lc_ctrl_csr_rw	1.100s	17.600us	20	20	100.00
		lc_ctrl_csr_aliasing	1.220s	17.048us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.060s	98.706us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	1.108m	1.128ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.390s	116.763us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.390s	116.763us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	19.400s	319.258us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	1.028m	1.415ms	50	50	100.00
		lc_ctrl_sec_cm	1.108m	1.128ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	1.028m	1.415ms	50	50	100.00
		lc_ctrl_sec_cm	1.108m	1.128ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	1.028m	1.415ms	50	50	100.00
		lc_ctrl_sec_cm	1.108m	1.128ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	1.028m	1.415ms	50	50	100.00
		lc_ctrl_sec_cm	1.108m	1.128ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	1.028m	1.415ms	50	50	100.00
		lc_ctrl_sec_cm	1.108m	1.128ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	1.028m	1.415ms	50	50	100.00
		lc_ctrl_sec_cm	1.108m	1.128ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	1.028m	1.415ms	50	50	100.00
		lc_ctrl_sec_cm	1.108m	1.128ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	1.028m	1.415ms	50	50	100.00
		lc_ctrl_sec_cm	1.108m	1.128ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.140s	482.208us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	13.450s	174.012us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	40.100s	1.343ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	23.230s	2.119ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	23.230s	2.119ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	24.530s	730.146us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	24.710s	3.114ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	24.710s	3.114ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	21.898m	73.233ms	5	50	10.00
V3		TOTAL			5	50	10.00
		TOTAL			984	1030	95.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.12	97.18	94.72	91.98	100.00	95.67	98.48	94.82

Failure Buckets

Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 24 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 24 failures.
  - 2.lc_ctrl_stress_all_with_rand_reset.3339320933
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:05c0cc6b-8bae-4b9d-8a8b-34d825dfa773
```
  - 4.lc_ctrl_stress_all_with_rand_reset.3183435438
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:8d654747-73c6-4695-88b1-6ccb5659312b
```
  - ... and 22 more failures.
Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 8 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.1287295645
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:9f5307c7-c016-4ff0-979b-228b08013ba2
```
  - 12.lc_ctrl_stress_all_with_rand_reset.308275792
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:d548bae0-48ae-4a18-a38f-b5f434f6f8b0
```
  - ... and 6 more failures.

UVM_FATAL (lc_ctrl_scoreboard.sv:265) scoreboard [scoreboard] Access unexpected addr * has 8 failures:

Test lc_ctrl_stress_all_with_rand_reset has 8 failures.

3.lc_ctrl_stress_all_with_rand_reset.3701878792
Line 7120, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 26564576206 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0xe7e13864
  UVM_INFO @ 26564576206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.lc_ctrl_stress_all_with_rand_reset.3645110224
Line 6203, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 7741400181 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x5f9cb800
  UVM_INFO @ 7741400181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.status.ready reset value: * called from ../src/lowrisc_dv_lc_ctrl_env_*/seq_lib/lc_ctrl_errors_vseq.sv: * has 2 failures:

Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

20.lc_ctrl_stress_all_with_rand_reset.2963940704
Line 9777, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 14954114816 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0 called from ../src/lowrisc_dv_lc_ctrl_env_0.1/seq_lib/lc_ctrl_errors_vseq.sv: 290
  UVM_INFO @ 14954114816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

44.lc_ctrl_stress_all_with_rand_reset.961641320
Line 21672, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/44.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 46200634836 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0 called from ../src/lowrisc_dv_lc_ctrl_env_0.1/seq_lib/lc_ctrl_errors_vseq.sv: 290
  UVM_INFO @ 46200634836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (jtag_riscv_monitor.sv:80) monitor [monitor] Bad status - DmiReserved(*) has 1 failures:
- Test lc_ctrl_jtag_csr_mem_rw_with_rand_reset has 1 failures.
  - 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4083986848
    Line 306, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @   4584593 ps: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
  UVM_INFO @   4584593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.status.initialized reset value: * has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 7.lc_ctrl_stress_all_with_rand_reset.984422921
    Line 35399, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 73233409601 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.initialized reset value: 0x0
  UVM_INFO @ 73233409601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_scoreboard.sv:234) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked* has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 16.lc_ctrl_stress_all_with_rand_reset.4264418368
    Line 8464, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9188843921 ps: (lc_ctrl_scoreboard.sv:234) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (5 [0x5] vs 10 [0xa]) Called from line: 97, LC_St DecLcStTestUnlocked3
  UVM_INFO @ 9188843921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.status.ready reset value: * has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 19.lc_ctrl_stress_all_with_rand_reset.1604745690
    Line 13507, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 31683770053 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0
  UVM_INFO @ 31683770053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```