LC_CTRL Simulation Results

Wednesday May 24 2023 07:09:34 UTC

GitHub Revision: `26b0ee226`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 844256362

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	11.040s	327.683us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.220s	16.969us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.070s	15.990us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.590s	693.242us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.450s	42.801us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.220s	29.706us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.070s	15.990us	20	20	100.00
		lc_ctrl_csr_aliasing	1.450s	42.801us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	15.030s	104.261us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	23.460s	447.507us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.930s	44.501us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.930s	256.698us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	1.077m	383.379us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	21.870s	527.798us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	1.077m	383.379us	50	50	100.00
		lc_ctrl_prog_failure	4.930s	256.698us	50	50	100.00
		lc_ctrl_errors	21.870s	527.798us	50	50	100.00
		lc_ctrl_security_escalation	14.880s	857.464us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.546m	4.540ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	32.470s	1.307ms	20	20	100.00
		lc_ctrl_jtag_errors	2.259m	5.399ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	12.840s	567.189us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	33.300s	923.540us	20	20	100.00
		lc_ctrl_jtag_prog_failure	32.470s	1.307ms	20	20	100.00
		lc_ctrl_jtag_errors	2.259m	5.399ms	20	20	100.00
		lc_ctrl_jtag_access	28.440s	1.306ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	37.720s	3.474ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.220s	280.829us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.690s	97.568us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	30.380s	2.687ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	15.580s	1.411ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.900s	47.038us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.710s	138.811us	9	10	90.00
		lc_ctrl_jtag_alert_test	3.460s	139.299us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	48.390s	2.053ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.200s	16.119us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	16.277m	30.845ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.250s	152.907us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.640s	143.961us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.640s	143.961us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.220s	16.969us	5	5	100.00
		lc_ctrl_csr_rw	1.070s	15.990us	20	20	100.00
		lc_ctrl_csr_aliasing	1.450s	42.801us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.760s	161.747us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.220s	16.969us	5	5	100.00
		lc_ctrl_csr_rw	1.070s	15.990us	20	20	100.00
		lc_ctrl_csr_aliasing	1.450s	42.801us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.760s	161.747us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	1.107m	580.751us	5	5	100.00
		lc_ctrl_tl_intg_err	3.790s	431.295us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.790s	431.295us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	23.460s	447.507us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	1.077m	383.379us	50	50	100.00
		lc_ctrl_sec_cm	1.107m	580.751us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	1.077m	383.379us	50	50	100.00
		lc_ctrl_sec_cm	1.107m	580.751us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	1.077m	383.379us	50	50	100.00
		lc_ctrl_sec_cm	1.107m	580.751us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	1.077m	383.379us	50	50	100.00
		lc_ctrl_sec_cm	1.107m	580.751us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	1.077m	383.379us	50	50	100.00
		lc_ctrl_sec_cm	1.107m	580.751us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	1.077m	383.379us	50	50	100.00
		lc_ctrl_sec_cm	1.107m	580.751us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	1.077m	383.379us	50	50	100.00
		lc_ctrl_sec_cm	1.107m	580.751us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	1.077m	383.379us	50	50	100.00
		lc_ctrl_sec_cm	1.107m	580.751us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	14.880s	857.464us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	15.030s	104.261us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	33.300s	923.540us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	22.150s	903.139us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	22.150s	903.139us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	25.200s	2.623ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	23.050s	2.675ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	23.050s	2.675ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	26.651m	150.360ms	3	50	6.00
V3		TOTAL			3	50	6.00
		TOTAL			982	1030	95.34

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.21	97.18	94.99	91.98	100.00	95.88	98.48	95.00

Failure Buckets

Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 29 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 29 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.3441810587
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:e877b644-e287-4f12-bead-1c75553e39eb
```
  - 1.lc_ctrl_stress_all_with_rand_reset.3566899152
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:499d1730-1d86-42da-90f3-81bc4155c41b
```
  - ... and 27 more failures.
Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 8 failures.
  - 4.lc_ctrl_stress_all_with_rand_reset.341850549
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:a2e9cdea-c755-43ad-9482-bb86993b29d7
```
  - 13.lc_ctrl_stress_all_with_rand_reset.933655115
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:95658acc-776d-4f34-b72d-bbcff2d7ff78
```
  - ... and 6 more failures.

UVM_FATAL (lc_ctrl_scoreboard.sv:265) scoreboard [scoreboard] Access unexpected addr * has 6 failures:

Test lc_ctrl_stress_all_with_rand_reset has 6 failures.

7.lc_ctrl_stress_all_with_rand_reset.570780265
Line 2199, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 6086697940 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0xbf246c00
  UVM_INFO @ 6086697940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.lc_ctrl_stress_all_with_rand_reset.2072610066
Line 18584, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 18051073714 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x3df0a000
  UVM_INFO @ 18051073714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (lc_ctrl_scoreboard.sv:239) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked* has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 2.lc_ctrl_stress_all_with_rand_reset.453968135
    Line 5481, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8672881017 ps: (lc_ctrl_scoreboard.sv:239) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 97, LC_St DecLcStTestLocked6
  UVM_INFO @ 8672881017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (jtag_riscv_monitor.sv:80) monitor [monitor] Bad status - DmiReserved(*) has 1 failures:
- Test lc_ctrl_jtag_csr_mem_rw_with_rand_reset has 1 failures.
  - 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.18224871
    Line 304, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  14541665 ps: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
  UVM_INFO @  14541665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:519) [lc_ctrl_smoke_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 3.lc_ctrl_stress_all_with_rand_reset.19504519
    Line 1678, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2570129057 ps: (cip_base_vseq.sv:519) [uvm_test_top.env.virtual_sequencer.lc_ctrl_smoke_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
  UVM_INFO @ 2570129057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.status.ready reset value: * called from ../src/lowrisc_dv_lc_ctrl_env_*/seq_lib/lc_ctrl_errors_vseq.sv: * has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 31.lc_ctrl_stress_all_with_rand_reset.2303491588
    Line 9915, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/31.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7625302454 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0 called from ../src/lowrisc_dv_lc_ctrl_env_0.1/seq_lib/lc_ctrl_errors_vseq.sv: 290
  UVM_INFO @ 7625302454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.status.initialized reset value: * has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 35.lc_ctrl_stress_all_with_rand_reset.1275117399
    Line 3071, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/35.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 76230828263 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.initialized reset value: 0x0
  UVM_INFO @ 76230828263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```