LC_CTRL Simulation Results

Thursday May 25 2023 07:02:34 UTC

GitHub Revision: `94eb0df12`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 77475240

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.970s	477.772us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.320s	22.522us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.040s	15.549us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.780s	257.580us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.660s	34.760us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.680s	28.909us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.040s	15.549us	20	20	100.00
		lc_ctrl_csr_aliasing	1.660s	34.760us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	16.540s	136.418us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	27.420s	1.776ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.930s	14.803us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.270s	994.268us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	57.340s	608.173us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.080s	1.205ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	57.340s	608.173us	50	50	100.00
		lc_ctrl_prog_failure	4.270s	994.268us	50	50	100.00
		lc_ctrl_errors	22.080s	1.205ms	50	50	100.00
		lc_ctrl_security_escalation	17.470s	481.100us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.639m	4.981ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	28.710s	1.183ms	20	20	100.00
		lc_ctrl_jtag_errors	2.049m	4.750ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	20.100s	845.315us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	39.140s	1.048ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	28.710s	1.183ms	20	20	100.00
		lc_ctrl_jtag_errors	2.049m	4.750ms	20	20	100.00
		lc_ctrl_jtag_access	28.370s	1.293ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	27.300s	3.634ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	7.210s	285.990us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.300s	184.234us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	52.260s	2.680ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	29.020s	1.425ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.920s	48.969us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.760s	138.303us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.860s	105.455us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	41.450s	1.951ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.540s	21.469us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.066m	78.267ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.840s	49.949us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.290s	278.370us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.290s	278.370us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.320s	22.522us	5	5	100.00
		lc_ctrl_csr_rw	1.040s	15.549us	20	20	100.00
		lc_ctrl_csr_aliasing	1.660s	34.760us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.570s	52.424us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.320s	22.522us	5	5	100.00
		lc_ctrl_csr_rw	1.040s	15.549us	20	20	100.00
		lc_ctrl_csr_aliasing	1.660s	34.760us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.570s	52.424us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	1.181m	252.362us	5	5	100.00
		lc_ctrl_tl_intg_err	4.260s	163.966us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.260s	163.966us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	27.420s	1.776ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	57.340s	608.173us	50	50	100.00
		lc_ctrl_sec_cm	1.181m	252.362us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	57.340s	608.173us	50	50	100.00
		lc_ctrl_sec_cm	1.181m	252.362us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	57.340s	608.173us	50	50	100.00
		lc_ctrl_sec_cm	1.181m	252.362us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	57.340s	608.173us	50	50	100.00
		lc_ctrl_sec_cm	1.181m	252.362us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	57.340s	608.173us	50	50	100.00
		lc_ctrl_sec_cm	1.181m	252.362us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	57.340s	608.173us	50	50	100.00
		lc_ctrl_sec_cm	1.181m	252.362us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	57.340s	608.173us	50	50	100.00
		lc_ctrl_sec_cm	1.181m	252.362us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	57.340s	608.173us	50	50	100.00
		lc_ctrl_sec_cm	1.181m	252.362us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	17.470s	481.100us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	16.540s	136.418us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	39.140s	1.048ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	27.320s	5.465ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	27.320s	5.465ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	18.540s	4.108ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	17.550s	1.673ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	17.550s	1.673ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	25.545m	48.011ms	7	50	14.00
V3		TOTAL			7	50	14.00
		TOTAL			987	1030	95.83

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.86	97.18	94.81	91.98	97.67	95.88	98.48	95.00

Failure Buckets

Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 23 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 23 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.690833991
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:39edf260-c301-416c-a80b-e24e5876bb33
```
  - 2.lc_ctrl_stress_all_with_rand_reset.1979285286
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:96d1b9d9-a947-4ecf-be58-400e6b80ec43
```
  - ... and 21 more failures.
Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 11 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 11 failures.
  - 1.lc_ctrl_stress_all_with_rand_reset.393090598
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:c5c052bf-d8ba-4148-9039-76a684f2e464
```
  - 5.lc_ctrl_stress_all_with_rand_reset.847462815
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:03a0c968-ee2f-4b72-9a7e-ee816a68b5d8
```
  - ... and 9 more failures.

UVM_FATAL (lc_ctrl_scoreboard.sv:265) scoreboard [scoreboard] Access unexpected addr * has 2 failures:

Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

8.lc_ctrl_stress_all_with_rand_reset.1367683540
Line 17683, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 16899184460 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0xd30cac0c
  UVM_INFO @ 16899184460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

46.lc_ctrl_stress_all_with_rand_reset.1760442423
Line 7257, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/46.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 6784470954 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x2c8e1600
  UVM_INFO @ 6784470954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.status.ready reset value: * called from ../src/lowrisc_dv_lc_ctrl_env_*/seq_lib/lc_ctrl_errors_vseq.sv: * has 2 failures:

Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

16.lc_ctrl_stress_all_with_rand_reset.389057241
Line 845, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 812479303 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0 called from ../src/lowrisc_dv_lc_ctrl_env_0.1/seq_lib/lc_ctrl_errors_vseq.sv: 290
  UVM_INFO @ 812479303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.lc_ctrl_stress_all_with_rand_reset.2242677803
Line 5573, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 8153641591 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0 called from ../src/lowrisc_dv_lc_ctrl_env_0.1/seq_lib/lc_ctrl_errors_vseq.sv: 290
  UVM_INFO @ 8153641591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (lc_ctrl_scoreboard.sv:234) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked* has 2 failures:

Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

34.lc_ctrl_stress_all_with_rand_reset.2748285522
Line 9991, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 32620178651 ps: (lc_ctrl_scoreboard.sv:234) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (10 [0xa] vs 5 [0x5]) Called from line: 97, LC_St DecLcStTestUnlocked2
  UVM_INFO @ 32620178651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

45.lc_ctrl_stress_all_with_rand_reset.778012585
Line 1880, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/45.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1476453869 ps: (lc_ctrl_scoreboard.sv:234) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (5 [0x5] vs 10 [0xa]) Called from line: 97, LC_St DecLcStTestUnlocked4
  UVM_INFO @ 1476453869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (jtag_riscv_monitor.sv:80) monitor [monitor] Bad status - DmiReserved(*) has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 24.lc_ctrl_stress_all_with_rand_reset.3526569979
    Line 4936, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5788723071 ps: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
  UVM_INFO @ 5788723071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.transition_token_* reset value: * has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 36.lc_ctrl_stress_all_with_rand_reset.2279670121
    Line 6101, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/36.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6648925864 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 4162478558 [0xf81a61de]) Regname: lc_ctrl_reg_block.transition_token_0 reset value: 0x0
  UVM_INFO @ 6648925864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_scoreboard.sv:239) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked* has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 43.lc_ctrl_stress_all_with_rand_reset.2824654870
    Line 502, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/43.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 541520358 ps: (lc_ctrl_scoreboard.sv:239) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 97, LC_St DecLcStTestLocked0
  UVM_INFO @ 541520358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```