LC_CTRL Simulation Results

Friday May 26 2023 07:06:59 UTC

GitHub Revision: `213e792ea`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2340441291

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.600s	203.723us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.100s	25.227us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.130s	17.084us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.810s	61.834us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.550s	113.117us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.970s	24.681us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.130s	17.084us	20	20	100.00
		lc_ctrl_csr_aliasing	1.550s	113.117us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	15.840s	67.502us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	14.490s	1.383ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.970s	33.913us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.570s	103.953us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	1.047m	290.872us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	19.200s	5.113ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	1.047m	290.872us	50	50	100.00
		lc_ctrl_prog_failure	4.570s	103.953us	50	50	100.00
		lc_ctrl_errors	19.200s	5.113ms	50	50	100.00
		lc_ctrl_security_escalation	17.830s	879.329us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.495m	4.968ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.140s	789.638us	20	20	100.00
		lc_ctrl_jtag_errors	2.202m	5.045ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	16.970s	691.206us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	32.610s	975.056us	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.140s	789.638us	20	20	100.00
		lc_ctrl_jtag_errors	2.202m	5.045ms	20	20	100.00
		lc_ctrl_jtag_access	32.290s	1.505ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	36.480s	1.512ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.320s	273.188us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.140s	184.933us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	53.790s	2.687ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	26.820s	1.410ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.960s	48.256us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	2.650s	81.631us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.950s	186.323us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	35.130s	1.958ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.050s	38.714us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.285m	79.038ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.580s	87.058us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.280s	126.551us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.280s	126.551us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.100s	25.227us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	17.084us	20	20	100.00
		lc_ctrl_csr_aliasing	1.550s	113.117us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.070s	756.817us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.100s	25.227us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	17.084us	20	20	100.00
		lc_ctrl_csr_aliasing	1.550s	113.117us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.070s	756.817us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	1.145m	271.843us	5	5	100.00
		lc_ctrl_tl_intg_err	5.390s	201.489us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	5.390s	201.489us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	14.490s	1.383ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	1.047m	290.872us	50	50	100.00
		lc_ctrl_sec_cm	1.145m	271.843us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	1.047m	290.872us	50	50	100.00
		lc_ctrl_sec_cm	1.145m	271.843us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	1.047m	290.872us	50	50	100.00
		lc_ctrl_sec_cm	1.145m	271.843us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	1.047m	290.872us	50	50	100.00
		lc_ctrl_sec_cm	1.145m	271.843us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	1.047m	290.872us	50	50	100.00
		lc_ctrl_sec_cm	1.145m	271.843us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	1.047m	290.872us	50	50	100.00
		lc_ctrl_sec_cm	1.145m	271.843us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	1.047m	290.872us	50	50	100.00
		lc_ctrl_sec_cm	1.145m	271.843us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	1.047m	290.872us	50	50	100.00
		lc_ctrl_sec_cm	1.145m	271.843us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	17.830s	879.329us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	15.840s	67.502us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	32.610s	975.056us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	23.260s	1.207ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	23.260s	1.207ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	25.710s	1.104ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	17.150s	894.599us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	17.150s	894.599us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	26.413m	499.703ms	6	50	12.00
V3		TOTAL			6	50	12.00
		TOTAL			986	1030	95.73

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.24	97.18	95.26	91.98	100.00	95.88	98.73	94.64

Failure Buckets

Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 20 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 20 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.1462094399
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:71ef98b3-d3a1-4690-abfb-8d59af910bf9
```
  - 1.lc_ctrl_stress_all_with_rand_reset.3725559657
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:fe70c517-d314-4aed-b257-d4151b81084b
```
  - ... and 18 more failures.
Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 13 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 13 failures.
  - 2.lc_ctrl_stress_all_with_rand_reset.481164935
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:ad28e9e6-a72b-4aaf-8067-1b581aa9f121
```
  - 3.lc_ctrl_stress_all_with_rand_reset.1373018133
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:c2c065fa-94fd-4045-8b60-6069cf029c7e
```
  - ... and 11 more failures.

UVM_FATAL (lc_ctrl_scoreboard.sv:265) scoreboard [scoreboard] Access unexpected addr * has 7 failures:

Test lc_ctrl_stress_all_with_rand_reset has 7 failures.

6.lc_ctrl_stress_all_with_rand_reset.340631117
Line 32565, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 45008005804 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x5299a00
  UVM_INFO @ 45008005804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.lc_ctrl_stress_all_with_rand_reset.990849611
Line 7346, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 9343886127 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0xe051a800
  UVM_INFO @ 9343886127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (lc_ctrl_scoreboard.sv:371) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: lc_ctrl_reg_block.lc_transition_cnt has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 17.lc_ctrl_stress_all_with_rand_reset.4013204447
    Line 6243, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3392476385 ps: (lc_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (16 [0x10] vs 31 [0x1f]) reg name: lc_ctrl_reg_block.lc_transition_cnt
  UVM_INFO @ 3392476385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.status.initialized reset value: * has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 20.lc_ctrl_stress_all_with_rand_reset.3623873498
    Line 7095, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3849198831 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.initialized reset value: 0x0
  UVM_INFO @ 3849198831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (jtag_riscv_monitor.sv:80) monitor [monitor] Bad status - DmiReserved(*) has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 39.lc_ctrl_stress_all_with_rand_reset.344859681
    Line 20923, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 34432508838 ps: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
  UVM_INFO @ 34432508838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:519) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 47.lc_ctrl_stress_all_with_rand_reset.3258018132
    Line 9373, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/47.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11911133268 ps: (cip_base_vseq.sv:519) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 11911133268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```