LC_CTRL Simulation Results

Saturday May 27 2023 07:02:22 UTC

GitHub Revision: `c06cc3921`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 2359737659

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.590s	117.306us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.290s	21.846us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.100s	14.804us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.910s	80.838us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.360s	24.301us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.710s	79.537us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.100s	14.804us	20	20	100.00
		lc_ctrl_csr_aliasing	1.360s	24.301us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	20.080s	515.602us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	24.840s	402.466us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.940s	12.845us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.850s	213.939us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	57.490s	1.462ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.340s	1.006ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	57.490s	1.462ms	50	50	100.00
		lc_ctrl_prog_failure	4.850s	213.939us	50	50	100.00
		lc_ctrl_errors	22.340s	1.006ms	50	50	100.00
		lc_ctrl_security_escalation	14.990s	1.740ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.763m	5.039ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	27.210s	1.063ms	20	20	100.00
		lc_ctrl_jtag_errors	2.216m	5.242ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	16.530s	710.182us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	39.740s	1.347ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	27.210s	1.063ms	20	20	100.00
		lc_ctrl_jtag_errors	2.216m	5.242ms	20	20	100.00
		lc_ctrl_jtag_access	30.420s	1.479ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	25.840s	1.944ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.410s	281.783us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.010s	195.476us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	54.040s	2.668ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	28.350s	1.405ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.990s	340.261us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.540s	145.469us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.830s	101.421us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	18.630s	2.335ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.150s	16.171us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	9.667m	15.441ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.250s	22.322us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.980s	318.920us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.980s	318.920us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.290s	21.846us	5	5	100.00
		lc_ctrl_csr_rw	1.100s	14.804us	20	20	100.00
		lc_ctrl_csr_aliasing	1.360s	24.301us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.760s	22.048us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.290s	21.846us	5	5	100.00
		lc_ctrl_csr_rw	1.100s	14.804us	20	20	100.00
		lc_ctrl_csr_aliasing	1.360s	24.301us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.760s	22.048us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	57.100s	1.871ms	5	5	100.00
		lc_ctrl_tl_intg_err	3.800s	404.885us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.800s	404.885us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	24.840s	402.466us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	57.490s	1.462ms	50	50	100.00
		lc_ctrl_sec_cm	57.100s	1.871ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	57.490s	1.462ms	50	50	100.00
		lc_ctrl_sec_cm	57.100s	1.871ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	57.490s	1.462ms	50	50	100.00
		lc_ctrl_sec_cm	57.100s	1.871ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	57.490s	1.462ms	50	50	100.00
		lc_ctrl_sec_cm	57.100s	1.871ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	57.490s	1.462ms	50	50	100.00
		lc_ctrl_sec_cm	57.100s	1.871ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	57.490s	1.462ms	50	50	100.00
		lc_ctrl_sec_cm	57.100s	1.871ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	57.490s	1.462ms	50	50	100.00
		lc_ctrl_sec_cm	57.100s	1.871ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	57.490s	1.462ms	50	50	100.00
		lc_ctrl_sec_cm	57.100s	1.871ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	14.990s	1.740ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	20.080s	515.602us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	39.740s	1.347ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	28.580s	853.205us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	28.580s	853.205us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	28.410s	3.964ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	15.980s	487.365us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	15.980s	487.365us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	30.330m	133.426ms	6	50	12.00
V3		TOTAL			6	50	12.00
		TOTAL			986	1030	95.73

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.85	97.18	95.08	91.98	97.67	95.67	98.73	94.64

Failure Buckets

Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 18 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 18 failures.
  - 3.lc_ctrl_stress_all_with_rand_reset.4047479673
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:dcccee02-71a4-4203-9b13-18b2a53ae6de
```
  - 11.lc_ctrl_stress_all_with_rand_reset.1114910279
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:c69cb7b8-2b90-4162-aa3f-7abe66bee48c
```
  - ... and 16 more failures.
Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 9 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 9 failures.
  - 2.lc_ctrl_stress_all_with_rand_reset.4267240613
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:7444d54c-3808-4d31-a5d6-d510e79dd478
```
  - 4.lc_ctrl_stress_all_with_rand_reset.3426087084
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:c8b2912a-2db1-4cf4-a19a-b5b400f78208
```
  - ... and 7 more failures.

UVM_ERROR (jtag_riscv_monitor.sv:80) monitor [monitor] Bad status - DmiReserved(*) has 5 failures:

Test lc_ctrl_stress_all_with_rand_reset has 5 failures.

6.lc_ctrl_stress_all_with_rand_reset.1566637683
Line 19394, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 51055571317 ps: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
  UVM_INFO @ 51055571317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.lc_ctrl_stress_all_with_rand_reset.1026607634
Line 17033, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 18048598161 ps: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
  UVM_INFO @ 18048598161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (lc_ctrl_scoreboard.sv:265) scoreboard [scoreboard] Access unexpected addr * has 4 failures:

Test lc_ctrl_stress_all_with_rand_reset has 4 failures.

5.lc_ctrl_stress_all_with_rand_reset.2092060924
Line 21704, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 48261431990 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x2a3ffd38
  UVM_INFO @ 48261431990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.lc_ctrl_stress_all_with_rand_reset.3999695006
Line 6072, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 9164929010 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0xe852d074
  UVM_INFO @ 9164929010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.status.ready reset value: * called from ../src/lowrisc_dv_lc_ctrl_env_*/seq_lib/lc_ctrl_errors_vseq.sv: * has 2 failures:

Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

15.lc_ctrl_stress_all_with_rand_reset.3867747832
Line 3015, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/15.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 11456480908 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0 called from ../src/lowrisc_dv_lc_ctrl_env_0.1/seq_lib/lc_ctrl_errors_vseq.sv: 290
  UVM_INFO @ 11456480908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

31.lc_ctrl_stress_all_with_rand_reset.4196200229
Line 943, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/31.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1158411728 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0 called from ../src/lowrisc_dv_lc_ctrl_env_0.1/seq_lib/lc_ctrl_errors_vseq.sv: 290
  UVM_INFO @ 1158411728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (lc_ctrl_scoreboard.sv:239) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStRaw has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 7.lc_ctrl_stress_all_with_rand_reset.1983261135
    Line 3424, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4552096092 ps: (lc_ctrl_scoreboard.sv:239) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 97, LC_St DecLcStRaw
  UVM_INFO @ 4552096092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.transition_token_* reset value: * has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 12.lc_ctrl_stress_all_with_rand_reset.571030995
    Line 4555, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6056223936 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1773475054 [0x69b514ee]) Regname: lc_ctrl_reg_block.transition_token_2 reset value: 0x0
  UVM_INFO @ 6056223936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:519) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 19.lc_ctrl_stress_all_with_rand_reset.2361271284
    Line 27901, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 52527555264 ps: (cip_base_vseq.sv:519) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 52527555264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 24.lc_ctrl_stress_all_with_rand_reset.850115476
    Line 28347, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Error-[CNST-STOF] Constraint solver timeout failure
  ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
    Exceeded cpu time limit during solve.
    Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
    limit.  The default cpu limit is 1000 seconds per partition.
```
UVM_ERROR (lc_ctrl_scoreboard.sv:234) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked* has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 27.lc_ctrl_stress_all_with_rand_reset.776623132
    Line 9004, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19337753354 ps: (lc_ctrl_scoreboard.sv:234) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (5 [0x5] vs 10 [0xa]) Called from line: 97, LC_St DecLcStTestUnlocked5
  UVM_INFO @ 19337753354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_scoreboard.sv:239) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked* has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 37.lc_ctrl_stress_all_with_rand_reset.1531396815
    Line 20586, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/37.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 29951463210 ps: (lc_ctrl_scoreboard.sv:239) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 97, LC_St DecLcStTestLocked5
  UVM_INFO @ 29951463210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```