LC_CTRL Simulation Results

Monday May 29 2023 07:02:33 UTC

GitHub Revision: 877a77116

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88555427

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke lc_ctrl_smoke 6.550s 225.256us 50 50 100.00
V1 csr_hw_reset lc_ctrl_csr_hw_reset 1.190s 123.879us 5 5 100.00
V1 csr_rw lc_ctrl_csr_rw 1.200s 19.995us 20 20 100.00
V1 csr_bit_bash lc_ctrl_csr_bit_bash 2.350s 171.941us 5 5 100.00
V1 csr_aliasing lc_ctrl_csr_aliasing 1.630s 381.719us 5 5 100.00
V1 csr_mem_rw_with_rand_reset lc_ctrl_csr_mem_rw_with_rand_reset 2.260s 27.488us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr lc_ctrl_csr_rw 1.200s 19.995us 20 20 100.00
lc_ctrl_csr_aliasing 1.630s 381.719us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 state_post_trans lc_ctrl_state_post_trans 15.390s 249.166us 50 50 100.00
V2 regwen_during_op lc_ctrl_regwen_during_op 21.650s 1.648ms 10 10 100.00
V2 rand_wr_claim_transition_if lc_ctrl_claim_transition_if 0.940s 13.108us 10 10 100.00
V2 lc_prog_failure lc_ctrl_prog_failure 6.030s 642.035us 50 50 100.00
V2 lc_state_failure lc_ctrl_state_failure 52.110s 367.963us 50 50 100.00
V2 lc_errors lc_ctrl_errors 25.900s 2.700ms 50 50 100.00
V2 security_escalation lc_ctrl_state_failure 52.110s 367.963us 50 50 100.00
lc_ctrl_prog_failure 6.030s 642.035us 50 50 100.00
lc_ctrl_errors 25.900s 2.700ms 50 50 100.00
lc_ctrl_security_escalation 16.600s 483.330us 50 50 100.00
lc_ctrl_jtag_state_failure 2.379m 4.135ms 20 20 100.00
lc_ctrl_jtag_prog_failure 21.580s 836.659us 20 20 100.00
lc_ctrl_jtag_errors 2.342m 5.516ms 20 20 100.00
V2 jtag_access lc_ctrl_jtag_smoke 16.800s 697.255us 20 20 100.00
lc_ctrl_jtag_state_post_trans 36.060s 1.226ms 20 20 100.00
lc_ctrl_jtag_prog_failure 21.580s 836.659us 20 20 100.00
lc_ctrl_jtag_errors 2.342m 5.516ms 20 20 100.00
lc_ctrl_jtag_access 24.230s 1.144ms 50 50 100.00
lc_ctrl_jtag_regwen_during_op 36.040s 2.800ms 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 4.410s 272.940us 10 10 100.00
lc_ctrl_jtag_csr_rw 4.460s 188.102us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 29.950s 2.668ms 10 10 100.00
lc_ctrl_jtag_csr_aliasing 28.910s 1.410ms 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.570s 33.600us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.960s 137.641us 9 10 90.00
lc_ctrl_jtag_alert_test 3.130s 128.451us 10 10 100.00
V2 jtag_priority lc_ctrl_jtag_priority 55.730s 2.739ms 10 10 100.00
V2 lc_ctrl_volatile_unlock lc_ctrl_volatile_unlock_smoke 1.300s 21.191us 50 50 100.00
V2 stress_all lc_ctrl_stress_all 14.432m 27.368ms 50 50 100.00
V2 alert_test lc_ctrl_alert_test 1.350s 108.982us 50 50 100.00
V2 tl_d_oob_addr_access lc_ctrl_tl_errors 5.360s 268.296us 20 20 100.00
V2 tl_d_illegal_access lc_ctrl_tl_errors 5.360s 268.296us 20 20 100.00
V2 tl_d_outstanding_access lc_ctrl_csr_hw_reset 1.190s 123.879us 5 5 100.00
lc_ctrl_csr_rw 1.200s 19.995us 20 20 100.00
lc_ctrl_csr_aliasing 1.630s 381.719us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.040s 80.645us 20 20 100.00
V2 tl_d_partial_access lc_ctrl_csr_hw_reset 1.190s 123.879us 5 5 100.00
lc_ctrl_csr_rw 1.200s 19.995us 20 20 100.00
lc_ctrl_csr_aliasing 1.630s 381.719us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.040s 80.645us 20 20 100.00
V2 TOTAL 699 700 99.86
V2S tl_intg_err lc_ctrl_sec_cm 1.057m 447.687us 5 5 100.00
lc_ctrl_tl_intg_err 3.580s 188.837us 20 20 100.00
V2S sec_cm_bus_integrity lc_ctrl_tl_intg_err 3.580s 188.837us 20 20 100.00
V2S sec_cm_transition_config_regwen lc_ctrl_regwen_during_op 21.650s 1.648ms 10 10 100.00
V2S sec_cm_manuf_state_sparse lc_ctrl_state_failure 52.110s 367.963us 50 50 100.00
lc_ctrl_sec_cm 1.057m 447.687us 5 5 100.00
V2S sec_cm_transition_ctr_sparse lc_ctrl_state_failure 52.110s 367.963us 50 50 100.00
lc_ctrl_sec_cm 1.057m 447.687us 5 5 100.00
V2S sec_cm_manuf_state_bkgn_chk lc_ctrl_state_failure 52.110s 367.963us 50 50 100.00
lc_ctrl_sec_cm 1.057m 447.687us 5 5 100.00
V2S sec_cm_transition_ctr_bkgn_chk lc_ctrl_state_failure 52.110s 367.963us 50 50 100.00
lc_ctrl_sec_cm 1.057m 447.687us 5 5 100.00
V2S sec_cm_state_config_sparse lc_ctrl_state_failure 52.110s 367.963us 50 50 100.00
lc_ctrl_sec_cm 1.057m 447.687us 5 5 100.00
V2S sec_cm_main_fsm_sparse lc_ctrl_state_failure 52.110s 367.963us 50 50 100.00
lc_ctrl_sec_cm 1.057m 447.687us 5 5 100.00
V2S sec_cm_kmac_fsm_sparse lc_ctrl_state_failure 52.110s 367.963us 50 50 100.00
lc_ctrl_sec_cm 1.057m 447.687us 5 5 100.00
V2S sec_cm_main_fsm_local_esc lc_ctrl_state_failure 52.110s 367.963us 50 50 100.00
lc_ctrl_sec_cm 1.057m 447.687us 5 5 100.00
V2S sec_cm_main_fsm_global_esc lc_ctrl_security_escalation 16.600s 483.330us 50 50 100.00
V2S sec_cm_main_ctrl_flow_consistency lc_ctrl_state_post_trans 15.390s 249.166us 50 50 100.00
lc_ctrl_jtag_state_post_trans 36.060s 1.226ms 20 20 100.00
V2S sec_cm_intersig_mubi lc_ctrl_sec_mubi 22.740s 944.286us 50 50 100.00
V2S sec_cm_token_valid_ctrl_mubi lc_ctrl_sec_mubi 22.740s 944.286us 50 50 100.00
V2S sec_cm_token_digest lc_ctrl_sec_token_digest 24.410s 10.799ms 50 50 100.00
V2S sec_cm_token_mux_ctrl_redun lc_ctrl_sec_token_mux 22.640s 2.710ms 50 50 100.00
V2S sec_cm_token_valid_mux_redun lc_ctrl_sec_token_mux 22.640s 2.710ms 50 50 100.00
V2S TOTAL 175 175 100.00
V3 stress_all_with_rand_reset lc_ctrl_stress_all_with_rand_reset 14.670m 120.976ms 4 50 8.00
V3 TOTAL 4 50 8.00
TOTAL 983 1030 95.44

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 27 27 26 96.30
V2S 5 5 5 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.17 97.18 94.90 91.98 100.00 95.67 98.48 95.00

Failure Buckets

Past Results