Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.66 96.94 91.76 84.26 90.70 94.70 98.48 91.79


Total tests in report: 980
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
41.76 41.76 31.34 31.34 38.14 38.14 18.64 18.64 90.70 90.70 22.20 22.20 75.38 75.38 15.89 15.89 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.9453593290124549041607630655474314177103406763485200373494155464770072246117
67.00 25.25 71.52 40.17 52.46 14.32 39.37 20.73 90.70 0.00 78.41 56.21 92.64 17.26 43.93 28.04 /workspace/coverage/default/49.lc_ctrl_errors.87485089985670633302127035850865764107264823078667570821947424770895928630935
75.01 8.00 78.10 6.58 60.16 7.70 59.09 19.72 90.70 0.00 86.76 8.35 94.16 1.52 56.07 12.14 /workspace/coverage/default/19.lc_ctrl_stress_all.50710520127118002108462316373480177725025972176577035920124915786576593890203
81.28 6.27 88.77 10.67 83.71 23.55 65.14 6.05 90.70 0.00 89.41 2.65 95.18 1.02 56.07 0.00 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.54843891378414085810332420423977970995859759627674008411164116991968477068988
85.32 4.04 88.87 0.10 85.50 1.79 79.08 13.94 90.70 0.00 90.02 0.61 95.94 0.76 67.14 11.07 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.45641165552327531517563554697136382650393639584834706326066230590910536495056
87.21 1.89 95.30 6.43 85.77 0.27 79.32 0.24 90.70 0.00 91.65 1.63 95.94 0.00 71.79 4.64 /workspace/coverage/default/0.lc_ctrl_sec_mubi.18488189016580783700592663304091007019013753828622664257286773962707658156094
88.96 1.75 95.61 0.31 87.38 1.61 79.42 0.10 90.70 0.00 92.46 0.81 96.45 0.51 80.71 8.93 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.69134581051343895240464332151727045997836312726161685746712670625033569487839
89.84 0.87 95.81 0.20 88.00 0.63 82.08 2.66 90.70 0.00 93.48 1.02 96.45 0.00 82.32 1.61 /workspace/coverage/default/33.lc_ctrl_sec_token_mux.107530620386759870675056898631281188660911795597967738744775698397872207582997
90.55 0.71 95.81 0.00 88.36 0.36 82.08 0.00 90.70 0.00 93.48 0.00 96.45 0.00 86.96 4.64 /workspace/coverage/default/18.lc_ctrl_security_escalation.11627870205343103813919622666944070363552696465323908856033050372154386241218
90.98 0.43 96.22 0.41 89.08 0.72 82.10 0.02 90.70 0.00 93.48 0.00 97.97 1.52 87.32 0.36 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.107438267761084771464388096702069511069547872448343510383851528404395151878028
91.36 0.38 96.78 0.56 90.15 1.07 82.12 0.02 90.70 0.00 94.30 0.81 97.97 0.00 87.50 0.18 /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.90432775881773570393071376967109435165107327366048903588049367471245654276992
91.67 0.31 96.78 0.00 90.15 0.00 82.32 0.20 90.70 0.00 94.30 0.00 97.97 0.00 89.46 1.96 /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.114123701764904619691234933323955097857392258186462666106001748300063051897930
91.96 0.29 96.84 0.05 90.78 0.63 82.50 0.18 90.70 0.00 94.50 0.20 98.22 0.25 90.18 0.71 /workspace/coverage/default/0.lc_ctrl_sec_cm.77441694423278901720412568349593055297780543047490573504441743950477134246805
92.15 0.19 96.94 0.10 90.96 0.18 82.92 0.42 90.70 0.00 94.70 0.20 98.48 0.25 90.36 0.18 /workspace/coverage/default/0.lc_ctrl_jtag_access.93215230357570700686483770903140507270894037377564394506281647162605884219384
92.32 0.17 96.94 0.00 90.96 0.00 84.12 1.20 90.70 0.00 94.70 0.00 98.48 0.00 90.36 0.00 /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.82275019534947239775406299445620743853149885456545288783388605281894502578910
92.45 0.13 96.94 0.00 90.96 0.00 84.12 0.00 90.70 0.00 94.70 0.00 98.48 0.00 91.25 0.89 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.84409513814721306474044063206040364041000614221420943689441906789454350876816
92.57 0.12 96.94 0.00 91.76 0.81 84.14 0.02 90.70 0.00 94.70 0.00 98.48 0.00 91.25 0.00 /workspace/coverage/default/12.lc_ctrl_alert_test.6553361949119367754280657762017496631432243227859189432060783341023664290481
92.61 0.04 96.94 0.00 91.76 0.00 84.26 0.12 90.70 0.00 94.70 0.00 98.48 0.00 91.43 0.18 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.21868758646737310453794532139418292470985703079148338902301262922786808624240
92.64 0.03 96.94 0.00 91.76 0.00 84.26 0.00 90.70 0.00 94.70 0.00 98.48 0.00 91.61 0.18 /workspace/coverage/default/11.lc_ctrl_state_post_trans.96790254062451047985010940108342387390753079160857550250463382123868774224089
92.66 0.03 96.94 0.00 91.76 0.00 84.26 0.00 90.70 0.00 94.70 0.00 98.48 0.00 91.79 0.18 /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.33439163416846457099015991460117905184158397616232091458971036187878724188601


Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.16290686735668327925237918272220957125171047262654411201521052131660949014121
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.108858101959938519293593757832948757071136228564929091961302514992572998128660
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.83460878728489635983785928623155409368735513816812524232101611515667527532167
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.66950464173302947052574005227393920023193108878976679194082856498965563589818
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.90195106346387469159560000680095946401206188895174168456271306427369847536035
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.73655510119059978002283080772681509861930170701889559000819565615949411785927
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.63355651139104811014877470577112592874720384202099904987407512355438932282973
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.79078019271718838075413857331426804979424963885005648451944155921472019051066
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.18364242716013967096261607184909517425344944053350714647428278674678288371233
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.11650004854904075503089858705013387841595977349822951827913891152820770569817
/workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.32068564275319456874181199588983920647934182508544903949960425983907760173548
/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.25982133609712314118712342370922417342046361263490055647811964346661351786422
/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.35357144637480437770082611509147385213028299106921553695633130404396972741972
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.39822468288715526453474399548630379625552270735721232669920559956268009747211
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.18014829050367792049362956666437602348869369690997949950984983684945285931322
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.53365302487128394646448876603380060619766472293927112140621652250638503585052
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.36681187110295752648772539233849384357654754356109259175011529878905971227343
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.58033402995863189071599704800597294863699570008426833086411599100433785604279
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.8725998357730691331627018072554149151346378943310831893333422958672116263928
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.19846137826665708186722539291828396077052482616957399032229101090490784402421
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.38755182480076917081489896712385663967335437628739955223760674444670094586330
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.95785416405007151747771961197753258553200277177957147324792469553047942033309
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.40569550486612450008624445780124439947846172625153963067918019819281838772187
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.98979330097014323465687435269932166037016839613987085621217318889054288198509
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.58711926536117017589183411334184219038081082422099398627222548708296777226819
/workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.70552396300259163517500784716817000859682895270947637445200245956066037966569
/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.108370605215513493911097443159055628359260427369654750171217543164144130634051
/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.51561762586612151252012727882126860176356806625758748668252525013297113545435
/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.104674096743643305395900525450252564538590766257547773228813753778293427092795
/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.72925461630715270573553672194135524385465805626607427033711058860113596978919
/workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.53468034219021467366634786249143312064936158963781961021996460552419928058722
/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.6591105513026295883756785920479012665960269760226367943551797110348554113876
/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.96478745938657651685360503330939501593407596803513876393285889363814341959986
/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.102644714253189353531721670692117909192469007011024555346740755280614351366978
/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.51164555356477297914177202710936130986455383408933732118764511447703740489195
/workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.42151676455771676842913765192551220820450756405630982467133969548778566052459
/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.93621744690106765486676758806884924339384422738837050141776764624709483897155
/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.93222235221002225735879841317031550228677843104574983576043529001107418239345
/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.69088335036718042171068683544248673941293266887253594944358773044026449771142
/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.61087181204682136406038013604606186608314593637997048653311658142978498386138
/workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.22298377406410336882587356258332290899304366953259790368222372735604177271776
/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.48091241148828168241451185348492950158236728359201482977639250950727203601709
/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.95770812897880409432928766032728358389738893893580543325305399040795399163325
/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.31101487015116773753138671215348715197681518271697802397560933292677749680286
/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.72776124205403955219874859833666540010812713636923341383382996525491426574158
/workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.34729912522762681040725945177486928815289201318826973634076530583599429294455
/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.46492813175005850294111732486790469924424256018787321919070962282331255183306
/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.20051483477260892212553155450932606037907617905759847702738671998711108439409
/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.96274333192335925656468590752743617030316648095071687568080482365605090325952
/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.75228150861905699342397435930343170648575099621390498286518174880665458981500
/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.17272410572909076834677081885576234753498146004927380794026680508656660244045
/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.112375062096570231558391358075469780423406829461242013253657331578466109657090
/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.114205524607912824199342747732320575801996679878981996220977771760825895608313
/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.29094445130791408003079815528012313193387717761075783579497676338346485255934
/workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.107848197603356311001542415223485959293816471297503907902177463554569331903920
/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.62976134355004312504545421050884345675981885428785347046161376236814609126068
/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.74961123203085663856612373219867416352120181117314104816544307304965755195046
/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.97476081032665002187694705236024954457391541898032244781781619709846287829074
/workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.69710872368846589094349317242937087655108113989137237956576075166056085114776
/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.69524492449189090346437856425361892087959544048453362124685828548733188886220
/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.78858823306247876759727202690101602119198624884649278329206592123115956948904
/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.107094602402691719537895103495224076651219667004757170087572385557117556831041
/workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.37707716911070513490459596236922160399984060401167227484356573976502941254391
/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.26668235253910376632113342977433557134018912899345288589636174344375070468561
/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.31997516233946982130589198327098689163525054010497797929058313894190818911117
/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.80269124688055611185811798072316975106483675861282217080611122231981973910474
/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.42777649472345041578733050386974722434180405223723969357547799504541757747220
/workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.83624750081544231418195348505027749506369296455025824092851222718489269546744
/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.99050994239932042507719212386344576965398176512486135300892297273183128710291
/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.17385105501831325757958963347922519132290887704072430075714664534698289117988
/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.55563301017322139754813485201482992499164533466865448572968615958411333302250
/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.29761321890574697976302568576397912276588423538321711403981920488357402161575
/workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3336476537406936244206582538404620107876771472649794855196232577746465727659
/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.73335595329188843530158035319876569591269655566316200163795093335787791025153
/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.9703354673668057363658771485037192619035980746224350318388382643856640473050
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.69537186780716441012558117639797517222382419325934245730673831271041623302651
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.34980416125604583017177150845077131565676695741381855156675419357921824397659
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.36893234713992094072606029947188499500031184739359704039298664614031225853803
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.58543841315435884389006537967209106705385339528946449829158223076386265078138
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.31207019736292745558916049083494051619574349690479930471012123883127935483103
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.78397021028438003059147262660352861378698168305890426462938498861608093446205
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.86879716720660940221350481148276274985858334165671786502475404591134033918380
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.40075745306210171547071339209285382070540987944650228263985451792136293326626
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.30474126944108506210646432507119678694826367192737873506437507397738491312049
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.88479559783713340851757605707870984541146357552508986589702320561679921374355
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.18615349425781662988181523238360565430871467560074299123434403675137961132826
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.69390043855948202620511234931795630057691130371818171615001234054815687487521
/workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.78001687890098474893775502112404657978146102590288758070873008203135477925942
/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.46200694964750313334843963927206184310273097874902035689835028610465857051138
/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.52676315914933763372309978031313308010745501079144510020816595688324293203509
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.16696984512750830032334951765235567916036838661142830181759655095375646242276
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.72048131555944688315819194826897145714509881574403081408358202320473170074955
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.54239216135557883736924312012847453563559320723569895485067455056721826651672
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/workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.77289527867870337267355795577718867148430291052796867091785362618070812141344




Total test records in report: 980
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TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T46 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.9453593290124549041607630655474314177103406763485200373494155464770072246117 Nov 22 12:33:53 PM PST 23 Nov 22 12:33:55 PM PST 23 66993279 ps
T69 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.114205524607912824199342747732320575801996679878981996220977771760825895608313 Nov 22 12:33:43 PM PST 23 Nov 22 12:33:45 PM PST 23 41172057 ps
T70 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.58711926536117017589183411334184219038081082422099398627222548708296777226819 Nov 22 12:32:51 PM PST 23 Nov 22 12:32:58 PM PST 23 66993279 ps
T74 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.43309688497226276760913666622165641245758106375302723450370145581498079989921 Nov 22 12:33:02 PM PST 23 Nov 22 12:33:08 PM PST 23 197527949 ps
T73 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.26668235253910376632113342977433557134018912899345288589636174344375070468561 Nov 22 12:33:36 PM PST 23 Nov 22 12:33:40 PM PST 23 219831342 ps
T71 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.21868758646737310453794532139418292470985703079148338902301262922786808624240 Nov 22 12:33:09 PM PST 23 Nov 22 12:33:13 PM PST 23 41172057 ps
T92 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.18014829050367792049362956666437602348869369690997949950984983684945285931322 Nov 22 12:32:49 PM PST 23 Nov 22 12:32:58 PM PST 23 140599833 ps
T75 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.54843891378414085810332420423977970995859759627674008411164116991968477068988 Nov 22 12:33:07 PM PST 23 Nov 22 12:33:14 PM PST 23 360562359 ps
T93 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.11650004854904075503089858705013387841595977349822951827913891152820770569817 Nov 22 12:32:49 PM PST 23 Nov 22 12:32:58 PM PST 23 66993279 ps
T76 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.86879716720660940221350481148276274985858334165671786502475404591134033918380 Nov 22 12:32:57 PM PST 23 Nov 22 12:33:14 PM PST 23 1837157689 ps
T95 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.69134581051343895240464332151727045997836312726161685746712670625033569487839 Nov 22 12:33:28 PM PST 23 Nov 22 12:33:32 PM PST 23 219831342 ps
T81 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.107438267761084771464388096702069511069547872448343510383851528404395151878028 Nov 22 12:33:04 PM PST 23 Nov 22 12:33:11 PM PST 23 33332834 ps
T97 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.18364242716013967096261607184909517425344944053350714647428278674678288371233 Nov 22 12:33:01 PM PST 23 Nov 22 12:33:07 PM PST 23 241456169 ps
T98 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.31207019736292745558916049083494051619574349690479930471012123883127935483103 Nov 22 12:33:01 PM PST 23 Nov 22 12:33:05 PM PST 23 24850759 ps
T96 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.99050994239932042507719212386344576965398176512486135300892297273183128710291 Nov 22 12:33:47 PM PST 23 Nov 22 12:33:51 PM PST 23 219831342 ps
T107 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.96243207227018934075003655781065605415011845914473478211293254845003986334898 Nov 22 12:33:07 PM PST 23 Nov 22 12:33:15 PM PST 23 219831342 ps
T72 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.78858823306247876759727202690101602119198624884649278329206592123115956948904 Nov 22 12:33:32 PM PST 23 Nov 22 12:33:34 PM PST 23 41172057 ps
T108 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.25982133609712314118712342370922417342046361263490055647811964346661351786422 Nov 22 12:32:48 PM PST 23 Nov 22 12:33:00 PM PST 23 219831342 ps
T109 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.50309241460251429452856670612811302712328251867055763442278968275836204012566 Nov 22 12:33:07 PM PST 23 Nov 22 12:33:15 PM PST 23 219831342 ps
T99 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.88479559783713340851757605707870984541146357552508986589702320561679921374355 Nov 22 12:33:00 PM PST 23 Nov 22 12:33:06 PM PST 23 191438712 ps
T114 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.37707716911070513490459596236922160399984060401167227484356573976502941254391 Nov 22 12:33:28 PM PST 23 Nov 22 12:33:30 PM PST 23 66993279 ps
T78 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.45641165552327531517563554697136382650393639584834706326066230590910536495056 Nov 22 12:33:30 PM PST 23 Nov 22 12:33:34 PM PST 23 208277863 ps
T115 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.69710872368846589094349317242937087655108113989137237956576075166056085114776 Nov 22 12:33:28 PM PST 23 Nov 22 12:33:30 PM PST 23 66993279 ps
T143 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.31101487015116773753138671215348715197681518271697802397560933292677749680286 Nov 22 12:33:27 PM PST 23 Nov 22 12:33:30 PM PST 23 41172057 ps
T144 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.69088335036718042171068683544248673941293266887253594944358773044026449771142 Nov 22 12:33:01 PM PST 23 Nov 22 12:33:05 PM PST 23 41172057 ps
T116 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.29094445130791408003079815528012313193387717761075783579497676338346485255934 Nov 22 12:33:26 PM PST 23 Nov 22 12:33:28 PM PST 23 24850759 ps
T117 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.42151676455771676842913765192551220820450756405630982467133969548778566052459 Nov 22 12:32:57 PM PST 23 Nov 22 12:33:04 PM PST 23 66993279 ps
T79 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.9703354673668057363658771485037192619035980746224350318388382643856640473050 Nov 22 12:33:35 PM PST 23 Nov 22 12:33:39 PM PST 23 208277863 ps
T118 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.69390043855948202620511234931795630057691130371818171615001234054815687487521 Nov 22 12:33:10 PM PST 23 Nov 22 12:33:15 PM PST 23 66993279 ps
T145 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.74961123203085663856612373219867416352120181117314104816544307304965755195046 Nov 22 12:33:35 PM PST 23 Nov 22 12:33:37 PM PST 23 41172057 ps
T110 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.73335595329188843530158035319876569591269655566316200163795093335787791025153 Nov 22 12:33:46 PM PST 23 Nov 22 12:33:50 PM PST 23 219831342 ps
T100 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.112733775206534276258480993882024040180619053132481021456423970746966721340423 Nov 22 12:33:16 PM PST 23 Nov 22 12:33:20 PM PST 23 197527949 ps
T111 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.80603760118465971876195354709661643076614634092164483448134005313562076409615 Nov 22 12:33:13 PM PST 23 Nov 22 12:33:19 PM PST 23 219831342 ps
T133 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.86362409493708916238817983250761722742999975129205193279915444266981227196699 Nov 22 12:33:10 PM PST 23 Nov 22 12:33:15 PM PST 23 66993279 ps
T119 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.88889892501687811271046781269904625507074232598007972214208029492851762065661 Nov 22 12:33:01 PM PST 23 Nov 22 12:33:06 PM PST 23 24850759 ps
T136 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.84409513814721306474044063206040364041000614221420943689441906789454350876816 Nov 22 12:32:52 PM PST 23 Nov 22 12:32:59 PM PST 23 140599833 ps
T101 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.90195106346387469159560000680095946401206188895174168456271306427369847536035 Nov 22 12:32:54 PM PST 23 Nov 22 12:33:09 PM PST 23 1837157689 ps
T102 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.99335770565367820973979065006066902778980632793120739252492487020324372461939 Nov 22 12:33:00 PM PST 23 Nov 22 12:33:19 PM PST 23 3460251847 ps
T103 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.55656585506477729456407237559991970393247714446435557019149802306270799101919 Nov 22 12:33:04 PM PST 23 Nov 22 12:33:18 PM PST 23 1837157689 ps
T112 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.93621744690106765486676758806884924339384422738837050141776764624709483897155 Nov 22 12:32:57 PM PST 23 Nov 22 12:33:06 PM PST 23 219831342 ps
T134 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.11614009350342435832263757940575258647652495283298575124205755636689345520019 Nov 22 12:33:02 PM PST 23 Nov 22 12:33:07 PM PST 23 66993279 ps
T146 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.33674711785782099517532651867315121147505118870076489717906529040675827908549 Nov 22 12:33:02 PM PST 23 Nov 22 12:33:07 PM PST 23 41172057 ps
T120 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.51164555356477297914177202710936130986455383408933732118764511447703740489195 Nov 22 12:33:11 PM PST 23 Nov 22 12:33:15 PM PST 23 24850759 ps
T80 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.40793535307473479914184206903005478606436469497373858062279158801736072639921 Nov 22 12:33:09 PM PST 23 Nov 22 12:33:15 PM PST 23 208277863 ps
T135 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.86900656628649066337295990321864922689859384806255264147301882535852519381952 Nov 22 12:33:00 PM PST 23 Nov 22 12:33:05 PM PST 23 66993279 ps
T104 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.98979330097014323465687435269932166037016839613987085621217318889054288198509 Nov 22 12:33:03 PM PST 23 Nov 22 12:33:11 PM PST 23 241456169 ps
T121 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.39822468288715526453474399548630379625552270735721232669920559956268009747211 Nov 22 12:33:10 PM PST 23 Nov 22 12:33:15 PM PST 23 58636203 ps
T122 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.29761321890574697976302568576397912276588423538321711403981920488357402161575 Nov 22 12:33:35 PM PST 23 Nov 22 12:33:37 PM PST 23 24850759 ps
T147 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.80269124688055611185811798072316975106483675861282217080611122231981973910474 Nov 22 12:33:37 PM PST 23 Nov 22 12:33:39 PM PST 23 41172057 ps
T148 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.51561762586612151252012727882126860176356806625758748668252525013297113545435 Nov 22 12:32:51 PM PST 23 Nov 22 12:32:59 PM PST 23 208277863 ps
T123 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.97476081032665002187694705236024954457391541898032244781781619709846287829074 Nov 22 12:33:46 PM PST 23 Nov 22 12:33:48 PM PST 23 24850759 ps
T124 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.69537186780716441012558117639797517222382419325934245730673831271041623302651 Nov 22 12:33:00 PM PST 23 Nov 22 12:33:05 PM PST 23 58636203 ps
T149 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.30467135679735767563991927995058695982934806647986501781360898502689992712797 Nov 22 12:33:09 PM PST 23 Nov 22 12:33:13 PM PST 23 41172057 ps
T125 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.47483334098513390368156420401471146903024343903587273036317384960968581862759 Nov 22 12:33:00 PM PST 23 Nov 22 12:33:05 PM PST 23 24850759 ps
T150 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.78001687890098474893775502112404657978146102590288758070873008203135477925942 Nov 22 12:33:03 PM PST 23 Nov 22 12:33:11 PM PST 23 66993279 ps
T105 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.10052038011943551477867675871116884235082812363481689000114176873318106743727 Nov 22 12:33:08 PM PST 23 Nov 22 12:33:27 PM PST 23 3460251847 ps
T113 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.108370605215513493911097443159055628359260427369654750171217543164144130634051 Nov 22 12:32:59 PM PST 23 Nov 22 12:33:07 PM PST 23 219831342 ps
T151 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.14154898411790156787353427346279018391370113603864515279115707992719570674416 Nov 22 12:33:05 PM PST 23 Nov 22 12:33:12 PM PST 23 66993279 ps
T152 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.96009567981560044104952545179198199004265001279989035370275320184372796558249 Nov 22 12:33:07 PM PST 23 Nov 22 12:33:12 PM PST 23 24850759 ps
T106 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.46208879560406366533460323376147018585311386289615747529336097623047044221819 Nov 22 12:33:13 PM PST 23 Nov 22 12:33:17 PM PST 23 191438712 ps
T153 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.12739223252209390190580707443147431116559412153475885632095475363863373931819 Nov 22 12:33:05 PM PST 23 Nov 22 12:33:17 PM PST 23 24850759 ps
T154 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.93984833030986996080315569659095830128255080660931901126352133768017376866377 Nov 22 12:32:58 PM PST 23 Nov 22 12:33:04 PM PST 23 66993279 ps
T155 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.111018813826561822073685519759938804691372903501515119064189885679251273624023 Nov 22 12:33:02 PM PST 23 Nov 22 12:33:09 PM PST 23 360562359 ps
T142 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.72048131555944688315819194826897145714509881574403081408358202320473170074955 Nov 22 12:33:09 PM PST 23 Nov 22 12:33:14 PM PST 23 140599833 ps
T156 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.30474126944108506210646432507119678694826367192737873506437507397738491312049 Nov 22 12:33:01 PM PST 23 Nov 22 12:33:08 PM PST 23 360562359 ps
T157 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.107094602402691719537895103495224076651219667004757170087572385557117556831041 Nov 22 12:33:29 PM PST 23 Nov 22 12:33:30 PM PST 23 24850759 ps
T158 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.38755182480076917081489896712385663967335437628739955223760674444670094586330 Nov 22 12:32:49 PM PST 23 Nov 22 12:33:12 PM PST 23 3460251847 ps
T159 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.75521684947862874492426927123433375765301384303038709426176962585811063267541 Nov 22 12:33:02 PM PST 23 Nov 22 12:33:14 PM PST 23 1837157689 ps
T160 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.34729912522762681040725945177486928815289201318826973634076530583599429294455 Nov 22 12:33:16 PM PST 23 Nov 22 12:33:18 PM PST 23 66993279 ps
T161 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.40569550486612450008624445780124439947846172625153963067918019819281838772187 Nov 22 12:33:10 PM PST 23 Nov 22 12:33:16 PM PST 23 191438712 ps
T162 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.58033402995863189071599704800597294863699570008426833086411599100433785604279 Nov 22 12:33:10 PM PST 23 Nov 22 12:33:15 PM PST 23 24850759 ps
T126 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.16696984512750830032334951765235567916036838661142830181759655095375646242276 Nov 22 12:33:01 PM PST 23 Nov 22 12:33:05 PM PST 23 58636203 ps
T127 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.108858101959938519293593757832948757071136228564929091961302514992572998128660 Nov 22 12:33:10 PM PST 23 Nov 22 12:33:15 PM PST 23 33332834 ps
T163 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.17272410572909076834677081885576234753498146004927380794026680508656660244045 Nov 22 12:33:32 PM PST 23 Nov 22 12:33:36 PM PST 23 219831342 ps
T164 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.56540894995996026701791910611699816152185512640782345477969148864628364655346 Nov 22 12:32:57 PM PST 23 Nov 22 12:33:04 PM PST 23 197527949 ps
T165 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.70552396300259163517500784716817000859682895270947637445200245956066037966569 Nov 22 12:32:52 PM PST 23 Nov 22 12:32:58 PM PST 23 66993279 ps
T166 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.32372577852463893824726693111168565000946677459180412386429508520954063195123 Nov 22 12:33:05 PM PST 23 Nov 22 12:33:12 PM PST 23 197527949 ps
T167 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.79191628151167010142124863741751273241464789286087900287882525331763641290987 Nov 22 12:33:04 PM PST 23 Nov 22 12:33:26 PM PST 23 3460251847 ps
T168 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.65374654659189260646259480608885260721058880354658120751839436932048804447633 Nov 22 12:33:00 PM PST 23 Nov 22 12:33:05 PM PST 23 241456169 ps
T169 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.75051703161510168356383949658424807087000349716605731482828335117316658396020 Nov 22 12:33:09 PM PST 23 Nov 22 12:33:21 PM PST 23 1837157689 ps
T170 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.86626626038293808395326772955526671073124423727240701384370159367067644995019 Nov 22 12:33:02 PM PST 23 Nov 22 12:33:07 PM PST 23 66993279 ps
T171 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.112469788786199892947300249689488663266578971717996755440378032668537077417197 Nov 22 12:33:04 PM PST 23 Nov 22 12:33:11 PM PST 23 66993279 ps
T172 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.38178985204746555368861910777191657920205719885617514408362478929077119472769 Nov 22 12:33:02 PM PST 23 Nov 22 12:33:09 PM PST 23 66993279 ps
T173 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.84697601135515573934596366397835620875613201500773558640163810084496968567803 Nov 22 12:33:01 PM PST 23 Nov 22 12:33:07 PM PST 23 66993279 ps
T174 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.72925461630715270573553672194135524385465805626607427033711058860113596978919 Nov 22 12:33:11 PM PST 23 Nov 22 12:33:15 PM PST 23 24850759 ps
T175 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.72776124205403955219874859833666540010812713636923341383382996525491426574158 Nov 22 12:33:28 PM PST 23 Nov 22 12:33:30 PM PST 23 24850759 ps
T176 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.71990786308506562295553864032210779082876367351695972421270534318934985628700 Nov 22 12:33:00 PM PST 23 Nov 22 12:33:05 PM PST 23 24850759 ps
T177 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.8841146846238396976982235305142562500676310481501391658221068184766215223497 Nov 22 12:33:16 PM PST 23 Nov 22 12:33:19 PM PST 23 41172057 ps
T178 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.66327557947478189852549398825468496238129805150101968111819541115447237426381 Nov 22 12:33:00 PM PST 23 Nov 22 12:33:20 PM PST 23 3460251847 ps
T179 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.5463135432598599474422533374007736495870541512745967959526151858640896441329 Nov 22 12:33:03 PM PST 23 Nov 22 12:33:11 PM PST 23 241456169 ps
T180 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.75228150861905699342397435930343170648575099621390498286518174880665458981500 Nov 22 12:33:26 PM PST 23 Nov 22 12:33:28 PM PST 23 24850759 ps
T181 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.55372198941864724285649143007805004221605455766463263316352737008257462132149 Nov 22 12:32:53 PM PST 23 Nov 22 12:32:59 PM PST 23 241456169 ps
T182 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.22298377406410336882587356258332290899304366953259790368222372735604177271776 Nov 22 12:33:02 PM PST 23 Nov 22 12:33:07 PM PST 23 66993279 ps
T183 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.79297221727088397686181025381840675960421137232933743159120320713185455932137 Nov 22 12:33:02 PM PST 23 Nov 22 12:33:07 PM PST 23 191438712 ps
T184 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.78813920100907907305155735304407317256130978603914926075126180854155941927421 Nov 22 12:33:16 PM PST 23 Nov 22 12:33:33 PM PST 23 3460251847 ps
T185 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.55563301017322139754813485201482992499164533466865448572968615958411333302250 Nov 22 12:33:35 PM PST 23 Nov 22 12:33:38 PM PST 23 41172057 ps
T186 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.61087181204682136406038013604606186608314593637997048653311658142978498386138 Nov 22 12:33:00 PM PST 23 Nov 22 12:33:05 PM PST 23 24850759 ps
T187 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.77885555237399559052812849051439594892232393572732818684225029303042857744173 Nov 22 12:33:10 PM PST 23 Nov 22 12:33:17 PM PST 23 208277863 ps
T128 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.97398336208847055417376822467397758309029131101659029081770090896062569333111 Nov 22 12:33:04 PM PST 23 Nov 22 12:33:11 PM PST 23 58636203 ps
T188 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.83460878728489635983785928623155409368735513816812524232101611515667527532167 Nov 22 12:32:46 PM PST 23 Nov 22 12:32:48 PM PST 23 24850759 ps
T189 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.67299125829071186015261126912721539239984096813980018713617944599362051690537 Nov 22 12:33:02 PM PST 23 Nov 22 12:33:08 PM PST 23 24850759 ps
T190 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.19232237590941478194864917808906184946244420085429212861433877476010917018351 Nov 22 12:33:13 PM PST 23 Nov 22 12:33:17 PM PST 23 66993279 ps
T191 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.20051483477260892212553155450932606037907617905759847702738671998711108439409 Nov 22 12:33:28 PM PST 23 Nov 22 12:33:31 PM PST 23 208277863 ps
T192 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.70842541600217961871071052713512137303682388531596146580501512616004905719118 Nov 22 12:33:01 PM PST 23 Nov 22 12:33:07 PM PST 23 360562359 ps
T193 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3336476537406936244206582538404620107876771472649794855196232577746465727659 Nov 22 12:33:35 PM PST 23 Nov 22 12:33:38 PM PST 23 66993279 ps
T194 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.466904210435340541314779166375476500397416124403957977101689898367172002594 Nov 22 12:33:11 PM PST 23 Nov 22 12:33:23 PM PST 23 1837157689 ps
T195 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.114086009307253270678873208679928115418778632389099350083636832907436816399306 Nov 22 12:33:03 PM PST 23 Nov 22 12:33:11 PM PST 23 219831342 ps
T196 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1359860279350725264112618168881355251841461604236486951647758582168175802487 Nov 22 12:33:01 PM PST 23 Nov 22 12:33:07 PM PST 23 191438712 ps
T197 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.8222255085577506521139538213455678516342211596407327184740617630171149364982 Nov 22 12:32:59 PM PST 23 Nov 22 12:33:07 PM PST 23 219831342 ps
T198 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.53468034219021467366634786249143312064936158963781961021996460552419928058722 Nov 22 12:32:57 PM PST 23 Nov 22 12:33:04 PM PST 23 66993279 ps
T199 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.35357144637480437770082611509147385213028299106921553695633130404396972741972 Nov 22 12:32:49 PM PST 23 Nov 22 12:32:59 PM PST 23 208277863 ps
T200 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.95785416405007151747771961197753258553200277177957147324792469553047942033309 Nov 22 12:32:49 PM PST 23 Nov 22 12:32:59 PM PST 23 360562359 ps
T201 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1867527112614205243184217455735231239815704629874018794941525077066461794255 Nov 22 12:32:57 PM PST 23 Nov 22 12:33:04 PM PST 23 66993279 ps
T202 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.62976134355004312504545421050884345675981885428785347046161376236814609126068 Nov 22 12:33:26 PM PST 23 Nov 22 12:33:30 PM PST 23 208277863 ps
T203 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.42777649472345041578733050386974722434180405223723969357547799504541757747220 Nov 22 12:33:29 PM PST 23 Nov 22 12:33:30 PM PST 23 24850759 ps
T204 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1771048145097610067581207997767249651220798505778638814818817978385410094771 Nov 22 12:33:01 PM PST 23 Nov 22 12:33:07 PM PST 23 191438712 ps
T205 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.22860630374029013256334333652683348764485556323777798572807400884865612725114 Nov 22 12:33:02 PM PST 23 Nov 22 12:33:09 PM PST 23 208277863 ps
T206 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.93222235221002225735879841317031550228677843104574983576043529001107418239345 Nov 22 12:33:10 PM PST 23 Nov 22 12:33:17 PM PST 23 208277863 ps
T207 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.54549870547319106955082171186571699762417643253175095711231637171794250437991 Nov 22 12:33:11 PM PST 23 Nov 22 12:33:18 PM PST 23 219831342 ps
T208 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.20735603795453707013799290717315741626831641867237338859037607909442663801159 Nov 22 12:33:04 PM PST 23 Nov 22 12:33:13 PM PST 23 208277863 ps
T209 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.96274333192335925656468590752743617030316648095071687568080482365605090325952 Nov 22 12:33:45 PM PST 23 Nov 22 12:33:47 PM PST 23 41172057 ps
T210 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.54609444209015977147036967317845475540872529119142255510540456046752043809494 Nov 22 12:33:01 PM PST 23 Nov 22 12:33:06 PM PST 23 360562359 ps
T129 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.53365302487128394646448876603380060619766472293927112140621652250638503585052 Nov 22 12:32:56 PM PST 23 Nov 22 12:33:03 PM PST 23 33332834 ps
T211 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.67273440906367141885184845172874026525067683620444412290376523603010587411680 Nov 22 12:33:05 PM PST 23 Nov 22 12:33:12 PM PST 23 241456169 ps
T212 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.46260847117038879672013576919029688069605571773021673839255934079810884278882 Nov 22 12:33:03 PM PST 23 Nov 22 12:33:12 PM PST 23 208277863 ps
T213 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.18071578371383836603603944241682444569563671249008376214152086528173692063426 Nov 22 12:33:03 PM PST 23 Nov 22 12:33:25 PM PST 23 3460251847 ps
T214 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.12597556916241669134555035238264843377416477075678977500345737442247885421689 Nov 22 12:33:08 PM PST 23 Nov 22 12:33:13 PM PST 23 41172057 ps
T215 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.102644714253189353531721670692117909192469007011024555346740755280614351366978 Nov 22 12:33:08 PM PST 23 Nov 22 12:33:13 PM PST 23 41172057 ps
T216 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.8725998357730691331627018072554149151346378943310831893333422958672116263928 Nov 22 12:32:52 PM PST 23 Nov 22 12:32:58 PM PST 23 197527949 ps
T217 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.47975488496616062320137178112066532161018110732409712843630120128612473408542 Nov 22 12:32:58 PM PST 23 Nov 22 12:33:05 PM PST 23 360562359 ps
T218 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.52676315914933763372309978031313308010745501079144510020816595688324293203509 Nov 22 12:32:52 PM PST 23 Nov 22 12:33:00 PM PST 23 208277863 ps
T219 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.6591105513026295883756785920479012665960269760226367943551797110348554113876 Nov 22 12:32:59 PM PST 23 Nov 22 12:33:07 PM PST 23 219831342 ps
T220 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.114635720028576398599523550543223181749221327918880610504615373773664718556113 Nov 22 12:33:04 PM PST 23 Nov 22 12:33:11 PM PST 23 197527949 ps
T221 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.69524492449189090346437856425361892087959544048453362124685828548733188886220 Nov 22 12:33:28 PM PST 23 Nov 22 12:33:32 PM PST 23 219831342 ps
T222 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.78397021028438003059147262660352861378698168305890426462938498861608093446205 Nov 22 12:32:52 PM PST 23 Nov 22 12:33:04 PM PST 23 197527949 ps
T223 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.86049430855968165529642726423128956224596681883851042266067968138485224573690 Nov 22 12:33:03 PM PST 23 Nov 22 12:33:11 PM PST 23 241456169 ps
T224 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.95770812897880409432928766032728358389738893893580543325305399040795399163325 Nov 22 12:32:57 PM PST 23 Nov 22 12:33:06 PM PST 23 208277863 ps
T225 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.9829804539235935900870815368764354962293624631056948753380901153276703308239 Nov 22 12:33:03 PM PST 23 Nov 22 12:33:11 PM PST 23 360562359 ps
T226 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.104674096743643305395900525450252564538590766257547773228813753778293427092795 Nov 22 12:33:02 PM PST 23 Nov 22 12:33:07 PM PST 23 41172057 ps
T227 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.79078019271718838075413857331426804979424963885005648451944155921472019051066 Nov 22 12:33:01 PM PST 23 Nov 22 12:33:06 PM PST 23 191438712 ps
T228 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.96478745938657651685360503330939501593407596803513876393285889363814341959986 Nov 22 12:33:22 PM PST 23 Nov 22 12:33:26 PM PST 23 208277863 ps
T229 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.14051216981437889498371381138356319357399905805757153769866439620020478753537 Nov 22 12:33:03 PM PST 23 Nov 22 12:33:12 PM PST 23 208277863 ps
T130 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.54239216135557883736924312012847453563559320723569895485067455056721826651672 Nov 22 12:33:03 PM PST 23 Nov 22 12:33:11 PM PST 23 33332834 ps
T230 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.15326191825796678357764955445881846508925325664464043929097113785873937076564 Nov 22 12:33:01 PM PST 23 Nov 22 12:33:07 PM PST 23 241456169 ps
T231 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.63355651139104811014877470577112592874720384202099904987407512355438932282973 Nov 22 12:33:01 PM PST 23 Nov 22 12:33:08 PM PST 23 360562359 ps
T232 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.33461747688456170758129938345505347961605516632093597905952141268896032266252 Nov 22 12:33:00 PM PST 23 Nov 22 12:33:07 PM PST 23 219831342 ps
T233 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.45080524352381596332622298480073313217359445341031237509937212527549906797850 Nov 22 12:33:01 PM PST 23 Nov 22 12:33:08 PM PST 23 208277863 ps
T234 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.17252621783537062329387925468896885722962330326654238093397808915703671456837 Nov 22 12:33:02 PM PST 23 Nov 22 12:33:07 PM PST 23 191438712 ps
T235 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.69198659068404105509471447321351743886778343811149956501923739773568827705422 Nov 22 12:33:03 PM PST 23 Nov 22 12:33:18 PM PST 23 1837157689 ps
T236 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.112375062096570231558391358075469780423406829461242013253657331578466109657090 Nov 22 12:33:27 PM PST 23 Nov 22 12:33:31 PM PST 23 208277863 ps
T237 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.19846137826665708186722539291828396077052482616957399032229101090490784402421 Nov 22 12:33:09 PM PST 23 Nov 22 12:33:21 PM PST 23 1837157689 ps
T238 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.86814867605795657317296062446958955013568982991960260368352729073825802193885 Nov 22 12:33:01 PM PST 23 Nov 22 12:33:05 PM PST 23 41172057 ps
T131 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.16290686735668327925237918272220957125171047262654411201521052131660949014121 Nov 22 12:33:01 PM PST 23 Nov 22 12:33:05 PM PST 23 58636203 ps
T239 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.32068564275319456874181199588983920647934182508544903949960425983907760173548 Nov 22 12:33:00 PM PST 23 Nov 22 12:33:05 PM PST 23 66993279 ps
T240 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.46937776171288034568896770847008895243318107467437375616155561224970675016606 Nov 22 12:32:58 PM PST 23 Nov 22 12:33:05 PM PST 23 197527949 ps
T241 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.18615349425781662988181523238360565430871467560074299123434403675137961132826 Nov 22 12:33:09 PM PST 23 Nov 22 12:33:14 PM PST 23 241456169 ps
T242 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.34980416125604583017177150845077131565676695741381855156675419357921824397659 Nov 22 12:32:53 PM PST 23 Nov 22 12:32:59 PM PST 23 140599833 ps
T243 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.31997516233946982130589198327098689163525054010497797929058313894190818911117 Nov 22 12:33:35 PM PST 23 Nov 22 12:33:39 PM PST 23 208277863 ps
T244 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.36681187110295752648772539233849384357654754356109259175011529878905971227343 Nov 22 12:32:53 PM PST 23 Nov 22 12:32:59 PM PST 23 41172057 ps
T245 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.23289074423208710333224752416844074733457826162958083396427221980704703073684 Nov 22 12:33:09 PM PST 23 Nov 22 12:33:13 PM PST 23 66993279 ps
T246 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.16766411307405916089093250924850292267665486879083539599559477938495495279301 Nov 22 12:33:11 PM PST 23 Nov 22 12:33:23 PM PST 23 1837157689 ps
T247 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.73655510119059978002283080772681509861930170701889559000819565615949411785927 Nov 22 12:32:55 PM PST 23 Nov 22 12:33:17 PM PST 23 3460251847 ps
T248 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.17385105501831325757958963347922519132290887704072430075714664534698289117988 Nov 22 12:33:29 PM PST 23 Nov 22 12:33:33 PM PST 23 208277863 ps
T249 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.40075745306210171547071339209285382070540987944650228263985451792136293326626 Nov 22 12:33:02 PM PST 23 Nov 22 12:33:22 PM PST 23 3460251847 ps
T250 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.51082117002471533513524396152893468008636718726761790189596901158688845700969 Nov 22 12:33:00 PM PST 23 Nov 22 12:33:20 PM PST 23 3460251847 ps
T251 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.56107988966567609848111060348189697291595333101140751661625616841255155484348 Nov 22 12:33:05 PM PST 23 Nov 22 12:33:12 PM PST 23 140599833 ps
T252 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.66950464173302947052574005227393920023193108878976679194082856498965563589818 Nov 22 12:33:02 PM PST 23 Nov 22 12:33:09 PM PST 23 197527949 ps
T253 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.50476617482002279349133016726681257891480938886596245201225438731749056887511 Nov 22 12:33:02 PM PST 23 Nov 22 12:33:08 PM PST 23 191438712 ps
T254 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.61501670762857964761300312583429952661391571476697724689604613467061339033289 Nov 22 12:32:56 PM PST 23 Nov 22 12:33:04 PM PST 23 360562359 ps
T255 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.83624750081544231418195348505027749506369296455025824092851222718489269546744 Nov 22 12:34:40 PM PST 23 Nov 22 12:34:46 PM PST 23 66993279 ps
T256 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.113445633127958460468947372893291862889637435987103685778836881632876775094166 Nov 22 12:33:13 PM PST 23 Nov 22 12:33:17 PM PST 23 41172057 ps
T132 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.36893234713992094072606029947188499500031184739359704039298664614031225853803 Nov 22 12:33:08 PM PST 23 Nov 22 12:33:13 PM PST 23 33332834 ps
T257 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.107848197603356311001542415223485959293816471297503907902177463554569331903920 Nov 22 12:33:34 PM PST 23 Nov 22 12:33:37 PM PST 23 66993279 ps
T258 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.101258309673239098837884916172433047391958738674728841361542690012609010304287 Nov 22 12:33:01 PM PST 23 Nov 22 12:33:06 PM PST 23 241456169 ps
T259 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.88202634999689032325343783616887870682950260758639620557426309501987093491212 Nov 22 12:33:01 PM PST 23 Nov 22 12:33:06 PM PST 23 66993279 ps
T260 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.58543841315435884389006537967209106705385339528946449829158223076386265078138 Nov 22 12:33:10 PM PST 23 Nov 22 12:33:15 PM PST 23 41172057 ps
T261 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.46200694964750313334843963927206184310273097874902035689835028610465857051138 Nov 22 12:32:49 PM PST 23 Nov 22 12:33:00 PM PST 23 219831342 ps
T262 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.96278279999274371477553373405353595287757379966294916779304374957935139984982 Nov 22 12:33:11 PM PST 23 Nov 22 12:33:23 PM PST 23 1837157689 ps
T263 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.46492813175005850294111732486790469924424256018787321919070962282331255183306 Nov 22 12:33:42 PM PST 23 Nov 22 12:33:46 PM PST 23 219831342 ps
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T38 /workspace/coverage/default/45.lc_ctrl_stress_all.111743422303470033606178168150800456276105932694154060817666186269660038841905 Nov 22 01:39:50 PM PST 23 Nov 22 01:44:38 PM PST 23 36820395678 ps
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T267 /workspace/coverage/default/40.lc_ctrl_prog_failure.31586557998554671721066710543940276663235510900326823479883078987701491103824 Nov 22 01:39:29 PM PST 23 Nov 22 01:39:33 PM PST 23 159313969 ps
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T43 /workspace/coverage/default/3.lc_ctrl_errors.6704046842581794747067155746817451332711408549846639935303113939686765396957 Nov 22 01:37:03 PM PST 23 Nov 22 01:37:19 PM PST 23 978628843 ps
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T274 /workspace/coverage/default/22.lc_ctrl_sec_token_digest.62862826073205128963468350465985230312101431534434765815457901372065993792328 Nov 22 01:38:08 PM PST 23 Nov 22 01:38:30 PM PST 23 1321911811 ps
T275 /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.4335532778706226722945297606719529513961064609420247235048029810367590458139 Nov 22 01:36:48 PM PST 23 Nov 22 01:36:50 PM PST 23 16404398 ps
T276 /workspace/coverage/default/41.lc_ctrl_state_failure.2573731584567754187749887337361920479033858628441957756429651976544196487983 Nov 22 01:39:49 PM PST 23 Nov 22 01:40:11 PM PST 23 487150632 ps
T277 /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.10339691455061670028391955395569605066974522761147121682646695745380299106016 Nov 22 01:37:52 PM PST 23 Nov 22 01:37:59 PM PST 23 16404398 ps
T278 /workspace/coverage/default/39.lc_ctrl_sec_token_digest.115584289226805231380064678852687256429631008611020203011745694185610889907839 Nov 22 01:39:28 PM PST 23 Nov 22 01:39:44 PM PST 23 1321911811 ps
T279 /workspace/coverage/default/17.lc_ctrl_state_failure.7324083319885235387115569900952356697198752668370977030959353271640190214556 Nov 22 01:38:02 PM PST 23 Nov 22 01:38:28 PM PST 23 487150632 ps
T280 /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.82275019534947239775406299445620743853149885456545288783388605281894502578910 Nov 22 01:36:45 PM PST 23 Nov 22 01:37:38 PM PST 23 5030489285 ps
T57 /workspace/coverage/default/12.lc_ctrl_stress_all.59035700742502985679839919110799057184369186403289468771108605468252795949044 Nov 22 01:37:43 PM PST 23 Nov 22 01:42:23 PM PST 23 36820395678 ps
T281 /workspace/coverage/default/27.lc_ctrl_state_failure.75902629283502904829205095767428110780688322742094929026879253805285684834904 Nov 22 01:38:26 PM PST 23 Nov 22 01:38:48 PM PST 23 487150632 ps
T282 /workspace/coverage/default/15.lc_ctrl_sec_token_digest.72004939203499068571078495490428516681019916808019963971333861783758239581860 Nov 22 01:38:04 PM PST 23 Nov 22 01:38:25 PM PST 23 1321911811 ps
T283 /workspace/coverage/default/40.lc_ctrl_state_failure.9600609577643963474230944662125871976680595179989537702302871498759085027948 Nov 22 01:39:16 PM PST 23 Nov 22 01:39:40 PM PST 23 487150632 ps
T284 /workspace/coverage/default/9.lc_ctrl_sec_mubi.89086582747031849756703145753566753944727352344895332672438790347252283937023 Nov 22 01:37:52 PM PST 23 Nov 22 01:38:12 PM PST 23 1010128591 ps
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