LC_CTRL Simulation Results

Wednesday November 22 2023 20:02:38 UTC

GitHub Revision: 4002b28ec4

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56541452733628775295814943325285397402671097056517970046183331126493552547969

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke lc_ctrl_smoke 4.880s 291.295us 50 50 100.00
V1 csr_hw_reset lc_ctrl_csr_hw_reset 1.010s 33.333us 5 5 100.00
V1 csr_rw lc_ctrl_csr_rw 0.910s 24.851us 20 20 100.00
V1 csr_bit_bash lc_ctrl_csr_bit_bash 1.840s 140.600us 5 5 100.00
V1 csr_aliasing lc_ctrl_csr_aliasing 1.250s 58.636us 5 5 100.00
V1 csr_mem_rw_with_rand_reset lc_ctrl_csr_mem_rw_with_rand_reset 1.260s 41.172us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr lc_ctrl_csr_rw 0.910s 24.851us 20 20 100.00
lc_ctrl_csr_aliasing 1.250s 58.636us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 state_post_trans lc_ctrl_state_post_trans 7.460s 217.117us 50 50 100.00
V2 regwen_during_op lc_ctrl_regwen_during_op 6.170s 420.615us 10 10 100.00
V2 rand_wr_claim_transition_if lc_ctrl_claim_transition_if 0.820s 19.637us 10 10 100.00
V2 lc_prog_failure lc_ctrl_prog_failure 3.190s 159.314us 50 50 100.00
V2 lc_state_failure lc_ctrl_state_failure 22.780s 487.151us 50 50 100.00
V2 lc_errors lc_ctrl_errors 15.580s 978.629us 50 50 100.00
V2 security_escalation lc_ctrl_state_failure 22.780s 487.151us 50 50 100.00
lc_ctrl_prog_failure 3.190s 159.314us 50 50 100.00
lc_ctrl_errors 15.580s 978.629us 50 50 100.00
lc_ctrl_security_escalation 9.320s 625.328us 50 50 100.00
lc_ctrl_jtag_state_failure 53.170s 5.030ms 20 20 100.00
lc_ctrl_jtag_prog_failure 11.600s 1.481ms 20 20 100.00
lc_ctrl_jtag_errors 42.600s 5.873ms 20 20 100.00
V2 jtag_access lc_ctrl_jtag_smoke 9.410s 1.349ms 20 20 100.00
lc_ctrl_jtag_state_post_trans 15.980s 1.491ms 20 20 100.00
lc_ctrl_jtag_prog_failure 11.600s 1.481ms 20 20 100.00
lc_ctrl_jtag_errors 42.600s 5.873ms 20 20 100.00
lc_ctrl_jtag_access 10.060s 1.895ms 50 50 100.00
lc_ctrl_jtag_regwen_during_op 10.420s 1.406ms 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 2.410s 360.562us 10 10 100.00
lc_ctrl_jtag_csr_rw 1.820s 241.456us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 15.730s 3.460ms 10 10 100.00
lc_ctrl_jtag_csr_aliasing 8.830s 1.837ms 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.350s 66.993us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.900s 191.439us 10 10 100.00
lc_ctrl_jtag_alert_test 1.690s 197.528us 10 10 100.00
V2 jtag_priority lc_ctrl_jtag_priority 14.110s 2.798ms 10 10 100.00
V2 lc_ctrl_volatile_unlock lc_ctrl_volatile_unlock_smoke 0.810s 16.404us 50 50 100.00
V2 stress_all lc_ctrl_stress_all 4.917m 36.820ms 50 50 100.00
V2 alert_test lc_ctrl_alert_test 1.010s 42.190us 50 50 100.00
V2 tl_d_oob_addr_access lc_ctrl_tl_errors 3.390s 219.831us 20 20 100.00
V2 tl_d_illegal_access lc_ctrl_tl_errors 3.390s 219.831us 20 20 100.00
V2 tl_d_outstanding_access lc_ctrl_csr_hw_reset 1.010s 33.333us 5 5 100.00
lc_ctrl_csr_rw 0.910s 24.851us 20 20 100.00
lc_ctrl_csr_aliasing 1.250s 58.636us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.400s 66.993us 20 20 100.00
V2 tl_d_partial_access lc_ctrl_csr_hw_reset 1.010s 33.333us 5 5 100.00
lc_ctrl_csr_rw 0.910s 24.851us 20 20 100.00
lc_ctrl_csr_aliasing 1.250s 58.636us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.400s 66.993us 20 20 100.00
V2 TOTAL 700 700 100.00
V2S tl_intg_err lc_ctrl_sec_cm 37.170s 386.473us 5 5 100.00
lc_ctrl_tl_intg_err 2.970s 208.278us 20 20 100.00
V2S sec_cm_bus_integrity lc_ctrl_tl_intg_err 2.970s 208.278us 20 20 100.00
V2S sec_cm_transition_config_regwen lc_ctrl_regwen_during_op 6.170s 420.615us 10 10 100.00
V2S sec_cm_manuf_state_sparse lc_ctrl_state_failure 22.780s 487.151us 50 50 100.00
lc_ctrl_sec_cm 37.170s 386.473us 5 5 100.00
V2S sec_cm_transition_ctr_sparse lc_ctrl_state_failure 22.780s 487.151us 50 50 100.00
lc_ctrl_sec_cm 37.170s 386.473us 5 5 100.00
V2S sec_cm_manuf_state_bkgn_chk lc_ctrl_state_failure 22.780s 487.151us 50 50 100.00
lc_ctrl_sec_cm 37.170s 386.473us 5 5 100.00
V2S sec_cm_transition_ctr_bkgn_chk lc_ctrl_state_failure 22.780s 487.151us 50 50 100.00
lc_ctrl_sec_cm 37.170s 386.473us 5 5 100.00
V2S sec_cm_state_config_sparse lc_ctrl_state_failure 22.780s 487.151us 50 50 100.00
lc_ctrl_sec_cm 37.170s 386.473us 5 5 100.00
V2S sec_cm_main_fsm_sparse lc_ctrl_state_failure 22.780s 487.151us 50 50 100.00
lc_ctrl_sec_cm 37.170s 386.473us 5 5 100.00
V2S sec_cm_kmac_fsm_sparse lc_ctrl_state_failure 22.780s 487.151us 50 50 100.00
lc_ctrl_sec_cm 37.170s 386.473us 5 5 100.00
V2S sec_cm_main_fsm_local_esc lc_ctrl_state_failure 22.780s 487.151us 50 50 100.00
lc_ctrl_sec_cm 37.170s 386.473us 5 5 100.00
V2S sec_cm_main_fsm_global_esc lc_ctrl_security_escalation 9.320s 625.328us 50 50 100.00
V2S sec_cm_main_ctrl_flow_consistency lc_ctrl_state_post_trans 7.460s 217.117us 50 50 100.00
lc_ctrl_jtag_state_post_trans 15.980s 1.491ms 20 20 100.00
V2S sec_cm_intersig_mubi lc_ctrl_sec_mubi 16.520s 1.010ms 50 50 100.00
V2S sec_cm_token_valid_ctrl_mubi lc_ctrl_sec_mubi 16.520s 1.010ms 50 50 100.00
V2S sec_cm_token_digest lc_ctrl_sec_token_digest 18.040s 1.322ms 50 50 100.00
V2S sec_cm_token_mux_ctrl_redun lc_ctrl_sec_token_mux 11.900s 964.986us 50 50 100.00
V2S sec_cm_token_valid_mux_redun lc_ctrl_sec_token_mux 11.900s 964.986us 50 50 100.00
V2S TOTAL 175 175 100.00
V3 stress_all_with_rand_reset lc_ctrl_stress_all_with_rand_reset 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 980 1030 95.15

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 27 27 27 100.00
V2S 5 5 5 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
92.66 96.94 91.76 84.26 90.70 94.70 98.48 91.79

Failure Buckets

Past Results