Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41605 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T3 |
58 |
auto[1] |
1480 |
1 |
|
|
T12 |
8 |
|
T17 |
8 |
|
T25 |
13 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
42333 |
1 |
|
|
T1 |
78 |
|
T2 |
82 |
|
T3 |
58 |
auto[1] |
752 |
1 |
|
|
T1 |
13 |
|
T23 |
15 |
|
T73 |
13 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41781 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T3 |
48 |
auto[1] |
1304 |
1 |
|
|
T3 |
10 |
|
T4 |
41 |
|
T16 |
5 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41791 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T3 |
55 |
auto[1] |
1294 |
1 |
|
|
T3 |
3 |
|
T4 |
36 |
|
T16 |
4 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41689 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T3 |
51 |
auto[1] |
1396 |
1 |
|
|
T3 |
7 |
|
T4 |
55 |
|
T16 |
8 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
39822 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T3 |
58 |
no_err_inj |
3263 |
1 |
|
|
T11 |
10 |
|
T4 |
50 |
|
T17 |
7 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41708 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T3 |
58 |
auto[1] |
1377 |
1 |
|
|
T12 |
12 |
|
T17 |
10 |
|
T25 |
6 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
42341 |
1 |
|
|
T1 |
72 |
|
T2 |
82 |
|
T3 |
58 |
auto[1] |
744 |
1 |
|
|
T1 |
19 |
|
T23 |
10 |
|
T73 |
8 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
33138 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T11 |
10 |
auto[1] |
9947 |
1 |
|
|
T3 |
58 |
|
T4 |
34 |
|
T17 |
1 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41749 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T3 |
54 |
auto[1] |
1336 |
1 |
|
|
T3 |
4 |
|
T4 |
48 |
|
T16 |
10 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41803 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T3 |
50 |
auto[1] |
1282 |
1 |
|
|
T3 |
8 |
|
T4 |
38 |
|
T16 |
10 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41741 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T3 |
49 |
auto[1] |
1344 |
1 |
|
|
T3 |
9 |
|
T4 |
33 |
|
T16 |
10 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41685 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T3 |
58 |
auto[1] |
1400 |
1 |
|
|
T12 |
13 |
|
T17 |
10 |
|
T25 |
6 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41281 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T3 |
58 |
auto[1] |
1804 |
1 |
|
|
T4 |
22 |
|
T17 |
17 |
|
T72 |
9 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
42336 |
1 |
|
|
T1 |
73 |
|
T2 |
82 |
|
T3 |
58 |
auto[1] |
749 |
1 |
|
|
T1 |
18 |
|
T23 |
18 |
|
T73 |
19 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
42416 |
1 |
|
|
T1 |
72 |
|
T2 |
82 |
|
T3 |
58 |
auto[1] |
669 |
1 |
|
|
T1 |
19 |
|
T23 |
10 |
|
T73 |
8 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
42340 |
1 |
|
|
T1 |
69 |
|
T2 |
82 |
|
T3 |
58 |
auto[1] |
745 |
1 |
|
|
T1 |
22 |
|
T23 |
15 |
|
T73 |
12 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41235 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T3 |
58 |
auto[1] |
1850 |
1 |
|
|
T4 |
42 |
|
T17 |
10 |
|
T102 |
10 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39422 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T3 |
58 |
auto[1] |
3663 |
1 |
|
|
T57 |
79 |
|
T58 |
70 |
|
T59 |
89 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41771 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T3 |
51 |
auto[1] |
1314 |
1 |
|
|
T3 |
7 |
|
T4 |
34 |
|
T16 |
8 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41735 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T3 |
53 |
auto[1] |
1350 |
1 |
|
|
T3 |
5 |
|
T4 |
39 |
|
T16 |
10 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41782 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T3 |
53 |
auto[1] |
1303 |
1 |
|
|
T3 |
5 |
|
T4 |
40 |
|
T16 |
12 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41695 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T3 |
58 |
auto[1] |
1390 |
1 |
|
|
T12 |
9 |
|
T17 |
13 |
|
T25 |
8 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
37863 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T3 |
58 |
auto[1] |
5222 |
1 |
|
|
T12 |
11 |
|
T15 |
60 |
|
T24 |
53 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39358 |
1 |
|
|
T1 |
91 |
|
T3 |
58 |
|
T11 |
10 |
auto[1] |
3727 |
1 |
|
|
T2 |
82 |
|
T13 |
72 |
|
T14 |
59 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
43085 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T3 |
58 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41744 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T3 |
58 |
auto[1] |
1341 |
1 |
|
|
T12 |
10 |
|
T17 |
11 |
|
T25 |
4 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41684 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T3 |
58 |
auto[1] |
1401 |
1 |
|
|
T12 |
14 |
|
T17 |
9 |
|
T25 |
7 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41650 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T3 |
58 |
auto[1] |
1435 |
1 |
|
|
T12 |
12 |
|
T17 |
8 |
|
T25 |
8 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
38913 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T3 |
58 |
auto[0] |
no_err_inj |
2322 |
1 |
|
|
T11 |
10 |
|
T4 |
29 |
|
T68 |
7 |
auto[1] |
err_inj |
909 |
1 |
|
|
T4 |
21 |
|
T17 |
3 |
|
T102 |
7 |
auto[1] |
no_err_inj |
941 |
1 |
|
|
T4 |
21 |
|
T17 |
7 |
|
T102 |
3 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39998 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T3 |
53 |
auto[0] |
auto[1] |
1237 |
1 |
|
|
T3 |
5 |
|
T4 |
35 |
|
T16 |
10 |
auto[1] |
auto[0] |
1737 |
1 |
|
|
T4 |
38 |
|
T17 |
9 |
|
T102 |
9 |
auto[1] |
auto[1] |
113 |
1 |
|
|
T4 |
4 |
|
T17 |
1 |
|
T102 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
40050 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T3 |
50 |
auto[0] |
auto[1] |
1185 |
1 |
|
|
T3 |
8 |
|
T4 |
35 |
|
T16 |
10 |
auto[1] |
auto[0] |
1753 |
1 |
|
|
T4 |
39 |
|
T17 |
10 |
|
T102 |
9 |
auto[1] |
auto[1] |
97 |
1 |
|
|
T4 |
3 |
|
T102 |
1 |
|
T211 |
2 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
40027 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T3 |
53 |
auto[0] |
auto[1] |
1208 |
1 |
|
|
T3 |
5 |
|
T4 |
36 |
|
T16 |
12 |
auto[1] |
auto[0] |
1755 |
1 |
|
|
T4 |
38 |
|
T17 |
10 |
|
T102 |
8 |
auto[1] |
auto[1] |
95 |
1 |
|
|
T4 |
4 |
|
T102 |
2 |
|
T211 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
40023 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T3 |
55 |
auto[0] |
auto[1] |
1212 |
1 |
|
|
T3 |
3 |
|
T4 |
36 |
|
T16 |
4 |
auto[1] |
auto[0] |
1768 |
1 |
|
|
T4 |
42 |
|
T17 |
10 |
|
T102 |
10 |
auto[1] |
auto[1] |
82 |
1 |
|
|
T21 |
3 |
|
T99 |
1 |
|
T34 |
2 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39944 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T3 |
51 |
auto[0] |
auto[1] |
1291 |
1 |
|
|
T3 |
7 |
|
T4 |
51 |
|
T16 |
8 |
auto[1] |
auto[0] |
1745 |
1 |
|
|
T4 |
38 |
|
T17 |
10 |
|
T102 |
8 |
auto[1] |
auto[1] |
105 |
1 |
|
|
T4 |
4 |
|
T102 |
2 |
|
T21 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
40026 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T3 |
48 |
auto[0] |
auto[1] |
1209 |
1 |
|
|
T3 |
10 |
|
T4 |
39 |
|
T16 |
5 |
auto[1] |
auto[0] |
1755 |
1 |
|
|
T4 |
40 |
|
T17 |
9 |
|
T102 |
10 |
auto[1] |
auto[1] |
95 |
1 |
|
|
T4 |
2 |
|
T17 |
1 |
|
T21 |
2 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
32142 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T11 |
10 |
auto[0] |
auto[1] |
996 |
1 |
|
|
T12 |
8 |
|
T17 |
8 |
|
T25 |
13 |
auto[1] |
auto[0] |
9463 |
1 |
|
|
T3 |
58 |
|
T4 |
34 |
|
T17 |
1 |
auto[1] |
auto[1] |
484 |
1 |
|
|
T35 |
15 |
|
T51 |
18 |
|
T109 |
10 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
32225 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T11 |
10 |
auto[0] |
auto[1] |
913 |
1 |
|
|
T12 |
12 |
|
T17 |
10 |
|
T25 |
6 |
auto[1] |
auto[0] |
9483 |
1 |
|
|
T3 |
58 |
|
T4 |
34 |
|
T17 |
1 |
auto[1] |
auto[1] |
464 |
1 |
|
|
T35 |
14 |
|
T51 |
16 |
|
T109 |
10 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
32046 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T11 |
10 |
auto[0] |
auto[1] |
1092 |
1 |
|
|
T4 |
22 |
|
T17 |
16 |
|
T72 |
9 |
auto[1] |
auto[0] |
9235 |
1 |
|
|
T3 |
58 |
|
T4 |
34 |
|
T18 |
64 |
auto[1] |
auto[1] |
712 |
1 |
|
|
T17 |
1 |
|
T35 |
19 |
|
T38 |
20 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
32202 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T11 |
10 |
auto[0] |
auto[1] |
936 |
1 |
|
|
T12 |
13 |
|
T17 |
10 |
|
T25 |
6 |
auto[1] |
auto[0] |
9483 |
1 |
|
|
T3 |
58 |
|
T4 |
34 |
|
T17 |
1 |
auto[1] |
auto[1] |
464 |
1 |
|
|
T35 |
14 |
|
T51 |
25 |
|
T109 |
8 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
28440 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T11 |
10 |
auto[0] |
auto[1] |
4698 |
1 |
|
|
T12 |
11 |
|
T15 |
60 |
|
T24 |
53 |
auto[1] |
auto[0] |
9423 |
1 |
|
|
T3 |
58 |
|
T4 |
34 |
|
T17 |
1 |
auto[1] |
auto[1] |
524 |
1 |
|
|
T35 |
12 |
|
T51 |
12 |
|
T109 |
14 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
32262 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T11 |
10 |
auto[0] |
auto[1] |
876 |
1 |
|
|
T4 |
37 |
|
T16 |
10 |
|
T17 |
1 |
auto[1] |
auto[0] |
9473 |
1 |
|
|
T3 |
53 |
|
T4 |
32 |
|
T17 |
1 |
auto[1] |
auto[1] |
474 |
1 |
|
|
T3 |
5 |
|
T4 |
2 |
|
T18 |
8 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
32290 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T11 |
10 |
auto[0] |
auto[1] |
848 |
1 |
|
|
T4 |
32 |
|
T16 |
8 |
|
T101 |
9 |
auto[1] |
auto[0] |
9481 |
1 |
|
|
T3 |
51 |
|
T4 |
32 |
|
T17 |
1 |
auto[1] |
auto[1] |
466 |
1 |
|
|
T3 |
7 |
|
T4 |
2 |
|
T18 |
7 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
32302 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T11 |
10 |
auto[0] |
auto[1] |
836 |
1 |
|
|
T4 |
35 |
|
T16 |
10 |
|
T101 |
5 |
auto[1] |
auto[0] |
9501 |
1 |
|
|
T3 |
50 |
|
T4 |
31 |
|
T17 |
1 |
auto[1] |
auto[1] |
446 |
1 |
|
|
T3 |
8 |
|
T4 |
3 |
|
T18 |
5 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
32287 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T11 |
10 |
auto[0] |
auto[1] |
851 |
1 |
|
|
T4 |
48 |
|
T16 |
10 |
|
T17 |
1 |
auto[1] |
auto[0] |
9462 |
1 |
|
|
T3 |
54 |
|
T4 |
34 |
|
T17 |
1 |
auto[1] |
auto[1] |
485 |
1 |
|
|
T3 |
4 |
|
T18 |
4 |
|
T19 |
5 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
32291 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T11 |
10 |
auto[0] |
auto[1] |
847 |
1 |
|
|
T4 |
36 |
|
T16 |
4 |
|
T101 |
9 |
auto[1] |
auto[0] |
9500 |
1 |
|
|
T3 |
55 |
|
T4 |
34 |
|
T17 |
1 |
auto[1] |
auto[1] |
447 |
1 |
|
|
T3 |
3 |
|
T18 |
9 |
|
T19 |
3 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
32305 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T11 |
10 |
auto[0] |
auto[1] |
833 |
1 |
|
|
T4 |
40 |
|
T16 |
5 |
|
T17 |
1 |
auto[1] |
auto[0] |
9476 |
1 |
|
|
T3 |
48 |
|
T4 |
33 |
|
T17 |
1 |
auto[1] |
auto[1] |
471 |
1 |
|
|
T3 |
10 |
|
T4 |
1 |
|
T18 |
6 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
32194 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T11 |
10 |
auto[0] |
auto[1] |
944 |
1 |
|
|
T12 |
12 |
|
T17 |
8 |
|
T25 |
8 |
auto[1] |
auto[0] |
9456 |
1 |
|
|
T3 |
58 |
|
T4 |
34 |
|
T17 |
1 |
auto[1] |
auto[1] |
491 |
1 |
|
|
T35 |
12 |
|
T51 |
19 |
|
T109 |
8 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
32183 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T11 |
10 |
auto[0] |
auto[1] |
955 |
1 |
|
|
T12 |
14 |
|
T17 |
9 |
|
T25 |
7 |
auto[1] |
auto[0] |
9501 |
1 |
|
|
T3 |
58 |
|
T4 |
34 |
|
T17 |
1 |
auto[1] |
auto[1] |
446 |
1 |
|
|
T35 |
9 |
|
T51 |
18 |
|
T109 |
7 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31893 |
1 |
|
|
T1 |
91 |
|
T2 |
82 |
|
T11 |
10 |
auto[0] |
auto[1] |
1245 |
1 |
|
|
T4 |
20 |
|
T17 |
10 |
|
T102 |
10 |
auto[1] |
auto[0] |
9342 |
1 |
|
|
T3 |
58 |
|
T4 |
12 |
|
T17 |
1 |
auto[1] |
auto[1] |
605 |
1 |
|
|
T4 |
22 |
|
T21 |
10 |
|
T99 |
23 |