Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

66697120

1

T1

49288

T2

28844

T3

97884

auto[1]

1207730

1

T1

1386

T3

2058

T12

396

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

66683784

1

T1

48892

T2

28844

T3

97198

auto[1]

1221066

1

T1

1782

T3

2744

T12

396

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5432316	1			T1	8789		T2	7822		T3	18569
auto[IdleSt]	15375397	1			T1	6142		T2	6983		T3	3310
auto[ClkMuxSt]	29959	1			T1	72		T2	82		T11	10
auto[CntIncrSt]	29772	1			T1	72		T2	82		T11	10
auto[CntProgSt]	1459570	1			T1	8109		T2	164		T11	303
auto[TransCheckSt]	23353	1			T1	59		T2	82		T11	10
auto[TokenHashSt]	24673647	1			T1	4776		T2	712		T11	40060
auto[FlashRmaSt]	23070	1			T1	84		T2	79		T11	33
auto[TokenCheck0St]	10164	1			T1	47		T2	27		T11	10
auto[TokenCheck1St]	7325	1			T1	30		T2	9		T11	10
auto[TransProgSt]	346367	1			T1	4218		T11	175		T12	687
auto[PostTransSt]	8756747	1			T1	11349		T2	12802		T11	1041
auto[ScrapSt]	77872	1			T113	513		T188	3189		T190	1333
auto[EscalateSt]	4916006	1			T1	4279		T3	19781		T12	1079
auto[InvalidSt]	6741931	1			T1	2648		T3	58274		T4	45092

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1354	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	6741931	1			T1	2648		T3	58274		T4	45092
EscalateSt	4916006	1			T1	4279		T3	19781		T12	1079
ScrapSt	77872	1			T113	513		T188	3189		T190	1333
PostTransSt	8756747	1			T1	11349		T2	12802		T11	1041
TransProgSt	346367	1			T1	4218		T11	175		T12	687
TokenCheck1St	7325	1			T1	30		T2	9		T11	10
TokenCheck0St	10164	1			T1	47		T2	27		T11	10
FlashRmaSt	23070	1			T1	84		T2	79		T11	33
TokenHashSt	24673647	1			T1	4776		T2	712		T11	40060
TransCheckSt	23353	1			T1	59		T2	82		T11	10
CntProgSt	1459570	1			T1	8109		T2	164		T11	303
CntIncrSt	29772	1			T1	72		T2	82		T11	10
ClkMuxSt	29959	1			T1	72		T2	82		T11	10
IdleSt	15375397	1			T1	6142		T2	6983		T3	3310
ResetSt	5432316	1			T1	8789		T2	7822		T3	18569
arcs[ResetSt=>IdleSt]	43569	1			T1	92		T2	83		T3	50
arcs[IdleSt=>ScrapSt]	224	1			T113	1		T188	1		T190	1
arcs[IdleSt=>ClkMuxSt]	29823	1			T1	72		T2	82		T11	10
arcs[ClkMuxSt=>CntIncrSt]	29772	1			T1	72		T2	82		T11	10
arcs[CntIncrSt=>PostTransSt]	1401	1			T12	14		T17	9		T25	7
arcs[CntIncrSt=>CntProgSt]	28304	1			T1	72		T2	82		T11	10
arcs[CntProgSt=>PostTransSt]	3998	1			T1	13		T12	8		T4	22
arcs[CntProgSt=>TransCheckSt]	23353	1			T1	59		T2	82		T11	10
arcs[TransCheckSt=>PostTransSt]	3332	1			T2	49		T12	12		T13	37
arcs[TransCheckSt=>TokenHashSt]	19871	1			T1	59		T2	33		T11	10
arcs[TokenHashSt=>PostTransSt]	8847	1			T1	12		T2	6		T12	30
arcs[TokenHashSt=>FlashRmaSt]	10264	1			T1	47		T2	27		T11	10
arcs[FlashRmaSt=>TokenCheck0St]	10164	1			T1	47		T2	27		T11	10
arcs[TokenCheck0St=>PostTransSt]	2815	1			T1	17		T2	18		T12	12
arcs[TokenCheck0St=>TokenCheck1St]	7325	1			T1	30		T2	9		T11	10
arcs[TokenCheck1St=>PostTransSt]	612	1			T1	1		T2	9		T13	7
arcs[TransProgSt=>PostTransSt]	5869	1			T1	29		T11	10		T12	13
arcs[IdleSt=>EscalateSt]	182	1			T59	9		T60	5		T61	4
arcs[ClkMuxSt=>EscalateSt]	51	1			T57	1		T58	1		T59	1
arcs[CntIncrSt=>EscalateSt]	67	1			T57	1		T58	2		T59	1
arcs[CntProgSt=>EscalateSt]	953	1			T57	31		T58	21		T59	24
arcs[TransCheckSt=>EscalateSt]	150	1			T62	5		T65	6		T60	12
arcs[TokenHashSt=>EscalateSt]	748	1			T57	11		T58	9		T59	12
arcs[FlashRmaSt=>EscalateSt]	100	1			T57	6		T58	1		T59	3
arcs[TokenCheck0St=>EscalateSt]	24	1			T57	1		T59	1		T62	1
arcs[TokenCheck1St=>EscalateSt]	130	1			T58	4		T59	6		T62	1
arcs[TransProgSt=>EscalateSt]	714	1			T57	14		T58	23		T59	18
arcs[PostTransSt=>EscalateSt]	4257	1			T1	13		T12	8		T4	22
arcs[InvalidSt=>EscalateSt]	11251	1			T1	19		T3	49		T4	332

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5432154	1			T1	8789		T2	7822		T3	18569
auto[0]	auto[IdleSt]	15375267	1			T1	6142		T2	6983		T3	3310
auto[0]	auto[ClkMuxSt]	29920	1			T1	72		T2	82		T11	10
auto[0]	auto[CntIncrSt]	29723	1			T1	72		T2	82		T11	10
auto[0]	auto[CntProgSt]	1458964	1			T1	8109		T2	164		T11	303
auto[0]	auto[TransCheckSt]	23242	1			T1	59		T2	82		T11	10
auto[0]	auto[TokenHashSt]	24673147	1			T1	4776		T2	712		T11	40060
auto[0]	auto[FlashRmaSt]	23008	1			T1	84		T2	79		T11	33
auto[0]	auto[TokenCheck0St]	10150	1			T1	47		T2	27		T11	10
auto[0]	auto[TokenCheck1St]	7239	1			T1	30		T2	9		T11	10
auto[0]	auto[TransProgSt]	345888	1			T1	4218		T11	175		T12	687
auto[0]	auto[PostTransSt]	8754609	1			T1	11341		T2	12802		T11	1041
auto[0]	auto[ScrapSt]	77829	1			T113	513		T188	3189		T190	1333
auto[0]	auto[EscalateSt]	3718297	1			T1	2907		T3	17744		T12	687
auto[0]	auto[InvalidSt]	6736329	1			T1	2642		T3	58253		T4	44938
auto[1]	auto[ResetSt]	162	1			T57	6		T58	4		T59	8
auto[1]	auto[IdleSt]	130	1			T59	6		T60	3		T61	2
auto[1]	auto[ClkMuxSt]	39	1			T57	1		T59	1		T60	2
auto[1]	auto[CntIncrSt]	49	1			T57	1		T58	2		T62	1
auto[1]	auto[CntProgSt]	606	1			T57	23		T58	13		T59	18
auto[1]	auto[TransCheckSt]	111	1			T62	2		T65	4		T60	9
auto[1]	auto[TokenHashSt]	500	1			T57	7		T58	7		T59	8
auto[1]	auto[FlashRmaSt]	62	1			T57	4		T58	1		T59	3
auto[1]	auto[TokenCheck0St]	14	1			T57	1		T62	1		T65	1
auto[1]	auto[TokenCheck1St]	86	1			T58	2		T59	5		T62	1
auto[1]	auto[TransProgSt]	479	1			T57	9		T58	19		T59	11
auto[1]	auto[PostTransSt]	2138	1			T1	8		T12	4		T4	15
auto[1]	auto[ScrapSt]	43	1			T58	1		T62	2		T65	1
auto[1]	auto[EscalateSt]	1197709	1			T1	1372		T3	2037		T12	392
auto[1]	auto[InvalidSt]	5602	1			T1	6		T3	21		T4	154

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5432143	1			T1	8789		T2	7822		T3	18569
auto[0]	auto[IdleSt]	15375278	1			T1	6142		T2	6983		T3	3310
auto[0]	auto[ClkMuxSt]	29923	1			T1	72		T2	82		T11	10
auto[0]	auto[CntIncrSt]	29732	1			T1	72		T2	82		T11	10
auto[0]	auto[CntProgSt]	1458937	1			T1	8109		T2	164		T11	303
auto[0]	auto[TransCheckSt]	23259	1			T1	59		T2	82		T11	10
auto[0]	auto[TokenHashSt]	24673150	1			T1	4776		T2	712		T11	40060
auto[0]	auto[FlashRmaSt]	23002	1			T1	84		T2	79		T11	33
auto[0]	auto[TokenCheck0St]	10148	1			T1	47		T2	27		T11	10
auto[0]	auto[TokenCheck1St]	7234	1			T1	30		T2	9		T11	10
auto[0]	auto[TransProgSt]	345894	1			T1	4218		T11	175		T12	687
auto[0]	auto[PostTransSt]	8754549	1			T1	11344		T2	12802		T11	1041
auto[0]	auto[ScrapSt]	77819	1			T113	513		T188	3189		T190	1333
auto[0]	auto[EscalateSt]	3705081	1			T1	2515		T3	17065		T12	687
auto[0]	auto[InvalidSt]	6736281	1			T1	2635		T3	58246		T4	44913
auto[1]	auto[ResetSt]	173	1			T57	9		T58	5		T59	5
auto[1]	auto[IdleSt]	119	1			T59	6		T60	5		T61	3
auto[1]	auto[ClkMuxSt]	36	1			T57	1		T58	1		T59	1
auto[1]	auto[CntIncrSt]	40	1			T58	1		T59	1		T62	2
auto[1]	auto[CntProgSt]	633	1			T57	19		T58	13		T59	15
auto[1]	auto[TransCheckSt]	94	1			T62	5		T65	5		T60	5
auto[1]	auto[TokenHashSt]	497	1			T57	6		T58	4		T59	8
auto[1]	auto[FlashRmaSt]	68	1			T57	3		T59	1		T62	4
auto[1]	auto[TokenCheck0St]	16	1			T57	1		T59	1		T210	1
auto[1]	auto[TokenCheck1St]	91	1			T58	3		T59	5		T60	1
auto[1]	auto[TransProgSt]	473	1			T57	10		T58	19		T59	13
auto[1]	auto[PostTransSt]	2198	1			T1	5		T12	4		T4	7
auto[1]	auto[ScrapSt]	53	1			T59	1		T62	1		T65	1
auto[1]	auto[EscalateSt]	1210925	1			T1	1764		T3	2716		T12	392
auto[1]	auto[InvalidSt]	5650	1			T1	13		T3	28		T4	179