Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.30 97.29 95.52 91.98 100.00 95.93 98.73 94.64


Total test records in report: 989
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T768 /workspace/coverage/default/45.lc_ctrl_state_failure.1481787063 Dec 20 12:56:25 PM PST 23 Dec 20 12:56:59 PM PST 23 429255256 ps
T769 /workspace/coverage/default/11.lc_ctrl_security_escalation.1675777932 Dec 20 12:55:19 PM PST 23 Dec 20 12:55:46 PM PST 23 2142532800 ps
T770 /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3494778355 Dec 20 12:55:29 PM PST 23 Dec 20 12:55:45 PM PST 23 10630998 ps
T771 /workspace/coverage/default/7.lc_ctrl_jtag_smoke.3077539938 Dec 20 12:55:17 PM PST 23 Dec 20 12:55:35 PM PST 23 341800474 ps
T772 /workspace/coverage/default/23.lc_ctrl_prog_failure.650734161 Dec 20 12:56:02 PM PST 23 Dec 20 12:56:18 PM PST 23 577391829 ps
T773 /workspace/coverage/default/40.lc_ctrl_sec_token_mux.3077195010 Dec 20 12:56:36 PM PST 23 Dec 20 12:56:48 PM PST 23 162321369 ps
T774 /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1662977622 Dec 20 12:55:16 PM PST 23 Dec 20 12:55:34 PM PST 23 160169122 ps
T775 /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2043689003 Dec 20 12:55:41 PM PST 23 Dec 20 12:56:04 PM PST 23 215579524 ps
T776 /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3278908299 Dec 20 12:55:40 PM PST 23 Dec 20 12:55:55 PM PST 23 13020535 ps
T777 /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.3840584192 Dec 20 12:56:00 PM PST 23 Dec 20 12:56:48 PM PST 23 5919052516 ps
T778 /workspace/coverage/default/26.lc_ctrl_errors.1593313311 Dec 20 12:56:00 PM PST 23 Dec 20 12:56:27 PM PST 23 1192656822 ps
T779 /workspace/coverage/default/38.lc_ctrl_sec_token_mux.1253640560 Dec 20 12:56:45 PM PST 23 Dec 20 12:56:57 PM PST 23 654727246 ps
T780 /workspace/coverage/default/35.lc_ctrl_smoke.558308213 Dec 20 12:56:21 PM PST 23 Dec 20 12:56:30 PM PST 23 177877926 ps
T781 /workspace/coverage/default/0.lc_ctrl_sec_mubi.3358421178 Dec 20 12:55:21 PM PST 23 Dec 20 12:55:48 PM PST 23 444810397 ps
T782 /workspace/coverage/default/32.lc_ctrl_prog_failure.750908352 Dec 20 12:56:25 PM PST 23 Dec 20 12:56:35 PM PST 23 433195741 ps
T783 /workspace/coverage/default/22.lc_ctrl_sec_token_digest.4125915459 Dec 20 12:55:56 PM PST 23 Dec 20 12:56:22 PM PST 23 300496297 ps
T784 /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.378874765 Dec 20 12:55:24 PM PST 23 Dec 20 12:55:49 PM PST 23 1361593069 ps
T785 /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1966851899 Dec 20 12:56:12 PM PST 23 Dec 20 12:56:23 PM PST 23 14482760 ps
T786 /workspace/coverage/default/31.lc_ctrl_sec_token_mux.961951696 Dec 20 12:56:28 PM PST 23 Dec 20 12:56:43 PM PST 23 836283377 ps
T787 /workspace/coverage/default/30.lc_ctrl_state_failure.338914228 Dec 20 12:56:11 PM PST 23 Dec 20 12:56:45 PM PST 23 1039822799 ps
T788 /workspace/coverage/default/49.lc_ctrl_sec_token_digest.587283484 Dec 20 12:57:00 PM PST 23 Dec 20 12:57:30 PM PST 23 1611695129 ps
T789 /workspace/coverage/default/40.lc_ctrl_stress_all.1155704100 Dec 20 12:56:46 PM PST 23 Dec 20 01:01:23 PM PST 23 20247735490 ps
T790 /workspace/coverage/default/41.lc_ctrl_state_failure.2806152535 Dec 20 12:56:40 PM PST 23 Dec 20 12:57:14 PM PST 23 291548795 ps
T791 /workspace/coverage/default/44.lc_ctrl_alert_test.912781616 Dec 20 12:56:20 PM PST 23 Dec 20 12:56:28 PM PST 23 59356239 ps
T792 /workspace/coverage/default/0.lc_ctrl_jtag_errors.140680946 Dec 20 12:55:25 PM PST 23 Dec 20 12:56:37 PM PST 23 4376572671 ps
T793 /workspace/coverage/default/21.lc_ctrl_state_failure.1026062562 Dec 20 12:55:50 PM PST 23 Dec 20 12:56:30 PM PST 23 902062925 ps
T794 /workspace/coverage/default/18.lc_ctrl_state_post_trans.2538391389 Dec 20 12:55:35 PM PST 23 Dec 20 12:55:52 PM PST 23 134525689 ps
T795 /workspace/coverage/default/24.lc_ctrl_sec_mubi.228643045 Dec 20 12:56:02 PM PST 23 Dec 20 12:56:26 PM PST 23 364388110 ps
T796 /workspace/coverage/default/11.lc_ctrl_jtag_access.1739254546 Dec 20 12:55:18 PM PST 23 Dec 20 12:55:39 PM PST 23 187304686 ps
T797 /workspace/coverage/default/7.lc_ctrl_sec_token_digest.2197575086 Dec 20 12:55:26 PM PST 23 Dec 20 12:55:49 PM PST 23 1127670164 ps
T798 /workspace/coverage/default/36.lc_ctrl_alert_test.3417610466 Dec 20 12:56:27 PM PST 23 Dec 20 12:56:35 PM PST 23 31970433 ps
T799 /workspace/coverage/default/23.lc_ctrl_stress_all.83922314 Dec 20 12:55:56 PM PST 23 Dec 20 01:00:19 PM PST 23 7768844264 ps
T800 /workspace/coverage/default/29.lc_ctrl_smoke.1589085554 Dec 20 12:56:20 PM PST 23 Dec 20 12:56:30 PM PST 23 58865710 ps
T801 /workspace/coverage/default/11.lc_ctrl_smoke.20450965 Dec 20 12:55:23 PM PST 23 Dec 20 12:55:40 PM PST 23 108192999 ps
T802 /workspace/coverage/default/20.lc_ctrl_sec_token_digest.3103401721 Dec 20 12:55:51 PM PST 23 Dec 20 12:56:17 PM PST 23 1124702381 ps
T803 /workspace/coverage/default/28.lc_ctrl_sec_mubi.2136958801 Dec 20 12:56:28 PM PST 23 Dec 20 12:56:46 PM PST 23 1805071470 ps
T804 /workspace/coverage/default/3.lc_ctrl_state_failure.3196928779 Dec 20 12:55:29 PM PST 23 Dec 20 12:56:08 PM PST 23 228973592 ps
T805 /workspace/coverage/default/5.lc_ctrl_prog_failure.4048073232 Dec 20 12:55:24 PM PST 23 Dec 20 12:55:41 PM PST 23 34771600 ps
T806 /workspace/coverage/default/29.lc_ctrl_errors.3379582582 Dec 20 12:56:20 PM PST 23 Dec 20 12:56:38 PM PST 23 255839256 ps
T807 /workspace/coverage/default/7.lc_ctrl_security_escalation.1383976922 Dec 20 12:55:30 PM PST 23 Dec 20 12:55:51 PM PST 23 318058052 ps
T808 /workspace/coverage/default/47.lc_ctrl_sec_mubi.103467878 Dec 20 12:57:08 PM PST 23 Dec 20 12:57:38 PM PST 23 332930160 ps
T809 /workspace/coverage/default/45.lc_ctrl_sec_mubi.819771233 Dec 20 12:56:46 PM PST 23 Dec 20 12:57:01 PM PST 23 942067627 ps
T810 /workspace/coverage/default/42.lc_ctrl_state_post_trans.3801169686 Dec 20 12:56:43 PM PST 23 Dec 20 12:56:54 PM PST 23 182569896 ps
T811 /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2752803353 Dec 20 12:56:48 PM PST 23 Dec 20 12:57:01 PM PST 23 544650280 ps
T812 /workspace/coverage/default/26.lc_ctrl_security_escalation.1743655195 Dec 20 12:56:24 PM PST 23 Dec 20 12:56:37 PM PST 23 943355494 ps
T813 /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.1158427006 Dec 20 12:55:24 PM PST 23 Dec 20 12:56:07 PM PST 23 985466611 ps
T814 /workspace/coverage/default/25.lc_ctrl_jtag_access.810041037 Dec 20 12:55:56 PM PST 23 Dec 20 12:56:12 PM PST 23 101241989 ps
T815 /workspace/coverage/default/6.lc_ctrl_alert_test.1904066308 Dec 20 12:55:24 PM PST 23 Dec 20 12:55:40 PM PST 23 32641726 ps
T816 /workspace/coverage/default/48.lc_ctrl_stress_all.756224754 Dec 20 12:56:33 PM PST 23 Dec 20 12:58:40 PM PST 23 29779730973 ps
T817 /workspace/coverage/default/8.lc_ctrl_state_post_trans.2775632721 Dec 20 12:55:25 PM PST 23 Dec 20 12:55:45 PM PST 23 59919719 ps
T818 /workspace/coverage/default/39.lc_ctrl_sec_token_digest.352222466 Dec 20 12:56:38 PM PST 23 Dec 20 12:56:51 PM PST 23 249281276 ps
T819 /workspace/coverage/default/17.lc_ctrl_prog_failure.3795971243 Dec 20 12:55:42 PM PST 23 Dec 20 12:55:59 PM PST 23 34631249 ps
T820 /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.4259813785 Dec 20 12:55:00 PM PST 23 Dec 20 12:55:36 PM PST 23 830149396 ps
T821 /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3599762928 Dec 20 12:55:39 PM PST 23 Dec 20 12:56:24 PM PST 23 944992959 ps
T822 /workspace/coverage/default/35.lc_ctrl_stress_all.2272059677 Dec 20 12:56:54 PM PST 23 Dec 20 12:59:37 PM PST 23 9931925269 ps
T823 /workspace/coverage/default/7.lc_ctrl_smoke.1518615581 Dec 20 12:55:28 PM PST 23 Dec 20 12:55:47 PM PST 23 146514814 ps
T824 /workspace/coverage/default/2.lc_ctrl_jtag_errors.3553947914 Dec 20 12:55:27 PM PST 23 Dec 20 12:56:57 PM PST 23 2827866454 ps
T84 /workspace/coverage/default/49.lc_ctrl_smoke.3220659985 Dec 20 12:56:35 PM PST 23 Dec 20 12:56:43 PM PST 23 173256443 ps
T825 /workspace/coverage/default/40.lc_ctrl_prog_failure.1244439100 Dec 20 12:57:02 PM PST 23 Dec 20 12:57:21 PM PST 23 58014838 ps
T826 /workspace/coverage/default/17.lc_ctrl_sec_mubi.4221257354 Dec 20 12:55:30 PM PST 23 Dec 20 12:56:03 PM PST 23 885881159 ps
T827 /workspace/coverage/default/5.lc_ctrl_jtag_access.101906743 Dec 20 12:55:20 PM PST 23 Dec 20 12:55:39 PM PST 23 1067979771 ps
T828 /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.3536593288 Dec 20 12:55:18 PM PST 23 Dec 20 12:55:50 PM PST 23 1466447702 ps
T96 /workspace/coverage/default/28.lc_ctrl_stress_all.1720900888 Dec 20 12:56:18 PM PST 23 Dec 20 12:57:56 PM PST 23 2528971901 ps
T829 /workspace/coverage/default/38.lc_ctrl_state_failure.3557724947 Dec 20 12:56:13 PM PST 23 Dec 20 12:56:54 PM PST 23 307953302 ps
T97 /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1497274352 Dec 20 12:55:16 PM PST 23 Dec 20 12:55:55 PM PST 23 4630935140 ps
T830 /workspace/coverage/default/14.lc_ctrl_sec_mubi.48446238 Dec 20 12:55:31 PM PST 23 Dec 20 12:55:57 PM PST 23 1630645630 ps
T831 /workspace/coverage/default/3.lc_ctrl_sec_mubi.3352505421 Dec 20 12:55:15 PM PST 23 Dec 20 12:55:42 PM PST 23 476957659 ps
T832 /workspace/coverage/default/40.lc_ctrl_state_post_trans.3166507210 Dec 20 12:56:39 PM PST 23 Dec 20 12:56:48 PM PST 23 728959657 ps
T833 /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.449417611 Dec 20 12:55:18 PM PST 23 Dec 20 12:55:34 PM PST 23 89658158 ps
T834 /workspace/coverage/default/9.lc_ctrl_errors.1237077806 Dec 20 12:55:22 PM PST 23 Dec 20 12:55:50 PM PST 23 2043481954 ps
T835 /workspace/coverage/default/8.lc_ctrl_stress_all.1456586126 Dec 20 12:55:24 PM PST 23 Dec 20 12:59:04 PM PST 23 47155075073 ps
T836 /workspace/coverage/default/3.lc_ctrl_prog_failure.1203672369 Dec 20 12:55:01 PM PST 23 Dec 20 12:55:24 PM PST 23 52547969 ps
T837 /workspace/coverage/default/7.lc_ctrl_state_failure.792007424 Dec 20 12:55:15 PM PST 23 Dec 20 12:56:08 PM PST 23 288017827 ps
T838 /workspace/coverage/default/6.lc_ctrl_jtag_errors.754594411 Dec 20 12:55:16 PM PST 23 Dec 20 12:56:29 PM PST 23 8138180944 ps
T839 /workspace/coverage/default/14.lc_ctrl_errors.1718197824 Dec 20 12:55:39 PM PST 23 Dec 20 12:56:07 PM PST 23 1752441557 ps
T840 /workspace/coverage/default/13.lc_ctrl_state_post_trans.1167499941 Dec 20 12:55:41 PM PST 23 Dec 20 12:56:02 PM PST 23 46969353 ps
T841 /workspace/coverage/default/34.lc_ctrl_stress_all.307225941 Dec 20 12:56:28 PM PST 23 Dec 20 01:00:59 PM PST 23 12241997748 ps
T842 /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.2807450798 Dec 20 12:56:38 PM PST 23 Dec 20 12:56:44 PM PST 23 16114131 ps
T843 /workspace/coverage/default/28.lc_ctrl_security_escalation.2305520914 Dec 20 12:56:25 PM PST 23 Dec 20 12:56:43 PM PST 23 1172212109 ps
T844 /workspace/coverage/default/7.lc_ctrl_prog_failure.189496681 Dec 20 12:55:23 PM PST 23 Dec 20 12:55:41 PM PST 23 271614848 ps
T845 /workspace/coverage/default/37.lc_ctrl_sec_mubi.1570907113 Dec 20 12:57:07 PM PST 23 Dec 20 12:57:36 PM PST 23 627484830 ps
T846 /workspace/coverage/default/9.lc_ctrl_claim_transition_if.3511808295 Dec 20 12:55:30 PM PST 23 Dec 20 12:55:46 PM PST 23 26729539 ps
T847 /workspace/coverage/default/20.lc_ctrl_errors.305597850 Dec 20 12:55:48 PM PST 23 Dec 20 12:56:18 PM PST 23 1821056933 ps
T848 /workspace/coverage/default/38.lc_ctrl_stress_all.2438167350 Dec 20 12:56:40 PM PST 23 Dec 20 12:59:00 PM PST 23 71400042002 ps
T849 /workspace/coverage/default/25.lc_ctrl_sec_mubi.1649064773 Dec 20 12:56:00 PM PST 23 Dec 20 12:56:21 PM PST 23 161859807 ps
T850 /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.3256638515 Dec 20 12:55:57 PM PST 23 Dec 20 12:56:12 PM PST 23 29513860 ps
T851 /workspace/coverage/default/33.lc_ctrl_alert_test.2393312175 Dec 20 12:56:58 PM PST 23 Dec 20 12:57:11 PM PST 23 11582556 ps
T852 /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.289985739 Dec 20 12:55:44 PM PST 23 Dec 20 12:56:00 PM PST 23 43680682 ps
T853 /workspace/coverage/default/35.lc_ctrl_security_escalation.3207576788 Dec 20 12:56:34 PM PST 23 Dec 20 12:56:50 PM PST 23 3317615890 ps
T854 /workspace/coverage/default/25.lc_ctrl_state_post_trans.2926386872 Dec 20 12:55:52 PM PST 23 Dec 20 12:56:13 PM PST 23 201749384 ps
T855 /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.4004248718 Dec 20 12:55:41 PM PST 23 Dec 20 12:56:06 PM PST 23 1115260592 ps
T856 /workspace/coverage/default/0.lc_ctrl_prog_failure.3457470371 Dec 20 12:55:17 PM PST 23 Dec 20 12:55:40 PM PST 23 251560288 ps
T857 /workspace/coverage/default/7.lc_ctrl_state_post_trans.2340856822 Dec 20 12:55:21 PM PST 23 Dec 20 12:55:42 PM PST 23 201129104 ps
T858 /workspace/coverage/default/23.lc_ctrl_errors.2578238123 Dec 20 12:55:59 PM PST 23 Dec 20 12:56:25 PM PST 23 2451612134 ps
T859 /workspace/coverage/default/1.lc_ctrl_sec_mubi.2011483632 Dec 20 12:55:00 PM PST 23 Dec 20 12:55:31 PM PST 23 3135533880 ps
T860 /workspace/coverage/default/1.lc_ctrl_jtag_access.1344490167 Dec 20 12:55:06 PM PST 23 Dec 20 12:55:33 PM PST 23 731825715 ps
T861 /workspace/coverage/default/16.lc_ctrl_state_post_trans.340464621 Dec 20 12:55:40 PM PST 23 Dec 20 12:56:05 PM PST 23 89308626 ps
T862 /workspace/coverage/default/5.lc_ctrl_stress_all.959444572 Dec 20 12:55:15 PM PST 23 Dec 20 12:57:59 PM PST 23 19940771368 ps
T863 /workspace/coverage/default/6.lc_ctrl_jtag_access.2769236380 Dec 20 12:55:25 PM PST 23 Dec 20 12:55:43 PM PST 23 360501166 ps
T864 /workspace/coverage/default/44.lc_ctrl_security_escalation.2964493402 Dec 20 12:56:52 PM PST 23 Dec 20 12:57:15 PM PST 23 1703020770 ps
T865 /workspace/coverage/default/21.lc_ctrl_jtag_access.2417893981 Dec 20 12:56:14 PM PST 23 Dec 20 12:56:28 PM PST 23 163518236 ps
T866 /workspace/coverage/default/27.lc_ctrl_state_post_trans.1162916522 Dec 20 12:56:06 PM PST 23 Dec 20 12:56:21 PM PST 23 329950440 ps
T867 /workspace/coverage/default/26.lc_ctrl_state_post_trans.821144320 Dec 20 12:56:09 PM PST 23 Dec 20 12:56:28 PM PST 23 275023772 ps
T868 /workspace/coverage/default/37.lc_ctrl_stress_all.3741113357 Dec 20 12:56:18 PM PST 23 Dec 20 12:59:49 PM PST 23 11741597957 ps
T869 /workspace/coverage/default/31.lc_ctrl_jtag_access.3278004609 Dec 20 12:56:13 PM PST 23 Dec 20 12:56:25 PM PST 23 717589173 ps
T870 /workspace/coverage/default/30.lc_ctrl_sec_token_digest.778053778 Dec 20 12:56:30 PM PST 23 Dec 20 12:56:47 PM PST 23 530006311 ps
T871 /workspace/coverage/default/6.lc_ctrl_sec_mubi.868420685 Dec 20 12:55:31 PM PST 23 Dec 20 12:56:06 PM PST 23 827603589 ps
T872 /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1989659958 Dec 20 12:55:50 PM PST 23 Dec 20 12:56:15 PM PST 23 277802992 ps
T873 /workspace/coverage/default/24.lc_ctrl_jtag_access.573140420 Dec 20 12:55:53 PM PST 23 Dec 20 12:56:16 PM PST 23 1883728618 ps
T874 /workspace/coverage/default/40.lc_ctrl_security_escalation.1622859392 Dec 20 12:56:30 PM PST 23 Dec 20 12:56:44 PM PST 23 705239945 ps
T875 /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1252315493 Dec 20 12:55:16 PM PST 23 Dec 20 12:56:16 PM PST 23 1609485908 ps
T876 /workspace/coverage/default/4.lc_ctrl_claim_transition_if.1485975400 Dec 20 12:55:00 PM PST 23 Dec 20 12:55:21 PM PST 23 14033865 ps
T877 /workspace/coverage/default/46.lc_ctrl_sec_token_mux.1657579788 Dec 20 12:56:46 PM PST 23 Dec 20 12:57:01 PM PST 23 1178402694 ps
T85 /workspace/coverage/default/20.lc_ctrl_alert_test.162457838 Dec 20 12:55:48 PM PST 23 Dec 20 12:56:04 PM PST 23 16419784 ps
T878 /workspace/coverage/default/10.lc_ctrl_errors.1461996778 Dec 20 12:55:17 PM PST 23 Dec 20 12:55:48 PM PST 23 1098943650 ps
T879 /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.3997712309 Dec 20 12:55:42 PM PST 23 Dec 20 12:56:05 PM PST 23 348614770 ps
T880 /workspace/coverage/default/15.lc_ctrl_prog_failure.1696996245 Dec 20 12:55:33 PM PST 23 Dec 20 12:55:49 PM PST 23 986900837 ps
T881 /workspace/coverage/default/22.lc_ctrl_jtag_access.3817906113 Dec 20 12:55:59 PM PST 23 Dec 20 12:56:19 PM PST 23 603857727 ps
T882 /workspace/coverage/default/7.lc_ctrl_jtag_access.231166664 Dec 20 12:55:25 PM PST 23 Dec 20 12:55:43 PM PST 23 109254679 ps
T883 /workspace/coverage/default/22.lc_ctrl_smoke.1474399717 Dec 20 12:55:59 PM PST 23 Dec 20 12:56:14 PM PST 23 30301373 ps
T884 /workspace/coverage/default/0.lc_ctrl_sec_token_digest.1178115206 Dec 20 12:55:01 PM PST 23 Dec 20 12:55:38 PM PST 23 710526402 ps
T885 /workspace/coverage/default/14.lc_ctrl_prog_failure.2396971722 Dec 20 12:55:31 PM PST 23 Dec 20 12:55:48 PM PST 23 125733115 ps
T886 /workspace/coverage/default/17.lc_ctrl_errors.103652677 Dec 20 12:55:40 PM PST 23 Dec 20 12:56:10 PM PST 23 1604106543 ps
T887 /workspace/coverage/default/34.lc_ctrl_smoke.1884586045 Dec 20 12:56:39 PM PST 23 Dec 20 12:56:48 PM PST 23 93866319 ps
T888 /workspace/coverage/default/26.lc_ctrl_jtag_access.85105204 Dec 20 12:56:00 PM PST 23 Dec 20 12:56:26 PM PST 23 2081826930 ps
T889 /workspace/coverage/default/39.lc_ctrl_stress_all.1592934131 Dec 20 12:56:42 PM PST 23 Dec 20 12:59:21 PM PST 23 9531305839 ps
T86 /workspace/coverage/default/10.lc_ctrl_jtag_smoke.4179365298 Dec 20 12:55:27 PM PST 23 Dec 20 12:55:48 PM PST 23 2108460375 ps
T890 /workspace/coverage/default/46.lc_ctrl_prog_failure.57420415 Dec 20 12:56:34 PM PST 23 Dec 20 12:56:43 PM PST 23 133600515 ps
T87 /workspace/coverage/default/2.lc_ctrl_jtag_smoke.3322735110 Dec 20 12:55:20 PM PST 23 Dec 20 12:55:37 PM PST 23 1251257293 ps
T891 /workspace/coverage/default/34.lc_ctrl_jtag_access.3077321152 Dec 20 12:56:23 PM PST 23 Dec 20 12:56:33 PM PST 23 880449691 ps
T892 /workspace/coverage/default/2.lc_ctrl_sec_token_digest.69195250 Dec 20 12:55:26 PM PST 23 Dec 20 12:55:53 PM PST 23 1174164315 ps
T185 /workspace/coverage/default/5.lc_ctrl_security_escalation.2782714241 Dec 20 12:55:16 PM PST 23 Dec 20 12:55:43 PM PST 23 376170321 ps
T893 /workspace/coverage/default/1.lc_ctrl_jtag_errors.952717253 Dec 20 12:54:53 PM PST 23 Dec 20 12:55:45 PM PST 23 1130763683 ps
T894 /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.3473417613 Dec 20 12:55:37 PM PST 23 Dec 20 12:56:28 PM PST 23 6064503625 ps
T895 /workspace/coverage/default/10.lc_ctrl_smoke.425837429 Dec 20 12:55:25 PM PST 23 Dec 20 12:55:42 PM PST 23 212513002 ps
T896 /workspace/coverage/default/40.lc_ctrl_sec_mubi.3852610039 Dec 20 12:56:59 PM PST 23 Dec 20 12:57:32 PM PST 23 1398110750 ps
T897 /workspace/coverage/default/39.lc_ctrl_sec_mubi.2892426255 Dec 20 12:56:58 PM PST 23 Dec 20 12:57:28 PM PST 23 819808623 ps
T898 /workspace/coverage/default/35.lc_ctrl_state_failure.720657311 Dec 20 12:56:23 PM PST 23 Dec 20 12:56:53 PM PST 23 864725369 ps
T899 /workspace/coverage/default/28.lc_ctrl_smoke.2924307809 Dec 20 12:56:07 PM PST 23 Dec 20 12:56:20 PM PST 23 114713497 ps
T900 /workspace/coverage/default/5.lc_ctrl_regwen_during_op.1660496720 Dec 20 12:55:05 PM PST 23 Dec 20 12:55:37 PM PST 23 384907612 ps
T901 /workspace/coverage/default/7.lc_ctrl_errors.3037266768 Dec 20 12:55:16 PM PST 23 Dec 20 12:55:52 PM PST 23 2748898656 ps
T902 /workspace/coverage/default/49.lc_ctrl_sec_token_mux.2557063719 Dec 20 12:56:46 PM PST 23 Dec 20 12:57:06 PM PST 23 194639960 ps
T903 /workspace/coverage/default/8.lc_ctrl_security_escalation.2895210636 Dec 20 12:55:30 PM PST 23 Dec 20 12:55:53 PM PST 23 629075273 ps
T904 /workspace/coverage/default/45.lc_ctrl_errors.1819453858 Dec 20 12:56:33 PM PST 23 Dec 20 12:56:54 PM PST 23 6749561898 ps
T905 /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3429938573 Dec 20 12:56:33 PM PST 23 Dec 20 12:56:40 PM PST 23 15940117 ps
T906 /workspace/coverage/default/43.lc_ctrl_security_escalation.1800824355 Dec 20 12:56:46 PM PST 23 Dec 20 12:57:04 PM PST 23 323720323 ps
T907 /workspace/coverage/default/3.lc_ctrl_security_escalation.1161070378 Dec 20 12:55:01 PM PST 23 Dec 20 12:55:31 PM PST 23 713890732 ps
T908 /workspace/coverage/default/3.lc_ctrl_jtag_access.3312002843 Dec 20 12:54:58 PM PST 23 Dec 20 12:55:27 PM PST 23 773034245 ps
T909 /workspace/coverage/default/7.lc_ctrl_stress_all.1321875596 Dec 20 12:55:36 PM PST 23 Dec 20 12:56:49 PM PST 23 8154610409 ps
T910 /workspace/coverage/default/22.lc_ctrl_errors.3455586346 Dec 20 12:55:59 PM PST 23 Dec 20 12:56:25 PM PST 23 438477279 ps
T911 /workspace/coverage/default/30.lc_ctrl_stress_all.1066670352 Dec 20 12:56:11 PM PST 23 Dec 20 01:03:24 PM PST 23 31403591542 ps
T912 /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.2407736949 Dec 20 12:55:30 PM PST 23 Dec 20 12:55:54 PM PST 23 1826981404 ps
T913 /workspace/coverage/default/22.lc_ctrl_state_post_trans.968692778 Dec 20 12:55:56 PM PST 23 Dec 20 12:56:18 PM PST 23 148192604 ps
T914 /workspace/coverage/default/0.lc_ctrl_stress_all.3175184038 Dec 20 12:55:26 PM PST 23 Dec 20 12:56:24 PM PST 23 7995400538 ps
T915 /workspace/coverage/default/12.lc_ctrl_sec_mubi.2718569563 Dec 20 12:55:38 PM PST 23 Dec 20 12:56:01 PM PST 23 202354706 ps
T916 /workspace/coverage/default/22.lc_ctrl_prog_failure.3905902733 Dec 20 12:55:48 PM PST 23 Dec 20 12:56:06 PM PST 23 78990897 ps
T917 /workspace/coverage/default/32.lc_ctrl_state_failure.1166416056 Dec 20 12:56:26 PM PST 23 Dec 20 12:56:54 PM PST 23 836160003 ps
T918 /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.4082902382 Dec 20 12:55:36 PM PST 23 Dec 20 12:56:09 PM PST 23 525626910 ps
T919 /workspace/coverage/default/41.lc_ctrl_alert_test.2414593958 Dec 20 12:56:18 PM PST 23 Dec 20 12:56:27 PM PST 23 244597538 ps
T920 /workspace/coverage/default/49.lc_ctrl_security_escalation.2343018294 Dec 20 12:56:39 PM PST 23 Dec 20 12:56:53 PM PST 23 415531816 ps
T921 /workspace/coverage/default/9.lc_ctrl_jtag_priority.392434270 Dec 20 12:55:21 PM PST 23 Dec 20 12:55:40 PM PST 23 352476657 ps
T922 /workspace/coverage/default/17.lc_ctrl_state_failure.3498517428 Dec 20 12:55:36 PM PST 23 Dec 20 12:56:12 PM PST 23 2881769565 ps
T923 /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2461602528 Dec 20 12:55:30 PM PST 23 Dec 20 12:55:58 PM PST 23 350874579 ps
T924 /workspace/coverage/default/3.lc_ctrl_regwen_during_op.3065774458 Dec 20 12:54:59 PM PST 23 Dec 20 12:55:32 PM PST 23 1281173977 ps
T925 /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.2753478142 Dec 20 12:55:59 PM PST 23 Dec 20 12:56:24 PM PST 23 471990576 ps
T926 /workspace/coverage/default/13.lc_ctrl_stress_all.2386650593 Dec 20 12:55:40 PM PST 23 Dec 20 01:00:07 PM PST 23 46818860690 ps
T927 /workspace/coverage/default/27.lc_ctrl_security_escalation.1886585043 Dec 20 12:56:03 PM PST 23 Dec 20 12:56:23 PM PST 23 949456538 ps
T928 /workspace/coverage/default/16.lc_ctrl_jtag_smoke.1398871708 Dec 20 12:55:49 PM PST 23 Dec 20 12:56:07 PM PST 23 735385813 ps
T929 /workspace/coverage/default/14.lc_ctrl_security_escalation.3571159468 Dec 20 12:55:36 PM PST 23 Dec 20 12:55:59 PM PST 23 561018134 ps
T930 /workspace/coverage/default/28.lc_ctrl_sec_token_digest.1735305702 Dec 20 12:56:21 PM PST 23 Dec 20 12:56:37 PM PST 23 243349860 ps
T116 /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.1001507624 Dec 20 12:56:03 PM PST 23 Dec 20 01:05:32 PM PST 23 32229285794 ps
T117 /workspace/coverage/default/13.lc_ctrl_state_failure.577509593 Dec 20 12:55:53 PM PST 23 Dec 20 12:56:39 PM PST 23 3461385307 ps
T118 /workspace/coverage/default/42.lc_ctrl_security_escalation.499066679 Dec 20 12:56:56 PM PST 23 Dec 20 12:57:15 PM PST 23 267519338 ps
T119 /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.930565058 Dec 20 12:55:04 PM PST 23 Dec 20 12:55:30 PM PST 23 521982879 ps
T120 /workspace/coverage/default/24.lc_ctrl_prog_failure.8767667 Dec 20 12:56:03 PM PST 23 Dec 20 12:56:17 PM PST 23 127263247 ps
T121 /workspace/coverage/default/19.lc_ctrl_jtag_access.998584100 Dec 20 12:55:52 PM PST 23 Dec 20 12:56:10 PM PST 23 1021814653 ps
T122 /workspace/coverage/default/6.lc_ctrl_errors.735541182 Dec 20 12:55:23 PM PST 23 Dec 20 12:55:51 PM PST 23 446715185 ps
T123 /workspace/coverage/default/41.lc_ctrl_errors.3825508264 Dec 20 12:56:41 PM PST 23 Dec 20 12:56:58 PM PST 23 496802456 ps
T124 /workspace/coverage/default/10.lc_ctrl_sec_mubi.3134749261 Dec 20 12:55:25 PM PST 23 Dec 20 12:55:49 PM PST 23 519788780 ps
T931 /workspace/coverage/default/47.lc_ctrl_alert_test.3600258263 Dec 20 12:56:57 PM PST 23 Dec 20 12:57:09 PM PST 23 22491733 ps
T135 /workspace/coverage/default/29.lc_ctrl_stress_all.3858899216 Dec 20 12:56:25 PM PST 23 Dec 20 01:00:49 PM PST 23 64108510404 ps
T932 /workspace/coverage/default/20.lc_ctrl_security_escalation.3273347911 Dec 20 12:55:52 PM PST 23 Dec 20 12:56:14 PM PST 23 1017025577 ps
T933 /workspace/coverage/default/43.lc_ctrl_state_post_trans.1859058821 Dec 20 12:56:29 PM PST 23 Dec 20 12:56:42 PM PST 23 84061402 ps
T934 /workspace/coverage/default/38.lc_ctrl_state_post_trans.1604179149 Dec 20 12:56:24 PM PST 23 Dec 20 12:56:39 PM PST 23 87101716 ps
T935 /workspace/coverage/default/24.lc_ctrl_sec_token_digest.590194964 Dec 20 12:56:04 PM PST 23 Dec 20 12:56:28 PM PST 23 1228172078 ps
T936 /workspace/coverage/default/20.lc_ctrl_sec_token_mux.3785172768 Dec 20 12:55:50 PM PST 23 Dec 20 12:56:17 PM PST 23 1648091830 ps
T937 /workspace/coverage/default/5.lc_ctrl_sec_token_digest.3037466169 Dec 20 12:55:16 PM PST 23 Dec 20 12:55:49 PM PST 23 405831131 ps
T938 /workspace/coverage/default/48.lc_ctrl_smoke.1668928806 Dec 20 12:57:11 PM PST 23 Dec 20 12:57:29 PM PST 23 42876014 ps
T939 /workspace/coverage/default/11.lc_ctrl_alert_test.1183325053 Dec 20 12:55:31 PM PST 23 Dec 20 12:55:46 PM PST 23 31956084 ps
T940 /workspace/coverage/default/31.lc_ctrl_sec_token_digest.1162619252 Dec 20 12:56:39 PM PST 23 Dec 20 12:56:53 PM PST 23 2848862305 ps
T941 /workspace/coverage/default/32.lc_ctrl_sec_mubi.2024485567 Dec 20 12:56:38 PM PST 23 Dec 20 12:56:54 PM PST 23 518550941 ps
T942 /workspace/coverage/default/38.lc_ctrl_jtag_access.2086520435 Dec 20 12:56:24 PM PST 23 Dec 20 12:56:41 PM PST 23 358180779 ps
T943 /workspace/coverage/default/36.lc_ctrl_security_escalation.2475020764 Dec 20 12:56:40 PM PST 23 Dec 20 12:56:55 PM PST 23 377358648 ps
T944 /workspace/coverage/default/49.lc_ctrl_alert_test.880332110 Dec 20 12:56:38 PM PST 23 Dec 20 12:56:44 PM PST 23 19348067 ps
T945 /workspace/coverage/default/38.lc_ctrl_errors.1724322956 Dec 20 12:56:15 PM PST 23 Dec 20 12:56:37 PM PST 23 235195011 ps
T946 /workspace/coverage/default/46.lc_ctrl_state_failure.3909168444 Dec 20 12:56:48 PM PST 23 Dec 20 12:57:14 PM PST 23 493273508 ps
T947 /workspace/coverage/default/0.lc_ctrl_state_failure.1550554672 Dec 20 12:55:03 PM PST 23 Dec 20 12:55:48 PM PST 23 184255956 ps
T948 /workspace/coverage/default/35.lc_ctrl_jtag_access.841136877 Dec 20 12:56:40 PM PST 23 Dec 20 12:56:56 PM PST 23 1019840722 ps
T949 /workspace/coverage/default/9.lc_ctrl_stress_all.1516045610 Dec 20 12:55:30 PM PST 23 Dec 20 12:57:14 PM PST 23 3524272817 ps
T950 /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3572894148 Dec 20 12:55:16 PM PST 23 Dec 20 12:55:43 PM PST 23 683104165 ps
T951 /workspace/coverage/default/32.lc_ctrl_state_post_trans.370775862 Dec 20 12:56:39 PM PST 23 Dec 20 12:56:51 PM PST 23 114299104 ps
T952 /workspace/coverage/default/35.lc_ctrl_state_post_trans.3057800575 Dec 20 12:56:30 PM PST 23 Dec 20 12:56:39 PM PST 23 282742214 ps
T953 /workspace/coverage/default/15.lc_ctrl_state_failure.3534997118 Dec 20 12:55:44 PM PST 23 Dec 20 12:56:17 PM PST 23 614922901 ps
T954 /workspace/coverage/default/45.lc_ctrl_jtag_access.1521069524 Dec 20 12:56:25 PM PST 23 Dec 20 12:56:41 PM PST 23 720025945 ps
T955 /workspace/coverage/default/37.lc_ctrl_state_failure.3232602025 Dec 20 12:56:56 PM PST 23 Dec 20 12:57:32 PM PST 23 605181711 ps
T956 /workspace/coverage/default/9.lc_ctrl_jtag_access.3922883810 Dec 20 12:55:34 PM PST 23 Dec 20 12:55:55 PM PST 23 1544165393 ps
T957 /workspace/coverage/default/23.lc_ctrl_smoke.2799932037 Dec 20 12:56:06 PM PST 23 Dec 20 12:56:20 PM PST 23 258662624 ps
T958 /workspace/coverage/default/17.lc_ctrl_sec_token_digest.17424897 Dec 20 12:55:54 PM PST 23 Dec 20 12:56:22 PM PST 23 1353293987 ps
T959 /workspace/coverage/default/0.lc_ctrl_state_post_trans.707513261 Dec 20 12:55:17 PM PST 23 Dec 20 12:55:44 PM PST 23 77200081 ps
T960 /workspace/coverage/default/2.lc_ctrl_state_failure.35391110 Dec 20 12:55:21 PM PST 23 Dec 20 12:56:00 PM PST 23 236518703 ps
T961 /workspace/coverage/default/9.lc_ctrl_sec_token_mux.1397952326 Dec 20 12:55:30 PM PST 23 Dec 20 12:55:56 PM PST 23 315492413 ps
T962 /workspace/coverage/default/35.lc_ctrl_prog_failure.3977310974 Dec 20 12:56:40 PM PST 23 Dec 20 12:56:48 PM PST 23 68096027 ps
T963 /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.88276332 Dec 20 12:55:26 PM PST 23 Dec 20 12:55:58 PM PST 23 2510980685 ps
T964 /workspace/coverage/default/18.lc_ctrl_jtag_smoke.3677561547 Dec 20 12:55:44 PM PST 23 Dec 20 12:56:04 PM PST 23 1229386186 ps
T965 /workspace/coverage/default/41.lc_ctrl_sec_mubi.506544700 Dec 20 12:56:28 PM PST 23 Dec 20 12:56:45 PM PST 23 482734393 ps
T966 /workspace/coverage/default/14.lc_ctrl_sec_token_mux.3676834436 Dec 20 12:55:29 PM PST 23 Dec 20 12:55:53 PM PST 23 816306936 ps
T967 /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.1599350465 Dec 20 12:55:54 PM PST 23 Dec 20 01:04:14 PM PST 23 22689662851 ps
T968 /workspace/coverage/default/1.lc_ctrl_state_failure.2624347668 Dec 20 12:55:00 PM PST 23 Dec 20 12:55:41 PM PST 23 2499768113 ps
T969 /workspace/coverage/default/27.lc_ctrl_prog_failure.4069811424 Dec 20 12:56:06 PM PST 23 Dec 20 12:56:21 PM PST 23 310483849 ps
T970 /workspace/coverage/default/31.lc_ctrl_smoke.3298391686 Dec 20 12:56:18 PM PST 23 Dec 20 12:56:29 PM PST 23 60609315 ps
T971 /workspace/coverage/default/5.lc_ctrl_smoke.3275761474 Dec 20 12:55:17 PM PST 23 Dec 20 12:55:41 PM PST 23 630521255 ps
T972 /workspace/coverage/default/13.lc_ctrl_errors.2259531348 Dec 20 12:55:39 PM PST 23 Dec 20 12:56:04 PM PST 23 279253289 ps
T973 /workspace/coverage/default/41.lc_ctrl_prog_failure.23268317 Dec 20 12:56:23 PM PST 23 Dec 20 12:56:31 PM PST 23 124184689 ps
T974 /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.3265681071 Dec 20 12:55:46 PM PST 23 Dec 20 01:05:14 PM PST 23 98087253011 ps
T975 /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3909320719 Dec 20 12:56:25 PM PST 23 Dec 20 12:56:33 PM PST 23 16190822 ps
T976 /workspace/coverage/default/31.lc_ctrl_stress_all.2768860954 Dec 20 12:56:26 PM PST 23 Dec 20 12:58:28 PM PST 23 2491322609 ps
T977 /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1485566252 Dec 20 12:57:02 PM PST 23 Dec 20 12:57:19 PM PST 23 13404232 ps
T978 /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3157133025 Dec 20 12:55:16 PM PST 23 Dec 20 12:55:52 PM PST 23 342351371 ps
T979 /workspace/coverage/default/47.lc_ctrl_smoke.1703226249 Dec 20 12:57:02 PM PST 23 Dec 20 12:57:20 PM PST 23 61594827 ps
T980 /workspace/coverage/default/8.lc_ctrl_sec_mubi.3562904199 Dec 20 12:55:16 PM PST 23 Dec 20 12:55:44 PM PST 23 317244990 ps
T981 /workspace/coverage/default/29.lc_ctrl_prog_failure.3702245269 Dec 20 12:56:17 PM PST 23 Dec 20 12:56:28 PM PST 23 533210581 ps
T982 /workspace/coverage/default/38.lc_ctrl_smoke.1178972550 Dec 20 12:56:15 PM PST 23 Dec 20 12:56:28 PM PST 23 318241978 ps
T983 /workspace/coverage/default/12.lc_ctrl_smoke.1482492934 Dec 20 12:55:34 PM PST 23 Dec 20 12:55:49 PM PST 23 78142803 ps
T984 /workspace/coverage/default/2.lc_ctrl_stress_all.2454113063 Dec 20 12:55:16 PM PST 23 Dec 20 12:56:31 PM PST 23 8036693424 ps
T985 /workspace/coverage/default/28.lc_ctrl_alert_test.1462082072 Dec 20 12:56:31 PM PST 23 Dec 20 12:56:38 PM PST 23 81038055 ps
T986 /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3706130217 Dec 20 12:56:29 PM PST 23 Dec 20 12:56:36 PM PST 23 30638483 ps
T987 /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.376121247 Dec 20 12:55:35 PM PST 23 Dec 20 12:56:22 PM PST 23 1114606476 ps
T988 /workspace/coverage/default/3.lc_ctrl_jtag_errors.1988113561 Dec 20 12:55:02 PM PST 23 Dec 20 12:56:18 PM PST 23 8389989677 ps
T989 /workspace/coverage/default/34.lc_ctrl_errors.15318304 Dec 20 12:56:37 PM PST 23 Dec 20 12:56:59 PM PST 23 1588337536 ps

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.3952235421
Short name T1
Test name
Test status
Simulation time 2026970788 ps
CPU time 14.56 seconds
Started Dec 20 12:55:24 PM PST 23
Finished Dec 20 12:55:53 PM PST 23
Peak memory 219352 kb
Host smart-7b91b91e-0f8a-4846-bf80-61765cdf8848
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952235421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.3952235421
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.2061483171
Short name T3
Test name
Test status
Simulation time 1009532640 ps
CPU time 45.3 seconds
Started Dec 20 12:55:55 PM PST 23
Finished Dec 20 12:56:55 PM PST 23
Peak memory 251528 kb
Host smart-be905b2a-aafa-48e5-9667-942af4658044
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061483171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.2061483171
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.3199289949
Short name T59
Test name
Test status
Simulation time 1820732653 ps
CPU time 17.93 seconds
Started Dec 20 12:56:41 PM PST 23
Finished Dec 20 12:57:04 PM PST 23
Peak memory 218300 kb
Host smart-5c2a11a5-34fc-4b47-bb01-6ed9046aaf2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199289949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.3199289949
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.3775674646
Short name T99
Test name
Test status
Simulation time 8930800920 ps
CPU time 196.35 seconds
Started Dec 20 12:57:05 PM PST 23
Finished Dec 20 01:00:38 PM PST 23
Peak memory 251108 kb
Host smart-91ebf363-5247-43f8-ade9-c38b031e26aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775674646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.3775674646
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.958927454
Short name T113
Test name
Test status
Simulation time 233237122 ps
CPU time 2.85 seconds
Started Dec 20 12:37:22 PM PST 23
Finished Dec 20 12:38:37 PM PST 23
Peak memory 222096 kb
Host smart-de4bf4ff-25a3-42e3-9b37-b33d6ff9d953
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958927454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_e
rr.958927454
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.3483138796
Short name T52
Test name
Test status
Simulation time 13794732736 ps
CPU time 445.99 seconds
Started Dec 20 12:56:52 PM PST 23
Finished Dec 20 01:04:34 PM PST 23
Peak memory 283388 kb
Host smart-50e4ff5a-9bb6-48cd-9d58-5c9579f3fa3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3483138796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.3483138796
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1711570730
Short name T139
Test name
Test status
Simulation time 117192783 ps
CPU time 1.37 seconds
Started Dec 20 12:37:00 PM PST 23
Finished Dec 20 12:37:39 PM PST 23
Peak memory 219416 kb
Host smart-4a23a853-eeed-400e-8f45-9c5ea1990df0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711570730 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.1711570730
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2914251383
Short name T43
Test name
Test status
Simulation time 57348204 ps
CPU time 0.89 seconds
Started Dec 20 12:55:08 PM PST 23
Finished Dec 20 12:55:29 PM PST 23
Peak memory 208836 kb
Host smart-d2357834-9db3-41fb-af18-546d79d20a06
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914251383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.2914251383
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.3311485996
Short name T4
Test name
Test status
Simulation time 7286652731 ps
CPU time 261.26 seconds
Started Dec 20 12:57:06 PM PST 23
Finished Dec 20 01:01:44 PM PST 23
Peak memory 333332 kb
Host smart-f086086f-26a6-40c7-b915-54c83e59fc73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3311485996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.3311485996
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.2378797806
Short name T63
Test name
Test status
Simulation time 210400256 ps
CPU time 22.65 seconds
Started Dec 20 12:54:58 PM PST 23
Finished Dec 20 12:55:40 PM PST 23
Peak memory 284328 kb
Host smart-8130d6db-2fbc-4f0f-b0c0-d5ed846e8c0c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378797806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.2378797806
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2323643485
Short name T104
Test name
Test status
Simulation time 275117840 ps
CPU time 2.17 seconds
Started Dec 20 12:37:17 PM PST 23
Finished Dec 20 12:38:16 PM PST 23
Peak memory 210804 kb
Host smart-0deca55d-79a4-4375-9ce2-1b98356e508d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323643485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.2323643485
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.3688761892
Short name T321
Test name
Test status
Simulation time 860461242 ps
CPU time 9.56 seconds
Started Dec 20 12:55:23 PM PST 23
Finished Dec 20 12:55:47 PM PST 23
Peak memory 218284 kb
Host smart-5357b2fd-4275-42d4-8307-bad1678aaaae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688761892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
3688761892
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.786265133
Short name T62
Test name
Test status
Simulation time 2119477150 ps
CPU time 12.98 seconds
Started Dec 20 12:55:48 PM PST 23
Finished Dec 20 12:56:16 PM PST 23
Peak memory 218288 kb
Host smart-9a70ad58-7661-47f2-8db2-b59af6e27e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786265133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.786265133
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.2782714241
Short name T185
Test name
Test status
Simulation time 376170321 ps
CPU time 10.57 seconds
Started Dec 20 12:55:16 PM PST 23
Finished Dec 20 12:55:43 PM PST 23
Peak memory 218296 kb
Host smart-89b1fd7e-d90e-436a-8eaf-98213d1a084d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782714241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.2782714241
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.355487332
Short name T182
Test name
Test status
Simulation time 53541303 ps
CPU time 0.84 seconds
Started Dec 20 12:37:12 PM PST 23
Finished Dec 20 12:38:00 PM PST 23
Peak memory 209532 kb
Host smart-8022377f-675d-4820-ae90-38aabe927b9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355487332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.355487332
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.1332369512
Short name T48
Test name
Test status
Simulation time 4693274509 ps
CPU time 61.08 seconds
Started Dec 20 12:55:40 PM PST 23
Finished Dec 20 12:56:56 PM PST 23
Peak memory 218788 kb
Host smart-c829a03a-d225-4b5d-a923-82006db5861d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332369512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.1332369512
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.897453128
Short name T10
Test name
Test status
Simulation time 24545826 ps
CPU time 1.23 seconds
Started Dec 20 12:56:12 PM PST 23
Finished Dec 20 12:56:23 PM PST 23
Peak memory 209796 kb
Host smart-1c0ecde8-8f0c-4ee3-b362-1602c1d95228
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897453128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.897453128
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.61411488
Short name T147
Test name
Test status
Simulation time 473171317 ps
CPU time 3.3 seconds
Started Dec 20 12:37:01 PM PST 23
Finished Dec 20 12:37:44 PM PST 23
Peak memory 217768 kb
Host smart-d0773cb3-1f52-4894-8207-a4bce39e3844
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61411488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.61411488
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.1204484810
Short name T8
Test name
Test status
Simulation time 1664727468 ps
CPU time 4.85 seconds
Started Dec 20 12:56:00 PM PST 23
Finished Dec 20 12:56:18 PM PST 23
Peak memory 209748 kb
Host smart-e1764c81-7320-4529-a61c-3ad844141efd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204484810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_a
ccess.1204484810
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2075526618
Short name T138
Test name
Test status
Simulation time 391002136 ps
CPU time 2.51 seconds
Started Dec 20 12:36:31 PM PST 23
Finished Dec 20 12:36:38 PM PST 23
Peak memory 217852 kb
Host smart-958d28e8-4623-4727-93a1-a33fc5eae404
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075526618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2075526618
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2881344304
Short name T151
Test name
Test status
Simulation time 123748133 ps
CPU time 3.41 seconds
Started Dec 20 12:37:02 PM PST 23
Finished Dec 20 12:37:45 PM PST 23
Peak memory 221556 kb
Host smart-b27446e2-7763-45f7-bf19-b27dd44ae49f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881344304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.2881344304
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.301520978
Short name T134
Test name
Test status
Simulation time 28191374779 ps
CPU time 50.63 seconds
Started Dec 20 12:55:20 PM PST 23
Finished Dec 20 12:56:29 PM PST 23
Peak memory 267652 kb
Host smart-bbc459d6-9731-4285-a6c2-a9f13d06fd7a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301520978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_state_failure.301520978
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1313740754
Short name T150
Test name
Test status
Simulation time 206172804 ps
CPU time 3.8 seconds
Started Dec 20 12:37:05 PM PST 23
Finished Dec 20 12:37:48 PM PST 23
Peak memory 217908 kb
Host smart-bac787e5-7cd8-40a3-8cbc-573e53c847b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313740754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.1313740754
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3831993714
Short name T108
Test name
Test status
Simulation time 45025981 ps
CPU time 0.98 seconds
Started Dec 20 12:36:58 PM PST 23
Finished Dec 20 12:37:36 PM PST 23
Peak memory 209680 kb
Host smart-4d40717f-c1a2-49f9-8c33-e6daea3eb86b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831993714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.3831993714
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.29312447
Short name T156
Test name
Test status
Simulation time 111389132 ps
CPU time 2.41 seconds
Started Dec 20 12:36:31 PM PST 23
Finished Dec 20 12:36:38 PM PST 23
Peak memory 217884 kb
Host smart-ff17e709-a9ab-47f0-8164-02609591443d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29312447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg_e
rr.29312447
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.489093094
Short name T354
Test name
Test status
Simulation time 12970248 ps
CPU time 0.74 seconds
Started Dec 20 12:55:33 PM PST 23
Finished Dec 20 12:55:47 PM PST 23
Peak memory 208052 kb
Host smart-f630a9be-4756-4ca7-9743-65dd30d03feb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489093094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ct
rl_volatile_unlock_smoke.489093094
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.1001507624
Short name T116
Test name
Test status
Simulation time 32229285794 ps
CPU time 556.52 seconds
Started Dec 20 12:56:03 PM PST 23
Finished Dec 20 01:05:32 PM PST 23
Peak memory 276612 kb
Host smart-4907d0c9-3c97-42b9-9db8-79d0ba8c03c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1001507624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.1001507624
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3627151455
Short name T136
Test name
Test status
Simulation time 216793392 ps
CPU time 2.03 seconds
Started Dec 20 12:37:21 PM PST 23
Finished Dec 20 12:38:40 PM PST 23
Peak memory 219076 kb
Host smart-153d5d64-e693-4881-865d-c20dcd5fb643
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362715
1455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3627151455
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.860403038
Short name T23
Test name
Test status
Simulation time 1665709216 ps
CPU time 9.36 seconds
Started Dec 20 12:56:15 PM PST 23
Finished Dec 20 12:56:33 PM PST 23
Peak memory 218296 kb
Host smart-320b96d2-def2-4efd-88dd-fb7eda420cda
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860403038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.860403038
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.1086907218
Short name T71
Test name
Test status
Simulation time 299505600 ps
CPU time 18.99 seconds
Started Dec 20 12:54:57 PM PST 23
Finished Dec 20 12:55:34 PM PST 23
Peak memory 214144 kb
Host smart-b495ab51-ec90-496a-9183-c918ee2cc8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086907218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.1086907218
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.174779022
Short name T157
Test name
Test status
Simulation time 65735350 ps
CPU time 2.58 seconds
Started Dec 20 12:37:37 PM PST 23
Finished Dec 20 12:38:53 PM PST 23
Peak memory 217796 kb
Host smart-30f254c7-ca37-4a74-a635-4d09467b6863
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174779022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e
rr.174779022
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3827778251
Short name T160
Test name
Test status
Simulation time 2554562140 ps
CPU time 2.34 seconds
Started Dec 20 12:37:07 PM PST 23
Finished Dec 20 12:37:51 PM PST 23
Peak memory 217908 kb
Host smart-4f22cd3c-45e9-4b07-b380-fb32e0c77ac9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827778251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.3827778251
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1975725515
Short name T162
Test name
Test status
Simulation time 468633266 ps
CPU time 2.71 seconds
Started Dec 20 12:36:54 PM PST 23
Finished Dec 20 12:37:32 PM PST 23
Peak memory 221944 kb
Host smart-0d32a458-0b5c-456a-9c9a-2e041c1e60ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975725515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.1975725515
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.719255091
Short name T159
Test name
Test status
Simulation time 43602353 ps
CPU time 1.73 seconds
Started Dec 20 12:36:31 PM PST 23
Finished Dec 20 12:36:37 PM PST 23
Peak memory 221696 kb
Host smart-623f391b-bdc6-488b-8e9d-02955aef9e2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719255091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_e
rr.719255091
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.893711031
Short name T208
Test name
Test status
Simulation time 65220157 ps
CPU time 0.94 seconds
Started Dec 20 12:55:17 PM PST 23
Finished Dec 20 12:55:34 PM PST 23
Peak memory 209628 kb
Host smart-01f3a174-bb31-4372-9024-32bb38e55520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893711031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.893711031
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.940283679
Short name T209
Test name
Test status
Simulation time 20213991 ps
CPU time 0.88 seconds
Started Dec 20 12:55:17 PM PST 23
Finished Dec 20 12:55:34 PM PST 23
Peak memory 209636 kb
Host smart-772ffb07-4e73-474c-b668-72b86940fcde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940283679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.940283679
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.107905572
Short name T144
Test name
Test status
Simulation time 75045693 ps
CPU time 2.53 seconds
Started Dec 20 12:37:24 PM PST 23
Finished Dec 20 12:38:36 PM PST 23
Peak memory 222076 kb
Host smart-de3a6d31-5602-4a13-adc5-5799b47c497e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107905572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg_
err.107905572
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3072898786
Short name T163
Test name
Test status
Simulation time 63861344 ps
CPU time 1.95 seconds
Started Dec 20 12:37:29 PM PST 23
Finished Dec 20 12:38:44 PM PST 23
Peak memory 221512 kb
Host smart-f24e1191-e207-445e-b96d-8fd404af1df8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072898786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.3072898786
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3602718546
Short name T259
Test name
Test status
Simulation time 98419299 ps
CPU time 3.01 seconds
Started Dec 20 12:37:21 PM PST 23
Finished Dec 20 12:38:28 PM PST 23
Peak memory 226136 kb
Host smart-c5243d4c-d3c9-4cc2-b3c2-6ca94bd5b3e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360271
8546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3602718546
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1094671974
Short name T317
Test name
Test status
Simulation time 185326502 ps
CPU time 2.25 seconds
Started Dec 20 12:37:15 PM PST 23
Finished Dec 20 12:38:08 PM PST 23
Peak memory 210900 kb
Host smart-421b3b08-2069-40b5-b73d-0955c5b7994b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094671974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1094671974
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.4256491481
Short name T154
Test name
Test status
Simulation time 200563895 ps
CPU time 3.12 seconds
Started Dec 20 12:37:21 PM PST 23
Finished Dec 20 12:38:28 PM PST 23
Peak memory 217696 kb
Host smart-7a1daeb0-8208-41f1-a09c-57687df80ab9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256491481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.4256491481
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1603206370
Short name T146
Test name
Test status
Simulation time 180003013 ps
CPU time 2.78 seconds
Started Dec 20 12:36:25 PM PST 23
Finished Dec 20 12:36:29 PM PST 23
Peak memory 221944 kb
Host smart-53785d3a-aaed-461c-8b30-df681806cd88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603206370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.1603206370
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3907660493
Short name T158
Test name
Test status
Simulation time 218051409 ps
CPU time 3.95 seconds
Started Dec 20 12:37:07 PM PST 23
Finished Dec 20 12:37:51 PM PST 23
Peak memory 217928 kb
Host smart-7bd70c2c-04ee-4f97-8275-134cf4f32d25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907660493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.3907660493
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.2754317169
Short name T56
Test name
Test status
Simulation time 7120881456 ps
CPU time 20.46 seconds
Started Dec 20 12:55:31 PM PST 23
Finished Dec 20 12:56:06 PM PST 23
Peak memory 218416 kb
Host smart-31a3ae36-d396-4dbb-93f5-0bb970d59403
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754317169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.2754317169
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.456907368
Short name T12
Test name
Test status
Simulation time 378966461 ps
CPU time 16.95 seconds
Started Dec 20 12:55:55 PM PST 23
Finished Dec 20 12:56:27 PM PST 23
Peak memory 218288 kb
Host smart-95ff3934-5b82-4010-b217-6d30b64d3548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456907368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.456907368
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1246415333
Short name T107
Test name
Test status
Simulation time 51903369 ps
CPU time 1.15 seconds
Started Dec 20 12:37:17 PM PST 23
Finished Dec 20 12:38:14 PM PST 23
Peak memory 209496 kb
Host smart-ab9117ea-18ef-4b76-9104-38a4f2e21c90
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246415333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.1246415333
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.38544898
Short name T193
Test name
Test status
Simulation time 119396221 ps
CPU time 1.14 seconds
Started Dec 20 12:37:12 PM PST 23
Finished Dec 20 12:37:59 PM PST 23
Peak memory 209412 kb
Host smart-0b77e2a5-4e0d-41b4-ac0d-382612aa53c0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38544898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasing.38544898
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3698076170
Short name T235
Test name
Test status
Simulation time 75421678 ps
CPU time 1.27 seconds
Started Dec 20 12:37:22 PM PST 23
Finished Dec 20 12:38:27 PM PST 23
Peak memory 209408 kb
Host smart-c531d775-caeb-476a-a0ae-b247a5ad910e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698076170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.3698076170
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1535981437
Short name T202
Test name
Test status
Simulation time 17492565 ps
CPU time 1.08 seconds
Started Dec 20 12:36:54 PM PST 23
Finished Dec 20 12:37:30 PM PST 23
Peak memory 209900 kb
Host smart-9d54c616-a2e0-41d1-b709-e7119ec2b458
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535981437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.1535981437
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.930026501
Short name T220
Test name
Test status
Simulation time 90121775 ps
CPU time 1.26 seconds
Started Dec 20 12:37:16 PM PST 23
Finished Dec 20 12:38:11 PM PST 23
Peak memory 219096 kb
Host smart-268fc80e-e4d8-44c7-8a6e-387d520d201f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930026501 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.930026501
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3872636384
Short name T251
Test name
Test status
Simulation time 545962988 ps
CPU time 1.42 seconds
Started Dec 20 12:37:20 PM PST 23
Finished Dec 20 12:38:23 PM PST 23
Peak memory 207812 kb
Host smart-82cac3b4-bf28-4dd1-9b8e-62918ba32e68
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872636384 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3872636384
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3355165965
Short name T319
Test name
Test status
Simulation time 502162940 ps
CPU time 11.32 seconds
Started Dec 20 12:37:27 PM PST 23
Finished Dec 20 12:38:48 PM PST 23
Peak memory 208320 kb
Host smart-69e491f3-9576-4b08-ae44-bcb23058246d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355165965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.3355165965
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.456482079
Short name T214
Test name
Test status
Simulation time 2276475407 ps
CPU time 23.51 seconds
Started Dec 20 12:37:06 PM PST 23
Finished Dec 20 12:38:09 PM PST 23
Peak memory 209684 kb
Host smart-6c0e2ad6-677c-4af7-b4a7-8742504802f4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456482079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.456482079
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3609416796
Short name T313
Test name
Test status
Simulation time 92990673 ps
CPU time 2.78 seconds
Started Dec 20 12:37:01 PM PST 23
Finished Dec 20 12:37:43 PM PST 23
Peak memory 211108 kb
Host smart-be17b029-070a-4e4b-be22-2fe3dccbc7bf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609416796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.3609416796
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3867421621
Short name T269
Test name
Test status
Simulation time 62008154 ps
CPU time 1.89 seconds
Started Dec 20 12:37:04 PM PST 23
Finished Dec 20 12:37:47 PM PST 23
Peak memory 209372 kb
Host smart-b176d214-7ba6-4a4c-9f06-1763deb3c099
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867421621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.3867421621
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.970364020
Short name T141
Test name
Test status
Simulation time 22051357 ps
CPU time 1.17 seconds
Started Dec 20 12:37:01 PM PST 23
Finished Dec 20 12:37:41 PM PST 23
Peak memory 211304 kb
Host smart-3d83caa1-5cbe-46d0-a4df-e36384fbdce7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970364020 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.970364020
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.37235455
Short name T287
Test name
Test status
Simulation time 17512873 ps
CPU time 1.17 seconds
Started Dec 20 12:37:12 PM PST 23
Finished Dec 20 12:38:03 PM PST 23
Peak memory 209600 kb
Host smart-d545f4f6-7770-4065-8cf5-2313e091d14e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37235455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_s
ame_csr_outstanding.37235455
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.376708518
Short name T148
Test name
Test status
Simulation time 28258318 ps
CPU time 2.09 seconds
Started Dec 20 12:37:27 PM PST 23
Finished Dec 20 12:38:39 PM PST 23
Peak memory 217560 kb
Host smart-1399b0fd-38ca-496d-a8a8-6ccb347b2e94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376708518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.376708518
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2341369425
Short name T267
Test name
Test status
Simulation time 46922634 ps
CPU time 1.03 seconds
Started Dec 20 12:37:17 PM PST 23
Finished Dec 20 12:38:14 PM PST 23
Peak memory 209732 kb
Host smart-376c0352-3e91-4496-9da2-7066b71ca65e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341369425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.2341369425
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2383424175
Short name T172
Test name
Test status
Simulation time 97002160 ps
CPU time 3.05 seconds
Started Dec 20 12:37:19 PM PST 23
Finished Dec 20 12:38:22 PM PST 23
Peak memory 209600 kb
Host smart-bed94a86-a569-4fd9-99ee-baea5006fc4e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383424175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.2383424175
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3774661417
Short name T183
Test name
Test status
Simulation time 67940036 ps
CPU time 1.2 seconds
Started Dec 20 12:37:27 PM PST 23
Finished Dec 20 12:38:47 PM PST 23
Peak memory 211576 kb
Host smart-4335ac31-e82f-41a8-a2d3-37da204c2fee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774661417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.3774661417
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1441169378
Short name T152
Test name
Test status
Simulation time 24128559 ps
CPU time 1.2 seconds
Started Dec 20 12:36:28 PM PST 23
Finished Dec 20 12:36:32 PM PST 23
Peak memory 218004 kb
Host smart-f4991baa-26a8-4406-a19f-f0faa954481c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441169378 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.1441169378
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2991894050
Short name T191
Test name
Test status
Simulation time 43988527 ps
CPU time 0.87 seconds
Started Dec 20 12:37:22 PM PST 23
Finished Dec 20 12:38:29 PM PST 23
Peak memory 209368 kb
Host smart-147bd65e-deb4-4c30-a725-c5b15f450a51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991894050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.2991894050
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.4025585702
Short name T273
Test name
Test status
Simulation time 172650422 ps
CPU time 1.61 seconds
Started Dec 20 12:37:24 PM PST 23
Finished Dec 20 12:38:34 PM PST 23
Peak memory 209416 kb
Host smart-a7aa8dcc-e246-48fc-9e17-93c7d1639fc9
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025585702 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.4025585702
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2976888226
Short name T276
Test name
Test status
Simulation time 510908490 ps
CPU time 4.47 seconds
Started Dec 20 12:37:11 PM PST 23
Finished Dec 20 12:38:03 PM PST 23
Peak memory 208660 kb
Host smart-9a1dc00c-6443-4962-8849-3e4201215bf9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976888226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.2976888226
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2670934985
Short name T238
Test name
Test status
Simulation time 1596515582 ps
CPU time 30.09 seconds
Started Dec 20 12:37:11 PM PST 23
Finished Dec 20 12:38:26 PM PST 23
Peak memory 209376 kb
Host smart-d4756ff4-d63b-47a8-b46d-3c6b9de166e8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670934985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.2670934985
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.168708407
Short name T272
Test name
Test status
Simulation time 153525761 ps
CPU time 1.32 seconds
Started Dec 20 12:37:20 PM PST 23
Finished Dec 20 12:38:22 PM PST 23
Peak memory 217784 kb
Host smart-1a4d1c69-35b4-437f-af17-faeccffaa024
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168708
407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.168708407
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2007820091
Short name T199
Test name
Test status
Simulation time 79948647 ps
CPU time 0.95 seconds
Started Dec 20 12:37:24 PM PST 23
Finished Dec 20 12:38:36 PM PST 23
Peak memory 209608 kb
Host smart-6c18d729-7e2f-4542-801d-0c0f8018483b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007820091 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.2007820091
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3635466825
Short name T190
Test name
Test status
Simulation time 19750283 ps
CPU time 1.25 seconds
Started Dec 20 12:36:44 PM PST 23
Finished Dec 20 12:37:10 PM PST 23
Peak memory 211540 kb
Host smart-ed26c807-00ae-46ba-89e4-51aeb8b8e339
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635466825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.3635466825
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.386487983
Short name T103
Test name
Test status
Simulation time 455410932 ps
CPU time 2.7 seconds
Started Dec 20 12:37:25 PM PST 23
Finished Dec 20 12:38:39 PM PST 23
Peak memory 217604 kb
Host smart-13d724ea-b38d-4e06-b63e-690ef3e127ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386487983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.386487983
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1552422760
Short name T179
Test name
Test status
Simulation time 63483147 ps
CPU time 1.24 seconds
Started Dec 20 12:37:28 PM PST 23
Finished Dec 20 12:38:40 PM PST 23
Peak memory 219276 kb
Host smart-b7bd2cca-bb9d-4242-9d79-07a5bb797530
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552422760 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.1552422760
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1131189874
Short name T296
Test name
Test status
Simulation time 18956153 ps
CPU time 0.99 seconds
Started Dec 20 12:37:05 PM PST 23
Finished Dec 20 12:37:47 PM PST 23
Peak memory 209544 kb
Host smart-2a86fdef-f830-4c48-8114-9564d452c80e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131189874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1131189874
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2031894175
Short name T204
Test name
Test status
Simulation time 76781369 ps
CPU time 1.18 seconds
Started Dec 20 12:36:47 PM PST 23
Finished Dec 20 12:37:17 PM PST 23
Peak memory 209620 kb
Host smart-8e0b11a8-147a-41f0-b6fa-b831f6cb4c24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031894175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.2031894175
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3341254080
Short name T142
Test name
Test status
Simulation time 594561392 ps
CPU time 3.76 seconds
Started Dec 20 12:36:36 PM PST 23
Finished Dec 20 12:36:49 PM PST 23
Peak memory 217716 kb
Host smart-aec734c4-ec5a-45b6-ba37-9ab31ee8f27d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341254080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.3341254080
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1589540995
Short name T164
Test name
Test status
Simulation time 64622400 ps
CPU time 2.09 seconds
Started Dec 20 12:36:32 PM PST 23
Finished Dec 20 12:36:39 PM PST 23
Peak memory 221948 kb
Host smart-ba0660a9-ec5b-4d11-a2c4-8e1320eb01aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589540995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.1589540995
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1965380517
Short name T297
Test name
Test status
Simulation time 13530352 ps
CPU time 1.02 seconds
Started Dec 20 12:36:48 PM PST 23
Finished Dec 20 12:37:20 PM PST 23
Peak memory 208988 kb
Host smart-ff158a22-7208-428a-aa12-b8d958fd49d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965380517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.1965380517
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2103204299
Short name T291
Test name
Test status
Simulation time 28280919 ps
CPU time 1.35 seconds
Started Dec 20 12:36:42 PM PST 23
Finished Dec 20 12:37:01 PM PST 23
Peak memory 209792 kb
Host smart-1ecb77f5-6278-4160-baaf-0b4220121cb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103204299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.2103204299
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2884511935
Short name T288
Test name
Test status
Simulation time 125760913 ps
CPU time 5.1 seconds
Started Dec 20 12:36:55 PM PST 23
Finished Dec 20 12:37:35 PM PST 23
Peak memory 217648 kb
Host smart-91c457bb-9b48-489d-a462-0302ed424abc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884511935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.2884511935
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3396234992
Short name T145
Test name
Test status
Simulation time 77196527 ps
CPU time 3.29 seconds
Started Dec 20 12:36:35 PM PST 23
Finished Dec 20 12:36:47 PM PST 23
Peak memory 222400 kb
Host smart-30c8c384-4143-4a6f-a20a-16b5943eebe9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396234992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.3396234992
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2709962560
Short name T176
Test name
Test status
Simulation time 73518496 ps
CPU time 0.89 seconds
Started Dec 20 12:36:42 PM PST 23
Finished Dec 20 12:37:02 PM PST 23
Peak memory 217728 kb
Host smart-b37fb2c7-b585-42f6-b225-6bdfc957929e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709962560 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.2709962560
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2323258761
Short name T316
Test name
Test status
Simulation time 45122456 ps
CPU time 0.87 seconds
Started Dec 20 12:37:10 PM PST 23
Finished Dec 20 12:37:55 PM PST 23
Peak memory 209172 kb
Host smart-3f06a25e-3103-4906-a677-e34151ef7197
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323258761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.2323258761
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.4220216623
Short name T262
Test name
Test status
Simulation time 45652350 ps
CPU time 1.32 seconds
Started Dec 20 12:36:53 PM PST 23
Finished Dec 20 12:37:30 PM PST 23
Peak memory 209552 kb
Host smart-a0f18217-f212-4e9c-8afa-ff67c77a4e02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220216623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.4220216623
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2350794746
Short name T226
Test name
Test status
Simulation time 60906056 ps
CPU time 1.84 seconds
Started Dec 20 12:37:06 PM PST 23
Finished Dec 20 12:37:50 PM PST 23
Peak memory 217612 kb
Host smart-77eab95b-774f-44c6-9df8-847724dfa6bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350794746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.2350794746
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.4220857021
Short name T318
Test name
Test status
Simulation time 78406014 ps
CPU time 3.2 seconds
Started Dec 20 12:37:05 PM PST 23
Finished Dec 20 12:37:48 PM PST 23
Peak memory 222068 kb
Host smart-9b684c91-b271-4bb5-b6a0-4040f267d0ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220857021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.4220857021
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3739922348
Short name T264
Test name
Test status
Simulation time 18534072 ps
CPU time 1.05 seconds
Started Dec 20 12:37:10 PM PST 23
Finished Dec 20 12:37:56 PM PST 23
Peak memory 220288 kb
Host smart-9f543437-1dcf-4f33-9a11-ba193b111bbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739922348 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.3739922348
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.484168578
Short name T195
Test name
Test status
Simulation time 17391764 ps
CPU time 1.03 seconds
Started Dec 20 12:37:21 PM PST 23
Finished Dec 20 12:38:26 PM PST 23
Peak memory 209484 kb
Host smart-ad302a68-5e57-4dbe-8f20-6c88ac9987e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484168578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.484168578
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2174754167
Short name T243
Test name
Test status
Simulation time 19584729 ps
CPU time 1.05 seconds
Started Dec 20 12:37:13 PM PST 23
Finished Dec 20 12:38:03 PM PST 23
Peak memory 209396 kb
Host smart-712fa545-e5f0-4a48-8014-d36d0433d425
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174754167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.2174754167
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1901586392
Short name T260
Test name
Test status
Simulation time 98346364 ps
CPU time 1.82 seconds
Started Dec 20 12:37:05 PM PST 23
Finished Dec 20 12:37:47 PM PST 23
Peak memory 217596 kb
Host smart-1fe76e04-070b-4e0e-aba3-602041815bec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901586392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.1901586392
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2002317050
Short name T228
Test name
Test status
Simulation time 18572913 ps
CPU time 1.28 seconds
Started Dec 20 12:37:02 PM PST 23
Finished Dec 20 12:37:42 PM PST 23
Peak memory 218884 kb
Host smart-f420e4d4-fbc0-4d82-ad96-03a22c1e69a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002317050 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.2002317050
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2528882699
Short name T248
Test name
Test status
Simulation time 29419329 ps
CPU time 1 seconds
Started Dec 20 12:36:59 PM PST 23
Finished Dec 20 12:37:38 PM PST 23
Peak memory 209604 kb
Host smart-7b433eb1-158e-4981-9bf5-54022566f443
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528882699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.2528882699
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1933305633
Short name T140
Test name
Test status
Simulation time 35118559 ps
CPU time 1.16 seconds
Started Dec 20 12:37:05 PM PST 23
Finished Dec 20 12:37:47 PM PST 23
Peak memory 211368 kb
Host smart-08208a2a-e1d2-48e3-940a-ac480e8ebfa1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933305633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.1933305633
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.280113294
Short name T143
Test name
Test status
Simulation time 21901213 ps
CPU time 1.55 seconds
Started Dec 20 12:37:09 PM PST 23
Finished Dec 20 12:37:53 PM PST 23
Peak memory 217768 kb
Host smart-c2525e06-8698-4afa-ba74-8da8b1b3507b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280113294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.280113294
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.203204358
Short name T233
Test name
Test status
Simulation time 14832134 ps
CPU time 0.94 seconds
Started Dec 20 12:37:10 PM PST 23
Finished Dec 20 12:37:56 PM PST 23
Peak memory 216848 kb
Host smart-ce922241-626a-4881-be8f-dc61adee21df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203204358 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.203204358
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.335370452
Short name T106
Test name
Test status
Simulation time 48158212 ps
CPU time 0.99 seconds
Started Dec 20 12:37:03 PM PST 23
Finished Dec 20 12:37:44 PM PST 23
Peak memory 209156 kb
Host smart-6f811375-078e-48d3-8167-1df457ef5aec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335370452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.335370452
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.348864968
Short name T311
Test name
Test status
Simulation time 23197672 ps
CPU time 1.26 seconds
Started Dec 20 12:37:24 PM PST 23
Finished Dec 20 12:38:33 PM PST 23
Peak memory 209620 kb
Host smart-c3b64ecd-b445-4a07-833f-1bee2a62f2f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348864968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_same_csr_outstanding.348864968
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.344277765
Short name T270
Test name
Test status
Simulation time 33349444 ps
CPU time 2.41 seconds
Started Dec 20 12:37:28 PM PST 23
Finished Dec 20 12:38:43 PM PST 23
Peak memory 217768 kb
Host smart-082c0ac4-10ab-4b2b-aa31-b1fc50ad5dcf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344277765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.344277765
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.229661953
Short name T292
Test name
Test status
Simulation time 18071744 ps
CPU time 1.02 seconds
Started Dec 20 12:37:37 PM PST 23
Finished Dec 20 12:38:55 PM PST 23
Peak memory 217708 kb
Host smart-9001281c-481f-48db-8713-4c237ce1ede1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229661953 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.229661953
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1574903721
Short name T200
Test name
Test status
Simulation time 14890471 ps
CPU time 1.01 seconds
Started Dec 20 12:37:35 PM PST 23
Finished Dec 20 12:38:49 PM PST 23
Peak memory 208904 kb
Host smart-a889b6e3-ea77-4af5-bd21-e0a19f89b60d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574903721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1574903721
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.9933755
Short name T217
Test name
Test status
Simulation time 37301638 ps
CPU time 1.69 seconds
Started Dec 20 12:37:14 PM PST 23
Finished Dec 20 12:38:06 PM PST 23
Peak memory 211440 kb
Host smart-3e166d1e-d2b0-4470-96a2-a9627c90bf44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9933755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_s
ame_csr_outstanding.9933755
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1759965220
Short name T232
Test name
Test status
Simulation time 103519940 ps
CPU time 2.18 seconds
Started Dec 20 12:36:39 PM PST 23
Finished Dec 20 12:36:53 PM PST 23
Peak memory 217752 kb
Host smart-eb519983-ae0c-4284-9a4a-4cb0204f2b3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759965220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.1759965220
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.626935805
Short name T246
Test name
Test status
Simulation time 78621585 ps
CPU time 1.12 seconds
Started Dec 20 12:37:12 PM PST 23
Finished Dec 20 12:38:00 PM PST 23
Peak memory 217960 kb
Host smart-5eb55ed4-384d-41d0-ad33-c901cb0eb028
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626935805 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.626935805
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2202756152
Short name T197
Test name
Test status
Simulation time 242073669 ps
CPU time 0.83 seconds
Started Dec 20 12:37:20 PM PST 23
Finished Dec 20 12:38:20 PM PST 23
Peak memory 209648 kb
Host smart-59c85aa6-3bc9-4974-b303-570eb8981179
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202756152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.2202756152
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1158070758
Short name T320
Test name
Test status
Simulation time 276936686 ps
CPU time 1.68 seconds
Started Dec 20 12:36:57 PM PST 23
Finished Dec 20 12:37:43 PM PST 23
Peak memory 209484 kb
Host smart-c1f969c5-1f44-43eb-b94f-a1fd17c94dd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158070758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.1158070758
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3937821708
Short name T137
Test name
Test status
Simulation time 49375451 ps
CPU time 1.47 seconds
Started Dec 20 12:37:01 PM PST 23
Finished Dec 20 12:37:42 PM PST 23
Peak memory 218076 kb
Host smart-682f4afb-0df9-4120-a248-59300787e174
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937821708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.3937821708
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.968750836
Short name T114
Test name
Test status
Simulation time 200392541 ps
CPU time 2.5 seconds
Started Dec 20 12:37:13 PM PST 23
Finished Dec 20 12:38:03 PM PST 23
Peak memory 222028 kb
Host smart-6cabb2c6-15ab-412e-b33a-444eddaef258
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968750836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg_
err.968750836
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3377207463
Short name T261
Test name
Test status
Simulation time 40950521 ps
CPU time 0.94 seconds
Started Dec 20 12:36:40 PM PST 23
Finished Dec 20 12:36:55 PM PST 23
Peak memory 217824 kb
Host smart-4e42a255-3bca-41a6-ac64-bcb266231c6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377207463 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.3377207463
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2896355729
Short name T299
Test name
Test status
Simulation time 18541738 ps
CPU time 0.88 seconds
Started Dec 20 12:37:37 PM PST 23
Finished Dec 20 12:38:51 PM PST 23
Peak memory 209620 kb
Host smart-7a9b072a-91a8-4ea0-8422-402d8a70c70e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896355729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.2896355729
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1709448239
Short name T155
Test name
Test status
Simulation time 21250532 ps
CPU time 1.7 seconds
Started Dec 20 12:37:43 PM PST 23
Finished Dec 20 12:39:00 PM PST 23
Peak memory 217692 kb
Host smart-cba614ed-9ba2-4e66-aa08-dd1a28c2e07c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709448239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.1709448239
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1802114692
Short name T161
Test name
Test status
Simulation time 159577017 ps
CPU time 2.4 seconds
Started Dec 20 12:37:18 PM PST 23
Finished Dec 20 12:38:17 PM PST 23
Peak memory 217816 kb
Host smart-42330d2f-4b43-43e2-bda6-3a5842eb0362
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802114692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.1802114692
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1196650024
Short name T230
Test name
Test status
Simulation time 32496059 ps
CPU time 1.77 seconds
Started Dec 20 12:37:17 PM PST 23
Finished Dec 20 12:38:14 PM PST 23
Peak memory 217912 kb
Host smart-50107ccd-b88f-4fef-a34e-006c6d13454d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196650024 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.1196650024
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1649654802
Short name T203
Test name
Test status
Simulation time 19008998 ps
CPU time 1.01 seconds
Started Dec 20 12:36:43 PM PST 23
Finished Dec 20 12:37:08 PM PST 23
Peak memory 217236 kb
Host smart-c680349f-6552-41f4-93d6-a74145371664
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649654802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.1649654802
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.4078723674
Short name T300
Test name
Test status
Simulation time 18749362 ps
CPU time 1.24 seconds
Started Dec 20 12:36:39 PM PST 23
Finished Dec 20 12:36:55 PM PST 23
Peak memory 209584 kb
Host smart-01f6fba7-db37-4caf-90fd-97ccfb2cb2be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078723674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.4078723674
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2360566572
Short name T314
Test name
Test status
Simulation time 69462629 ps
CPU time 2.91 seconds
Started Dec 20 12:37:49 PM PST 23
Finished Dec 20 12:39:05 PM PST 23
Peak memory 217792 kb
Host smart-b1bb43d0-8901-46e2-9901-c2c5deeae33f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360566572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2360566572
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3204664634
Short name T216
Test name
Test status
Simulation time 33140384 ps
CPU time 1.24 seconds
Started Dec 20 12:36:34 PM PST 23
Finished Dec 20 12:36:43 PM PST 23
Peak memory 208860 kb
Host smart-e0a26d6d-4204-4480-ba29-3616c6e0eda7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204664634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.3204664634
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.254546105
Short name T307
Test name
Test status
Simulation time 28175097 ps
CPU time 1.49 seconds
Started Dec 20 12:36:32 PM PST 23
Finished Dec 20 12:36:39 PM PST 23
Peak memory 209768 kb
Host smart-c468a8f9-b68a-4bdd-ae43-cc90ff787e7a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254546105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bash
.254546105
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1633297705
Short name T184
Test name
Test status
Simulation time 39240262 ps
CPU time 1.3 seconds
Started Dec 20 12:36:28 PM PST 23
Finished Dec 20 12:36:33 PM PST 23
Peak memory 211356 kb
Host smart-fdc042ae-9071-4eff-bea2-2bc763d547b6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633297705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.1633297705
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2602140740
Short name T186
Test name
Test status
Simulation time 51302475 ps
CPU time 1.41 seconds
Started Dec 20 12:37:19 PM PST 23
Finished Dec 20 12:38:21 PM PST 23
Peak memory 219840 kb
Host smart-6dc4868b-108f-4b81-a7ed-fbf188bf1842
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602140740 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.2602140740
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1398136128
Short name T165
Test name
Test status
Simulation time 13610603 ps
CPU time 0.94 seconds
Started Dec 20 12:36:43 PM PST 23
Finished Dec 20 12:37:06 PM PST 23
Peak memory 209600 kb
Host smart-97a2aac6-1cef-43c1-96f8-e51f45443b58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398136128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.1398136128
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.4085528022
Short name T290
Test name
Test status
Simulation time 166236081 ps
CPU time 1.07 seconds
Started Dec 20 12:36:28 PM PST 23
Finished Dec 20 12:36:34 PM PST 23
Peak memory 209416 kb
Host smart-3172839c-b10e-418c-86c1-2d4a6e4d0319
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085528022 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.4085528022
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.611003924
Short name T174
Test name
Test status
Simulation time 644507554 ps
CPU time 4.48 seconds
Started Dec 20 12:36:50 PM PST 23
Finished Dec 20 12:37:27 PM PST 23
Peak memory 209556 kb
Host smart-472bd851-523d-4f11-b918-e7fd281da7d7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611003924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.611003924
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3137851589
Short name T175
Test name
Test status
Simulation time 343160382 ps
CPU time 8.86 seconds
Started Dec 20 12:37:08 PM PST 23
Finished Dec 20 12:38:00 PM PST 23
Peak memory 209544 kb
Host smart-8691b43a-8bbc-4eca-9f81-c1a103e54f6b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137851589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.3137851589
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2279937038
Short name T115
Test name
Test status
Simulation time 178189107 ps
CPU time 1.31 seconds
Started Dec 20 12:37:09 PM PST 23
Finished Dec 20 12:37:53 PM PST 23
Peak memory 210712 kb
Host smart-8373f95a-d57a-4333-a016-9aa36285965b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279937038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.2279937038
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3206607647
Short name T258
Test name
Test status
Simulation time 42353998 ps
CPU time 1.11 seconds
Started Dec 20 12:36:37 PM PST 23
Finished Dec 20 12:36:50 PM PST 23
Peak memory 209592 kb
Host smart-e3114960-82a0-4ac5-89c5-5b041d45a985
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320660
7647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3206607647
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1252943954
Short name T309
Test name
Test status
Simulation time 86207146 ps
CPU time 1.27 seconds
Started Dec 20 12:36:44 PM PST 23
Finished Dec 20 12:37:08 PM PST 23
Peak memory 209556 kb
Host smart-084cebd1-5888-4647-98fe-af399c15faec
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252943954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.1252943954
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3890661035
Short name T253
Test name
Test status
Simulation time 122317326 ps
CPU time 1.01 seconds
Started Dec 20 12:36:42 PM PST 23
Finished Dec 20 12:37:02 PM PST 23
Peak memory 209572 kb
Host smart-084e7a30-d514-4275-b32a-3c258e90419a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890661035 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.3890661035
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1808329370
Short name T315
Test name
Test status
Simulation time 66365280 ps
CPU time 0.95 seconds
Started Dec 20 12:36:47 PM PST 23
Finished Dec 20 12:37:17 PM PST 23
Peak memory 209548 kb
Host smart-a2e8e649-42db-48f3-97c0-95cd0ad388c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808329370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.1808329370
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1497038338
Short name T298
Test name
Test status
Simulation time 31795070 ps
CPU time 2.47 seconds
Started Dec 20 12:36:26 PM PST 23
Finished Dec 20 12:36:29 PM PST 23
Peak memory 217760 kb
Host smart-b681a2af-6569-43d5-816d-97efcd4b96e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497038338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.1497038338
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3696237785
Short name T192
Test name
Test status
Simulation time 38590483 ps
CPU time 1 seconds
Started Dec 20 12:37:27 PM PST 23
Finished Dec 20 12:38:41 PM PST 23
Peak memory 209520 kb
Host smart-c9143305-889e-47c7-9456-e1a37db33bc2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696237785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.3696237785
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2415934835
Short name T205
Test name
Test status
Simulation time 81564421 ps
CPU time 1.71 seconds
Started Dec 20 12:37:24 PM PST 23
Finished Dec 20 12:38:33 PM PST 23
Peak memory 209732 kb
Host smart-6d0ff8a0-7874-4656-bf3d-6d953f0b6e4e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415934835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.2415934835
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1122320057
Short name T294
Test name
Test status
Simulation time 31829355 ps
CPU time 0.79 seconds
Started Dec 20 12:37:23 PM PST 23
Finished Dec 20 12:38:29 PM PST 23
Peak memory 209340 kb
Host smart-e8f97dd0-e702-4600-8b02-808ad8260c0c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122320057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.1122320057
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.36831813
Short name T308
Test name
Test status
Simulation time 55952813 ps
CPU time 1.23 seconds
Started Dec 20 12:37:26 PM PST 23
Finished Dec 20 12:38:39 PM PST 23
Peak memory 219524 kb
Host smart-19528a53-f4f4-4838-800d-6a695ec2d738
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36831813 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.36831813
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2619910852
Short name T196
Test name
Test status
Simulation time 57950733 ps
CPU time 1 seconds
Started Dec 20 12:36:58 PM PST 23
Finished Dec 20 12:37:36 PM PST 23
Peak memory 209612 kb
Host smart-22f5e8fc-3eb1-4f87-a589-a79d4161ed2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619910852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2619910852
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3664065657
Short name T281
Test name
Test status
Simulation time 133065686 ps
CPU time 0.99 seconds
Started Dec 20 12:37:08 PM PST 23
Finished Dec 20 12:37:51 PM PST 23
Peak memory 209484 kb
Host smart-0c5b01e2-e19b-4310-bf7f-4d09f5b76887
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664065657 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.3664065657
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3507369237
Short name T219
Test name
Test status
Simulation time 361715706 ps
CPU time 3.96 seconds
Started Dec 20 12:37:11 PM PST 23
Finished Dec 20 12:38:01 PM PST 23
Peak memory 209540 kb
Host smart-95113959-9ab7-4596-a297-97d29692ac16
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507369237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.3507369237
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.857667256
Short name T278
Test name
Test status
Simulation time 2004315074 ps
CPU time 41 seconds
Started Dec 20 12:36:49 PM PST 23
Finished Dec 20 12:38:01 PM PST 23
Peak memory 209528 kb
Host smart-2ea0daa0-fce1-47dd-8580-cafb0bafd2f7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857667256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.857667256
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.207277077
Short name T280
Test name
Test status
Simulation time 328879909 ps
CPU time 1.97 seconds
Started Dec 20 12:37:16 PM PST 23
Finished Dec 20 12:38:11 PM PST 23
Peak memory 210964 kb
Host smart-7f886307-811f-4976-a9de-bd357b638a65
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207277077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.207277077
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.4273149569
Short name T304
Test name
Test status
Simulation time 701470936 ps
CPU time 3.83 seconds
Started Dec 20 12:37:25 PM PST 23
Finished Dec 20 12:38:40 PM PST 23
Peak memory 209392 kb
Host smart-ee994bdf-f4a4-4951-929f-3c50ec051dd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273149569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.4273149569
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1423407747
Short name T245
Test name
Test status
Simulation time 17627866 ps
CPU time 1.01 seconds
Started Dec 20 12:36:43 PM PST 23
Finished Dec 20 12:37:06 PM PST 23
Peak memory 209644 kb
Host smart-45b9ad3f-723b-4874-b600-2d90c18cf363
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423407747 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.1423407747
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.271258132
Short name T181
Test name
Test status
Simulation time 28666068 ps
CPU time 1.36 seconds
Started Dec 20 12:36:50 PM PST 23
Finished Dec 20 12:37:22 PM PST 23
Peak memory 209524 kb
Host smart-eab7a5f1-11fd-4491-aee3-d0e06213d27c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271258132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.271258132
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1378719632
Short name T303
Test name
Test status
Simulation time 52383427 ps
CPU time 3.2 seconds
Started Dec 20 12:37:08 PM PST 23
Finished Dec 20 12:38:05 PM PST 23
Peak memory 221816 kb
Host smart-e81fdbb4-80ce-4b83-a58d-f97ecb320601
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378719632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.1378719632
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2010222210
Short name T198
Test name
Test status
Simulation time 165915495 ps
CPU time 1.69 seconds
Started Dec 20 12:37:19 PM PST 23
Finished Dec 20 12:38:19 PM PST 23
Peak memory 209592 kb
Host smart-d10cb84b-6587-4565-97ea-282a19966057
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010222210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.2010222210
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3820776379
Short name T268
Test name
Test status
Simulation time 26037182 ps
CPU time 1.45 seconds
Started Dec 20 12:37:23 PM PST 23
Finished Dec 20 12:38:30 PM PST 23
Peak memory 209836 kb
Host smart-72227187-fdfd-4809-8087-42f08125d057
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820776379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.3820776379
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1878436437
Short name T194
Test name
Test status
Simulation time 40016181 ps
CPU time 0.98 seconds
Started Dec 20 12:37:20 PM PST 23
Finished Dec 20 12:38:22 PM PST 23
Peak memory 210044 kb
Host smart-a100ca4d-8020-4d5b-87f7-f3de14d69e12
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878436437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.1878436437
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1752764929
Short name T271
Test name
Test status
Simulation time 15501989 ps
CPU time 1.05 seconds
Started Dec 20 12:37:16 PM PST 23
Finished Dec 20 12:38:09 PM PST 23
Peak memory 217840 kb
Host smart-5ac25914-8fb1-439e-96b4-9ac2037e6cdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752764929 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.1752764929
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3175782652
Short name T218
Test name
Test status
Simulation time 13488655 ps
CPU time 0.97 seconds
Started Dec 20 12:37:15 PM PST 23
Finished Dec 20 12:38:10 PM PST 23
Peak memory 209464 kb
Host smart-4ccf070d-fdfc-4e95-8ef5-9c011304266c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175782652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3175782652
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1521741971
Short name T289
Test name
Test status
Simulation time 100706135 ps
CPU time 2.78 seconds
Started Dec 20 12:37:02 PM PST 23
Finished Dec 20 12:37:43 PM PST 23
Peak memory 209532 kb
Host smart-eebc64fe-4d1c-4442-9f19-f5ae79d345b5
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521741971 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.1521741971
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2575395271
Short name T256
Test name
Test status
Simulation time 1017123617 ps
CPU time 3.07 seconds
Started Dec 20 12:37:34 PM PST 23
Finished Dec 20 12:38:52 PM PST 23
Peak memory 209572 kb
Host smart-5578fa8a-cf14-45d4-9f24-37dec0e03131
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575395271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.2575395271
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3021156257
Short name T234
Test name
Test status
Simulation time 8833322280 ps
CPU time 10.75 seconds
Started Dec 20 12:37:20 PM PST 23
Finished Dec 20 12:38:33 PM PST 23
Peak memory 209396 kb
Host smart-35b1c514-47c2-47dd-9b3f-4972d18238e0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021156257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3021156257
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3200431850
Short name T168
Test name
Test status
Simulation time 493480925 ps
CPU time 2.12 seconds
Started Dec 20 12:37:18 PM PST 23
Finished Dec 20 12:38:16 PM PST 23
Peak memory 210756 kb
Host smart-9968afe1-2d65-41f0-8d90-b03c1cc77e41
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200431850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.3200431850
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2679078476
Short name T229
Test name
Test status
Simulation time 28888685 ps
CPU time 1.09 seconds
Started Dec 20 12:36:44 PM PST 23
Finished Dec 20 12:37:08 PM PST 23
Peak memory 218064 kb
Host smart-c54cf225-19c0-426d-ac53-a7d49bd34c2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267907
8476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2679078476
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1700593638
Short name T178
Test name
Test status
Simulation time 65111990 ps
CPU time 1.17 seconds
Started Dec 20 12:37:25 PM PST 23
Finished Dec 20 12:38:37 PM PST 23
Peak memory 208172 kb
Host smart-d4af2a2e-8efc-4b54-83a2-5cab385e0dcf
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700593638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1700593638
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.916725981
Short name T301
Test name
Test status
Simulation time 79993656 ps
CPU time 1.75 seconds
Started Dec 20 12:37:13 PM PST 23
Finished Dec 20 12:38:02 PM PST 23
Peak memory 211264 kb
Host smart-67bc61ff-41bf-46e9-b33c-15a5b351036b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916725981 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.916725981
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1316532483
Short name T173
Test name
Test status
Simulation time 112000296 ps
CPU time 1.27 seconds
Started Dec 20 12:36:50 PM PST 23
Finished Dec 20 12:37:23 PM PST 23
Peak memory 209628 kb
Host smart-d8f9a16d-af0d-405c-b878-c89c45c6f670
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316532483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1316532483
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.569484090
Short name T285
Test name
Test status
Simulation time 131056874 ps
CPU time 1.86 seconds
Started Dec 20 12:36:59 PM PST 23
Finished Dec 20 12:37:38 PM PST 23
Peak memory 217780 kb
Host smart-d01887c8-0a97-4dd7-8218-98408e561cc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569484090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.569484090
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.118704919
Short name T153
Test name
Test status
Simulation time 103839239 ps
CPU time 3.79 seconds
Started Dec 20 12:37:26 PM PST 23
Finished Dec 20 12:38:42 PM PST 23
Peak memory 217872 kb
Host smart-1898e676-f95c-4bd8-8cb9-eeb78f73fb44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118704919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_e
rr.118704919
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.860569735
Short name T263
Test name
Test status
Simulation time 219332932 ps
CPU time 0.98 seconds
Started Dec 20 12:36:44 PM PST 23
Finished Dec 20 12:37:08 PM PST 23
Peak memory 217824 kb
Host smart-34ae1e84-674f-40e0-9e13-127ab51fbfe7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860569735 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.860569735
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3887231903
Short name T282
Test name
Test status
Simulation time 26218817 ps
CPU time 0.98 seconds
Started Dec 20 12:36:58 PM PST 23
Finished Dec 20 12:37:37 PM PST 23
Peak memory 209044 kb
Host smart-6e474195-a7b8-445b-bd54-fe21892c2e6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887231903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.3887231903
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.326172349
Short name T167
Test name
Test status
Simulation time 638691741 ps
CPU time 1.93 seconds
Started Dec 20 12:36:36 PM PST 23
Finished Dec 20 12:36:49 PM PST 23
Peak memory 209480 kb
Host smart-09deda73-a901-449e-8485-bc22d525a00e
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326172349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.lc_ctrl_jtag_alert_test.326172349
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2215027603
Short name T293
Test name
Test status
Simulation time 636818264 ps
CPU time 5.59 seconds
Started Dec 20 12:37:36 PM PST 23
Finished Dec 20 12:38:57 PM PST 23
Peak memory 209404 kb
Host smart-f7e75f1d-5213-4602-b98e-75f96c996ebe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215027603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.2215027603
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2969654012
Short name T223
Test name
Test status
Simulation time 1584058362 ps
CPU time 9 seconds
Started Dec 20 12:37:15 PM PST 23
Finished Dec 20 12:38:14 PM PST 23
Peak memory 209308 kb
Host smart-c2eeaae8-1080-4da7-9815-fb477179663a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969654012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.2969654012
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.180165046
Short name T249
Test name
Test status
Simulation time 253258302 ps
CPU time 2.42 seconds
Started Dec 20 12:36:55 PM PST 23
Finished Dec 20 12:37:33 PM PST 23
Peak memory 210884 kb
Host smart-bdce401d-8b7c-4bf5-b596-9dcda5eef509
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180165046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.180165046
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1308307189
Short name T277
Test name
Test status
Simulation time 216153777 ps
CPU time 1.83 seconds
Started Dec 20 12:37:21 PM PST 23
Finished Dec 20 12:38:27 PM PST 23
Peak memory 218712 kb
Host smart-84fb58a9-39e3-4d06-a586-345a0bf2dd7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130830
7189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1308307189
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3862620822
Short name T170
Test name
Test status
Simulation time 41469411 ps
CPU time 1.04 seconds
Started Dec 20 12:36:32 PM PST 23
Finished Dec 20 12:36:37 PM PST 23
Peak memory 209524 kb
Host smart-ad4571e5-f13e-4f42-a87f-b18df9769bc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862620822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.3862620822
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.178595423
Short name T188
Test name
Test status
Simulation time 85899611 ps
CPU time 1.41 seconds
Started Dec 20 12:37:11 PM PST 23
Finished Dec 20 12:37:58 PM PST 23
Peak memory 209732 kb
Host smart-c8ad67a5-192b-4d57-a6e9-c4e24075c386
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178595423 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.178595423
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.4185636155
Short name T247
Test name
Test status
Simulation time 31121959 ps
CPU time 1.19 seconds
Started Dec 20 12:36:30 PM PST 23
Finished Dec 20 12:36:36 PM PST 23
Peak memory 209784 kb
Host smart-1aa7159e-2370-4f8c-999a-38a1fbcb20cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185636155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.4185636155
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3031721264
Short name T255
Test name
Test status
Simulation time 96530673 ps
CPU time 3.71 seconds
Started Dec 20 12:36:36 PM PST 23
Finished Dec 20 12:36:49 PM PST 23
Peak memory 217664 kb
Host smart-e245a2b9-a3f7-4950-8c45-96fc66e85e23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031721264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.3031721264
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1378482356
Short name T225
Test name
Test status
Simulation time 93477144 ps
CPU time 1.76 seconds
Started Dec 20 12:36:59 PM PST 23
Finished Dec 20 12:37:38 PM PST 23
Peak memory 219496 kb
Host smart-d1fc96bb-785f-4106-83bb-d7ce3e6dd903
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378482356 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.1378482356
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.2449089372
Short name T201
Test name
Test status
Simulation time 27508551 ps
CPU time 0.98 seconds
Started Dec 20 12:36:38 PM PST 23
Finished Dec 20 12:36:52 PM PST 23
Peak memory 209172 kb
Host smart-142f9bff-3fbb-44c2-b705-6ad3705d88b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449089372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.2449089372
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1944526166
Short name T231
Test name
Test status
Simulation time 241881941 ps
CPU time 1.97 seconds
Started Dec 20 12:36:44 PM PST 23
Finished Dec 20 12:37:09 PM PST 23
Peak memory 207968 kb
Host smart-2e45fcf9-b801-4113-bef4-992c86248fb8
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944526166 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.1944526166
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3273465078
Short name T266
Test name
Test status
Simulation time 988707675 ps
CPU time 22.36 seconds
Started Dec 20 12:36:43 PM PST 23
Finished Dec 20 12:37:28 PM PST 23
Peak memory 209460 kb
Host smart-ad1578d9-1ec2-496e-a654-5c13ec2c2612
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273465078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.3273465078
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2830348529
Short name T215
Test name
Test status
Simulation time 603801050 ps
CPU time 6.37 seconds
Started Dec 20 12:37:08 PM PST 23
Finished Dec 20 12:37:57 PM PST 23
Peak memory 208500 kb
Host smart-89ae976e-8b04-44bc-8331-d090cbb5b472
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830348529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.2830348529
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1967039011
Short name T177
Test name
Test status
Simulation time 80286583 ps
CPU time 1.52 seconds
Started Dec 20 12:36:32 PM PST 23
Finished Dec 20 12:36:38 PM PST 23
Peak memory 211000 kb
Host smart-6fb4316c-8845-46b2-9136-fab0113b8999
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967039011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.1967039011
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2033768092
Short name T105
Test name
Test status
Simulation time 33206615 ps
CPU time 1.07 seconds
Started Dec 20 12:36:43 PM PST 23
Finished Dec 20 12:37:08 PM PST 23
Peak memory 217944 kb
Host smart-67631578-5358-4d71-a56a-8619eeb52929
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203376
8092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2033768092
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3224717459
Short name T224
Test name
Test status
Simulation time 176121043 ps
CPU time 1.1 seconds
Started Dec 20 12:36:32 PM PST 23
Finished Dec 20 12:36:38 PM PST 23
Peak memory 209464 kb
Host smart-d838ae55-0689-4bab-aabd-755e64d477a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224717459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.3224717459
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.4186664572
Short name T166
Test name
Test status
Simulation time 103503713 ps
CPU time 0.99 seconds
Started Dec 20 12:36:41 PM PST 23
Finished Dec 20 12:36:58 PM PST 23
Peak memory 209612 kb
Host smart-d43a4941-e920-4518-b08b-60b9f303bb22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186664572 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.4186664572
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3670117354
Short name T244
Test name
Test status
Simulation time 51562228 ps
CPU time 1.05 seconds
Started Dec 20 12:36:42 PM PST 23
Finished Dec 20 12:37:00 PM PST 23
Peak memory 209540 kb
Host smart-5d69ceb0-6081-4051-9cf8-f38762b06d16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670117354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.3670117354
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1888054670
Short name T149
Test name
Test status
Simulation time 297594224 ps
CPU time 5.14 seconds
Started Dec 20 12:36:48 PM PST 23
Finished Dec 20 12:37:23 PM PST 23
Peak memory 217664 kb
Host smart-0722c398-fcfa-4e4e-8764-5c46a5705bc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888054670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.1888054670
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3430234935
Short name T239
Test name
Test status
Simulation time 58296939 ps
CPU time 1.65 seconds
Started Dec 20 12:37:26 PM PST 23
Finished Dec 20 12:38:40 PM PST 23
Peak memory 219660 kb
Host smart-1ca26a26-94e0-4615-9352-f7ea40800130
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430234935 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.3430234935
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3575674008
Short name T265
Test name
Test status
Simulation time 137168879 ps
CPU time 0.86 seconds
Started Dec 20 12:36:55 PM PST 23
Finished Dec 20 12:37:31 PM PST 23
Peak memory 209436 kb
Host smart-d4227e6d-22d8-45f3-baf4-8d76d7ebfbce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575674008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.3575674008
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.58032777
Short name T171
Test name
Test status
Simulation time 126508465 ps
CPU time 1.46 seconds
Started Dec 20 12:37:18 PM PST 23
Finished Dec 20 12:38:18 PM PST 23
Peak memory 209580 kb
Host smart-c7fea09b-6e94-46ec-8474-df3a2c66bfde
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58032777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_alert_test.58032777
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.606909111
Short name T279
Test name
Test status
Simulation time 1767600496 ps
CPU time 3.54 seconds
Started Dec 20 12:37:15 PM PST 23
Finished Dec 20 12:38:13 PM PST 23
Peak memory 209436 kb
Host smart-bf1ab8b4-0bf4-45b3-98ad-c3c5ca63e362
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606909111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.606909111
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2179746473
Short name T240
Test name
Test status
Simulation time 477252366 ps
CPU time 11.46 seconds
Started Dec 20 12:37:17 PM PST 23
Finished Dec 20 12:38:23 PM PST 23
Peak memory 209552 kb
Host smart-2513fdd0-88f1-4480-81aa-c786eb40aa7e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179746473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.2179746473
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2877444920
Short name T275
Test name
Test status
Simulation time 341021173 ps
CPU time 1.54 seconds
Started Dec 20 12:37:38 PM PST 23
Finished Dec 20 12:38:55 PM PST 23
Peak memory 210652 kb
Host smart-55c2d612-f84a-4f3e-9134-45c1e948b5bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877444920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.2877444920
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1369746817
Short name T222
Test name
Test status
Simulation time 55788776 ps
CPU time 1.11 seconds
Started Dec 20 12:37:07 PM PST 23
Finished Dec 20 12:37:48 PM PST 23
Peak memory 218264 kb
Host smart-5fe5ad81-59d4-494d-994f-b1c33ea6608d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136974
6817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1369746817
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1530053544
Short name T227
Test name
Test status
Simulation time 267672795 ps
CPU time 0.97 seconds
Started Dec 20 12:36:53 PM PST 23
Finished Dec 20 12:37:28 PM PST 23
Peak memory 209500 kb
Host smart-51c632b1-9403-4790-b147-279d51183e95
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530053544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.1530053544
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1480103995
Short name T250
Test name
Test status
Simulation time 25838354 ps
CPU time 0.94 seconds
Started Dec 20 12:36:59 PM PST 23
Finished Dec 20 12:37:38 PM PST 23
Peak memory 209672 kb
Host smart-3cfd2e41-533a-4d17-a96e-1c241f87c24b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480103995 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1480103995
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.110233078
Short name T237
Test name
Test status
Simulation time 339340572 ps
CPU time 1.16 seconds
Started Dec 20 12:37:03 PM PST 23
Finished Dec 20 12:37:43 PM PST 23
Peak memory 211340 kb
Host smart-5ceb0079-96bd-4e33-8af6-55144955c4f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110233078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
same_csr_outstanding.110233078
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3281935582
Short name T254
Test name
Test status
Simulation time 73971711 ps
CPU time 2.25 seconds
Started Dec 20 12:37:05 PM PST 23
Finished Dec 20 12:37:46 PM PST 23
Peak memory 217704 kb
Host smart-e23790b0-cde3-4834-8c32-8b18fe885836
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281935582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3281935582
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.4210681359
Short name T180
Test name
Test status
Simulation time 62394734 ps
CPU time 1.26 seconds
Started Dec 20 12:37:31 PM PST 23
Finished Dec 20 12:38:46 PM PST 23
Peak memory 217780 kb
Host smart-05f05216-8a0e-4c16-93b8-03a6e46e16d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210681359 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.4210681359
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1387267612
Short name T302
Test name
Test status
Simulation time 58937743 ps
CPU time 1.03 seconds
Started Dec 20 12:37:04 PM PST 23
Finished Dec 20 12:37:59 PM PST 23
Peak memory 209680 kb
Host smart-fe2cd3b3-e043-4952-9aa6-14415a14ca9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387267612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.1387267612
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2985765991
Short name T221
Test name
Test status
Simulation time 122258936 ps
CPU time 0.91 seconds
Started Dec 20 12:37:15 PM PST 23
Finished Dec 20 12:38:10 PM PST 23
Peak memory 209068 kb
Host smart-d6ae160b-798f-4a57-9b33-8c922e73669d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985765991 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.2985765991
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1020251255
Short name T274
Test name
Test status
Simulation time 506863723 ps
CPU time 4.75 seconds
Started Dec 20 12:37:10 PM PST 23
Finished Dec 20 12:37:59 PM PST 23
Peak memory 209532 kb
Host smart-9392bc1d-03ba-4289-afdb-dbf7c264b2e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020251255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.1020251255
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1825851496
Short name T310
Test name
Test status
Simulation time 1610558806 ps
CPU time 20.01 seconds
Started Dec 20 12:37:05 PM PST 23
Finished Dec 20 12:38:05 PM PST 23
Peak memory 209540 kb
Host smart-573faeec-1a13-4347-aeb1-6631ba9faeee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825851496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.1825851496
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.455319869
Short name T241
Test name
Test status
Simulation time 46257968 ps
CPU time 1.21 seconds
Started Dec 20 12:37:27 PM PST 23
Finished Dec 20 12:38:48 PM PST 23
Peak memory 210736 kb
Host smart-aea25fca-bccb-4f0a-aa1b-859543639aa3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455319869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.455319869
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2813247542
Short name T252
Test name
Test status
Simulation time 58178498 ps
CPU time 1.41 seconds
Started Dec 20 12:37:09 PM PST 23
Finished Dec 20 12:37:53 PM PST 23
Peak memory 217980 kb
Host smart-56f89820-7a8a-498b-8b7f-10d2a49ce2ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281324
7542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2813247542
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3304479456
Short name T169
Test name
Test status
Simulation time 34472028 ps
CPU time 1.44 seconds
Started Dec 20 12:37:00 PM PST 23
Finished Dec 20 12:37:39 PM PST 23
Peak memory 208508 kb
Host smart-b7ce49fb-53dd-45d4-b0cc-42a20cfb88e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304479456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.3304479456
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3058079618
Short name T295
Test name
Test status
Simulation time 21415975 ps
CPU time 1.18 seconds
Started Dec 20 12:37:25 PM PST 23
Finished Dec 20 12:38:35 PM PST 23
Peak memory 209212 kb
Host smart-aa0a083d-2b41-4864-8924-5e0e5bcae557
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058079618 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.3058079618
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1773777761
Short name T305
Test name
Test status
Simulation time 101173393 ps
CPU time 0.91 seconds
Started Dec 20 12:37:15 PM PST 23
Finished Dec 20 12:38:10 PM PST 23
Peak memory 209456 kb
Host smart-2ecdf2ab-1e83-40eb-bf3c-e353cff4774e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773777761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.1773777761
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3339310371
Short name T284
Test name
Test status
Simulation time 77697504 ps
CPU time 1.12 seconds
Started Dec 20 12:36:36 PM PST 23
Finished Dec 20 12:36:49 PM PST 23
Peak memory 217896 kb
Host smart-f83119e3-5bc1-49cf-873c-8ebc71e68145
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339310371 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.3339310371
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3205330710
Short name T189
Test name
Test status
Simulation time 15544549 ps
CPU time 0.86 seconds
Started Dec 20 12:36:33 PM PST 23
Finished Dec 20 12:36:39 PM PST 23
Peak memory 208796 kb
Host smart-efdbb3d5-8d2e-4dc8-b6c5-d3d913614d24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205330710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3205330710
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.538403476
Short name T286
Test name
Test status
Simulation time 97344614 ps
CPU time 1.11 seconds
Started Dec 20 12:36:51 PM PST 23
Finished Dec 20 12:37:24 PM PST 23
Peak memory 207900 kb
Host smart-0ba0feae-e3f2-4592-8b8c-1149c939d63d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538403476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.lc_ctrl_jtag_alert_test.538403476
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.524995048
Short name T312
Test name
Test status
Simulation time 641632487 ps
CPU time 6.36 seconds
Started Dec 20 12:37:19 PM PST 23
Finished Dec 20 12:38:26 PM PST 23
Peak memory 209348 kb
Host smart-e9d18f09-6fbf-4fe0-9dbe-b6cc6bcd5a28
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524995048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.524995048
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.761925707
Short name T283
Test name
Test status
Simulation time 476815107 ps
CPU time 4.73 seconds
Started Dec 20 12:37:17 PM PST 23
Finished Dec 20 12:38:18 PM PST 23
Peak memory 209564 kb
Host smart-e1aa1cf0-a903-45b5-8a70-e6edce9cf9c5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761925707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.761925707
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3630623513
Short name T242
Test name
Test status
Simulation time 73445639 ps
CPU time 1.45 seconds
Started Dec 20 12:37:28 PM PST 23
Finished Dec 20 12:38:41 PM PST 23
Peak memory 218348 kb
Host smart-a53e9ad6-6477-4a65-b93d-c8da91e47d67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363062
3513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3630623513
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3786571715
Short name T257
Test name
Test status
Simulation time 59908365 ps
CPU time 1.14 seconds
Started Dec 20 12:37:26 PM PST 23
Finished Dec 20 12:38:36 PM PST 23
Peak memory 209444 kb
Host smart-a282cffc-e344-40e4-896f-eb93e9e9be44
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786571715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.3786571715
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1797939843
Short name T236
Test name
Test status
Simulation time 68271429 ps
CPU time 0.87 seconds
Started Dec 20 12:37:13 PM PST 23
Finished Dec 20 12:38:01 PM PST 23
Peak memory 209680 kb
Host smart-f4a980f7-f831-41aa-ae39-2198a8b4ace3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797939843 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.1797939843
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.4041726342
Short name T187
Test name
Test status
Simulation time 25632917 ps
CPU time 1.32 seconds
Started Dec 20 12:36:31 PM PST 23
Finished Dec 20 12:36:37 PM PST 23
Peak memory 209688 kb
Host smart-aa37826c-9524-4510-8cfd-840fe62a2ce9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041726342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.4041726342
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3462961156
Short name T306
Test name
Test status
Simulation time 92429854 ps
CPU time 3.2 seconds
Started Dec 20 12:36:35 PM PST 23
Finished Dec 20 12:36:47 PM PST 23
Peak memory 218804 kb
Host smart-6f3d4468-43df-41a5-bee4-a9ba25787272
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462961156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.3462961156
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.3382293537
Short name T550
Test name
Test status
Simulation time 55560117 ps
CPU time 0.92 seconds
Started Dec 20 12:55:12 PM PST 23
Finished Dec 20 12:55:31 PM PST 23
Peak memory 208532 kb
Host smart-08c9a9cc-7de1-4272-880e-79bcf3f4cdfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382293537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.3382293537
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.1342228457
Short name T419
Test name
Test status
Simulation time 1116400037 ps
CPU time 13.51 seconds
Started Dec 20 12:55:04 PM PST 23
Finished Dec 20 12:55:40 PM PST 23
Peak memory 218224 kb
Host smart-67ba63d3-2d5c-444f-bd6b-6856e0f6599a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342228457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1342228457
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.2345267435
Short name T756
Test name
Test status
Simulation time 39587064 ps
CPU time 1.62 seconds
Started Dec 20 12:54:52 PM PST 23
Finished Dec 20 12:55:12 PM PST 23
Peak memory 209608 kb
Host smart-9806cc4c-ced2-4f06-a5b6-86e03327e7fb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345267435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_ac
cess.2345267435
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.140680946
Short name T792
Test name
Test status
Simulation time 4376572671 ps
CPU time 58.33 seconds
Started Dec 20 12:55:25 PM PST 23
Finished Dec 20 12:56:37 PM PST 23
Peak memory 218524 kb
Host smart-e337d686-3493-439c-973f-5fbb2072c0c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140680946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_err
ors.140680946
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.3901206028
Short name T6
Test name
Test status
Simulation time 622980848 ps
CPU time 6.47 seconds
Started Dec 20 12:55:24 PM PST 23
Finished Dec 20 12:55:45 PM PST 23
Peak memory 209836 kb
Host smart-bfa8f510-4723-4431-b86f-8d0137915ede
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901206028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
priority.3901206028
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.3265334263
Short name T739
Test name
Test status
Simulation time 189570270 ps
CPU time 5.91 seconds
Started Dec 20 12:55:28 PM PST 23
Finished Dec 20 12:55:48 PM PST 23
Peak memory 218180 kb
Host smart-0ca719d8-2302-40e6-8c1e-979dc7309bce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265334263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.3265334263
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1497274352
Short name T97
Test name
Test status
Simulation time 4630935140 ps
CPU time 21.64 seconds
Started Dec 20 12:55:16 PM PST 23
Finished Dec 20 12:55:55 PM PST 23
Peak memory 213868 kb
Host smart-b2807706-991c-4959-b09f-a9aa06ea712b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497274352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.1497274352
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.3724069151
Short name T517
Test name
Test status
Simulation time 1634367696 ps
CPU time 6.15 seconds
Started Dec 20 12:55:25 PM PST 23
Finished Dec 20 12:55:46 PM PST 23
Peak memory 213284 kb
Host smart-5c817058-be01-440b-a7dd-907a15bda1c4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724069151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
3724069151
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1084843553
Short name T662
Test name
Test status
Simulation time 11389510165 ps
CPU time 53.75 seconds
Started Dec 20 12:55:16 PM PST 23
Finished Dec 20 12:56:27 PM PST 23
Peak memory 251920 kb
Host smart-c2c6aff7-0f82-4878-b116-58bcb2eb1184
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084843553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1084843553
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.378874765
Short name T784
Test name
Test status
Simulation time 1361593069 ps
CPU time 10.51 seconds
Started Dec 20 12:55:24 PM PST 23
Finished Dec 20 12:55:49 PM PST 23
Peak memory 250744 kb
Host smart-c9c718b0-66cb-4801-9e8b-12b04d63749a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378874765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_state_post_trans.378874765
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.3457470371
Short name T856
Test name
Test status
Simulation time 251560288 ps
CPU time 3.15 seconds
Started Dec 20 12:55:17 PM PST 23
Finished Dec 20 12:55:40 PM PST 23
Peak memory 218268 kb
Host smart-0dd42c19-2d15-4072-908b-b877077f99b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457470371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.3457470371
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.3035460131
Short name T504
Test name
Test status
Simulation time 1088123357 ps
CPU time 10.83 seconds
Started Dec 20 12:55:19 PM PST 23
Finished Dec 20 12:55:45 PM PST 23
Peak memory 213676 kb
Host smart-4962bbf6-49e7-4fe5-8525-6dab647864f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035460131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.3035460131
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.3382165761
Short name T125
Test name
Test status
Simulation time 939449970 ps
CPU time 38.57 seconds
Started Dec 20 12:55:29 PM PST 23
Finished Dec 20 12:56:23 PM PST 23
Peak memory 268720 kb
Host smart-5c1f79b2-efb3-4edb-b47b-0cec6ddb43cc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382165761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.3382165761
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.3358421178
Short name T781
Test name
Test status
Simulation time 444810397 ps
CPU time 12.55 seconds
Started Dec 20 12:55:21 PM PST 23
Finished Dec 20 12:55:48 PM PST 23
Peak memory 219276 kb
Host smart-17311322-a751-4421-9003-9bc9f3addb10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358421178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.3358421178
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.1178115206
Short name T884
Test name
Test status
Simulation time 710526402 ps
CPU time 16.07 seconds
Started Dec 20 12:55:01 PM PST 23
Finished Dec 20 12:55:38 PM PST 23
Peak memory 218332 kb
Host smart-acc495aa-231b-44a3-b13f-81bb515769cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178115206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.1178115206
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.1751412109
Short name T609
Test name
Test status
Simulation time 319200088 ps
CPU time 8.66 seconds
Started Dec 20 12:55:27 PM PST 23
Finished Dec 20 12:55:50 PM PST 23
Peak memory 218188 kb
Host smart-3031a3f7-02f1-45ba-951b-3caafcb422b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751412109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.1
751412109
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.2006872326
Short name T378
Test name
Test status
Simulation time 2119125119 ps
CPU time 10.57 seconds
Started Dec 20 12:55:14 PM PST 23
Finished Dec 20 12:55:41 PM PST 23
Peak memory 218284 kb
Host smart-43366271-2f3c-446e-9b67-50e146eb0691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006872326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.2006872326
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.198425222
Short name T368
Test name
Test status
Simulation time 68636533 ps
CPU time 4.88 seconds
Started Dec 20 12:55:15 PM PST 23
Finished Dec 20 12:55:37 PM PST 23
Peak memory 214104 kb
Host smart-bae7c85f-9faf-4fd2-89bc-a3ffea853ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198425222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.198425222
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.1550554672
Short name T947
Test name
Test status
Simulation time 184255956 ps
CPU time 23.49 seconds
Started Dec 20 12:55:03 PM PST 23
Finished Dec 20 12:55:48 PM PST 23
Peak memory 245908 kb
Host smart-335f13ef-7ed7-467e-b402-6db3b5bbf65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550554672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.1550554672
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.707513261
Short name T959
Test name
Test status
Simulation time 77200081 ps
CPU time 10.72 seconds
Started Dec 20 12:55:17 PM PST 23
Finished Dec 20 12:55:44 PM PST 23
Peak memory 251200 kb
Host smart-fc8ca7d3-7c50-42a2-b6f0-b7c1d2d76495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707513261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.707513261
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.3175184038
Short name T914
Test name
Test status
Simulation time 7995400538 ps
CPU time 44.17 seconds
Started Dec 20 12:55:26 PM PST 23
Finished Dec 20 12:56:24 PM PST 23
Peak memory 275936 kb
Host smart-ce8dad8a-e09c-4d23-8734-005b08d6193a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175184038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.3175184038
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.1193976392
Short name T634
Test name
Test status
Simulation time 19938469 ps
CPU time 1.08 seconds
Started Dec 20 12:55:17 PM PST 23
Finished Dec 20 12:55:34 PM PST 23
Peak memory 208528 kb
Host smart-0657fc97-6959-4750-8f0f-fcbe3979ecae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193976392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.1193976392
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.878651148
Short name T206
Test name
Test status
Simulation time 13145895 ps
CPU time 0.96 seconds
Started Dec 20 12:55:01 PM PST 23
Finished Dec 20 12:55:24 PM PST 23
Peak memory 209688 kb
Host smart-9d3cb2cc-e53e-45ed-836e-73379cfcf12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878651148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.878651148
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.2406276881
Short name T745
Test name
Test status
Simulation time 225378363 ps
CPU time 7.83 seconds
Started Dec 20 12:54:57 PM PST 23
Finished Dec 20 12:55:23 PM PST 23
Peak memory 218136 kb
Host smart-fcb3a49e-6296-4495-9a95-3d7679ee23a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406276881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.2406276881
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.1344490167
Short name T860
Test name
Test status
Simulation time 731825715 ps
CPU time 4.87 seconds
Started Dec 20 12:55:06 PM PST 23
Finished Dec 20 12:55:33 PM PST 23
Peak memory 209716 kb
Host smart-72238a97-d83b-46f9-8565-9bec21d2299e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344490167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_ac
cess.1344490167
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.952717253
Short name T893
Test name
Test status
Simulation time 1130763683 ps
CPU time 33.74 seconds
Started Dec 20 12:54:53 PM PST 23
Finished Dec 20 12:55:45 PM PST 23
Peak memory 218240 kb
Host smart-5273a914-85e5-4fb6-a587-1987dc95262a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952717253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_err
ors.952717253
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2389278755
Short name T383
Test name
Test status
Simulation time 307007599 ps
CPU time 4.11 seconds
Started Dec 20 12:55:07 PM PST 23
Finished Dec 20 12:55:32 PM PST 23
Peak memory 217832 kb
Host smart-1e393b1d-60d8-4aba-94dc-49b5457b8692
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389278755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_
priority.2389278755
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.2040739008
Short name T377
Test name
Test status
Simulation time 195269902 ps
CPU time 6.46 seconds
Started Dec 20 12:55:01 PM PST 23
Finished Dec 20 12:55:29 PM PST 23
Peak memory 218192 kb
Host smart-fd0b0357-a520-4864-9d2d-802aa65e0e19
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040739008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.2040739008
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.188153356
Short name T20
Test name
Test status
Simulation time 6786435625 ps
CPU time 11.68 seconds
Started Dec 20 12:54:59 PM PST 23
Finished Dec 20 12:55:30 PM PST 23
Peak memory 213716 kb
Host smart-2ed07519-27cc-4c4c-8d70-15eb2e99db9b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188153356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_regwen_during_op.188153356
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.2290864646
Short name T392
Test name
Test status
Simulation time 176328848 ps
CPU time 2.75 seconds
Started Dec 20 12:55:06 PM PST 23
Finished Dec 20 12:55:30 PM PST 23
Peak memory 213116 kb
Host smart-a8657dec-775c-44d8-832c-5706d7fd21ad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290864646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
2290864646
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.1580009628
Short name T610
Test name
Test status
Simulation time 5273397234 ps
CPU time 31.88 seconds
Started Dec 20 12:54:58 PM PST 23
Finished Dec 20 12:55:49 PM PST 23
Peak memory 268016 kb
Host smart-13afeec3-0dbc-4448-a7e7-33fc901ef754
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580009628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.1580009628
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1561138759
Short name T691
Test name
Test status
Simulation time 901805542 ps
CPU time 28.31 seconds
Started Dec 20 12:55:06 PM PST 23
Finished Dec 20 12:55:56 PM PST 23
Peak memory 249832 kb
Host smart-17efd0e7-f180-4577-9b79-beefdc1a6a55
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561138759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1561138759
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.4272031921
Short name T482
Test name
Test status
Simulation time 95503071 ps
CPU time 3.35 seconds
Started Dec 20 12:54:55 PM PST 23
Finished Dec 20 12:55:16 PM PST 23
Peak memory 218168 kb
Host smart-1cc9d229-30a3-40f9-b0c2-bbbf0840fac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272031921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.4272031921
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.3066647041
Short name T126
Test name
Test status
Simulation time 454160800 ps
CPU time 20.27 seconds
Started Dec 20 12:55:06 PM PST 23
Finished Dec 20 12:55:48 PM PST 23
Peak memory 268200 kb
Host smart-a9fb3c45-75a8-4a7e-a579-85b2bb8d3d18
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066647041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.3066647041
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.2011483632
Short name T859
Test name
Test status
Simulation time 3135533880 ps
CPU time 10.95 seconds
Started Dec 20 12:55:00 PM PST 23
Finished Dec 20 12:55:31 PM PST 23
Peak memory 218328 kb
Host smart-59a17493-81ef-4c77-b3e8-3dc5943132c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011483632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.2011483632
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.1187655865
Short name T577
Test name
Test status
Simulation time 679085236 ps
CPU time 13.52 seconds
Started Dec 20 12:55:02 PM PST 23
Finished Dec 20 12:55:37 PM PST 23
Peak memory 218108 kb
Host smart-b2f43ad4-6fe5-4b86-a43b-05f01958e776
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187655865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.1187655865
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.3196273810
Short name T391
Test name
Test status
Simulation time 232057246 ps
CPU time 6.18 seconds
Started Dec 20 12:55:08 PM PST 23
Finished Dec 20 12:55:34 PM PST 23
Peak memory 218128 kb
Host smart-d82c3db7-e03c-48a0-9255-25f66d19aac8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196273810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.3
196273810
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.2204666980
Short name T572
Test name
Test status
Simulation time 265314756 ps
CPU time 6.34 seconds
Started Dec 20 12:54:59 PM PST 23
Finished Dec 20 12:55:26 PM PST 23
Peak memory 218124 kb
Host smart-c99385e9-2915-4714-b968-b3f1fb7a9d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204666980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.2204666980
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.754815770
Short name T483
Test name
Test status
Simulation time 27614317 ps
CPU time 1.53 seconds
Started Dec 20 12:55:16 PM PST 23
Finished Dec 20 12:55:35 PM PST 23
Peak memory 213004 kb
Host smart-bfd3c35b-6c33-425b-96db-90b1db1b143b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754815770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.754815770
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.2624347668
Short name T968
Test name
Test status
Simulation time 2499768113 ps
CPU time 21.32 seconds
Started Dec 20 12:55:00 PM PST 23
Finished Dec 20 12:55:41 PM PST 23
Peak memory 251248 kb
Host smart-878c95fd-b5da-4eb4-9930-47a68fc3f0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624347668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.2624347668
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.2751441625
Short name T36
Test name
Test status
Simulation time 90875580 ps
CPU time 7.42 seconds
Started Dec 20 12:55:00 PM PST 23
Finished Dec 20 12:55:28 PM PST 23
Peak memory 251088 kb
Host smart-f631bc82-73ab-401a-a3fa-0d765bab33bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751441625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.2751441625
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.2482315498
Short name T496
Test name
Test status
Simulation time 3143611174 ps
CPU time 64.88 seconds
Started Dec 20 12:55:05 PM PST 23
Finished Dec 20 12:56:31 PM PST 23
Peak memory 220680 kb
Host smart-18b63ac5-ad8b-44bd-a16c-fa046707b9d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482315498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.2482315498
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.1357362934
Short name T67
Test name
Test status
Simulation time 240412356343 ps
CPU time 524.06 seconds
Started Dec 20 12:55:13 PM PST 23
Finished Dec 20 01:04:15 PM PST 23
Peak memory 281644 kb
Host smart-10e2b506-7ef1-447e-a429-af3c81c6b2bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1357362934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.1357362934
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3955929435
Short name T385
Test name
Test status
Simulation time 70155848 ps
CPU time 0.84 seconds
Started Dec 20 12:55:30 PM PST 23
Finished Dec 20 12:55:46 PM PST 23
Peak memory 208452 kb
Host smart-d775fc18-f3d3-4374-bb95-66e27be254d8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955929435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.3955929435
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.3093609880
Short name T82
Test name
Test status
Simulation time 91034566 ps
CPU time 0.99 seconds
Started Dec 20 12:55:22 PM PST 23
Finished Dec 20 12:55:37 PM PST 23
Peak memory 208416 kb
Host smart-8bc7abaf-a513-4a4a-985a-21af60f78b86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093609880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.3093609880
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.1461996778
Short name T878
Test name
Test status
Simulation time 1098943650 ps
CPU time 12.09 seconds
Started Dec 20 12:55:17 PM PST 23
Finished Dec 20 12:55:48 PM PST 23
Peak memory 218332 kb
Host smart-6944485b-1d1f-4993-842d-219d1d1549b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461996778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.1461996778
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.2429786444
Short name T686
Test name
Test status
Simulation time 443520471 ps
CPU time 10.66 seconds
Started Dec 20 12:55:23 PM PST 23
Finished Dec 20 12:55:48 PM PST 23
Peak memory 209612 kb
Host smart-33a730d8-6cfb-4db8-a939-22c0df8b02f5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429786444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_a
ccess.2429786444
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.2931453830
Short name T730
Test name
Test status
Simulation time 5816666432 ps
CPU time 21.27 seconds
Started Dec 20 12:55:17 PM PST 23
Finished Dec 20 12:55:58 PM PST 23
Peak memory 218592 kb
Host smart-462059db-4a2b-42ca-8be8-1619f75e1e28
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931453830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.2931453830
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1264458552
Short name T701
Test name
Test status
Simulation time 380935501 ps
CPU time 11.38 seconds
Started Dec 20 12:55:19 PM PST 23
Finished Dec 20 12:55:46 PM PST 23
Peak memory 218084 kb
Host smart-92f128ca-cc0d-4bd8-9b59-d178db8a29fb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264458552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.1264458552
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.4179365298
Short name T86
Test name
Test status
Simulation time 2108460375 ps
CPU time 6.9 seconds
Started Dec 20 12:55:27 PM PST 23
Finished Dec 20 12:55:48 PM PST 23
Peak memory 213628 kb
Host smart-861f13e7-1bea-4ae6-a1ce-9df22718df37
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179365298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.4179365298
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.3984540675
Short name T441
Test name
Test status
Simulation time 2438499468 ps
CPU time 50.58 seconds
Started Dec 20 12:55:19 PM PST 23
Finished Dec 20 12:56:25 PM PST 23
Peak memory 251072 kb
Host smart-9eb9e1f8-b6e3-49e9-8819-89f01bbcb5fd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984540675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.3984540675
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.3144845798
Short name T703
Test name
Test status
Simulation time 290415480 ps
CPU time 14.95 seconds
Started Dec 20 12:55:18 PM PST 23
Finished Dec 20 12:55:49 PM PST 23
Peak memory 251120 kb
Host smart-ffebc8f3-84fe-4f8c-81bf-8d021b4d03ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144845798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.3144845798
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.2702162900
Short name T744
Test name
Test status
Simulation time 29028330 ps
CPU time 2.15 seconds
Started Dec 20 12:55:25 PM PST 23
Finished Dec 20 12:55:41 PM PST 23
Peak memory 218292 kb
Host smart-3340444e-8738-49e2-8eab-058d807b2803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702162900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.2702162900
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.3134749261
Short name T124
Test name
Test status
Simulation time 519788780 ps
CPU time 9.78 seconds
Started Dec 20 12:55:25 PM PST 23
Finished Dec 20 12:55:49 PM PST 23
Peak memory 218140 kb
Host smart-824bf365-bef4-41f8-800b-c407277395c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134749261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.3134749261
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1624065358
Short name T581
Test name
Test status
Simulation time 401032634 ps
CPU time 14.6 seconds
Started Dec 20 12:55:23 PM PST 23
Finished Dec 20 12:55:52 PM PST 23
Peak memory 218268 kb
Host smart-8d5fc2ec-9e25-442f-9637-d14b2a502021
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624065358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.1624065358
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.261631579
Short name T760
Test name
Test status
Simulation time 340398399 ps
CPU time 9.01 seconds
Started Dec 20 12:55:29 PM PST 23
Finished Dec 20 12:55:53 PM PST 23
Peak memory 218296 kb
Host smart-d6e6da53-d630-41f8-a85f-012534007659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261631579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.261631579
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.425837429
Short name T895
Test name
Test status
Simulation time 212513002 ps
CPU time 2.43 seconds
Started Dec 20 12:55:25 PM PST 23
Finished Dec 20 12:55:42 PM PST 23
Peak memory 213928 kb
Host smart-dfe43ddf-d5ce-4128-9d08-33ff9f52166f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425837429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.425837429
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.4026345921
Short name T548
Test name
Test status
Simulation time 337642149 ps
CPU time 26.89 seconds
Started Dec 20 12:55:34 PM PST 23
Finished Dec 20 12:56:14 PM PST 23
Peak memory 251108 kb
Host smart-39e5677e-0c68-419a-8a81-1cc19e2ebcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026345921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.4026345921
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.3325300625
Short name T717
Test name
Test status
Simulation time 355592831 ps
CPU time 7.33 seconds
Started Dec 20 12:55:19 PM PST 23
Finished Dec 20 12:55:41 PM PST 23
Peak memory 250736 kb
Host smart-803c12d6-cafa-43f4-a69b-de850c0b696a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325300625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.3325300625
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.464010531
Short name T659
Test name
Test status
Simulation time 6563351873 ps
CPU time 139.92 seconds
Started Dec 20 12:55:18 PM PST 23
Finished Dec 20 12:57:54 PM PST 23
Peak memory 283960 kb
Host smart-b2b5ab40-6222-4969-8826-3c1bcc9eb24b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464010531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.464010531
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3111943644
Short name T502
Test name
Test status
Simulation time 14404084 ps
CPU time 0.8 seconds
Started Dec 20 12:55:36 PM PST 23
Finished Dec 20 12:55:50 PM PST 23
Peak memory 208424 kb
Host smart-948f6f2f-84f0-4aa0-bfca-4c7419c985b6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111943644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.3111943644
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.1183325053
Short name T939
Test name
Test status
Simulation time 31956084 ps
CPU time 0.8 seconds
Started Dec 20 12:55:31 PM PST 23
Finished Dec 20 12:55:46 PM PST 23
Peak memory 209624 kb
Host smart-36f7d4a9-466a-4ce4-ba89-fc43dc61f089
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183325053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.1183325053
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.753876836
Short name T450
Test name
Test status
Simulation time 1537364581 ps
CPU time 16.22 seconds
Started Dec 20 12:55:12 PM PST 23
Finished Dec 20 12:55:46 PM PST 23
Peak memory 218292 kb
Host smart-03960dbb-436b-4845-975b-7798a732c6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753876836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.753876836
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.1739254546
Short name T796
Test name
Test status
Simulation time 187304686 ps
CPU time 5.39 seconds
Started Dec 20 12:55:18 PM PST 23
Finished Dec 20 12:55:39 PM PST 23
Peak memory 209644 kb
Host smart-2258a3dc-4f56-4098-b082-a6e4ea5a7ee7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739254546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_a
ccess.1739254546
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2537869898
Short name T635
Test name
Test status
Simulation time 7392068512 ps
CPU time 36.16 seconds
Started Dec 20 12:55:23 PM PST 23
Finished Dec 20 12:56:14 PM PST 23
Peak memory 218624 kb
Host smart-e6b8b1b6-4337-4a78-beef-92880126e92a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537869898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2537869898
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.3657588503
Short name T363
Test name
Test status
Simulation time 765465247 ps
CPU time 6.97 seconds
Started Dec 20 12:55:23 PM PST 23
Finished Dec 20 12:55:45 PM PST 23
Peak memory 218184 kb
Host smart-e2835344-f9bb-4505-b457-39b832ec50da
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657588503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.3657588503
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.930205991
Short name T579
Test name
Test status
Simulation time 524875721 ps
CPU time 4.69 seconds
Started Dec 20 12:55:19 PM PST 23
Finished Dec 20 12:55:39 PM PST 23
Peak memory 213216 kb
Host smart-06ca9e30-a832-4b88-8838-e64b58cd24cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930205991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke.
930205991
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.377271840
Short name T615
Test name
Test status
Simulation time 3259789467 ps
CPU time 37.35 seconds
Started Dec 20 12:55:12 PM PST 23
Finished Dec 20 12:56:07 PM PST 23
Peak memory 276792 kb
Host smart-f58c14fe-7d24-4de3-bf45-6a7fedfde594
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377271840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_state_failure.377271840
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.88276332
Short name T963
Test name
Test status
Simulation time 2510980685 ps
CPU time 18 seconds
Started Dec 20 12:55:26 PM PST 23
Finished Dec 20 12:55:58 PM PST 23
Peak memory 222872 kb
Host smart-20958146-6faf-46ca-bc93-f491e2f03a3e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88276332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_j
tag_state_post_trans.88276332
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.410228093
Short name T337
Test name
Test status
Simulation time 54702003 ps
CPU time 1.69 seconds
Started Dec 20 12:55:17 PM PST 23
Finished Dec 20 12:55:35 PM PST 23
Peak memory 218172 kb
Host smart-8c9d4704-6e8c-4a8f-b476-fb20126f5312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410228093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.410228093
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.2095932350
Short name T653
Test name
Test status
Simulation time 240175121 ps
CPU time 10.16 seconds
Started Dec 20 12:55:27 PM PST 23
Finished Dec 20 12:55:51 PM PST 23
Peak memory 218556 kb
Host smart-06c8db7f-c44f-4457-84d9-b8c387120e7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095932350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.2095932350
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.1121668593
Short name T752
Test name
Test status
Simulation time 1241468422 ps
CPU time 13.31 seconds
Started Dec 20 12:55:32 PM PST 23
Finished Dec 20 12:55:59 PM PST 23
Peak memory 218308 kb
Host smart-0a4a5e0b-c015-4422-ab3e-5632952c0b20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121668593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.1121668593
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.2963059810
Short name T607
Test name
Test status
Simulation time 615775300 ps
CPU time 10.2 seconds
Started Dec 20 12:55:23 PM PST 23
Finished Dec 20 12:55:47 PM PST 23
Peak memory 218304 kb
Host smart-a54fd9d1-f306-4284-90eb-42920957ebbc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963059810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
2963059810
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.1675777932
Short name T769
Test name
Test status
Simulation time 2142532800 ps
CPU time 12.03 seconds
Started Dec 20 12:55:19 PM PST 23
Finished Dec 20 12:55:46 PM PST 23
Peak memory 218360 kb
Host smart-1158b4a5-6a09-4cae-ac2c-f5a828e92a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675777932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.1675777932
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.20450965
Short name T801
Test name
Test status
Simulation time 108192999 ps
CPU time 3.05 seconds
Started Dec 20 12:55:23 PM PST 23
Finished Dec 20 12:55:40 PM PST 23
Peak memory 214068 kb
Host smart-981e4fe1-cb9d-4f31-a595-28df1800ed6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20450965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.20450965
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.4044227244
Short name T500
Test name
Test status
Simulation time 220425967 ps
CPU time 24.49 seconds
Started Dec 20 12:55:29 PM PST 23
Finished Dec 20 12:56:09 PM PST 23
Peak memory 251264 kb
Host smart-d20be80a-d3f6-462a-9b14-c5470e1873b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044227244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.4044227244
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.3709203425
Short name T438
Test name
Test status
Simulation time 78708485 ps
CPU time 6.44 seconds
Started Dec 20 12:55:30 PM PST 23
Finished Dec 20 12:55:51 PM PST 23
Peak memory 246332 kb
Host smart-4f4b8bf0-2f07-41eb-bc49-bfac71ce00fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709203425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.3709203425
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.3502454310
Short name T503
Test name
Test status
Simulation time 358996133 ps
CPU time 26.7 seconds
Started Dec 20 12:55:52 PM PST 23
Finished Dec 20 12:56:34 PM PST 23
Peak memory 251248 kb
Host smart-d5ee5f19-7840-4350-a9f9-b84ae12899b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502454310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.3502454310
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.1479474501
Short name T759
Test name
Test status
Simulation time 27720380 ps
CPU time 1.12 seconds
Started Dec 20 12:55:24 PM PST 23
Finished Dec 20 12:55:40 PM PST 23
Peak memory 212608 kb
Host smart-7205e30c-aed3-43d5-8df0-8867f2913b21
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479474501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.1479474501
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.3747301589
Short name T677
Test name
Test status
Simulation time 39082068 ps
CPU time 0.9 seconds
Started Dec 20 12:55:50 PM PST 23
Finished Dec 20 12:56:05 PM PST 23
Peak memory 209740 kb
Host smart-30f23ae8-1104-4c25-af0b-68960256d82c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747301589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.3747301589
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.2792832170
Short name T128
Test name
Test status
Simulation time 580151563 ps
CPU time 9.89 seconds
Started Dec 20 12:55:40 PM PST 23
Finished Dec 20 12:56:04 PM PST 23
Peak memory 218160 kb
Host smart-076de9a5-10ef-4b9f-9301-4b82fa851901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792832170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.2792832170
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.442582902
Short name T750
Test name
Test status
Simulation time 1381969348 ps
CPU time 8.98 seconds
Started Dec 20 12:55:33 PM PST 23
Finished Dec 20 12:55:55 PM PST 23
Peak memory 209716 kb
Host smart-8509c10b-d00f-4220-bfb0-e1ba27ca8d4a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442582902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_ac
cess.442582902
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.1614883189
Short name T474
Test name
Test status
Simulation time 431614356 ps
CPU time 6.2 seconds
Started Dec 20 12:55:34 PM PST 23
Finished Dec 20 12:55:54 PM PST 23
Peak memory 218344 kb
Host smart-89bdb0e7-78b8-48a5-9f33-bd0ac14def9e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614883189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.1614883189
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2807331033
Short name T359
Test name
Test status
Simulation time 106234386 ps
CPU time 1.94 seconds
Started Dec 20 12:55:37 PM PST 23
Finished Dec 20 12:55:52 PM PST 23
Peak memory 212732 kb
Host smart-70ab57e2-665c-4a98-a573-d7eb3a89dcc2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807331033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.2807331033
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3599762928
Short name T821
Test name
Test status
Simulation time 944992959 ps
CPU time 31.87 seconds
Started Dec 20 12:55:39 PM PST 23
Finished Dec 20 12:56:24 PM PST 23
Peak memory 251208 kb
Host smart-f1ae3111-aa7e-450a-9af3-a418a9387d67
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599762928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.3599762928
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.4004248718
Short name T855
Test name
Test status
Simulation time 1115260592 ps
CPU time 11.4 seconds
Started Dec 20 12:55:41 PM PST 23
Finished Dec 20 12:56:06 PM PST 23
Peak memory 251288 kb
Host smart-362c50a6-c82b-4954-a493-09ac9ea751c6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004248718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.4004248718
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.4072965832
Short name T660
Test name
Test status
Simulation time 71829605 ps
CPU time 2.89 seconds
Started Dec 20 12:55:38 PM PST 23
Finished Dec 20 12:55:55 PM PST 23
Peak memory 218244 kb
Host smart-1adf505a-06bf-44d9-9719-9206304d4033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072965832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.4072965832
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.2718569563
Short name T915
Test name
Test status
Simulation time 202354706 ps
CPU time 8.95 seconds
Started Dec 20 12:55:38 PM PST 23
Finished Dec 20 12:56:01 PM PST 23
Peak memory 218336 kb
Host smart-ace5b511-b21e-4a27-93a1-6db5fe8000ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718569563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.2718569563
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.70423787
Short name T538
Test name
Test status
Simulation time 1146635238 ps
CPU time 10.39 seconds
Started Dec 20 12:55:46 PM PST 23
Finished Dec 20 12:56:11 PM PST 23
Peak memory 218100 kb
Host smart-1b9fe679-8dcb-444d-9766-97a9b0b129fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70423787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_dig
est.70423787
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.1667814394
Short name T757
Test name
Test status
Simulation time 1431396769 ps
CPU time 9.05 seconds
Started Dec 20 12:55:43 PM PST 23
Finished Dec 20 12:56:07 PM PST 23
Peak memory 218320 kb
Host smart-91531f65-f19e-4b0c-86b1-d68e9fe3a1d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667814394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
1667814394
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.2575226555
Short name T418
Test name
Test status
Simulation time 5099068478 ps
CPU time 14.84 seconds
Started Dec 20 12:55:33 PM PST 23
Finished Dec 20 12:56:01 PM PST 23
Peak memory 218140 kb
Host smart-fc4db9a2-24a8-4e3c-89b2-fd6a4793fa44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575226555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.2575226555
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.1482492934
Short name T983
Test name
Test status
Simulation time 78142803 ps
CPU time 1.71 seconds
Started Dec 20 12:55:34 PM PST 23
Finished Dec 20 12:55:49 PM PST 23
Peak memory 213680 kb
Host smart-d1d25f12-d757-4a35-88b2-cb9794b26d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482492934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.1482492934
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.3073717065
Short name T101
Test name
Test status
Simulation time 1622533747 ps
CPU time 27.04 seconds
Started Dec 20 12:55:36 PM PST 23
Finished Dec 20 12:56:17 PM PST 23
Peak memory 251212 kb
Host smart-120daa2d-48ba-4a85-9d0a-d12da62175b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073717065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.3073717065
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.3959214214
Short name T211
Test name
Test status
Simulation time 77445644 ps
CPU time 3.85 seconds
Started Dec 20 12:55:21 PM PST 23
Finished Dec 20 12:55:40 PM PST 23
Peak memory 222500 kb
Host smart-17d3d029-1cd5-4346-b0a1-6e8eb18fca10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959214214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.3959214214
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.1073655570
Short name T416
Test name
Test status
Simulation time 7654511105 ps
CPU time 86.36 seconds
Started Dec 20 12:55:48 PM PST 23
Finished Dec 20 12:57:29 PM PST 23
Peak memory 268980 kb
Host smart-50eb35fa-7178-4e4c-ac14-83414e223835
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073655570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.1073655570
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3278908299
Short name T776
Test name
Test status
Simulation time 13020535 ps
CPU time 0.82 seconds
Started Dec 20 12:55:40 PM PST 23
Finished Dec 20 12:55:55 PM PST 23
Peak memory 208048 kb
Host smart-70dd35a2-a8e3-44a9-afb0-54ab89baad05
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278908299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3278908299
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.3131134169
Short name T111
Test name
Test status
Simulation time 17313432 ps
CPU time 0.86 seconds
Started Dec 20 12:55:42 PM PST 23
Finished Dec 20 12:55:58 PM PST 23
Peak memory 208352 kb
Host smart-963e2d3f-eabf-48e7-bfd0-0f051ba11fb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131134169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.3131134169
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.2259531348
Short name T972
Test name
Test status
Simulation time 279253289 ps
CPU time 11.61 seconds
Started Dec 20 12:55:39 PM PST 23
Finished Dec 20 12:56:04 PM PST 23
Peak memory 218376 kb
Host smart-9727a296-178b-4e26-96d7-23f948e99b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259531348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.2259531348
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.535983750
Short name T558
Test name
Test status
Simulation time 1376896873 ps
CPU time 16.22 seconds
Started Dec 20 12:55:40 PM PST 23
Finished Dec 20 12:56:10 PM PST 23
Peak memory 209852 kb
Host smart-8cca1d94-4a45-433c-87ac-12ce00a889e3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535983750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_ac
cess.535983750
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2629198807
Short name T510
Test name
Test status
Simulation time 1394033262 ps
CPU time 6.48 seconds
Started Dec 20 12:55:37 PM PST 23
Finished Dec 20 12:55:58 PM PST 23
Peak memory 218316 kb
Host smart-a1730ddf-3fec-4c58-957c-97d4ebf78f87
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629198807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2629198807
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.3157403327
Short name T709
Test name
Test status
Simulation time 1427748251 ps
CPU time 2.6 seconds
Started Dec 20 12:56:00 PM PST 23
Finished Dec 20 12:56:15 PM PST 23
Peak memory 212788 kb
Host smart-bff8812f-71ff-4eff-9392-af6951fd5e90
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157403327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.3157403327
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.3840584192
Short name T777
Test name
Test status
Simulation time 5919052516 ps
CPU time 34.29 seconds
Started Dec 20 12:56:00 PM PST 23
Finished Dec 20 12:56:48 PM PST 23
Peak memory 251004 kb
Host smart-06d83a72-bdbc-4728-a548-9265a46fa924
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840584192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.3840584192
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.2449028155
Short name T360
Test name
Test status
Simulation time 949197750 ps
CPU time 11.86 seconds
Started Dec 20 12:55:39 PM PST 23
Finished Dec 20 12:56:05 PM PST 23
Peak memory 245620 kb
Host smart-e321dfb6-4fbc-4726-b010-97fa011618bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449028155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.2449028155
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.1585653266
Short name T355
Test name
Test status
Simulation time 183944014 ps
CPU time 3.36 seconds
Started Dec 20 12:55:37 PM PST 23
Finished Dec 20 12:55:53 PM PST 23
Peak memory 218048 kb
Host smart-7935ef83-4783-4967-9f6a-488fee8ad16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585653266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.1585653266
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.1920588328
Short name T393
Test name
Test status
Simulation time 386059128 ps
CPU time 15.53 seconds
Started Dec 20 12:55:43 PM PST 23
Finished Dec 20 12:56:14 PM PST 23
Peak memory 218396 kb
Host smart-3e4515b7-f872-4cc6-997a-c692e1ca619b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920588328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.1920588328
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.4121954764
Short name T598
Test name
Test status
Simulation time 286999342 ps
CPU time 9.55 seconds
Started Dec 20 12:55:38 PM PST 23
Finished Dec 20 12:56:01 PM PST 23
Peak memory 218148 kb
Host smart-bd621eb1-57ee-4236-a3b5-4403a37e83b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121954764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.4121954764
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.3478518358
Short name T40
Test name
Test status
Simulation time 1254919520 ps
CPU time 5.36 seconds
Started Dec 20 12:55:33 PM PST 23
Finished Dec 20 12:55:52 PM PST 23
Peak memory 218212 kb
Host smart-cd62565d-1457-44f5-8666-6ac085a0dbe7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478518358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
3478518358
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.120696883
Short name T570
Test name
Test status
Simulation time 947546452 ps
CPU time 9.81 seconds
Started Dec 20 12:55:32 PM PST 23
Finished Dec 20 12:55:56 PM PST 23
Peak memory 218240 kb
Host smart-76220e19-be91-4a24-9164-37117f1e1f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120696883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.120696883
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.1717746957
Short name T501
Test name
Test status
Simulation time 365274500 ps
CPU time 2.75 seconds
Started Dec 20 12:55:40 PM PST 23
Finished Dec 20 12:55:57 PM PST 23
Peak memory 214340 kb
Host smart-7f1fbf47-9769-41ac-98f1-d2cd9f9e9af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717746957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.1717746957
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.577509593
Short name T117
Test name
Test status
Simulation time 3461385307 ps
CPU time 30.84 seconds
Started Dec 20 12:55:53 PM PST 23
Finished Dec 20 12:56:39 PM PST 23
Peak memory 251056 kb
Host smart-14ce83ec-5ba8-4cf8-9625-370924a5898f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577509593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.577509593
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.1167499941
Short name T840
Test name
Test status
Simulation time 46969353 ps
CPU time 5.85 seconds
Started Dec 20 12:55:41 PM PST 23
Finished Dec 20 12:56:02 PM PST 23
Peak memory 246448 kb
Host smart-4746764b-0317-401d-9abf-a40acbe6ee35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167499941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1167499941
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.2386650593
Short name T926
Test name
Test status
Simulation time 46818860690 ps
CPU time 252.3 seconds
Started Dec 20 12:55:40 PM PST 23
Finished Dec 20 01:00:07 PM PST 23
Peak memory 278556 kb
Host smart-4be179e1-1f21-432f-89a6-486aa9501d71
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386650593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.2386650593
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.1109442959
Short name T381
Test name
Test status
Simulation time 40638791 ps
CPU time 0.76 seconds
Started Dec 20 12:55:35 PM PST 23
Finished Dec 20 12:55:49 PM PST 23
Peak memory 208280 kb
Host smart-705ad845-248c-4ff9-bac6-f8f0b3887aeb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109442959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.1109442959
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.2487585753
Short name T630
Test name
Test status
Simulation time 95857271 ps
CPU time 0.85 seconds
Started Dec 20 12:55:38 PM PST 23
Finished Dec 20 12:55:52 PM PST 23
Peak memory 208252 kb
Host smart-1a6ccd23-1b53-4000-838c-7a85614b825d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487585753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.2487585753
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.1718197824
Short name T839
Test name
Test status
Simulation time 1752441557 ps
CPU time 14.17 seconds
Started Dec 20 12:55:39 PM PST 23
Finished Dec 20 12:56:07 PM PST 23
Peak memory 218256 kb
Host smart-35ae59f6-601b-4881-a747-7db17b55fc50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718197824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.1718197824
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.3329431154
Short name T478
Test name
Test status
Simulation time 552509619 ps
CPU time 7.79 seconds
Started Dec 20 12:55:51 PM PST 23
Finished Dec 20 12:56:14 PM PST 23
Peak memory 209824 kb
Host smart-1933291f-4416-4719-a43d-0919f02ff4b6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329431154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_a
ccess.3329431154
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.4081289733
Short name T747
Test name
Test status
Simulation time 6166612604 ps
CPU time 25.37 seconds
Started Dec 20 12:55:35 PM PST 23
Finished Dec 20 12:56:13 PM PST 23
Peak memory 218396 kb
Host smart-95865fa8-41af-452e-8509-5c6b6abd0852
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081289733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.4081289733
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.3528093037
Short name T725
Test name
Test status
Simulation time 387161104 ps
CPU time 6.77 seconds
Started Dec 20 12:55:35 PM PST 23
Finished Dec 20 12:55:56 PM PST 23
Peak memory 218088 kb
Host smart-704995f9-ce67-4204-bc9f-1a0a7e36d5db
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528093037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.3528093037
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.3884306479
Short name T468
Test name
Test status
Simulation time 330742298 ps
CPU time 8.78 seconds
Started Dec 20 12:55:26 PM PST 23
Finished Dec 20 12:55:49 PM PST 23
Peak memory 213112 kb
Host smart-6de9c642-bc8b-4bfb-94fb-2b61f8d81cb3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884306479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.3884306479
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.3473417613
Short name T894
Test name
Test status
Simulation time 6064503625 ps
CPU time 36.89 seconds
Started Dec 20 12:55:37 PM PST 23
Finished Dec 20 12:56:28 PM PST 23
Peak memory 251184 kb
Host smart-0a3d45ff-98d3-43e3-a967-b60e872db0a1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473417613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.3473417613
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.577800345
Short name T571
Test name
Test status
Simulation time 1012684904 ps
CPU time 8.27 seconds
Started Dec 20 12:55:37 PM PST 23
Finished Dec 20 12:56:00 PM PST 23
Peak memory 218300 kb
Host smart-c45573de-2591-4431-9cdf-bdd0f6366b24
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577800345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_
jtag_state_post_trans.577800345
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.2396971722
Short name T885
Test name
Test status
Simulation time 125733115 ps
CPU time 2.49 seconds
Started Dec 20 12:55:31 PM PST 23
Finished Dec 20 12:55:48 PM PST 23
Peak memory 218176 kb
Host smart-0e0c984a-22e9-4edf-8a5d-59f5d45d433a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396971722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2396971722
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.48446238
Short name T830
Test name
Test status
Simulation time 1630645630 ps
CPU time 11.77 seconds
Started Dec 20 12:55:31 PM PST 23
Finished Dec 20 12:55:57 PM PST 23
Peak memory 218880 kb
Host smart-075dd4b9-d7c8-4349-bbd7-a283d2bc0299
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48446238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.48446238
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.2535668252
Short name T15
Test name
Test status
Simulation time 286813261 ps
CPU time 10.84 seconds
Started Dec 20 12:55:40 PM PST 23
Finished Dec 20 12:56:05 PM PST 23
Peak memory 218256 kb
Host smart-0ecda5a9-66b6-4537-9f67-6ce88fdc03e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535668252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.2535668252
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.3676834436
Short name T966
Test name
Test status
Simulation time 816306936 ps
CPU time 9.06 seconds
Started Dec 20 12:55:29 PM PST 23
Finished Dec 20 12:55:53 PM PST 23
Peak memory 218196 kb
Host smart-c15d0405-9b26-4691-b61b-bbaa091fe690
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676834436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
3676834436
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.3571159468
Short name T929
Test name
Test status
Simulation time 561018134 ps
CPU time 10.03 seconds
Started Dec 20 12:55:36 PM PST 23
Finished Dec 20 12:55:59 PM PST 23
Peak memory 218144 kb
Host smart-6ff10ded-875e-4195-9982-e430f543d75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571159468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.3571159468
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.2115095019
Short name T79
Test name
Test status
Simulation time 19850032 ps
CPU time 0.92 seconds
Started Dec 20 12:55:39 PM PST 23
Finished Dec 20 12:55:54 PM PST 23
Peak memory 209736 kb
Host smart-5e78aecd-1e64-4d6a-a155-56cb30d28a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115095019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.2115095019
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.3697676621
Short name T404
Test name
Test status
Simulation time 313273013 ps
CPU time 29.82 seconds
Started Dec 20 12:55:31 PM PST 23
Finished Dec 20 12:56:15 PM PST 23
Peak memory 251184 kb
Host smart-88812bb6-4126-4806-8d33-fbdc2047932a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697676621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.3697676621
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.3213832193
Short name T723
Test name
Test status
Simulation time 261069432 ps
CPU time 3.73 seconds
Started Dec 20 12:55:33 PM PST 23
Finished Dec 20 12:55:50 PM PST 23
Peak memory 218292 kb
Host smart-24084068-4484-4ea9-beb2-ef3f561f9f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213832193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.3213832193
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.900639844
Short name T465
Test name
Test status
Simulation time 44388738053 ps
CPU time 300.07 seconds
Started Dec 20 12:55:41 PM PST 23
Finished Dec 20 01:00:55 PM PST 23
Peak memory 277208 kb
Host smart-87b83959-e18c-4bb7-b0a8-3f8df53b10e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900639844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.900639844
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.2051717994
Short name T699
Test name
Test status
Simulation time 12558467 ps
CPU time 0.93 seconds
Started Dec 20 12:55:33 PM PST 23
Finished Dec 20 12:55:47 PM PST 23
Peak memory 211412 kb
Host smart-655fc349-204a-467b-a0c2-ab2fd3713c8a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051717994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.2051717994
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.2085130878
Short name T431
Test name
Test status
Simulation time 13578335 ps
CPU time 0.96 seconds
Started Dec 20 12:55:58 PM PST 23
Finished Dec 20 12:56:13 PM PST 23
Peak memory 209656 kb
Host smart-d1f5d98b-0e65-44c3-94dd-e20556d24e65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085130878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.2085130878
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.2542854345
Short name T357
Test name
Test status
Simulation time 1706966378 ps
CPU time 18.75 seconds
Started Dec 20 12:55:40 PM PST 23
Finished Dec 20 12:56:13 PM PST 23
Peak memory 218260 kb
Host smart-bc26f3a8-54dd-4381-a052-af8dbf30a78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542854345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2542854345
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.3507195572
Short name T485
Test name
Test status
Simulation time 235396655 ps
CPU time 2.14 seconds
Started Dec 20 12:55:31 PM PST 23
Finished Dec 20 12:55:47 PM PST 23
Peak memory 209828 kb
Host smart-45a38812-fd24-4099-8879-b16f2ae63368
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507195572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_a
ccess.3507195572
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.484158992
Short name T585
Test name
Test status
Simulation time 1763964250 ps
CPU time 28.83 seconds
Started Dec 20 12:55:28 PM PST 23
Finished Dec 20 12:56:12 PM PST 23
Peak memory 218168 kb
Host smart-22c884db-5ac3-4a52-9391-4f2672ce0ff5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484158992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_er
rors.484158992
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.589377765
Short name T429
Test name
Test status
Simulation time 539684026 ps
CPU time 2.41 seconds
Started Dec 20 12:55:32 PM PST 23
Finished Dec 20 12:55:48 PM PST 23
Peak memory 218136 kb
Host smart-960704a0-da29-482c-8984-d8918edfd555
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589377765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_prog_failure.589377765
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.805731867
Short name T92
Test name
Test status
Simulation time 291512725 ps
CPU time 2.53 seconds
Started Dec 20 12:55:33 PM PST 23
Finished Dec 20 12:55:49 PM PST 23
Peak memory 212756 kb
Host smart-a15e2247-0af6-4adb-8074-e93fea304b5a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805731867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke.
805731867
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.2841794246
Short name T567
Test name
Test status
Simulation time 1387526576 ps
CPU time 58.98 seconds
Started Dec 20 12:55:37 PM PST 23
Finished Dec 20 12:56:49 PM PST 23
Peak memory 251156 kb
Host smart-7e825728-7945-4607-8c9b-2ddaebd4f9a6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841794246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.2841794246
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.2407736949
Short name T912
Test name
Test status
Simulation time 1826981404 ps
CPU time 8.76 seconds
Started Dec 20 12:55:30 PM PST 23
Finished Dec 20 12:55:54 PM PST 23
Peak memory 222788 kb
Host smart-ab7c6e2c-5920-4b3c-abd0-e4bd28e2ad29
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407736949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.2407736949
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.1696996245
Short name T880
Test name
Test status
Simulation time 986900837 ps
CPU time 3.21 seconds
Started Dec 20 12:55:33 PM PST 23
Finished Dec 20 12:55:49 PM PST 23
Peak memory 218156 kb
Host smart-80aa864c-ecaa-4906-af91-1fa1936e8e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696996245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1696996245
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.2225031271
Short name T546
Test name
Test status
Simulation time 3981404739 ps
CPU time 17.82 seconds
Started Dec 20 12:55:41 PM PST 23
Finished Dec 20 12:56:13 PM PST 23
Peak memory 219480 kb
Host smart-43a442c2-eacd-4c91-8000-41a48d7b126d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225031271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.2225031271
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.793265696
Short name T405
Test name
Test status
Simulation time 939318288 ps
CPU time 9.37 seconds
Started Dec 20 12:55:39 PM PST 23
Finished Dec 20 12:56:02 PM PST 23
Peak memory 218088 kb
Host smart-c1dae5cd-7ec8-41a1-81d8-89ff6710da3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793265696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_di
gest.793265696
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1989659958
Short name T872
Test name
Test status
Simulation time 277802992 ps
CPU time 9.87 seconds
Started Dec 20 12:55:50 PM PST 23
Finished Dec 20 12:56:15 PM PST 23
Peak memory 218296 kb
Host smart-08bef2c3-1d0c-42a2-a7be-892124bf8ede
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989659958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
1989659958
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.1455091368
Short name T514
Test name
Test status
Simulation time 301516303 ps
CPU time 11.54 seconds
Started Dec 20 12:55:33 PM PST 23
Finished Dec 20 12:55:58 PM PST 23
Peak memory 218156 kb
Host smart-5dc222a6-97db-4e0e-8f5d-3ff5d4b2ef2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455091368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.1455091368
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.1235862613
Short name T76
Test name
Test status
Simulation time 50873645 ps
CPU time 1.99 seconds
Started Dec 20 12:55:53 PM PST 23
Finished Dec 20 12:56:10 PM PST 23
Peak memory 213852 kb
Host smart-a2594fee-7067-43a3-8eb6-32d63500f0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235862613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1235862613
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.3534997118
Short name T953
Test name
Test status
Simulation time 614922901 ps
CPU time 18.33 seconds
Started Dec 20 12:55:44 PM PST 23
Finished Dec 20 12:56:17 PM PST 23
Peak memory 250992 kb
Host smart-02e442b4-244c-4c83-8e7e-069ede364310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534997118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.3534997118
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.4089212596
Short name T639
Test name
Test status
Simulation time 668782116 ps
CPU time 8.15 seconds
Started Dec 20 12:55:31 PM PST 23
Finished Dec 20 12:55:54 PM PST 23
Peak memory 251276 kb
Host smart-28a9d183-a717-4fcb-a167-8f9a84b6f28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089212596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.4089212596
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.2820925170
Short name T614
Test name
Test status
Simulation time 52494338177 ps
CPU time 87.27 seconds
Started Dec 20 12:55:17 PM PST 23
Finished Dec 20 12:57:01 PM PST 23
Peak memory 280340 kb
Host smart-90c2f32a-12cb-4a2e-936a-98e7aeabf1ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820925170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.2820925170
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.1486116323
Short name T611
Test name
Test status
Simulation time 36749864 ps
CPU time 1.1 seconds
Started Dec 20 12:55:35 PM PST 23
Finished Dec 20 12:55:50 PM PST 23
Peak memory 209804 kb
Host smart-ba02b965-ef5c-4132-85a0-9ee9638ae51c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486116323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.1486116323
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.2593596776
Short name T344
Test name
Test status
Simulation time 515770783 ps
CPU time 14.92 seconds
Started Dec 20 12:55:38 PM PST 23
Finished Dec 20 12:56:06 PM PST 23
Peak memory 218284 kb
Host smart-824d5030-c151-4729-8beb-9a95330d95eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593596776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.2593596776
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.60054572
Short name T449
Test name
Test status
Simulation time 1131800434 ps
CPU time 13.77 seconds
Started Dec 20 12:55:54 PM PST 23
Finished Dec 20 12:56:22 PM PST 23
Peak memory 209752 kb
Host smart-e89167e4-04d9-499b-afb6-3071db7a47b1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60054572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jta
g_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_acc
ess.60054572
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.1271696795
Short name T131
Test name
Test status
Simulation time 2542534338 ps
CPU time 19.25 seconds
Started Dec 20 12:55:48 PM PST 23
Finished Dec 20 12:56:22 PM PST 23
Peak memory 218096 kb
Host smart-af0bd2f5-efc7-402c-823a-a0fc34d450c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271696795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.1271696795
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.3093595296
Short name T342
Test name
Test status
Simulation time 1235613369 ps
CPU time 5.09 seconds
Started Dec 20 12:55:44 PM PST 23
Finished Dec 20 12:56:04 PM PST 23
Peak memory 218048 kb
Host smart-c11c48a0-80e6-4375-b185-0e907cbf6d1f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093595296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.3093595296
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.1398871708
Short name T928
Test name
Test status
Simulation time 735385813 ps
CPU time 3.69 seconds
Started Dec 20 12:55:49 PM PST 23
Finished Dec 20 12:56:07 PM PST 23
Peak memory 213396 kb
Host smart-db1b9836-1280-4d74-828d-53f0829c5184
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398871708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.1398871708
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2753856851
Short name T716
Test name
Test status
Simulation time 9824110628 ps
CPU time 83.61 seconds
Started Dec 20 12:55:35 PM PST 23
Finished Dec 20 12:57:12 PM PST 23
Peak memory 283604 kb
Host smart-e6f9d4d7-69d0-4221-9544-e36f3da407c4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753856851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.2753856851
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.376121247
Short name T987
Test name
Test status
Simulation time 1114606476 ps
CPU time 34.06 seconds
Started Dec 20 12:55:35 PM PST 23
Finished Dec 20 12:56:22 PM PST 23
Peak memory 251016 kb
Host smart-5749033e-3c66-4423-8096-5b770755617d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376121247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_
jtag_state_post_trans.376121247
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.921965215
Short name T406
Test name
Test status
Simulation time 81630745 ps
CPU time 2.05 seconds
Started Dec 20 12:55:57 PM PST 23
Finished Dec 20 12:56:13 PM PST 23
Peak memory 218052 kb
Host smart-cba29030-d968-456c-8178-39b109f42ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921965215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.921965215
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.2268567517
Short name T600
Test name
Test status
Simulation time 738245068 ps
CPU time 17.28 seconds
Started Dec 20 12:55:43 PM PST 23
Finished Dec 20 12:56:15 PM PST 23
Peak memory 219268 kb
Host smart-f10218a1-7e47-40ca-b20b-74ec4d486fbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268567517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.2268567517
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2454339574
Short name T24
Test name
Test status
Simulation time 196262804 ps
CPU time 7.14 seconds
Started Dec 20 12:55:49 PM PST 23
Finished Dec 20 12:56:11 PM PST 23
Peak memory 218356 kb
Host smart-094b45c5-7b77-4c78-8f7f-ad1c7965a025
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454339574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2454339574
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2084687055
Short name T742
Test name
Test status
Simulation time 1342526143 ps
CPU time 9.99 seconds
Started Dec 20 12:55:41 PM PST 23
Finished Dec 20 12:56:05 PM PST 23
Peak memory 218036 kb
Host smart-3aed1e91-c10d-411c-a26f-32a83b78ae3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084687055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
2084687055
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.3929795045
Short name T61
Test name
Test status
Simulation time 538904774 ps
CPU time 8.92 seconds
Started Dec 20 12:55:33 PM PST 23
Finished Dec 20 12:55:55 PM PST 23
Peak memory 218340 kb
Host smart-8bf5489d-be1a-46f7-8a07-d4bcdac81915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929795045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.3929795045
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.949777834
Short name T439
Test name
Test status
Simulation time 54444365 ps
CPU time 1.48 seconds
Started Dec 20 12:55:31 PM PST 23
Finished Dec 20 12:55:47 PM PST 23
Peak memory 213448 kb
Host smart-449572dd-4936-420b-a65c-3e09dfd8fc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949777834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.949777834
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.1611691703
Short name T133
Test name
Test status
Simulation time 4974926759 ps
CPU time 31.2 seconds
Started Dec 20 12:55:54 PM PST 23
Finished Dec 20 12:56:40 PM PST 23
Peak memory 251308 kb
Host smart-8410815a-b0cc-4fe6-9c75-e7fd15b54d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611691703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.1611691703
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.340464621
Short name T861
Test name
Test status
Simulation time 89308626 ps
CPU time 10.53 seconds
Started Dec 20 12:55:40 PM PST 23
Finished Dec 20 12:56:05 PM PST 23
Peak memory 251356 kb
Host smart-879c6a70-0cbb-4883-9325-de402515d1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340464621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.340464621
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.474004881
Short name T563
Test name
Test status
Simulation time 6434801027 ps
CPU time 61.89 seconds
Started Dec 20 12:55:53 PM PST 23
Finished Dec 20 12:57:10 PM PST 23
Peak memory 247108 kb
Host smart-f8fc2576-1e61-403a-bc54-df0879bbbad9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474004881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.474004881
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3494778355
Short name T770
Test name
Test status
Simulation time 10630998 ps
CPU time 0.79 seconds
Started Dec 20 12:55:29 PM PST 23
Finished Dec 20 12:55:45 PM PST 23
Peak memory 208384 kb
Host smart-e50d25c9-5ac2-4976-993b-c9bc634fd3a0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494778355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.3494778355
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.4235778595
Short name T508
Test name
Test status
Simulation time 39169175 ps
CPU time 0.86 seconds
Started Dec 20 12:55:48 PM PST 23
Finished Dec 20 12:56:04 PM PST 23
Peak memory 209800 kb
Host smart-7c6693c0-986b-4d63-88c2-58a2ba7a5cbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235778595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.4235778595
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.103652677
Short name T886
Test name
Test status
Simulation time 1604106543 ps
CPU time 15.93 seconds
Started Dec 20 12:55:40 PM PST 23
Finished Dec 20 12:56:10 PM PST 23
Peak memory 218252 kb
Host smart-e9dfbfdd-8dbc-460d-abb1-130e9b2214a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103652677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.103652677
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.2797890048
Short name T561
Test name
Test status
Simulation time 2368517384 ps
CPU time 4.51 seconds
Started Dec 20 12:55:33 PM PST 23
Finished Dec 20 12:55:51 PM PST 23
Peak memory 209828 kb
Host smart-d85c9616-7329-4861-b1d5-2e249fd5d9d2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797890048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_a
ccess.2797890048
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.201842924
Short name T613
Test name
Test status
Simulation time 3818788707 ps
CPU time 51.14 seconds
Started Dec 20 12:55:43 PM PST 23
Finished Dec 20 12:56:49 PM PST 23
Peak memory 218192 kb
Host smart-d216c7ca-8450-4870-908f-4787fa1a688e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201842924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_er
rors.201842924
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.3997712309
Short name T879
Test name
Test status
Simulation time 348614770 ps
CPU time 9.03 seconds
Started Dec 20 12:55:42 PM PST 23
Finished Dec 20 12:56:05 PM PST 23
Peak memory 218188 kb
Host smart-782540fc-9dea-4f27-824b-cea472db412c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997712309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.3997712309
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.1136266305
Short name T689
Test name
Test status
Simulation time 336188064 ps
CPU time 2.69 seconds
Started Dec 20 12:55:45 PM PST 23
Finished Dec 20 12:56:03 PM PST 23
Peak memory 212544 kb
Host smart-73a905b6-376e-4288-bb06-da7c788cee3b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136266305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.1136266305
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2274824383
Short name T540
Test name
Test status
Simulation time 5896693518 ps
CPU time 59.24 seconds
Started Dec 20 12:55:37 PM PST 23
Finished Dec 20 12:56:49 PM PST 23
Peak memory 278828 kb
Host smart-19ea122d-59cc-455f-9d04-8c930f7834b1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274824383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.2274824383
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.3659948181
Short name T530
Test name
Test status
Simulation time 513644007 ps
CPU time 8.43 seconds
Started Dec 20 12:55:41 PM PST 23
Finished Dec 20 12:56:04 PM PST 23
Peak memory 222708 kb
Host smart-a507fbaf-b82e-4bff-ad3d-6af90e987543
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659948181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.3659948181
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.3795971243
Short name T819
Test name
Test status
Simulation time 34631249 ps
CPU time 2.04 seconds
Started Dec 20 12:55:42 PM PST 23
Finished Dec 20 12:55:59 PM PST 23
Peak memory 218096 kb
Host smart-308c9f05-1e64-45d3-b485-2436df37e036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795971243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.3795971243
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.4221257354
Short name T826
Test name
Test status
Simulation time 885881159 ps
CPU time 18.41 seconds
Started Dec 20 12:55:30 PM PST 23
Finished Dec 20 12:56:03 PM PST 23
Peak memory 219216 kb
Host smart-20f582bb-856c-4400-a31f-48e866ee22bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221257354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.4221257354
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.17424897
Short name T958
Test name
Test status
Simulation time 1353293987 ps
CPU time 12.88 seconds
Started Dec 20 12:55:54 PM PST 23
Finished Dec 20 12:56:22 PM PST 23
Peak memory 218000 kb
Host smart-572cb3dc-69ab-42d7-bae1-444fccd6cbf3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17424897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_dig
est.17424897
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2043689003
Short name T775
Test name
Test status
Simulation time 215579524 ps
CPU time 8.19 seconds
Started Dec 20 12:55:41 PM PST 23
Finished Dec 20 12:56:04 PM PST 23
Peak memory 218188 kb
Host smart-05b0b0e1-f1bf-4062-b01d-2f6d23f85995
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043689003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2043689003
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.1463926589
Short name T547
Test name
Test status
Simulation time 557067815 ps
CPU time 7.45 seconds
Started Dec 20 12:55:32 PM PST 23
Finished Dec 20 12:55:53 PM PST 23
Peak memory 218260 kb
Host smart-a3aed267-0eaf-4e45-8b2d-38df354004c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463926589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.1463926589
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.292411520
Short name T94
Test name
Test status
Simulation time 717094688 ps
CPU time 4.44 seconds
Started Dec 20 12:55:37 PM PST 23
Finished Dec 20 12:55:55 PM PST 23
Peak memory 214004 kb
Host smart-2b6d9f0c-cf1c-4b0d-b1ea-00d91d02b7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292411520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.292411520
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.3498517428
Short name T922
Test name
Test status
Simulation time 2881769565 ps
CPU time 23.11 seconds
Started Dec 20 12:55:36 PM PST 23
Finished Dec 20 12:56:12 PM PST 23
Peak memory 251060 kb
Host smart-f661dd30-543a-4321-97c4-0917b5692a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498517428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.3498517428
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.1787275002
Short name T334
Test name
Test status
Simulation time 122491845 ps
CPU time 6.29 seconds
Started Dec 20 12:55:48 PM PST 23
Finished Dec 20 12:56:09 PM PST 23
Peak memory 250584 kb
Host smart-af90ad6f-ced0-4304-b2bd-824a5c4873bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787275002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.1787275002
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.3875697013
Short name T412
Test name
Test status
Simulation time 1861694277 ps
CPU time 67.39 seconds
Started Dec 20 12:55:46 PM PST 23
Finished Dec 20 12:57:09 PM PST 23
Peak memory 251300 kb
Host smart-ffe13d29-b558-4720-89ae-8d333f494211
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875697013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.3875697013
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.3265681071
Short name T974
Test name
Test status
Simulation time 98087253011 ps
CPU time 552.36 seconds
Started Dec 20 12:55:46 PM PST 23
Finished Dec 20 01:05:14 PM PST 23
Peak memory 272220 kb
Host smart-1b26ab26-24f7-473a-a879-062211dcd2b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3265681071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.3265681071
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.481830431
Short name T41
Test name
Test status
Simulation time 23877403 ps
CPU time 0.77 seconds
Started Dec 20 12:55:50 PM PST 23
Finished Dec 20 12:56:05 PM PST 23
Peak memory 208364 kb
Host smart-2fa241b7-4e86-4125-9b4f-c2959f09f197
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481830431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ct
rl_volatile_unlock_smoke.481830431
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.407682739
Short name T460
Test name
Test status
Simulation time 91847639 ps
CPU time 0.99 seconds
Started Dec 20 12:55:46 PM PST 23
Finished Dec 20 12:56:03 PM PST 23
Peak memory 209560 kb
Host smart-f9cfc051-427e-45eb-8c3d-f066e8e46ff5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407682739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.407682739
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.619459467
Short name T516
Test name
Test status
Simulation time 360466019 ps
CPU time 8.01 seconds
Started Dec 20 12:55:42 PM PST 23
Finished Dec 20 12:56:04 PM PST 23
Peak memory 218300 kb
Host smart-3d727d35-7aa0-4ac3-9cf9-6adde0ac1455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619459467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.619459467
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.4131821510
Short name T26
Test name
Test status
Simulation time 641607246 ps
CPU time 3.87 seconds
Started Dec 20 12:55:41 PM PST 23
Finished Dec 20 12:55:59 PM PST 23
Peak memory 209732 kb
Host smart-edba1473-a3e3-4163-be9b-7b3d1f7ff491
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131821510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_a
ccess.4131821510
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.1242361656
Short name T49
Test name
Test status
Simulation time 6911695456 ps
CPU time 40.58 seconds
Started Dec 20 12:55:42 PM PST 23
Finished Dec 20 12:56:36 PM PST 23
Peak memory 219064 kb
Host smart-0dcf0ea9-d7e1-46fc-8e94-8c8fee4970f8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242361656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.1242361656
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.1809903729
Short name T335
Test name
Test status
Simulation time 55037135 ps
CPU time 2.54 seconds
Started Dec 20 12:55:45 PM PST 23
Finished Dec 20 12:56:02 PM PST 23
Peak memory 218200 kb
Host smart-093ec36e-7b5f-4ddb-845d-436fff9ea1c5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809903729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.1809903729
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.3677561547
Short name T964
Test name
Test status
Simulation time 1229386186 ps
CPU time 4.49 seconds
Started Dec 20 12:55:44 PM PST 23
Finished Dec 20 12:56:04 PM PST 23
Peak memory 212988 kb
Host smart-6126eb6e-a0d3-4deb-9d0d-587bf2a3497e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677561547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.3677561547
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.1012527717
Short name T617
Test name
Test status
Simulation time 1735816950 ps
CPU time 41.31 seconds
Started Dec 20 12:55:39 PM PST 23
Finished Dec 20 12:56:34 PM PST 23
Peak memory 275576 kb
Host smart-ce419d53-77f4-4e11-a6aa-c5564fd91c78
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012527717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.1012527717
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.4082902382
Short name T918
Test name
Test status
Simulation time 525626910 ps
CPU time 19.6 seconds
Started Dec 20 12:55:36 PM PST 23
Finished Dec 20 12:56:09 PM PST 23
Peak memory 251052 kb
Host smart-68720629-048c-48de-903b-dfca8f2a8793
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082902382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.4082902382
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.976872672
Short name T559
Test name
Test status
Simulation time 1022952477 ps
CPU time 3.34 seconds
Started Dec 20 12:55:50 PM PST 23
Finished Dec 20 12:56:08 PM PST 23
Peak memory 218384 kb
Host smart-1f763836-392f-4661-80e9-08358c255e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976872672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.976872672
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.1139574596
Short name T458
Test name
Test status
Simulation time 585300188 ps
CPU time 12.74 seconds
Started Dec 20 12:55:56 PM PST 23
Finished Dec 20 12:56:23 PM PST 23
Peak memory 219084 kb
Host smart-f98c59f4-b8e5-4ed1-8a6c-edd2230fe5e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139574596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.1139574596
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.3921005652
Short name T326
Test name
Test status
Simulation time 1891648916 ps
CPU time 11.52 seconds
Started Dec 20 12:55:46 PM PST 23
Finished Dec 20 12:56:12 PM PST 23
Peak memory 218088 kb
Host smart-0bbee702-1fe8-439a-acdd-f340d1d30cc9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921005652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.3921005652
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.3718438164
Short name T13
Test name
Test status
Simulation time 275632075 ps
CPU time 8.16 seconds
Started Dec 20 12:55:34 PM PST 23
Finished Dec 20 12:55:56 PM PST 23
Peak memory 218256 kb
Host smart-478944a8-b6f5-4388-a5ed-e6e220833669
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718438164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
3718438164
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.3284631419
Short name T75
Test name
Test status
Simulation time 74279358 ps
CPU time 2.57 seconds
Started Dec 20 12:55:46 PM PST 23
Finished Dec 20 12:56:03 PM PST 23
Peak memory 214004 kb
Host smart-ac0f0da4-cccb-4e1b-a82a-128c9cef439d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284631419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.3284631419
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.2227851940
Short name T521
Test name
Test status
Simulation time 194039764 ps
CPU time 24.71 seconds
Started Dec 20 12:55:36 PM PST 23
Finished Dec 20 12:56:14 PM PST 23
Peak memory 251220 kb
Host smart-7e78c0c0-d8da-4bde-b07c-b422247d7a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227851940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2227851940
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.2538391389
Short name T794
Test name
Test status
Simulation time 134525689 ps
CPU time 3.4 seconds
Started Dec 20 12:55:35 PM PST 23
Finished Dec 20 12:55:52 PM PST 23
Peak memory 226704 kb
Host smart-b3222cfb-7a10-4283-bc72-bab96e6f75f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538391389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2538391389
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.492947138
Short name T35
Test name
Test status
Simulation time 12961217196 ps
CPU time 347.04 seconds
Started Dec 20 12:55:42 PM PST 23
Finished Dec 20 01:01:44 PM PST 23
Peak memory 224184 kb
Host smart-b69566e3-3b07-472f-969d-a7e124ba8e71
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492947138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.492947138
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.289985739
Short name T852
Test name
Test status
Simulation time 43680682 ps
CPU time 0.89 seconds
Started Dec 20 12:55:44 PM PST 23
Finished Dec 20 12:56:00 PM PST 23
Peak memory 208460 kb
Host smart-7c3dc77c-5aa8-4e50-9f04-9013b05c53d3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289985739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct
rl_volatile_unlock_smoke.289985739
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.3311950589
Short name T767
Test name
Test status
Simulation time 27664904 ps
CPU time 1.36 seconds
Started Dec 20 12:55:52 PM PST 23
Finished Dec 20 12:56:08 PM PST 23
Peak memory 209800 kb
Host smart-daa14fea-05bf-460b-96c5-0fdea8a9d492
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311950589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.3311950589
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2268112954
Short name T395
Test name
Test status
Simulation time 701588119 ps
CPU time 13.31 seconds
Started Dec 20 12:55:54 PM PST 23
Finished Dec 20 12:56:22 PM PST 23
Peak memory 218188 kb
Host smart-f429e55a-3038-426c-b148-f7c8b2750020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268112954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2268112954
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.998584100
Short name T121
Test name
Test status
Simulation time 1021814653 ps
CPU time 2.67 seconds
Started Dec 20 12:55:52 PM PST 23
Finished Dec 20 12:56:10 PM PST 23
Peak memory 209816 kb
Host smart-b9ca9858-3ab8-46ea-aa5e-94b297e1b08f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998584100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_ac
cess.998584100
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.3775895025
Short name T638
Test name
Test status
Simulation time 2436381001 ps
CPU time 40.22 seconds
Started Dec 20 12:56:00 PM PST 23
Finished Dec 20 12:56:54 PM PST 23
Peak memory 218320 kb
Host smart-2486e9aa-7ef3-44ec-a3c3-02a78d741539
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775895025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.3775895025
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.2958569631
Short name T396
Test name
Test status
Simulation time 1682706020 ps
CPU time 12.11 seconds
Started Dec 20 12:55:54 PM PST 23
Finished Dec 20 12:56:21 PM PST 23
Peak memory 218128 kb
Host smart-ddd3088e-6c30-4954-9d77-7652175a23b7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958569631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.2958569631
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.3923959812
Short name T330
Test name
Test status
Simulation time 523487085 ps
CPU time 5.84 seconds
Started Dec 20 12:55:57 PM PST 23
Finished Dec 20 12:56:17 PM PST 23
Peak memory 213616 kb
Host smart-3054057d-5001-4a54-b58c-f938446cd19a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923959812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.3923959812
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.2753478142
Short name T925
Test name
Test status
Simulation time 471990576 ps
CPU time 11.46 seconds
Started Dec 20 12:55:59 PM PST 23
Finished Dec 20 12:56:24 PM PST 23
Peak memory 251188 kb
Host smart-a589200e-9e33-4446-8f44-d2a6fe6a7286
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753478142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.2753478142
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.2784682898
Short name T765
Test name
Test status
Simulation time 53381262 ps
CPU time 2.52 seconds
Started Dec 20 12:56:02 PM PST 23
Finished Dec 20 12:56:17 PM PST 23
Peak memory 218248 kb
Host smart-e7903db3-ece6-41f0-8388-4dfb5dbf3fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784682898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.2784682898
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.838734228
Short name T400
Test name
Test status
Simulation time 1078018214 ps
CPU time 9.4 seconds
Started Dec 20 12:55:55 PM PST 23
Finished Dec 20 12:56:19 PM PST 23
Peak memory 218220 kb
Host smart-ad21af35-2c47-41c8-b6b1-c905844f76df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838734228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.838734228
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.2019201801
Short name T586
Test name
Test status
Simulation time 703772311 ps
CPU time 17.89 seconds
Started Dec 20 12:55:56 PM PST 23
Finished Dec 20 12:56:28 PM PST 23
Peak memory 218020 kb
Host smart-efdf8ff4-1bd4-43f2-9d29-2c2963dd0be4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019201801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.2019201801
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.3786175177
Short name T323
Test name
Test status
Simulation time 819356863 ps
CPU time 6.42 seconds
Started Dec 20 12:55:48 PM PST 23
Finished Dec 20 12:56:10 PM PST 23
Peak memory 218252 kb
Host smart-2b2f6e66-0f1c-47df-9db4-626ca6f6bb74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786175177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
3786175177
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.2386286994
Short name T654
Test name
Test status
Simulation time 1942490900 ps
CPU time 9.67 seconds
Started Dec 20 12:55:50 PM PST 23
Finished Dec 20 12:56:15 PM PST 23
Peak memory 218252 kb
Host smart-244cf649-cefc-4e29-b0eb-88d7fb0b442b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386286994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.2386286994
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.3965429425
Short name T748
Test name
Test status
Simulation time 68656469 ps
CPU time 2.31 seconds
Started Dec 20 12:55:51 PM PST 23
Finished Dec 20 12:56:09 PM PST 23
Peak memory 213984 kb
Host smart-f8ceddcd-02d0-4a34-adbf-b79d7829c9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965429425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.3965429425
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.1366275400
Short name T551
Test name
Test status
Simulation time 821280758 ps
CPU time 20.27 seconds
Started Dec 20 12:55:53 PM PST 23
Finished Dec 20 12:56:29 PM PST 23
Peak memory 250972 kb
Host smart-7dd6b2d6-f5bc-463f-9f38-df4363c8d04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366275400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.1366275400
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.2635773280
Short name T341
Test name
Test status
Simulation time 362151911 ps
CPU time 6.67 seconds
Started Dec 20 12:55:56 PM PST 23
Finished Dec 20 12:56:17 PM PST 23
Peak memory 251044 kb
Host smart-1b53f108-51c5-4396-9aa6-37ecce595d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635773280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.2635773280
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.3518507840
Short name T647
Test name
Test status
Simulation time 7977824297 ps
CPU time 155.33 seconds
Started Dec 20 12:56:03 PM PST 23
Finished Dec 20 12:58:51 PM PST 23
Peak memory 251244 kb
Host smart-a7322c4c-084c-446f-989e-2cb4d2424969
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518507840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.3518507840
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3432561487
Short name T764
Test name
Test status
Simulation time 39042714 ps
CPU time 0.73 seconds
Started Dec 20 12:56:06 PM PST 23
Finished Dec 20 12:56:19 PM PST 23
Peak memory 208080 kb
Host smart-1241a56a-9493-44a6-8429-7da8f6296bae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432561487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.3432561487
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.638155528
Short name T461
Test name
Test status
Simulation time 95880998 ps
CPU time 1.05 seconds
Started Dec 20 12:55:16 PM PST 23
Finished Dec 20 12:55:34 PM PST 23
Peak memory 208536 kb
Host smart-d470a91a-6468-4cd0-9289-7f56871359ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638155528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.638155528
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.531294366
Short name T379
Test name
Test status
Simulation time 11745888 ps
CPU time 0.78 seconds
Started Dec 20 12:55:11 PM PST 23
Finished Dec 20 12:55:30 PM PST 23
Peak memory 208260 kb
Host smart-c34f65e1-f916-4425-8d2f-9ec090072ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531294366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.531294366
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.769964744
Short name T708
Test name
Test status
Simulation time 239697079 ps
CPU time 8.9 seconds
Started Dec 20 12:54:59 PM PST 23
Finished Dec 20 12:55:29 PM PST 23
Peak memory 218248 kb
Host smart-44ec74d9-8014-4021-ba43-f4e8157d378f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769964744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.769964744
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.2673168002
Short name T477
Test name
Test status
Simulation time 198321169 ps
CPU time 5.59 seconds
Started Dec 20 12:55:24 PM PST 23
Finished Dec 20 12:55:44 PM PST 23
Peak memory 209720 kb
Host smart-69f12c3b-4067-4b0f-a43f-cbff4b80e4db
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673168002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_ac
cess.2673168002
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.3553947914
Short name T824
Test name
Test status
Simulation time 2827866454 ps
CPU time 75.29 seconds
Started Dec 20 12:55:27 PM PST 23
Finished Dec 20 12:56:57 PM PST 23
Peak memory 219316 kb
Host smart-4b1513a3-f224-4090-9f33-e9e7941581c4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553947914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.3553947914
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.3789957281
Short name T741
Test name
Test status
Simulation time 257497445 ps
CPU time 6.72 seconds
Started Dec 20 12:55:28 PM PST 23
Finished Dec 20 12:55:49 PM PST 23
Peak memory 218040 kb
Host smart-bcc37fc8-4781-4617-8899-ec65dfff3abe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789957281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_
priority.3789957281
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2496143605
Short name T711
Test name
Test status
Simulation time 1080346968 ps
CPU time 7.45 seconds
Started Dec 20 12:55:26 PM PST 23
Finished Dec 20 12:55:48 PM PST 23
Peak memory 218280 kb
Host smart-cd756544-19fa-433c-b70f-79006edb0aa2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496143605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.2496143605
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1410858622
Short name T371
Test name
Test status
Simulation time 1912772397 ps
CPU time 13.56 seconds
Started Dec 20 12:55:28 PM PST 23
Finished Dec 20 12:55:57 PM PST 23
Peak memory 213184 kb
Host smart-25f2e2ce-0eb4-4b13-9c7d-9853838726ea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410858622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.1410858622
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.3322735110
Short name T87
Test name
Test status
Simulation time 1251257293 ps
CPU time 2.66 seconds
Started Dec 20 12:55:20 PM PST 23
Finished Dec 20 12:55:37 PM PST 23
Peak memory 212904 kb
Host smart-3236edce-d638-4835-be37-53d3899c299f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322735110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
3322735110
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.3305446436
Short name T34
Test name
Test status
Simulation time 1566712990 ps
CPU time 12.51 seconds
Started Dec 20 12:55:29 PM PST 23
Finished Dec 20 12:55:56 PM PST 23
Peak memory 246844 kb
Host smart-944798d1-c7f1-4612-bb35-71faf5957c49
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305446436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.3305446436
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.3130064001
Short name T667
Test name
Test status
Simulation time 524876137 ps
CPU time 3.39 seconds
Started Dec 20 12:55:07 PM PST 23
Finished Dec 20 12:55:31 PM PST 23
Peak memory 218120 kb
Host smart-b9f26ecd-f5db-4cd2-b76c-59b43e2bedd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130064001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.3130064001
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.969618754
Short name T645
Test name
Test status
Simulation time 1408132845 ps
CPU time 9.63 seconds
Started Dec 20 12:55:22 PM PST 23
Finished Dec 20 12:55:46 PM PST 23
Peak memory 218244 kb
Host smart-663f1d14-aa5f-4c0b-a8f1-57d7cf7761d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969618754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.969618754
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.1738985983
Short name T110
Test name
Test status
Simulation time 120882322 ps
CPU time 25.6 seconds
Started Dec 20 12:55:27 PM PST 23
Finished Dec 20 12:56:07 PM PST 23
Peak memory 284420 kb
Host smart-7280b783-7772-4d1d-b3c4-cedfe5dc7ff2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738985983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.1738985983
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.3320430522
Short name T490
Test name
Test status
Simulation time 1599669435 ps
CPU time 16.83 seconds
Started Dec 20 12:55:23 PM PST 23
Finished Dec 20 12:55:54 PM PST 23
Peak memory 219276 kb
Host smart-59313daa-049f-4a43-a395-52021bac3caf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320430522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.3320430522
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.69195250
Short name T892
Test name
Test status
Simulation time 1174164315 ps
CPU time 12.51 seconds
Started Dec 20 12:55:26 PM PST 23
Finished Dec 20 12:55:53 PM PST 23
Peak memory 218192 kb
Host smart-9e51ed34-5212-44ed-acc7-09c1cf608a67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69195250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_dige
st.69195250
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.1197733400
Short name T349
Test name
Test status
Simulation time 273457303 ps
CPU time 5.72 seconds
Started Dec 20 12:55:27 PM PST 23
Finished Dec 20 12:55:48 PM PST 23
Peak memory 217996 kb
Host smart-3a7d6027-f3ed-4dc0-8ead-795f138ce748
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197733400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.1
197733400
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.4205691611
Short name T541
Test name
Test status
Simulation time 673688517 ps
CPU time 8.81 seconds
Started Dec 20 12:55:23 PM PST 23
Finished Dec 20 12:55:46 PM PST 23
Peak memory 218068 kb
Host smart-048ed5cb-1406-48e4-894c-491b942fd1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205691611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.4205691611
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.2562883663
Short name T651
Test name
Test status
Simulation time 21510254 ps
CPU time 1.59 seconds
Started Dec 20 12:55:06 PM PST 23
Finished Dec 20 12:55:31 PM PST 23
Peak memory 213788 kb
Host smart-f577e7d6-2aec-479b-914e-38ec06607f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562883663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.2562883663
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.35391110
Short name T960
Test name
Test status
Simulation time 236518703 ps
CPU time 24.47 seconds
Started Dec 20 12:55:21 PM PST 23
Finished Dec 20 12:56:00 PM PST 23
Peak memory 251020 kb
Host smart-9fffb41d-31ce-4cd1-91cf-0439f3475d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35391110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.35391110
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.2434243473
Short name T629
Test name
Test status
Simulation time 57309515 ps
CPU time 6.39 seconds
Started Dec 20 12:55:22 PM PST 23
Finished Dec 20 12:55:43 PM PST 23
Peak memory 246404 kb
Host smart-4e2ac7e3-5665-452e-ab46-b7ed5911e2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434243473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.2434243473
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.2454113063
Short name T984
Test name
Test status
Simulation time 8036693424 ps
CPU time 57.95 seconds
Started Dec 20 12:55:16 PM PST 23
Finished Dec 20 12:56:31 PM PST 23
Peak memory 251232 kb
Host smart-d2e6af22-3f18-477d-8df8-53e6eeed05fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454113063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.2454113063
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.4142911428
Short name T488
Test name
Test status
Simulation time 33620828807 ps
CPU time 305.13 seconds
Started Dec 20 12:55:25 PM PST 23
Finished Dec 20 01:00:45 PM PST 23
Peak memory 277248 kb
Host smart-f129093c-dc88-43f4-b986-acdb066b08a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4142911428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.4142911428
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.449417611
Short name T833
Test name
Test status
Simulation time 89658158 ps
CPU time 0.72 seconds
Started Dec 20 12:55:18 PM PST 23
Finished Dec 20 12:55:34 PM PST 23
Peak memory 208508 kb
Host smart-02cf5384-a76a-41a3-a9e2-72f0a961e6b2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449417611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctr
l_volatile_unlock_smoke.449417611
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.162457838
Short name T85
Test name
Test status
Simulation time 16419784 ps
CPU time 0.86 seconds
Started Dec 20 12:55:48 PM PST 23
Finished Dec 20 12:56:04 PM PST 23
Peak memory 209836 kb
Host smart-2db0c3c5-8175-47e5-b8cc-cd33db1b9871
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162457838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.162457838
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.305597850
Short name T847
Test name
Test status
Simulation time 1821056933 ps
CPU time 15.07 seconds
Started Dec 20 12:55:48 PM PST 23
Finished Dec 20 12:56:18 PM PST 23
Peak memory 218244 kb
Host smart-e506fc21-f8a4-4420-8399-c89f4f734967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305597850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.305597850
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.3121227826
Short name T575
Test name
Test status
Simulation time 874945442 ps
CPU time 10.8 seconds
Started Dec 20 12:55:51 PM PST 23
Finished Dec 20 12:56:17 PM PST 23
Peak memory 209592 kb
Host smart-77d016f7-c8e6-4636-b97b-89a823afde36
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121227826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_a
ccess.3121227826
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.210153322
Short name T358
Test name
Test status
Simulation time 64356199 ps
CPU time 1.88 seconds
Started Dec 20 12:56:00 PM PST 23
Finished Dec 20 12:56:15 PM PST 23
Peak memory 218156 kb
Host smart-ab6bc1d6-661d-47f0-a748-67f3195b6163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210153322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.210153322
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.536901509
Short name T569
Test name
Test status
Simulation time 954451740 ps
CPU time 12.01 seconds
Started Dec 20 12:55:59 PM PST 23
Finished Dec 20 12:56:25 PM PST 23
Peak memory 219176 kb
Host smart-096b96f9-f9c6-49aa-bc3a-5d3fc22a74e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536901509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.536901509
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.3103401721
Short name T802
Test name
Test status
Simulation time 1124702381 ps
CPU time 11.27 seconds
Started Dec 20 12:55:51 PM PST 23
Finished Dec 20 12:56:17 PM PST 23
Peak memory 218272 kb
Host smart-729d3ae5-b2ef-4a93-a0ef-bf8a28a63e68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103401721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.3103401721
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.3785172768
Short name T936
Test name
Test status
Simulation time 1648091830 ps
CPU time 12.17 seconds
Started Dec 20 12:55:50 PM PST 23
Finished Dec 20 12:56:17 PM PST 23
Peak memory 218092 kb
Host smart-8e1fb4cf-aa41-4f32-b80b-9f386b12f4a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785172768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
3785172768
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.3273347911
Short name T932
Test name
Test status
Simulation time 1017025577 ps
CPU time 7.36 seconds
Started Dec 20 12:55:52 PM PST 23
Finished Dec 20 12:56:14 PM PST 23
Peak memory 218272 kb
Host smart-f6645750-654e-451b-8810-796aed4a6668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273347911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.3273347911
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.3208755603
Short name T417
Test name
Test status
Simulation time 94372195 ps
CPU time 1.58 seconds
Started Dec 20 12:55:55 PM PST 23
Finished Dec 20 12:56:11 PM PST 23
Peak memory 217948 kb
Host smart-da0c9c6e-5e03-4d3c-b8c4-f4030b83c376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208755603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.3208755603
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.2692564510
Short name T397
Test name
Test status
Simulation time 767344020 ps
CPU time 23.61 seconds
Started Dec 20 12:55:51 PM PST 23
Finished Dec 20 12:56:30 PM PST 23
Peak memory 251076 kb
Host smart-0fd1e8ea-952f-4c49-9390-d265e23b83e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692564510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.2692564510
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.1947357956
Short name T102
Test name
Test status
Simulation time 63980289 ps
CPU time 6.36 seconds
Started Dec 20 12:55:55 PM PST 23
Finished Dec 20 12:56:16 PM PST 23
Peak memory 246772 kb
Host smart-f062f837-6722-4f03-90db-d8b8a8fe6f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947357956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.1947357956
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.4120859570
Short name T721
Test name
Test status
Simulation time 17514998679 ps
CPU time 178.6 seconds
Started Dec 20 12:56:02 PM PST 23
Finished Dec 20 12:59:13 PM PST 23
Peak memory 227584 kb
Host smart-a09b46c6-1cf9-4d0d-8c48-ce159b4afc15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120859570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.4120859570
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1472666793
Short name T44
Test name
Test status
Simulation time 111134769 ps
CPU time 0.78 seconds
Started Dec 20 12:55:55 PM PST 23
Finished Dec 20 12:56:11 PM PST 23
Peak memory 207968 kb
Host smart-05f1e1e0-658c-449e-8c27-87529fabd421
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472666793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.1472666793
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.864998715
Short name T554
Test name
Test status
Simulation time 15564586 ps
CPU time 1.03 seconds
Started Dec 20 12:56:06 PM PST 23
Finished Dec 20 12:56:19 PM PST 23
Peak memory 209704 kb
Host smart-afb9ef03-cd06-47f5-9afa-969ff190a9f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864998715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.864998715
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.3047772576
Short name T553
Test name
Test status
Simulation time 728108192 ps
CPU time 10.36 seconds
Started Dec 20 12:55:57 PM PST 23
Finished Dec 20 12:56:21 PM PST 23
Peak memory 218144 kb
Host smart-57125b0a-2885-423f-9fd0-c92b10065516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047772576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.3047772576
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.2417893981
Short name T865
Test name
Test status
Simulation time 163518236 ps
CPU time 4.93 seconds
Started Dec 20 12:56:14 PM PST 23
Finished Dec 20 12:56:28 PM PST 23
Peak memory 209768 kb
Host smart-0a081ee5-5a60-4285-88c4-ee6dfb0dc738
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417893981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_a
ccess.2417893981
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.2941114920
Short name T366
Test name
Test status
Simulation time 43460912 ps
CPU time 2.09 seconds
Started Dec 20 12:55:50 PM PST 23
Finished Dec 20 12:56:07 PM PST 23
Peak memory 218196 kb
Host smart-ea7005e4-40b3-4ba1-b79e-b1a20745971b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941114920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.2941114920
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.2720867777
Short name T728
Test name
Test status
Simulation time 837302945 ps
CPU time 20.02 seconds
Started Dec 20 12:56:01 PM PST 23
Finished Dec 20 12:56:34 PM PST 23
Peak memory 218780 kb
Host smart-0240f4d4-19b1-4b47-b1b2-f6fc116370d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720867777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.2720867777
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.3803035833
Short name T495
Test name
Test status
Simulation time 837380802 ps
CPU time 18.4 seconds
Started Dec 20 12:55:49 PM PST 23
Finished Dec 20 12:56:22 PM PST 23
Peak memory 218220 kb
Host smart-22c7ab2e-1aa6-4cc5-aff0-de4eadb386e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803035833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.3803035833
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.1264516885
Short name T350
Test name
Test status
Simulation time 596821063 ps
CPU time 8.68 seconds
Started Dec 20 12:55:48 PM PST 23
Finished Dec 20 12:56:12 PM PST 23
Peak memory 218160 kb
Host smart-0bd569f1-d8a3-49d6-bbd0-ad191f7909be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264516885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
1264516885
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.3068812506
Short name T60
Test name
Test status
Simulation time 346653728 ps
CPU time 12.9 seconds
Started Dec 20 12:55:47 PM PST 23
Finished Dec 20 12:56:15 PM PST 23
Peak memory 218136 kb
Host smart-70a3da38-8dda-42b0-99e7-8c57efe03bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068812506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.3068812506
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.875559483
Short name T348
Test name
Test status
Simulation time 23096736 ps
CPU time 1.64 seconds
Started Dec 20 12:55:56 PM PST 23
Finished Dec 20 12:56:12 PM PST 23
Peak memory 213596 kb
Host smart-c1efcf67-e5e6-44f3-910e-f1fdeb87d171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875559483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.875559483
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.1026062562
Short name T793
Test name
Test status
Simulation time 902062925 ps
CPU time 25.36 seconds
Started Dec 20 12:55:50 PM PST 23
Finished Dec 20 12:56:30 PM PST 23
Peak memory 251108 kb
Host smart-a400edad-9a91-4bec-a6e0-29c9caab5e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026062562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.1026062562
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.3313517563
Short name T352
Test name
Test status
Simulation time 126779499 ps
CPU time 7.34 seconds
Started Dec 20 12:55:56 PM PST 23
Finished Dec 20 12:56:18 PM PST 23
Peak memory 251172 kb
Host smart-71927f4e-adf0-4c4a-a5f6-a1e9dd4733b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313517563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.3313517563
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.1602254676
Short name T21
Test name
Test status
Simulation time 673465967 ps
CPU time 28.06 seconds
Started Dec 20 12:55:48 PM PST 23
Finished Dec 20 12:56:31 PM PST 23
Peak memory 251384 kb
Host smart-6168dd1f-4581-4ead-950d-f9717bb701c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602254676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.1602254676
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.3256638515
Short name T850
Test name
Test status
Simulation time 29513860 ps
CPU time 0.73 seconds
Started Dec 20 12:55:57 PM PST 23
Finished Dec 20 12:56:12 PM PST 23
Peak memory 208004 kb
Host smart-baaecff0-d3d0-4bdb-bdba-f7ac0eca6d09
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256638515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.3256638515
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.1858847019
Short name T714
Test name
Test status
Simulation time 47964733 ps
CPU time 0.8 seconds
Started Dec 20 12:55:58 PM PST 23
Finished Dec 20 12:56:12 PM PST 23
Peak memory 209588 kb
Host smart-3e966db3-cc66-45aa-b16f-7cfe716e7ffd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858847019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.1858847019
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.3455586346
Short name T910
Test name
Test status
Simulation time 438477279 ps
CPU time 13.15 seconds
Started Dec 20 12:55:59 PM PST 23
Finished Dec 20 12:56:25 PM PST 23
Peak memory 218100 kb
Host smart-00c4b048-0d7a-4077-9b53-1574409a0ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455586346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.3455586346
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.3817906113
Short name T881
Test name
Test status
Simulation time 603857727 ps
CPU time 7.12 seconds
Started Dec 20 12:55:59 PM PST 23
Finished Dec 20 12:56:19 PM PST 23
Peak memory 209712 kb
Host smart-9902cfd8-b7ca-4aa7-834d-345cb28d17cc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817906113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_a
ccess.3817906113
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.3905902733
Short name T916
Test name
Test status
Simulation time 78990897 ps
CPU time 3.75 seconds
Started Dec 20 12:55:48 PM PST 23
Finished Dec 20 12:56:06 PM PST 23
Peak memory 218340 kb
Host smart-7a649f7c-71cb-425e-a09a-a8c6c0c10a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905902733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.3905902733
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.3689433702
Short name T422
Test name
Test status
Simulation time 405320270 ps
CPU time 16.42 seconds
Started Dec 20 12:56:02 PM PST 23
Finished Dec 20 12:56:31 PM PST 23
Peak memory 219300 kb
Host smart-2fd3ae23-31f7-4e70-bc0e-a1cfe2859d6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689433702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.3689433702
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.4125915459
Short name T783
Test name
Test status
Simulation time 300496297 ps
CPU time 11.89 seconds
Started Dec 20 12:55:56 PM PST 23
Finished Dec 20 12:56:22 PM PST 23
Peak memory 218132 kb
Host smart-993bc804-10ea-401a-ad8b-a096800e8c2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125915459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.4125915459
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.4060233233
Short name T671
Test name
Test status
Simulation time 517160018 ps
CPU time 9.47 seconds
Started Dec 20 12:56:01 PM PST 23
Finished Dec 20 12:56:24 PM PST 23
Peak memory 218220 kb
Host smart-015278d8-b4ec-47fd-b380-ac956cc39aa6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060233233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
4060233233
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.1027509214
Short name T58
Test name
Test status
Simulation time 896691052 ps
CPU time 12.2 seconds
Started Dec 20 12:55:57 PM PST 23
Finished Dec 20 12:56:23 PM PST 23
Peak memory 218216 kb
Host smart-811d6581-fc67-4fae-9e4e-ac16498f360e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027509214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.1027509214
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.1474399717
Short name T883
Test name
Test status
Simulation time 30301373 ps
CPU time 1 seconds
Started Dec 20 12:55:59 PM PST 23
Finished Dec 20 12:56:14 PM PST 23
Peak memory 212900 kb
Host smart-a0854e61-363b-4f51-8408-7ec86fc55ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474399717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.1474399717
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.4183775533
Short name T578
Test name
Test status
Simulation time 298655350 ps
CPU time 18.46 seconds
Started Dec 20 12:56:00 PM PST 23
Finished Dec 20 12:56:32 PM PST 23
Peak memory 251236 kb
Host smart-0dc60156-e9ed-434a-a1f9-d7e0c18f5d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183775533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.4183775533
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.968692778
Short name T913
Test name
Test status
Simulation time 148192604 ps
CPU time 7.28 seconds
Started Dec 20 12:55:56 PM PST 23
Finished Dec 20 12:56:18 PM PST 23
Peak memory 250416 kb
Host smart-3e471af6-52eb-42fd-9213-0292ad899ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968692778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.968692778
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.582181762
Short name T707
Test name
Test status
Simulation time 3898886297 ps
CPU time 37.61 seconds
Started Dec 20 12:55:56 PM PST 23
Finished Dec 20 12:56:48 PM PST 23
Peak memory 267692 kb
Host smart-67e03b14-506a-498f-814b-5102339449c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582181762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.582181762
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2863512476
Short name T130
Test name
Test status
Simulation time 101156833 ps
CPU time 0.87 seconds
Started Dec 20 12:55:57 PM PST 23
Finished Dec 20 12:56:12 PM PST 23
Peak memory 208388 kb
Host smart-c80ced75-d219-4a33-ac3a-09c4f24470d4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863512476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.2863512476
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.2182309040
Short name T544
Test name
Test status
Simulation time 25066682 ps
CPU time 0.78 seconds
Started Dec 20 12:55:54 PM PST 23
Finished Dec 20 12:56:09 PM PST 23
Peak memory 209588 kb
Host smart-2768815d-a6c0-49ce-9dbe-5742097d2f94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182309040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.2182309040
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.2578238123
Short name T858
Test name
Test status
Simulation time 2451612134 ps
CPU time 12.93 seconds
Started Dec 20 12:55:59 PM PST 23
Finished Dec 20 12:56:25 PM PST 23
Peak memory 218332 kb
Host smart-1d1e0edf-910b-49c6-99d1-bbb7d2fd0909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578238123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.2578238123
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.318537484
Short name T674
Test name
Test status
Simulation time 1430130195 ps
CPU time 3.67 seconds
Started Dec 20 12:55:59 PM PST 23
Finished Dec 20 12:56:16 PM PST 23
Peak memory 209656 kb
Host smart-37b6449b-4d3a-441d-966b-5452a974431c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318537484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_ac
cess.318537484
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.650734161
Short name T772
Test name
Test status
Simulation time 577391829 ps
CPU time 3.65 seconds
Started Dec 20 12:56:02 PM PST 23
Finished Dec 20 12:56:18 PM PST 23
Peak memory 218280 kb
Host smart-88035c6f-4db0-44ac-b5c4-e971927347c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650734161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.650734161
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.3451904454
Short name T459
Test name
Test status
Simulation time 942731382 ps
CPU time 18.77 seconds
Started Dec 20 12:55:58 PM PST 23
Finished Dec 20 12:56:30 PM PST 23
Peak memory 218448 kb
Host smart-8b4a7e2d-fc79-4be6-8d36-dce1abe62f0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451904454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.3451904454
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.2151662928
Short name T322
Test name
Test status
Simulation time 254586308 ps
CPU time 7.02 seconds
Started Dec 20 12:56:03 PM PST 23
Finished Dec 20 12:56:22 PM PST 23
Peak memory 218176 kb
Host smart-e2f20fd5-720e-47d6-9f5b-6281c4a2a805
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151662928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.2151662928
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.3963447774
Short name T367
Test name
Test status
Simulation time 744193731 ps
CPU time 12.65 seconds
Started Dec 20 12:55:59 PM PST 23
Finished Dec 20 12:56:25 PM PST 23
Peak memory 218096 kb
Host smart-8cf48bf0-3ada-48e1-bbbc-c4fb53eb008c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963447774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
3963447774
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.1119585982
Short name T388
Test name
Test status
Simulation time 199779802 ps
CPU time 9 seconds
Started Dec 20 12:56:08 PM PST 23
Finished Dec 20 12:56:28 PM PST 23
Peak memory 218264 kb
Host smart-6af5fad8-7208-48bb-b3eb-6f2071ca0567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119585982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.1119585982
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.2799932037
Short name T957
Test name
Test status
Simulation time 258662624 ps
CPU time 2.4 seconds
Started Dec 20 12:56:06 PM PST 23
Finished Dec 20 12:56:20 PM PST 23
Peak memory 214424 kb
Host smart-413ebba1-915e-4c51-b559-9479454e8c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799932037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.2799932037
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.1419939087
Short name T506
Test name
Test status
Simulation time 197341645 ps
CPU time 25.69 seconds
Started Dec 20 12:55:52 PM PST 23
Finished Dec 20 12:56:33 PM PST 23
Peak memory 251164 kb
Host smart-798ecdff-1835-4290-85d5-3ce47c53bf0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419939087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.1419939087
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.2482841905
Short name T622
Test name
Test status
Simulation time 81998217 ps
CPU time 4.63 seconds
Started Dec 20 12:55:47 PM PST 23
Finished Dec 20 12:56:07 PM PST 23
Peak memory 226652 kb
Host smart-6cc6a4f9-95f7-4193-b34e-623aab05d6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482841905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2482841905
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.83922314
Short name T799
Test name
Test status
Simulation time 7768844264 ps
CPU time 248.37 seconds
Started Dec 20 12:55:56 PM PST 23
Finished Dec 20 01:00:19 PM PST 23
Peak memory 277220 kb
Host smart-53be9f5f-3799-4b22-a8d6-6590d24ff57f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83922314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.lc_ctrl_stress_all.83922314
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3849780580
Short name T42
Test name
Test status
Simulation time 24236893 ps
CPU time 1.41 seconds
Started Dec 20 12:55:57 PM PST 23
Finished Dec 20 12:56:12 PM PST 23
Peak memory 212740 kb
Host smart-a88df281-a47c-4fb2-81e8-a8399bc821c2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849780580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3849780580
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.3765934728
Short name T604
Test name
Test status
Simulation time 29936623 ps
CPU time 0.93 seconds
Started Dec 20 12:56:04 PM PST 23
Finished Dec 20 12:56:17 PM PST 23
Peak memory 209792 kb
Host smart-302a8c08-203b-4f16-86ff-0a37c3291978
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765934728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.3765934728
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2987099667
Short name T673
Test name
Test status
Simulation time 581237258 ps
CPU time 11.18 seconds
Started Dec 20 12:56:01 PM PST 23
Finished Dec 20 12:56:25 PM PST 23
Peak memory 218264 kb
Host smart-5b1865f0-b5cd-495c-874a-237b35b3dbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987099667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2987099667
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.573140420
Short name T873
Test name
Test status
Simulation time 1883728618 ps
CPU time 8.07 seconds
Started Dec 20 12:55:53 PM PST 23
Finished Dec 20 12:56:16 PM PST 23
Peak memory 209768 kb
Host smart-cb452838-32f9-49f1-8efa-9a8659ba6b06
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573140420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_ac
cess.573140420
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.8767667
Short name T120
Test name
Test status
Simulation time 127263247 ps
CPU time 1.61 seconds
Started Dec 20 12:56:03 PM PST 23
Finished Dec 20 12:56:17 PM PST 23
Peak memory 218100 kb
Host smart-5fe9bd82-30c7-4ccb-a8d1-eab529d0b848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8767667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.8767667
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.228643045
Short name T795
Test name
Test status
Simulation time 364388110 ps
CPU time 11.9 seconds
Started Dec 20 12:56:02 PM PST 23
Finished Dec 20 12:56:26 PM PST 23
Peak memory 219304 kb
Host smart-032746bd-3bb1-4d1e-88c8-4acbd22aa9c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228643045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.228643045
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.590194964
Short name T935
Test name
Test status
Simulation time 1228172078 ps
CPU time 11.76 seconds
Started Dec 20 12:56:04 PM PST 23
Finished Dec 20 12:56:28 PM PST 23
Peak memory 218168 kb
Host smart-13869644-41db-4f63-8f17-d13bef713e85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590194964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_di
gest.590194964
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.1176213232
Short name T452
Test name
Test status
Simulation time 1088350813 ps
CPU time 7.81 seconds
Started Dec 20 12:55:58 PM PST 23
Finished Dec 20 12:56:20 PM PST 23
Peak memory 218240 kb
Host smart-8b55efa1-53bf-49b8-a995-d26a51387408
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176213232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
1176213232
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.1483754739
Short name T518
Test name
Test status
Simulation time 182596826 ps
CPU time 8.06 seconds
Started Dec 20 12:55:56 PM PST 23
Finished Dec 20 12:56:18 PM PST 23
Peak memory 218332 kb
Host smart-29f8bd0c-d002-46af-9fe1-50feaf8f3468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483754739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.1483754739
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.2114862903
Short name T706
Test name
Test status
Simulation time 58364617 ps
CPU time 2.28 seconds
Started Dec 20 12:56:02 PM PST 23
Finished Dec 20 12:56:17 PM PST 23
Peak memory 213824 kb
Host smart-b722a874-f565-4a6c-b3a6-809d0eee02d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114862903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.2114862903
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.2421426281
Short name T729
Test name
Test status
Simulation time 838950471 ps
CPU time 18.8 seconds
Started Dec 20 12:55:56 PM PST 23
Finished Dec 20 12:56:29 PM PST 23
Peak memory 251188 kb
Host smart-f00f77f3-b147-4d66-b3ca-0667b7712011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421426281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.2421426281
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.4256226054
Short name T340
Test name
Test status
Simulation time 102369583 ps
CPU time 6.65 seconds
Started Dec 20 12:56:00 PM PST 23
Finished Dec 20 12:56:20 PM PST 23
Peak memory 250812 kb
Host smart-c1f1c0a4-4142-47a0-aa9e-86ac7ddab53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256226054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.4256226054
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.2914765481
Short name T524
Test name
Test status
Simulation time 3006545892 ps
CPU time 84.48 seconds
Started Dec 20 12:55:50 PM PST 23
Finished Dec 20 12:57:30 PM PST 23
Peak memory 226536 kb
Host smart-0e8b3b1a-b7ad-4a80-8678-6187854a6f5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914765481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.2914765481
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3445620334
Short name T89
Test name
Test status
Simulation time 19104936 ps
CPU time 1.2 seconds
Started Dec 20 12:55:59 PM PST 23
Finished Dec 20 12:56:13 PM PST 23
Peak memory 211612 kb
Host smart-3e8f4f58-8bd2-4309-a9bb-3eb8260a4cdd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445620334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.3445620334
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.2403781877
Short name T690
Test name
Test status
Simulation time 29996509 ps
CPU time 0.83 seconds
Started Dec 20 12:56:06 PM PST 23
Finished Dec 20 12:56:19 PM PST 23
Peak memory 209696 kb
Host smart-c0491417-c62b-4302-aea4-7959609a4995
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403781877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.2403781877
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.810041037
Short name T814
Test name
Test status
Simulation time 101241989 ps
CPU time 1.9 seconds
Started Dec 20 12:55:56 PM PST 23
Finished Dec 20 12:56:12 PM PST 23
Peak memory 209788 kb
Host smart-2b3e4445-b6fb-467d-8045-97a5e424b7d3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810041037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_ac
cess.810041037
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.265277785
Short name T733
Test name
Test status
Simulation time 75375483 ps
CPU time 2.11 seconds
Started Dec 20 12:56:02 PM PST 23
Finished Dec 20 12:56:17 PM PST 23
Peak memory 218276 kb
Host smart-f65c74dd-4619-45df-892c-c8ce1914d65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265277785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.265277785
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.1649064773
Short name T849
Test name
Test status
Simulation time 161859807 ps
CPU time 8.41 seconds
Started Dec 20 12:56:00 PM PST 23
Finished Dec 20 12:56:21 PM PST 23
Peak memory 218300 kb
Host smart-b217775a-18c5-41ef-ad76-30fdb3e51087
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649064773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.1649064773
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.3047681961
Short name T336
Test name
Test status
Simulation time 1117685829 ps
CPU time 11.2 seconds
Started Dec 20 12:56:08 PM PST 23
Finished Dec 20 12:56:31 PM PST 23
Peak memory 218164 kb
Host smart-017a4abb-259c-4364-9fe3-53a49b8efb64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047681961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.3047681961
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.2358534796
Short name T507
Test name
Test status
Simulation time 2018389651 ps
CPU time 5.8 seconds
Started Dec 20 12:55:56 PM PST 23
Finished Dec 20 12:56:16 PM PST 23
Peak memory 218040 kb
Host smart-5f69bb55-a473-40c3-bc38-1765da97ed7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358534796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
2358534796
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.2378698379
Short name T487
Test name
Test status
Simulation time 244288999 ps
CPU time 11.03 seconds
Started Dec 20 12:56:01 PM PST 23
Finished Dec 20 12:56:25 PM PST 23
Peak memory 218108 kb
Host smart-0a8f801f-282b-49b1-aa68-c6756a97935f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378698379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.2378698379
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.2858358213
Short name T69
Test name
Test status
Simulation time 707738018 ps
CPU time 2.91 seconds
Started Dec 20 12:55:59 PM PST 23
Finished Dec 20 12:56:15 PM PST 23
Peak memory 214048 kb
Host smart-7efb9814-ee51-4993-90f1-ea902c8f2933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858358213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.2858358213
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.683808981
Short name T599
Test name
Test status
Simulation time 483756746 ps
CPU time 31.21 seconds
Started Dec 20 12:56:03 PM PST 23
Finished Dec 20 12:56:47 PM PST 23
Peak memory 251112 kb
Host smart-842821c6-38e2-4024-8fa8-985d58fff183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683808981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.683808981
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.2926386872
Short name T854
Test name
Test status
Simulation time 201749384 ps
CPU time 6.51 seconds
Started Dec 20 12:55:52 PM PST 23
Finished Dec 20 12:56:13 PM PST 23
Peak memory 247212 kb
Host smart-2a1f7de9-ac36-4ec9-97a7-0824ccf786f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926386872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.2926386872
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.3752232645
Short name T17
Test name
Test status
Simulation time 1718832776 ps
CPU time 19.21 seconds
Started Dec 20 12:56:07 PM PST 23
Finished Dec 20 12:56:38 PM PST 23
Peak memory 251260 kb
Host smart-5e8a4319-c6c0-4cba-9ed4-a7032af7de88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752232645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.3752232645
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1309740479
Short name T596
Test name
Test status
Simulation time 112969960 ps
CPU time 0.99 seconds
Started Dec 20 12:55:47 PM PST 23
Finished Dec 20 12:56:04 PM PST 23
Peak memory 211584 kb
Host smart-1ff6ae3e-3562-445e-a513-aba028363eb8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309740479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.1309740479
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.1593313311
Short name T778
Test name
Test status
Simulation time 1192656822 ps
CPU time 13.71 seconds
Started Dec 20 12:56:00 PM PST 23
Finished Dec 20 12:56:27 PM PST 23
Peak memory 218136 kb
Host smart-0f5560ff-7790-4a35-a243-6668c6abbf8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593313311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.1593313311
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.85105204
Short name T888
Test name
Test status
Simulation time 2081826930 ps
CPU time 13.23 seconds
Started Dec 20 12:56:00 PM PST 23
Finished Dec 20 12:56:26 PM PST 23
Peak memory 209772 kb
Host smart-3a4d5875-8452-4348-bb07-f60adfe2e2c9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85105204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jta
g_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_acc
ess.85105204
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.683559851
Short name T401
Test name
Test status
Simulation time 52496253 ps
CPU time 2.22 seconds
Started Dec 20 12:56:03 PM PST 23
Finished Dec 20 12:56:17 PM PST 23
Peak memory 218304 kb
Host smart-0d184679-de99-4ca5-bc46-471fabf04a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683559851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.683559851
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.1994024107
Short name T649
Test name
Test status
Simulation time 1164701300 ps
CPU time 13.71 seconds
Started Dec 20 12:55:59 PM PST 23
Finished Dec 20 12:56:26 PM PST 23
Peak memory 219348 kb
Host smart-60c30cf6-ef5b-4c09-9a34-c70621ac5ab5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994024107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.1994024107
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.3682713688
Short name T642
Test name
Test status
Simulation time 6764311219 ps
CPU time 12.61 seconds
Started Dec 20 12:56:04 PM PST 23
Finished Dec 20 12:56:29 PM PST 23
Peak memory 218272 kb
Host smart-29946734-f0b7-4c9a-8835-2ace9a85c28a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682713688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.3682713688
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1037005848
Short name T732
Test name
Test status
Simulation time 778446774 ps
CPU time 6.08 seconds
Started Dec 20 12:56:04 PM PST 23
Finished Dec 20 12:56:22 PM PST 23
Peak memory 218328 kb
Host smart-c13cff8c-56e7-4ee4-83be-0c16bdaf8aa0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037005848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
1037005848
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.1743655195
Short name T812
Test name
Test status
Simulation time 943355494 ps
CPU time 6.29 seconds
Started Dec 20 12:56:24 PM PST 23
Finished Dec 20 12:56:37 PM PST 23
Peak memory 218156 kb
Host smart-e7ad59ea-758c-407c-9534-ff59a984d548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743655195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.1743655195
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.540311771
Short name T81
Test name
Test status
Simulation time 45069505 ps
CPU time 1.71 seconds
Started Dec 20 12:56:03 PM PST 23
Finished Dec 20 12:56:18 PM PST 23
Peak memory 213936 kb
Host smart-58f056e1-cba7-4175-85cd-0dcc9120f156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540311771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.540311771
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.2520732036
Short name T432
Test name
Test status
Simulation time 927069222 ps
CPU time 24.56 seconds
Started Dec 20 12:56:06 PM PST 23
Finished Dec 20 12:56:42 PM PST 23
Peak memory 251036 kb
Host smart-62b0ee01-eea6-4c58-9b6b-9d69bc823c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520732036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.2520732036
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.821144320
Short name T867
Test name
Test status
Simulation time 275023772 ps
CPU time 8.4 seconds
Started Dec 20 12:56:09 PM PST 23
Finished Dec 20 12:56:28 PM PST 23
Peak memory 251192 kb
Host smart-9fa22b8c-0e24-4670-9a33-422d9b0c94f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821144320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.821144320
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.3582655229
Short name T537
Test name
Test status
Simulation time 28307590702 ps
CPU time 158.57 seconds
Started Dec 20 12:56:08 PM PST 23
Finished Dec 20 12:58:58 PM PST 23
Peak memory 272612 kb
Host smart-a678b128-7308-4143-968c-d75998918ab3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582655229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.3582655229
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.1599350465
Short name T967
Test name
Test status
Simulation time 22689662851 ps
CPU time 484.34 seconds
Started Dec 20 12:55:54 PM PST 23
Finished Dec 20 01:04:14 PM PST 23
Peak memory 410508 kb
Host smart-73959b41-8ef2-442a-bc0f-34a213e1c724
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1599350465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.1599350465
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1491475796
Short name T480
Test name
Test status
Simulation time 32468634 ps
CPU time 0.72 seconds
Started Dec 20 12:56:08 PM PST 23
Finished Dec 20 12:56:20 PM PST 23
Peak memory 206632 kb
Host smart-a4198873-4f6a-4cde-8836-e6d967828889
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491475796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1491475796
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.1110401969
Short name T498
Test name
Test status
Simulation time 21436065 ps
CPU time 0.91 seconds
Started Dec 20 12:56:13 PM PST 23
Finished Dec 20 12:56:23 PM PST 23
Peak memory 209608 kb
Host smart-6c3c3cd8-de58-4bff-a324-287741159c0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110401969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.1110401969
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.954531359
Short name T726
Test name
Test status
Simulation time 326846265 ps
CPU time 9.15 seconds
Started Dec 20 12:56:04 PM PST 23
Finished Dec 20 12:56:25 PM PST 23
Peak memory 218352 kb
Host smart-1cc579d8-ced0-41bf-9b66-84f11adfc107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954531359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.954531359
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.4069811424
Short name T969
Test name
Test status
Simulation time 310483849 ps
CPU time 3.14 seconds
Started Dec 20 12:56:06 PM PST 23
Finished Dec 20 12:56:21 PM PST 23
Peak memory 218320 kb
Host smart-b0280a84-6d94-4061-a8de-08610f5776d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069811424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.4069811424
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.72656689
Short name T533
Test name
Test status
Simulation time 314398405 ps
CPU time 13.16 seconds
Started Dec 20 12:56:02 PM PST 23
Finished Dec 20 12:56:28 PM PST 23
Peak memory 219188 kb
Host smart-d2eb2433-2cfc-40ab-88d5-90c828d8b7ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72656689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.72656689
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.462443416
Short name T595
Test name
Test status
Simulation time 385147016 ps
CPU time 9.14 seconds
Started Dec 20 12:56:00 PM PST 23
Finished Dec 20 12:56:23 PM PST 23
Peak memory 218216 kb
Host smart-a351e776-d1aa-4d4b-96d3-ad786a02438c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462443416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_di
gest.462443416
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.1041201299
Short name T443
Test name
Test status
Simulation time 520779179 ps
CPU time 16.67 seconds
Started Dec 20 12:56:05 PM PST 23
Finished Dec 20 12:56:33 PM PST 23
Peak memory 218076 kb
Host smart-1ac7aa6b-552a-461c-b485-0516e373bedb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041201299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
1041201299
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.1886585043
Short name T927
Test name
Test status
Simulation time 949456538 ps
CPU time 6.95 seconds
Started Dec 20 12:56:03 PM PST 23
Finished Dec 20 12:56:23 PM PST 23
Peak memory 218260 kb
Host smart-ec77e508-ec20-4310-8a06-d16731f2ba1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886585043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.1886585043
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.3395379265
Short name T564
Test name
Test status
Simulation time 849452849 ps
CPU time 12.16 seconds
Started Dec 20 12:56:04 PM PST 23
Finished Dec 20 12:56:29 PM PST 23
Peak memory 214844 kb
Host smart-c3b4a1aa-1ba5-4ea0-a0f1-3b82c1b835ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395379265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3395379265
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.1983801840
Short name T372
Test name
Test status
Simulation time 304749321 ps
CPU time 23.76 seconds
Started Dec 20 12:56:06 PM PST 23
Finished Dec 20 12:56:41 PM PST 23
Peak memory 251100 kb
Host smart-7c1e7c2d-2eae-474b-942a-416034eace13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983801840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.1983801840
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.1162916522
Short name T866
Test name
Test status
Simulation time 329950440 ps
CPU time 2.94 seconds
Started Dec 20 12:56:06 PM PST 23
Finished Dec 20 12:56:21 PM PST 23
Peak memory 222052 kb
Host smart-4a4622f2-8742-428a-925f-f0bb3b29c670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162916522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.1162916522
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.3456948322
Short name T584
Test name
Test status
Simulation time 21341712438 ps
CPU time 184.76 seconds
Started Dec 20 12:56:01 PM PST 23
Finished Dec 20 12:59:19 PM PST 23
Peak memory 275444 kb
Host smart-3c77def4-4774-4de9-8868-d47c189ebd4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456948322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.3456948322
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3554987694
Short name T679
Test name
Test status
Simulation time 21060133 ps
CPU time 0.78 seconds
Started Dec 20 12:56:07 PM PST 23
Finished Dec 20 12:56:19 PM PST 23
Peak memory 208068 kb
Host smart-06cb7e67-4f5f-450f-860e-f8b2d3b9df37
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554987694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.3554987694
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.1462082072
Short name T985
Test name
Test status
Simulation time 81038055 ps
CPU time 0.98 seconds
Started Dec 20 12:56:31 PM PST 23
Finished Dec 20 12:56:38 PM PST 23
Peak memory 209756 kb
Host smart-13623b92-3049-4737-8527-8b1b1db21d5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462082072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.1462082072
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.2084154896
Short name T78
Test name
Test status
Simulation time 3258425870 ps
CPU time 13.51 seconds
Started Dec 20 12:56:18 PM PST 23
Finished Dec 20 12:56:39 PM PST 23
Peak memory 218324 kb
Host smart-bc91c495-ef63-499c-b27d-001f4bbd2a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084154896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.2084154896
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.240631398
Short name T9
Test name
Test status
Simulation time 293840148 ps
CPU time 2.54 seconds
Started Dec 20 12:56:18 PM PST 23
Finished Dec 20 12:56:28 PM PST 23
Peak memory 209716 kb
Host smart-8164008d-4748-4175-bce6-f76f4130d67a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240631398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_ac
cess.240631398
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2301164159
Short name T445
Test name
Test status
Simulation time 161453976 ps
CPU time 1.74 seconds
Started Dec 20 12:56:20 PM PST 23
Finished Dec 20 12:56:29 PM PST 23
Peak memory 218348 kb
Host smart-4b90412d-e8fa-4b5b-b98e-32f1749764f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301164159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2301164159
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.2136958801
Short name T803
Test name
Test status
Simulation time 1805071470 ps
CPU time 11.47 seconds
Started Dec 20 12:56:28 PM PST 23
Finished Dec 20 12:56:46 PM PST 23
Peak memory 218604 kb
Host smart-417c1661-ac00-4893-873f-012346101c27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136958801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.2136958801
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.1735305702
Short name T930
Test name
Test status
Simulation time 243349860 ps
CPU time 9.98 seconds
Started Dec 20 12:56:21 PM PST 23
Finished Dec 20 12:56:37 PM PST 23
Peak memory 218200 kb
Host smart-6284b836-040f-4409-88ab-cb70e1715f92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735305702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.1735305702
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.3566564024
Short name T749
Test name
Test status
Simulation time 669530450 ps
CPU time 10.96 seconds
Started Dec 20 12:56:11 PM PST 23
Finished Dec 20 12:56:32 PM PST 23
Peak memory 218216 kb
Host smart-7b68206f-c802-4c57-8f72-77fd931eb9ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566564024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
3566564024
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.2305520914
Short name T843
Test name
Test status
Simulation time 1172212109 ps
CPU time 10.91 seconds
Started Dec 20 12:56:25 PM PST 23
Finished Dec 20 12:56:43 PM PST 23
Peak memory 218156 kb
Host smart-0aa64b4b-2618-49e7-83b8-00359d6b3cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305520914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.2305520914
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.2924307809
Short name T899
Test name
Test status
Simulation time 114713497 ps
CPU time 2 seconds
Started Dec 20 12:56:07 PM PST 23
Finished Dec 20 12:56:20 PM PST 23
Peak memory 213800 kb
Host smart-f0a06db0-f823-430a-9149-3c968f501960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924307809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.2924307809
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.358484547
Short name T425
Test name
Test status
Simulation time 1028774209 ps
CPU time 24.35 seconds
Started Dec 20 12:56:11 PM PST 23
Finished Dec 20 12:56:45 PM PST 23
Peak memory 251136 kb
Host smart-cb36fc9e-171a-491e-87c4-c442b2395051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358484547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.358484547
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.940490829
Short name T669
Test name
Test status
Simulation time 223084173 ps
CPU time 3.16 seconds
Started Dec 20 12:56:20 PM PST 23
Finished Dec 20 12:56:30 PM PST 23
Peak memory 222344 kb
Host smart-06ce0eef-b965-4c32-8769-51eb6a50b4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940490829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.940490829
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.1720900888
Short name T96
Test name
Test status
Simulation time 2528971901 ps
CPU time 90.04 seconds
Started Dec 20 12:56:18 PM PST 23
Finished Dec 20 12:57:56 PM PST 23
Peak memory 276384 kb
Host smart-8f11cd13-47b8-40ac-a341-0473bfc8929f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720900888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.1720900888
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.196710408
Short name T464
Test name
Test status
Simulation time 57052002 ps
CPU time 0.92 seconds
Started Dec 20 12:56:02 PM PST 23
Finished Dec 20 12:56:15 PM PST 23
Peak memory 212704 kb
Host smart-571defc4-3a2f-4473-bb70-1d1acc6cbdc7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196710408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ct
rl_volatile_unlock_smoke.196710408
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.1645603141
Short name T436
Test name
Test status
Simulation time 57915755 ps
CPU time 0.84 seconds
Started Dec 20 12:56:11 PM PST 23
Finished Dec 20 12:56:22 PM PST 23
Peak memory 208436 kb
Host smart-5d18e1fd-beb7-4d0a-8b45-aab4cf1f054e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645603141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.1645603141
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.3379582582
Short name T806
Test name
Test status
Simulation time 255839256 ps
CPU time 11.01 seconds
Started Dec 20 12:56:20 PM PST 23
Finished Dec 20 12:56:38 PM PST 23
Peak memory 218124 kb
Host smart-25c867c5-af7a-4a77-92e4-dc3fa42754cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379582582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.3379582582
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.1875823779
Short name T641
Test name
Test status
Simulation time 635249403 ps
CPU time 7.99 seconds
Started Dec 20 12:56:10 PM PST 23
Finished Dec 20 12:56:28 PM PST 23
Peak memory 209712 kb
Host smart-d8b62fe9-86b6-4f6b-853b-eb727fe001fd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875823779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_a
ccess.1875823779
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.3702245269
Short name T981
Test name
Test status
Simulation time 533210581 ps
CPU time 3.43 seconds
Started Dec 20 12:56:17 PM PST 23
Finished Dec 20 12:56:28 PM PST 23
Peak memory 218176 kb
Host smart-a23f3a75-0815-48d3-ae2d-6eed5424cfb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702245269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.3702245269
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.2819380130
Short name T484
Test name
Test status
Simulation time 567455869 ps
CPU time 16.11 seconds
Started Dec 20 12:56:18 PM PST 23
Finished Dec 20 12:56:42 PM PST 23
Peak memory 219268 kb
Host smart-e34ad123-a578-4325-a872-4cf315296a09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819380130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.2819380130
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.1130642467
Short name T361
Test name
Test status
Simulation time 303452715 ps
CPU time 12.91 seconds
Started Dec 20 12:56:10 PM PST 23
Finished Dec 20 12:56:33 PM PST 23
Peak memory 218196 kb
Host smart-b4f3a0ed-c279-4de3-92a8-48cc47b04376
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130642467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.1130642467
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.91460325
Short name T370
Test name
Test status
Simulation time 1026429269 ps
CPU time 9.04 seconds
Started Dec 20 12:56:10 PM PST 23
Finished Dec 20 12:56:29 PM PST 23
Peak memory 218308 kb
Host smart-4ceed8fc-384d-4682-b95c-35cdae7d967d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91460325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.91460325
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.635367681
Short name T627
Test name
Test status
Simulation time 167778287 ps
CPU time 6.33 seconds
Started Dec 20 12:56:10 PM PST 23
Finished Dec 20 12:56:27 PM PST 23
Peak memory 218280 kb
Host smart-eaa26cad-9ec6-44e2-857b-3b4abf5e5e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635367681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.635367681
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.1589085554
Short name T800
Test name
Test status
Simulation time 58865710 ps
CPU time 2.48 seconds
Started Dec 20 12:56:20 PM PST 23
Finished Dec 20 12:56:30 PM PST 23
Peak memory 214268 kb
Host smart-746b6e14-30a2-466f-88a2-d083274f5f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589085554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1589085554
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.3556688872
Short name T720
Test name
Test status
Simulation time 836561317 ps
CPU time 19.33 seconds
Started Dec 20 12:56:25 PM PST 23
Finished Dec 20 12:56:51 PM PST 23
Peak memory 251084 kb
Host smart-b2fdb22d-fa80-423f-8899-abb9a57146d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556688872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.3556688872
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.3619209231
Short name T333
Test name
Test status
Simulation time 128061767 ps
CPU time 11.19 seconds
Started Dec 20 12:56:14 PM PST 23
Finished Dec 20 12:56:35 PM PST 23
Peak memory 251260 kb
Host smart-1253ac06-c390-4d64-a7e5-a6dbbd2c8d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619209231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.3619209231
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.3858899216
Short name T135
Test name
Test status
Simulation time 64108510404 ps
CPU time 256.56 seconds
Started Dec 20 12:56:25 PM PST 23
Finished Dec 20 01:00:49 PM PST 23
Peak memory 281064 kb
Host smart-a584d0e7-9fba-4a53-b0b6-03b207fd6358
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858899216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.3858899216
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1966851899
Short name T785
Test name
Test status
Simulation time 14482760 ps
CPU time 1.07 seconds
Started Dec 20 12:56:12 PM PST 23
Finished Dec 20 12:56:23 PM PST 23
Peak memory 211584 kb
Host smart-1ead974f-0e28-4556-9183-9b39acd00e95
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966851899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.1966851899
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.1439505500
Short name T346
Test name
Test status
Simulation time 99519448 ps
CPU time 0.99 seconds
Started Dec 20 12:54:58 PM PST 23
Finished Dec 20 12:55:19 PM PST 23
Peak memory 209728 kb
Host smart-2c496bbf-391c-429a-af62-92e0c7fafe2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439505500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.1439505500
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.2299477933
Short name T618
Test name
Test status
Simulation time 19478060 ps
CPU time 0.77 seconds
Started Dec 20 12:55:00 PM PST 23
Finished Dec 20 12:55:21 PM PST 23
Peak memory 209484 kb
Host smart-bd1af690-9ff8-4fa6-94c7-aaf1567304dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299477933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.2299477933
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.3104170718
Short name T53
Test name
Test status
Simulation time 794046752 ps
CPU time 14.64 seconds
Started Dec 20 12:54:56 PM PST 23
Finished Dec 20 12:55:28 PM PST 23
Peak memory 218156 kb
Host smart-dc0e2a47-31d3-4316-a7bf-893390928d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104170718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.3104170718
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.3312002843
Short name T908
Test name
Test status
Simulation time 773034245 ps
CPU time 9.12 seconds
Started Dec 20 12:54:58 PM PST 23
Finished Dec 20 12:55:27 PM PST 23
Peak memory 209688 kb
Host smart-dc5ed788-eb8f-40a0-a522-0a9af70fc2f1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312002843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_ac
cess.3312002843
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.1988113561
Short name T988
Test name
Test status
Simulation time 8389989677 ps
CPU time 55.1 seconds
Started Dec 20 12:55:02 PM PST 23
Finished Dec 20 12:56:18 PM PST 23
Peak memory 219284 kb
Host smart-bc1ddfc1-b7d8-4d38-b6f6-5008c964e1c6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988113561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.1988113561
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.1451918150
Short name T5
Test name
Test status
Simulation time 454506566 ps
CPU time 7.77 seconds
Started Dec 20 12:55:13 PM PST 23
Finished Dec 20 12:55:38 PM PST 23
Peak memory 218004 kb
Host smart-4d23da18-6a1b-47a5-a35d-aed677357b17
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451918150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_
priority.1451918150
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.1036956647
Short name T696
Test name
Test status
Simulation time 362862694 ps
CPU time 11.08 seconds
Started Dec 20 12:55:00 PM PST 23
Finished Dec 20 12:55:32 PM PST 23
Peak memory 218228 kb
Host smart-54cb865b-02f4-43cf-b222-ffa5b89a14ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036956647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.1036956647
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2731004470
Short name T512
Test name
Test status
Simulation time 8025749450 ps
CPU time 15.76 seconds
Started Dec 20 12:55:07 PM PST 23
Finished Dec 20 12:55:44 PM PST 23
Peak memory 213940 kb
Host smart-7091efb4-e676-4aff-85a7-7fae437f7191
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731004470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.2731004470
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.1824667786
Short name T539
Test name
Test status
Simulation time 1079763016 ps
CPU time 3.8 seconds
Started Dec 20 12:55:00 PM PST 23
Finished Dec 20 12:55:23 PM PST 23
Peak memory 213116 kb
Host smart-1d690df0-ac49-4f00-98b7-9ce6fe6f1fdb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824667786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
1824667786
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.1644529247
Short name T680
Test name
Test status
Simulation time 1953870438 ps
CPU time 68.01 seconds
Started Dec 20 12:55:01 PM PST 23
Finished Dec 20 12:56:30 PM PST 23
Peak memory 252068 kb
Host smart-a259ea8f-2b81-48e9-ad9e-443f8d362e94
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644529247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.1644529247
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.40890823
Short name T454
Test name
Test status
Simulation time 394886724 ps
CPU time 12.86 seconds
Started Dec 20 12:54:59 PM PST 23
Finished Dec 20 12:55:32 PM PST 23
Peak memory 251208 kb
Host smart-112b5715-9c37-41c4-b313-b1d54def3ea3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40890823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jt
ag_state_post_trans.40890823
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.1203672369
Short name T836
Test name
Test status
Simulation time 52547969 ps
CPU time 1.79 seconds
Started Dec 20 12:55:01 PM PST 23
Finished Dec 20 12:55:24 PM PST 23
Peak memory 218288 kb
Host smart-e363c2e9-71f9-4e4a-833b-65dbf9b73fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203672369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.1203672369
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.3065774458
Short name T924
Test name
Test status
Simulation time 1281173977 ps
CPU time 12.1 seconds
Started Dec 20 12:54:59 PM PST 23
Finished Dec 20 12:55:32 PM PST 23
Peak memory 213860 kb
Host smart-bdec37de-047b-407f-b8c7-487ce1cd928c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065774458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.3065774458
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.3352505421
Short name T831
Test name
Test status
Simulation time 476957659 ps
CPU time 9.41 seconds
Started Dec 20 12:55:15 PM PST 23
Finished Dec 20 12:55:42 PM PST 23
Peak memory 219316 kb
Host smart-d15cb02e-f77e-4c53-b814-721a9430f664
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352505421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.3352505421
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.3377183949
Short name T698
Test name
Test status
Simulation time 592152583 ps
CPU time 11.34 seconds
Started Dec 20 12:55:02 PM PST 23
Finished Dec 20 12:55:34 PM PST 23
Peak memory 218208 kb
Host smart-77c9615f-907a-4b96-83d1-c87dee82b54f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377183949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.3377183949
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.126741491
Short name T763
Test name
Test status
Simulation time 2737591089 ps
CPU time 10.94 seconds
Started Dec 20 12:54:59 PM PST 23
Finished Dec 20 12:55:31 PM PST 23
Peak memory 218296 kb
Host smart-ac3b57c0-5bbf-4f8a-abc9-d1fa1eef07f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126741491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.126741491
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.1161070378
Short name T907
Test name
Test status
Simulation time 713890732 ps
CPU time 8.99 seconds
Started Dec 20 12:55:01 PM PST 23
Finished Dec 20 12:55:31 PM PST 23
Peak memory 218300 kb
Host smart-2f2efb92-038d-432f-a207-e80567291107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161070378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.1161070378
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.2276202069
Short name T365
Test name
Test status
Simulation time 216418614 ps
CPU time 1.87 seconds
Started Dec 20 12:55:16 PM PST 23
Finished Dec 20 12:55:35 PM PST 23
Peak memory 213524 kb
Host smart-e0a58495-0aee-4197-9369-25b54b7532f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276202069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.2276202069
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.3196928779
Short name T804
Test name
Test status
Simulation time 228973592 ps
CPU time 23.12 seconds
Started Dec 20 12:55:29 PM PST 23
Finished Dec 20 12:56:08 PM PST 23
Peak memory 251128 kb
Host smart-e4877d4d-f2f1-41bd-bb3c-1afa6f02dcea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196928779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3196928779
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.1993202399
Short name T420
Test name
Test status
Simulation time 61980600 ps
CPU time 6.76 seconds
Started Dec 20 12:54:59 PM PST 23
Finished Dec 20 12:55:26 PM PST 23
Peak memory 250640 kb
Host smart-c485a03a-8c4d-461f-988f-391750e36165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993202399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1993202399
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.2915210866
Short name T693
Test name
Test status
Simulation time 4100275160 ps
CPU time 137.38 seconds
Started Dec 20 12:55:17 PM PST 23
Finished Dec 20 12:57:54 PM PST 23
Peak memory 275676 kb
Host smart-5e824081-eec8-437b-b931-ec3915ec19d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915210866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.2915210866
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2418139385
Short name T743
Test name
Test status
Simulation time 50896062 ps
CPU time 0.87 seconds
Started Dec 20 12:55:22 PM PST 23
Finished Dec 20 12:55:37 PM PST 23
Peak memory 211544 kb
Host smart-c1d92e67-dea0-4a54-9781-57b56c98c2e9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418139385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.2418139385
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.3893650054
Short name T652
Test name
Test status
Simulation time 154702923 ps
CPU time 0.94 seconds
Started Dec 20 12:56:14 PM PST 23
Finished Dec 20 12:56:24 PM PST 23
Peak memory 209776 kb
Host smart-414c12b4-73fb-4929-bffd-74340dbbf5c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893650054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.3893650054
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.2311882135
Short name T606
Test name
Test status
Simulation time 426969480 ps
CPU time 15.75 seconds
Started Dec 20 12:56:17 PM PST 23
Finished Dec 20 12:56:41 PM PST 23
Peak memory 218112 kb
Host smart-b4d424d5-ee18-4b73-8ce3-ae7747559c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311882135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.2311882135
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.1338102637
Short name T32
Test name
Test status
Simulation time 5747623465 ps
CPU time 10.78 seconds
Started Dec 20 12:56:16 PM PST 23
Finished Dec 20 12:56:35 PM PST 23
Peak memory 209812 kb
Host smart-e5735c9b-1220-4dad-8637-84f399c039a3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338102637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_a
ccess.1338102637
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.934242105
Short name T407
Test name
Test status
Simulation time 25538180 ps
CPU time 1.79 seconds
Started Dec 20 12:56:12 PM PST 23
Finished Dec 20 12:56:23 PM PST 23
Peak memory 218388 kb
Host smart-763d216c-eca7-471a-a5fd-a51e3ad321ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934242105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.934242105
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.2352135540
Short name T612
Test name
Test status
Simulation time 243842924 ps
CPU time 9.7 seconds
Started Dec 20 12:56:12 PM PST 23
Finished Dec 20 12:56:31 PM PST 23
Peak memory 218148 kb
Host smart-21c5af04-92bd-454d-98a9-05a5f0e75d2e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352135540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.2352135540
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.778053778
Short name T870
Test name
Test status
Simulation time 530006311 ps
CPU time 11.29 seconds
Started Dec 20 12:56:30 PM PST 23
Finished Dec 20 12:56:47 PM PST 23
Peak memory 218100 kb
Host smart-0177ee8d-c94d-4d21-8b98-9a62cd095bd8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778053778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_di
gest.778053778
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1228207051
Short name T14
Test name
Test status
Simulation time 2934259084 ps
CPU time 8.61 seconds
Started Dec 20 12:56:19 PM PST 23
Finished Dec 20 12:56:35 PM PST 23
Peak memory 218176 kb
Host smart-a5a5a8a7-0834-4bc6-93f2-4689df9ceb62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228207051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
1228207051
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.1050855342
Short name T486
Test name
Test status
Simulation time 899802524 ps
CPU time 9.04 seconds
Started Dec 20 12:56:18 PM PST 23
Finished Dec 20 12:56:39 PM PST 23
Peak memory 218100 kb
Host smart-68571a88-5dcd-4ec7-83e8-066719d423d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050855342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.1050855342
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.1544064426
Short name T718
Test name
Test status
Simulation time 126434960 ps
CPU time 1.92 seconds
Started Dec 20 12:56:17 PM PST 23
Finished Dec 20 12:56:27 PM PST 23
Peak memory 213684 kb
Host smart-785c8ae5-d607-465f-94dc-7712a7240903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544064426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.1544064426
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.338914228
Short name T787
Test name
Test status
Simulation time 1039822799 ps
CPU time 23.24 seconds
Started Dec 20 12:56:11 PM PST 23
Finished Dec 20 12:56:45 PM PST 23
Peak memory 251184 kb
Host smart-6e998654-cc0e-44b4-a127-1199ac79668d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338914228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.338914228
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.3603511165
Short name T338
Test name
Test status
Simulation time 184445446 ps
CPU time 6.25 seconds
Started Dec 20 12:56:32 PM PST 23
Finished Dec 20 12:56:43 PM PST 23
Peak memory 246692 kb
Host smart-3021a3d4-2589-42d7-b0dd-bacee54d6c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603511165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.3603511165
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.1066670352
Short name T911
Test name
Test status
Simulation time 31403591542 ps
CPU time 422.23 seconds
Started Dec 20 12:56:11 PM PST 23
Finished Dec 20 01:03:24 PM PST 23
Peak memory 226560 kb
Host smart-aa93b220-2e5a-45b9-8d1b-f9df179bdc86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066670352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.1066670352
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.1484509149
Short name T45
Test name
Test status
Simulation time 26720540 ps
CPU time 0.95 seconds
Started Dec 20 12:56:21 PM PST 23
Finished Dec 20 12:56:29 PM PST 23
Peak memory 208404 kb
Host smart-cbd1faee-07bc-4f81-a2dc-03cf68320d02
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484509149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.1484509149
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.3126232992
Short name T428
Test name
Test status
Simulation time 33328724 ps
CPU time 1.08 seconds
Started Dec 20 12:56:23 PM PST 23
Finished Dec 20 12:56:31 PM PST 23
Peak memory 209796 kb
Host smart-c02ea30e-1d1c-48e2-8e1f-f95a362ed5d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126232992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3126232992
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.423199548
Short name T457
Test name
Test status
Simulation time 441879123 ps
CPU time 17.84 seconds
Started Dec 20 12:56:21 PM PST 23
Finished Dec 20 12:56:45 PM PST 23
Peak memory 218300 kb
Host smart-83918cff-a2e7-4067-aca8-3f802c20bacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423199548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.423199548
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.3278004609
Short name T869
Test name
Test status
Simulation time 717589173 ps
CPU time 2.7 seconds
Started Dec 20 12:56:13 PM PST 23
Finished Dec 20 12:56:25 PM PST 23
Peak memory 209604 kb
Host smart-82e0f395-6fb3-4804-aabf-9cac81909f2d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278004609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_a
ccess.3278004609
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.3126679799
Short name T574
Test name
Test status
Simulation time 34685738 ps
CPU time 1.45 seconds
Started Dec 20 12:56:20 PM PST 23
Finished Dec 20 12:56:28 PM PST 23
Peak memory 218348 kb
Host smart-f3c8a273-a7b6-4727-8c03-6fc0aa62d1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126679799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.3126679799
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.2271579324
Short name T440
Test name
Test status
Simulation time 5776525769 ps
CPU time 9.69 seconds
Started Dec 20 12:56:31 PM PST 23
Finished Dec 20 12:56:46 PM PST 23
Peak memory 219176 kb
Host smart-13f4cade-c742-486f-96c0-69ac8dee870d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271579324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2271579324
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.1162619252
Short name T940
Test name
Test status
Simulation time 2848862305 ps
CPU time 9.22 seconds
Started Dec 20 12:56:39 PM PST 23
Finished Dec 20 12:56:53 PM PST 23
Peak memory 218236 kb
Host smart-7bc36bad-d82a-45af-827f-5e7a54598dbe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162619252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.1162619252
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.961951696
Short name T786
Test name
Test status
Simulation time 836283377 ps
CPU time 7.7 seconds
Started Dec 20 12:56:28 PM PST 23
Finished Dec 20 12:56:43 PM PST 23
Peak memory 218068 kb
Host smart-a35650b3-754c-4887-b9d0-ca1f880afd6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961951696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.961951696
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.3898380215
Short name T766
Test name
Test status
Simulation time 2151514122 ps
CPU time 9.63 seconds
Started Dec 20 12:56:12 PM PST 23
Finished Dec 20 12:56:31 PM PST 23
Peak memory 218212 kb
Host smart-fdcdc0b3-c90b-4068-ab85-96b5ace9c84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898380215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.3898380215
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.3298391686
Short name T970
Test name
Test status
Simulation time 60609315 ps
CPU time 3.51 seconds
Started Dec 20 12:56:18 PM PST 23
Finished Dec 20 12:56:29 PM PST 23
Peak memory 214352 kb
Host smart-c87086e6-cbe0-4620-914f-63050e443f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298391686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.3298391686
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.3818796852
Short name T16
Test name
Test status
Simulation time 234172638 ps
CPU time 21.73 seconds
Started Dec 20 12:56:35 PM PST 23
Finished Dec 20 12:57:03 PM PST 23
Peak memory 251172 kb
Host smart-1f4c9039-b659-45ed-9848-9cce4816fdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818796852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.3818796852
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.180578056
Short name T587
Test name
Test status
Simulation time 169761513 ps
CPU time 2.74 seconds
Started Dec 20 12:56:18 PM PST 23
Finished Dec 20 12:56:28 PM PST 23
Peak memory 226680 kb
Host smart-07f2f682-20fd-4141-b80f-390bbedaad66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180578056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.180578056
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.2768860954
Short name T976
Test name
Test status
Simulation time 2491322609 ps
CPU time 115.38 seconds
Started Dec 20 12:56:26 PM PST 23
Finished Dec 20 12:58:28 PM PST 23
Peak memory 252352 kb
Host smart-3ea2bb54-7500-467d-aa1b-50fe185f69e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768860954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.2768860954
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2883940353
Short name T566
Test name
Test status
Simulation time 13889384 ps
CPU time 0.96 seconds
Started Dec 20 12:56:25 PM PST 23
Finished Dec 20 12:56:33 PM PST 23
Peak memory 208488 kb
Host smart-9d549177-4a13-4a57-b585-75e5d9f1a960
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883940353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.2883940353
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.3109485237
Short name T555
Test name
Test status
Simulation time 54812761 ps
CPU time 1.12 seconds
Started Dec 20 12:56:22 PM PST 23
Finished Dec 20 12:56:30 PM PST 23
Peak memory 208552 kb
Host smart-94f63ff1-6b46-4a3c-84bc-39a57456e72b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109485237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.3109485237
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.2563109177
Short name T55
Test name
Test status
Simulation time 392478121 ps
CPU time 11.89 seconds
Started Dec 20 12:56:30 PM PST 23
Finished Dec 20 12:56:48 PM PST 23
Peak memory 218052 kb
Host smart-5911c31b-49cc-4adb-affc-5cd08da88ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563109177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.2563109177
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.409635649
Short name T28
Test name
Test status
Simulation time 305298389 ps
CPU time 8.39 seconds
Started Dec 20 12:56:42 PM PST 23
Finished Dec 20 12:56:55 PM PST 23
Peak memory 209868 kb
Host smart-94c45ad9-4195-4e1e-9ba0-e1bfa67cb354
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409635649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_ac
cess.409635649
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.750908352
Short name T782
Test name
Test status
Simulation time 433195741 ps
CPU time 2.39 seconds
Started Dec 20 12:56:25 PM PST 23
Finished Dec 20 12:56:35 PM PST 23
Peak memory 218056 kb
Host smart-43063887-3133-47b4-a99a-ed0a85682450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750908352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.750908352
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.2024485567
Short name T941
Test name
Test status
Simulation time 518550941 ps
CPU time 10.84 seconds
Started Dec 20 12:56:38 PM PST 23
Finished Dec 20 12:56:54 PM PST 23
Peak memory 219280 kb
Host smart-cfcf9139-c2ae-4bf1-b70b-e8e05e179233
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024485567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.2024485567
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.854640841
Short name T343
Test name
Test status
Simulation time 1729639844 ps
CPU time 10.8 seconds
Started Dec 20 12:56:45 PM PST 23
Finished Dec 20 12:57:01 PM PST 23
Peak memory 218148 kb
Host smart-ef6cba59-5a89-44ba-93e7-136fb0454dff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854640841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_di
gest.854640841
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.1402278411
Short name T582
Test name
Test status
Simulation time 537523866 ps
CPU time 9.7 seconds
Started Dec 20 12:56:44 PM PST 23
Finished Dec 20 12:56:58 PM PST 23
Peak memory 218204 kb
Host smart-b1bb1ad8-a027-45e3-8666-eae57bf1b179
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402278411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
1402278411
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.1297909061
Short name T727
Test name
Test status
Simulation time 294923656 ps
CPU time 10.61 seconds
Started Dec 20 12:56:31 PM PST 23
Finished Dec 20 12:56:47 PM PST 23
Peak memory 218332 kb
Host smart-1786a345-0960-4713-bb80-e00c04c51a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297909061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.1297909061
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.2799180282
Short name T640
Test name
Test status
Simulation time 285180302 ps
CPU time 2.82 seconds
Started Dec 20 12:56:28 PM PST 23
Finished Dec 20 12:56:37 PM PST 23
Peak memory 213744 kb
Host smart-206e0716-0e48-4c29-ab51-8ffded2b4271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799180282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2799180282
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.1166416056
Short name T917
Test name
Test status
Simulation time 836160003 ps
CPU time 21.87 seconds
Started Dec 20 12:56:26 PM PST 23
Finished Dec 20 12:56:54 PM PST 23
Peak memory 251184 kb
Host smart-e2923dea-6341-4821-a771-16412f1fef00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166416056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.1166416056
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.370775862
Short name T951
Test name
Test status
Simulation time 114299104 ps
CPU time 6.29 seconds
Started Dec 20 12:56:39 PM PST 23
Finished Dec 20 12:56:51 PM PST 23
Peak memory 250672 kb
Host smart-2c774342-2914-4e55-a3db-5d1e25a3fcf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370775862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.370775862
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.434154416
Short name T375
Test name
Test status
Simulation time 12658555404 ps
CPU time 214.67 seconds
Started Dec 20 12:56:36 PM PST 23
Finished Dec 20 01:00:16 PM PST 23
Peak memory 272288 kb
Host smart-6891279a-8516-4f7f-90e6-5afda1ed8916
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434154416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.434154416
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3429938573
Short name T905
Test name
Test status
Simulation time 15940117 ps
CPU time 0.93 seconds
Started Dec 20 12:56:33 PM PST 23
Finished Dec 20 12:56:40 PM PST 23
Peak memory 208352 kb
Host smart-955a4fc3-f718-4e53-8e0e-b319197a223d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429938573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.3429938573
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.2393312175
Short name T851
Test name
Test status
Simulation time 11582556 ps
CPU time 0.96 seconds
Started Dec 20 12:56:58 PM PST 23
Finished Dec 20 12:57:11 PM PST 23
Peak memory 209784 kb
Host smart-dedbcfac-4da9-4af5-8fcc-ffa816c47d18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393312175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.2393312175
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.3502480225
Short name T565
Test name
Test status
Simulation time 241812744 ps
CPU time 8.22 seconds
Started Dec 20 12:56:45 PM PST 23
Finished Dec 20 12:56:58 PM PST 23
Peak memory 218256 kb
Host smart-7a4b5cfd-75bf-4c20-aef5-4e9e532ab2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502480225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3502480225
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.2717922093
Short name T447
Test name
Test status
Simulation time 528236147 ps
CPU time 6.97 seconds
Started Dec 20 12:56:50 PM PST 23
Finished Dec 20 12:57:04 PM PST 23
Peak memory 209740 kb
Host smart-4267af19-592b-4ba0-a45d-a83cfa2b404c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717922093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_a
ccess.2717922093
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.1915083814
Short name T325
Test name
Test status
Simulation time 121449692 ps
CPU time 2.51 seconds
Started Dec 20 12:56:45 PM PST 23
Finished Dec 20 12:56:52 PM PST 23
Peak memory 218256 kb
Host smart-a21e2493-a5d2-4d7d-9e79-5e58c70edfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915083814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.1915083814
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.2718207064
Short name T637
Test name
Test status
Simulation time 2934012008 ps
CPU time 12.79 seconds
Started Dec 20 12:56:34 PM PST 23
Finished Dec 20 12:56:53 PM PST 23
Peak memory 219384 kb
Host smart-536a9880-7c71-43d9-a47d-96d3f8a905b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718207064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.2718207064
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.232197378
Short name T712
Test name
Test status
Simulation time 873961195 ps
CPU time 14.58 seconds
Started Dec 20 12:57:02 PM PST 23
Finished Dec 20 12:57:33 PM PST 23
Peak memory 218232 kb
Host smart-a20bb0bf-354e-462d-bc69-740a5776ea02
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232197378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_di
gest.232197378
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.4028421211
Short name T672
Test name
Test status
Simulation time 630312526 ps
CPU time 21.56 seconds
Started Dec 20 12:57:15 PM PST 23
Finished Dec 20 12:57:54 PM PST 23
Peak memory 218196 kb
Host smart-3630acaa-47a7-4507-9d12-a4de80c26590
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028421211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
4028421211
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.4239711211
Short name T390
Test name
Test status
Simulation time 186199658 ps
CPU time 3.32 seconds
Started Dec 20 12:56:48 PM PST 23
Finished Dec 20 12:56:57 PM PST 23
Peak memory 214288 kb
Host smart-90c1de85-c04f-4569-a42b-8682e6f1afea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239711211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.4239711211
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.2208265227
Short name T463
Test name
Test status
Simulation time 320373681 ps
CPU time 20.28 seconds
Started Dec 20 12:56:41 PM PST 23
Finished Dec 20 12:57:06 PM PST 23
Peak memory 251248 kb
Host smart-4d368ad0-4488-4498-8d9b-89d045eaa12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208265227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2208265227
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.3040095601
Short name T661
Test name
Test status
Simulation time 267452834 ps
CPU time 8.33 seconds
Started Dec 20 12:57:01 PM PST 23
Finished Dec 20 12:57:26 PM PST 23
Peak memory 251092 kb
Host smart-6ca0a51f-30c9-4217-9650-3dea9be0b551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040095601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.3040095601
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.2047648226
Short name T746
Test name
Test status
Simulation time 288266089 ps
CPU time 24.71 seconds
Started Dec 20 12:56:50 PM PST 23
Finished Dec 20 12:57:21 PM PST 23
Peak memory 245800 kb
Host smart-d306ed02-7ca8-470e-9559-00f4a180290a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047648226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.2047648226
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.3291472174
Short name T46
Test name
Test status
Simulation time 18102207 ps
CPU time 0.85 seconds
Started Dec 20 12:56:44 PM PST 23
Finished Dec 20 12:56:50 PM PST 23
Peak memory 208376 kb
Host smart-4b97a077-3915-47f4-90fb-6c394ac3c07c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291472174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.3291472174
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.2974291227
Short name T414
Test name
Test status
Simulation time 16590539 ps
CPU time 0.85 seconds
Started Dec 20 12:56:29 PM PST 23
Finished Dec 20 12:56:36 PM PST 23
Peak memory 209840 kb
Host smart-8140991c-508d-4cf8-9c88-c0e3b006e264
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974291227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.2974291227
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.15318304
Short name T989
Test name
Test status
Simulation time 1588337536 ps
CPU time 16.49 seconds
Started Dec 20 12:56:37 PM PST 23
Finished Dec 20 12:56:59 PM PST 23
Peak memory 218184 kb
Host smart-58ba86c5-f15c-4c3f-9f68-3970e9a30ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15318304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.15318304
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.3077321152
Short name T891
Test name
Test status
Simulation time 880449691 ps
CPU time 2.97 seconds
Started Dec 20 12:56:23 PM PST 23
Finished Dec 20 12:56:33 PM PST 23
Peak memory 209768 kb
Host smart-ff3592d5-4bfe-4621-842a-92c986ed9968
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077321152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_a
ccess.3077321152
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.261104071
Short name T324
Test name
Test status
Simulation time 354531294 ps
CPU time 2.31 seconds
Started Dec 20 12:56:15 PM PST 23
Finished Dec 20 12:56:26 PM PST 23
Peak memory 218296 kb
Host smart-235b04e3-6573-4a61-a515-7b3a72ba2664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261104071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.261104071
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.402363829
Short name T455
Test name
Test status
Simulation time 491496391 ps
CPU time 18.84 seconds
Started Dec 20 12:56:30 PM PST 23
Finished Dec 20 12:56:55 PM PST 23
Peak memory 218236 kb
Host smart-e59f0b82-d2ec-4d93-afbd-6bb6b865e966
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402363829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_di
gest.402363829
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.3457854826
Short name T753
Test name
Test status
Simulation time 1354145189 ps
CPU time 9.39 seconds
Started Dec 20 12:56:12 PM PST 23
Finished Dec 20 12:56:31 PM PST 23
Peak memory 218232 kb
Host smart-3c6c1e55-806f-4adf-9ac9-9a00b5eaea51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457854826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
3457854826
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.4081443384
Short name T705
Test name
Test status
Simulation time 460132783 ps
CPU time 12.31 seconds
Started Dec 20 12:56:29 PM PST 23
Finished Dec 20 12:56:48 PM PST 23
Peak memory 218288 kb
Host smart-274ab790-a9a8-4ba9-9e08-4e8b2d920e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081443384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.4081443384
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.1884586045
Short name T887
Test name
Test status
Simulation time 93866319 ps
CPU time 4.1 seconds
Started Dec 20 12:56:39 PM PST 23
Finished Dec 20 12:56:48 PM PST 23
Peak memory 213988 kb
Host smart-86deca31-58a6-4189-b024-ceeba0c3fa5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884586045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.1884586045
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.173940235
Short name T433
Test name
Test status
Simulation time 965262293 ps
CPU time 21.4 seconds
Started Dec 20 12:56:55 PM PST 23
Finished Dec 20 12:57:26 PM PST 23
Peak memory 251072 kb
Host smart-0e876d5a-44ab-45ae-91b7-931f210e83e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173940235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.173940235
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.2987289854
Short name T605
Test name
Test status
Simulation time 46816442 ps
CPU time 7.11 seconds
Started Dec 20 12:56:42 PM PST 23
Finished Dec 20 12:56:54 PM PST 23
Peak memory 251284 kb
Host smart-2b819624-ca13-4c61-8fdb-12eed00c12bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987289854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2987289854
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.307225941
Short name T841
Test name
Test status
Simulation time 12241997748 ps
CPU time 263.9 seconds
Started Dec 20 12:56:28 PM PST 23
Finished Dec 20 01:00:59 PM PST 23
Peak memory 273780 kb
Host smart-d1e46940-843b-444a-8476-6084cca57899
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307225941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.307225941
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.3867973436
Short name T621
Test name
Test status
Simulation time 10591373 ps
CPU time 0.77 seconds
Started Dec 20 12:56:44 PM PST 23
Finished Dec 20 12:56:50 PM PST 23
Peak memory 208008 kb
Host smart-3e4a61a8-1a05-48e7-bb4d-94812167fb3b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867973436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.3867973436
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.4108392228
Short name T471
Test name
Test status
Simulation time 38329430 ps
CPU time 0.93 seconds
Started Dec 20 12:56:58 PM PST 23
Finished Dec 20 12:57:11 PM PST 23
Peak memory 209760 kb
Host smart-bc82ecac-9df8-44f7-8536-eaaee352df5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108392228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.4108392228
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.1906635178
Short name T616
Test name
Test status
Simulation time 1351595577 ps
CPU time 14.36 seconds
Started Dec 20 12:56:22 PM PST 23
Finished Dec 20 12:56:43 PM PST 23
Peak memory 218316 kb
Host smart-423b8203-1c85-47d3-bcdf-f24e41bb223a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906635178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.1906635178
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.841136877
Short name T948
Test name
Test status
Simulation time 1019840722 ps
CPU time 10.26 seconds
Started Dec 20 12:56:40 PM PST 23
Finished Dec 20 12:56:56 PM PST 23
Peak memory 209700 kb
Host smart-a4e06bc8-ca60-44ec-aa72-9eda0e6cf762
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841136877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_ac
cess.841136877
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.3977310974
Short name T962
Test name
Test status
Simulation time 68096027 ps
CPU time 3.59 seconds
Started Dec 20 12:56:40 PM PST 23
Finished Dec 20 12:56:48 PM PST 23
Peak memory 218120 kb
Host smart-8ed0655b-3e0f-4a9a-8481-d2190adcb998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977310974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.3977310974
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.222875534
Short name T754
Test name
Test status
Simulation time 1287704179 ps
CPU time 12.06 seconds
Started Dec 20 12:56:48 PM PST 23
Finished Dec 20 12:57:06 PM PST 23
Peak memory 218200 kb
Host smart-3476e610-2907-45d2-b737-7bb2abb7c850
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222875534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.222875534
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.1600305052
Short name T364
Test name
Test status
Simulation time 1526138056 ps
CPU time 11.96 seconds
Started Dec 20 12:56:48 PM PST 23
Finished Dec 20 12:57:06 PM PST 23
Peak memory 218328 kb
Host smart-aa6ae809-5956-4470-9f3a-443d654645ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600305052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.1600305052
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.3708079894
Short name T713
Test name
Test status
Simulation time 770117787 ps
CPU time 15.55 seconds
Started Dec 20 12:56:50 PM PST 23
Finished Dec 20 12:57:12 PM PST 23
Peak memory 218180 kb
Host smart-8008ba4c-22c9-4ad2-8402-b3e142ff38f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708079894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
3708079894
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.3207576788
Short name T853
Test name
Test status
Simulation time 3317615890 ps
CPU time 10.32 seconds
Started Dec 20 12:56:34 PM PST 23
Finished Dec 20 12:56:50 PM PST 23
Peak memory 218112 kb
Host smart-c4a7867a-fd8c-43a1-99e9-78fcdc693802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207576788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.3207576788
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.558308213
Short name T780
Test name
Test status
Simulation time 177877926 ps
CPU time 2.45 seconds
Started Dec 20 12:56:21 PM PST 23
Finished Dec 20 12:56:30 PM PST 23
Peak memory 213820 kb
Host smart-09364012-d6e1-4eb2-b918-8a9ab001935d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558308213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.558308213
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.720657311
Short name T898
Test name
Test status
Simulation time 864725369 ps
CPU time 22.89 seconds
Started Dec 20 12:56:23 PM PST 23
Finished Dec 20 12:56:53 PM PST 23
Peak memory 251220 kb
Host smart-a9de0bcc-ca2b-425c-8b14-9b16451d7c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720657311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.720657311
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.3057800575
Short name T952
Test name
Test status
Simulation time 282742214 ps
CPU time 2.99 seconds
Started Dec 20 12:56:30 PM PST 23
Finished Dec 20 12:56:39 PM PST 23
Peak memory 222144 kb
Host smart-647db0e5-dc89-4bf7-9961-32544ea0b70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057800575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.3057800575
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.2272059677
Short name T822
Test name
Test status
Simulation time 9931925269 ps
CPU time 144.17 seconds
Started Dec 20 12:56:54 PM PST 23
Finished Dec 20 12:59:37 PM PST 23
Peak memory 275860 kb
Host smart-a1884353-8d81-40d7-a115-0ea28432f551
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272059677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.2272059677
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.4227250094
Short name T37
Test name
Test status
Simulation time 14222243 ps
CPU time 0.77 seconds
Started Dec 20 12:56:40 PM PST 23
Finished Dec 20 12:56:46 PM PST 23
Peak memory 208412 kb
Host smart-f0a0e836-7df8-4ff9-acf5-a9e195e2abf3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227250094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.4227250094
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3417610466
Short name T798
Test name
Test status
Simulation time 31970433 ps
CPU time 0.99 seconds
Started Dec 20 12:56:27 PM PST 23
Finished Dec 20 12:56:35 PM PST 23
Peak memory 209796 kb
Host smart-7df582c8-b3b4-4ac4-ab22-1adc9430dc28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417610466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3417610466
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.877763834
Short name T738
Test name
Test status
Simulation time 483501352 ps
CPU time 13.87 seconds
Started Dec 20 12:56:43 PM PST 23
Finished Dec 20 12:57:02 PM PST 23
Peak memory 218248 kb
Host smart-d1ba35a0-0efb-489f-a554-5c1b33a466d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877763834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.877763834
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.2177094847
Short name T573
Test name
Test status
Simulation time 809562608 ps
CPU time 5.63 seconds
Started Dec 20 12:56:30 PM PST 23
Finished Dec 20 12:56:42 PM PST 23
Peak memory 209584 kb
Host smart-e8ebcb28-8164-43ee-9f86-0fded54ed0d7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177094847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_a
ccess.2177094847
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.3132224374
Short name T633
Test name
Test status
Simulation time 289736776 ps
CPU time 2.93 seconds
Started Dec 20 12:56:31 PM PST 23
Finished Dec 20 12:56:40 PM PST 23
Peak memory 218296 kb
Host smart-700d74af-9b2b-401c-aef3-d76288f7adc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132224374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.3132224374
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.1719452774
Short name T601
Test name
Test status
Simulation time 1478515579 ps
CPU time 10.08 seconds
Started Dec 20 12:56:49 PM PST 23
Finished Dec 20 12:57:05 PM PST 23
Peak memory 218092 kb
Host smart-85341d25-edd1-4908-81fa-404d9fe8f414
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719452774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1719452774
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.851209944
Short name T66
Test name
Test status
Simulation time 2060683812 ps
CPU time 12.02 seconds
Started Dec 20 12:56:52 PM PST 23
Finished Dec 20 12:57:12 PM PST 23
Peak memory 218244 kb
Host smart-a14949d6-7ea1-4450-9d65-a6fb7b9b40d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851209944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_di
gest.851209944
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.1691863134
Short name T2
Test name
Test status
Simulation time 588665893 ps
CPU time 10.63 seconds
Started Dec 20 12:56:57 PM PST 23
Finished Dec 20 12:57:19 PM PST 23
Peak memory 218220 kb
Host smart-07c0678d-3c26-4e5c-9e67-453615bd59a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691863134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
1691863134
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.2475020764
Short name T943
Test name
Test status
Simulation time 377358648 ps
CPU time 9.87 seconds
Started Dec 20 12:56:40 PM PST 23
Finished Dec 20 12:56:55 PM PST 23
Peak memory 218264 kb
Host smart-9120ad13-a681-4093-8f3f-2ee5424e7538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475020764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.2475020764
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.2480313899
Short name T88
Test name
Test status
Simulation time 61382782 ps
CPU time 1.84 seconds
Started Dec 20 12:56:32 PM PST 23
Finished Dec 20 12:56:39 PM PST 23
Peak memory 213612 kb
Host smart-154bdc36-7a72-4e15-8ec7-231253f875b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480313899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.2480313899
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.2331146672
Short name T494
Test name
Test status
Simulation time 496118567 ps
CPU time 27.7 seconds
Started Dec 20 12:56:41 PM PST 23
Finished Dec 20 12:57:14 PM PST 23
Peak memory 251208 kb
Host smart-4d7f3c02-9e48-48ca-99d8-2a953c80cb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331146672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.2331146672
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.2429388110
Short name T513
Test name
Test status
Simulation time 159215310 ps
CPU time 7.19 seconds
Started Dec 20 12:56:56 PM PST 23
Finished Dec 20 12:57:14 PM PST 23
Peak memory 247040 kb
Host smart-c258fddb-5d2f-474b-ac0d-9e28ef9c1ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429388110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.2429388110
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.1758499409
Short name T731
Test name
Test status
Simulation time 3697787858 ps
CPU time 55.97 seconds
Started Dec 20 12:56:41 PM PST 23
Finished Dec 20 12:57:42 PM PST 23
Peak memory 267704 kb
Host smart-32f39260-f03d-40c3-8418-ccb91e216180
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758499409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.1758499409
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1079013015
Short name T619
Test name
Test status
Simulation time 50488097 ps
CPU time 1.01 seconds
Started Dec 20 12:56:32 PM PST 23
Finished Dec 20 12:56:39 PM PST 23
Peak memory 212564 kb
Host smart-d204ef08-2e76-4d77-a326-fa20cbe8dc38
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079013015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.1079013015
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.1801053614
Short name T402
Test name
Test status
Simulation time 70083504 ps
CPU time 0.87 seconds
Started Dec 20 12:56:12 PM PST 23
Finished Dec 20 12:56:23 PM PST 23
Peak memory 209676 kb
Host smart-5cb683fb-2485-4600-aeca-c71faef1dc9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801053614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.1801053614
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.334405535
Short name T351
Test name
Test status
Simulation time 540900159 ps
CPU time 22.15 seconds
Started Dec 20 12:56:30 PM PST 23
Finished Dec 20 12:56:58 PM PST 23
Peak memory 218284 kb
Host smart-42605fd0-833b-459f-93cf-80b65b3f771e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334405535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.334405535
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.4082870177
Short name T560
Test name
Test status
Simulation time 800466880 ps
CPU time 8.43 seconds
Started Dec 20 12:57:04 PM PST 23
Finished Dec 20 12:57:28 PM PST 23
Peak memory 209684 kb
Host smart-4ea41f30-1cdb-4254-86ed-6d4335bdc5dc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082870177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_a
ccess.4082870177
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.589882875
Short name T568
Test name
Test status
Simulation time 48742885 ps
CPU time 2.41 seconds
Started Dec 20 12:56:51 PM PST 23
Finished Dec 20 12:57:01 PM PST 23
Peak memory 218148 kb
Host smart-8f8d5d02-2500-4db2-9f02-1075bfa5ce2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589882875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.589882875
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.1570907113
Short name T845
Test name
Test status
Simulation time 627484830 ps
CPU time 13.03 seconds
Started Dec 20 12:57:07 PM PST 23
Finished Dec 20 12:57:36 PM PST 23
Peak memory 218164 kb
Host smart-3c58e3e9-fcd2-4f85-ad88-bea938fb99af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570907113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.1570907113
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.652065053
Short name T456
Test name
Test status
Simulation time 865253419 ps
CPU time 16.63 seconds
Started Dec 20 12:57:13 PM PST 23
Finished Dec 20 12:57:46 PM PST 23
Peak memory 218308 kb
Host smart-c9745e1f-54ee-4a07-91b4-13f362ac57fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652065053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_di
gest.652065053
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.3853824777
Short name T505
Test name
Test status
Simulation time 1432326510 ps
CPU time 9.11 seconds
Started Dec 20 12:56:50 PM PST 23
Finished Dec 20 12:57:06 PM PST 23
Peak memory 218304 kb
Host smart-8e2b529d-2f60-43b8-b5b8-a2842a238c93
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853824777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
3853824777
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.2352187244
Short name T210
Test name
Test status
Simulation time 4260223448 ps
CPU time 11.28 seconds
Started Dec 20 12:56:55 PM PST 23
Finished Dec 20 12:57:16 PM PST 23
Peak memory 218400 kb
Host smart-b0d42cbf-69af-4f1f-bba7-2d86e7606b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352187244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.2352187244
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.1859964659
Short name T628
Test name
Test status
Simulation time 54656125 ps
CPU time 3.86 seconds
Started Dec 20 12:56:53 PM PST 23
Finished Dec 20 12:57:06 PM PST 23
Peak memory 213920 kb
Host smart-1ed6392b-5b60-40f6-9247-6d7244131c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859964659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.1859964659
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.3232602025
Short name T955
Test name
Test status
Simulation time 605181711 ps
CPU time 25.1 seconds
Started Dec 20 12:56:56 PM PST 23
Finished Dec 20 12:57:32 PM PST 23
Peak memory 251240 kb
Host smart-bc35c7e9-46da-4111-b9f3-1e6fbb9b8f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232602025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3232602025
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.2096148955
Short name T410
Test name
Test status
Simulation time 221950095 ps
CPU time 6.17 seconds
Started Dec 20 12:56:53 PM PST 23
Finished Dec 20 12:57:07 PM PST 23
Peak memory 244084 kb
Host smart-f7a357f8-17fa-43cb-a10e-3f28d3fdf0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096148955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.2096148955
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.3741113357
Short name T868
Test name
Test status
Simulation time 11741597957 ps
CPU time 203.44 seconds
Started Dec 20 12:56:18 PM PST 23
Finished Dec 20 12:59:49 PM PST 23
Peak memory 284016 kb
Host smart-050f7d55-a8aa-411e-9171-c6c680cd2fd2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741113357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.3741113357
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3999438813
Short name T724
Test name
Test status
Simulation time 31011699 ps
CPU time 0.88 seconds
Started Dec 20 12:56:59 PM PST 23
Finished Dec 20 12:57:13 PM PST 23
Peak memory 208520 kb
Host smart-e16001a8-3414-46fc-b686-bcfd4f4c7903
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999438813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.3999438813
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.1847228198
Short name T591
Test name
Test status
Simulation time 44126934 ps
CPU time 1.13 seconds
Started Dec 20 12:56:25 PM PST 23
Finished Dec 20 12:56:33 PM PST 23
Peak memory 209776 kb
Host smart-2937f735-0e42-4149-b989-231c0bc3b9ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847228198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.1847228198
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.1724322956
Short name T945
Test name
Test status
Simulation time 235195011 ps
CPU time 12.58 seconds
Started Dec 20 12:56:15 PM PST 23
Finished Dec 20 12:56:37 PM PST 23
Peak memory 218184 kb
Host smart-7e86e2fc-ab3a-4253-9998-21ffcef1801f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724322956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.1724322956
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.2086520435
Short name T942
Test name
Test status
Simulation time 358180779 ps
CPU time 9.74 seconds
Started Dec 20 12:56:24 PM PST 23
Finished Dec 20 12:56:41 PM PST 23
Peak memory 209644 kb
Host smart-959662f6-41d5-4023-a835-97ed271eb556
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086520435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_a
ccess.2086520435
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.3104097162
Short name T353
Test name
Test status
Simulation time 27513481 ps
CPU time 1.7 seconds
Started Dec 20 12:56:16 PM PST 23
Finished Dec 20 12:56:26 PM PST 23
Peak memory 218296 kb
Host smart-8d8e069a-edd6-40ac-90a3-80ad9353c8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104097162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3104097162
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.305643221
Short name T213
Test name
Test status
Simulation time 3924721244 ps
CPU time 9.46 seconds
Started Dec 20 12:56:22 PM PST 23
Finished Dec 20 12:56:39 PM PST 23
Peak memory 218352 kb
Host smart-cd6b8c5d-ff8f-4b68-b3e9-ddb73adf0eba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305643221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.305643221
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.2794007785
Short name T127
Test name
Test status
Simulation time 273265774 ps
CPU time 10.98 seconds
Started Dec 20 12:56:15 PM PST 23
Finished Dec 20 12:56:35 PM PST 23
Peak memory 218168 kb
Host smart-5b080473-fe7a-45e6-b8f5-78f7009fbaac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794007785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.2794007785
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.1253640560
Short name T779
Test name
Test status
Simulation time 654727246 ps
CPU time 7.45 seconds
Started Dec 20 12:56:45 PM PST 23
Finished Dec 20 12:56:57 PM PST 23
Peak memory 218220 kb
Host smart-0958bf27-a9d8-4c8e-a771-0d95b6371b5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253640560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
1253640560
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.1436878848
Short name T65
Test name
Test status
Simulation time 218715826 ps
CPU time 6.78 seconds
Started Dec 20 12:56:14 PM PST 23
Finished Dec 20 12:56:30 PM PST 23
Peak memory 218324 kb
Host smart-bb39615c-d30b-433b-ad27-fea93b22c121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436878848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.1436878848
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.1178972550
Short name T982
Test name
Test status
Simulation time 318241978 ps
CPU time 4.17 seconds
Started Dec 20 12:56:15 PM PST 23
Finished Dec 20 12:56:28 PM PST 23
Peak memory 214548 kb
Host smart-ced75eb3-8bb9-41ff-901b-9c0047972973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178972550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.1178972550
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.3557724947
Short name T829
Test name
Test status
Simulation time 307953302 ps
CPU time 31.5 seconds
Started Dec 20 12:56:13 PM PST 23
Finished Dec 20 12:56:54 PM PST 23
Peak memory 251104 kb
Host smart-add46b9a-4b3a-4c4c-b3c2-ccee1b73b53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557724947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3557724947
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.1604179149
Short name T934
Test name
Test status
Simulation time 87101716 ps
CPU time 7.78 seconds
Started Dec 20 12:56:24 PM PST 23
Finished Dec 20 12:56:39 PM PST 23
Peak memory 251008 kb
Host smart-c7c99b4b-615b-4b5b-a3c4-03b2ece103a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604179149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.1604179149
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.2438167350
Short name T848
Test name
Test status
Simulation time 71400042002 ps
CPU time 133.83 seconds
Started Dec 20 12:56:40 PM PST 23
Finished Dec 20 12:59:00 PM PST 23
Peak memory 253324 kb
Host smart-c282bfd4-bc59-400a-b290-b7292296fb57
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438167350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.2438167350
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.501109320
Short name T492
Test name
Test status
Simulation time 21989957 ps
CPU time 0.74 seconds
Started Dec 20 12:56:14 PM PST 23
Finished Dec 20 12:56:24 PM PST 23
Peak memory 208188 kb
Host smart-1053e2d2-4bb0-4e69-9dde-7c19a6b0609f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501109320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ct
rl_volatile_unlock_smoke.501109320
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.4048117135
Short name T489
Test name
Test status
Simulation time 75398469 ps
CPU time 0.86 seconds
Started Dec 20 12:56:22 PM PST 23
Finished Dec 20 12:56:30 PM PST 23
Peak memory 209664 kb
Host smart-d1c53297-b837-44ef-9267-cd598a074aff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048117135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.4048117135
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.2999387977
Short name T413
Test name
Test status
Simulation time 845503039 ps
CPU time 8.02 seconds
Started Dec 20 12:56:17 PM PST 23
Finished Dec 20 12:56:33 PM PST 23
Peak memory 218272 kb
Host smart-37c10041-98ce-436a-8d85-31d230a43e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999387977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.2999387977
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.393351623
Short name T403
Test name
Test status
Simulation time 42988651 ps
CPU time 1.7 seconds
Started Dec 20 12:56:38 PM PST 23
Finished Dec 20 12:56:45 PM PST 23
Peak memory 209640 kb
Host smart-85e246f3-85c1-4031-8c9e-8751fff41e7b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393351623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_ac
cess.393351623
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.3626590938
Short name T557
Test name
Test status
Simulation time 70352212 ps
CPU time 1.85 seconds
Started Dec 20 12:56:33 PM PST 23
Finished Dec 20 12:56:42 PM PST 23
Peak memory 218116 kb
Host smart-a616090b-9546-4256-9338-f6d688dc169f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626590938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.3626590938
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.2892426255
Short name T897
Test name
Test status
Simulation time 819808623 ps
CPU time 16.2 seconds
Started Dec 20 12:56:58 PM PST 23
Finished Dec 20 12:57:28 PM PST 23
Peak memory 218748 kb
Host smart-c8f0e6d7-f182-4739-b1d8-c64a14442049
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892426255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.2892426255
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.352222466
Short name T818
Test name
Test status
Simulation time 249281276 ps
CPU time 8.27 seconds
Started Dec 20 12:56:38 PM PST 23
Finished Dec 20 12:56:51 PM PST 23
Peak memory 218276 kb
Host smart-c6b63c1d-2ea1-4e31-87bd-e12f073c547c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352222466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_di
gest.352222466
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.1282249233
Short name T676
Test name
Test status
Simulation time 420778262 ps
CPU time 9.03 seconds
Started Dec 20 12:56:46 PM PST 23
Finished Dec 20 12:56:59 PM PST 23
Peak memory 218280 kb
Host smart-00ced59c-7198-4813-a2ef-ac034ffe4d7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282249233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
1282249233
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.2348206702
Short name T685
Test name
Test status
Simulation time 957880952 ps
CPU time 9.79 seconds
Started Dec 20 12:56:32 PM PST 23
Finished Dec 20 12:56:48 PM PST 23
Peak memory 218180 kb
Host smart-a569bc01-f65e-4ebc-8b3e-593f8e82687a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348206702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.2348206702
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.57420575
Short name T74
Test name
Test status
Simulation time 452499392 ps
CPU time 7.99 seconds
Started Dec 20 12:56:26 PM PST 23
Finished Dec 20 12:56:40 PM PST 23
Peak memory 218468 kb
Host smart-df8677e3-54b7-43dc-a4b2-4d50b30f5e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57420575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.57420575
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.2246194482
Short name T328
Test name
Test status
Simulation time 201317206 ps
CPU time 20 seconds
Started Dec 20 12:56:38 PM PST 23
Finished Dec 20 12:57:03 PM PST 23
Peak memory 251316 kb
Host smart-8a1d8da4-fce6-48e0-b044-58bb3f8357ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246194482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.2246194482
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.4190052533
Short name T646
Test name
Test status
Simulation time 62361023 ps
CPU time 3.35 seconds
Started Dec 20 12:56:51 PM PST 23
Finished Dec 20 12:57:02 PM PST 23
Peak memory 222508 kb
Host smart-46fd502b-8bd5-4bb9-ad44-7d978a9e2201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190052533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.4190052533
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.1592934131
Short name T889
Test name
Test status
Simulation time 9531305839 ps
CPU time 154.28 seconds
Started Dec 20 12:56:42 PM PST 23
Finished Dec 20 12:59:21 PM PST 23
Peak memory 284024 kb
Host smart-42628215-523b-4e90-b627-cfaa29e8c157
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592934131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.1592934131
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3706130217
Short name T986
Test name
Test status
Simulation time 30638483 ps
CPU time 0.85 seconds
Started Dec 20 12:56:29 PM PST 23
Finished Dec 20 12:56:36 PM PST 23
Peak memory 211504 kb
Host smart-3b548fc3-7f22-41c8-b4fa-883063f8b358
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706130217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.3706130217
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.2322931714
Short name T670
Test name
Test status
Simulation time 176382493 ps
CPU time 0.88 seconds
Started Dec 20 12:55:02 PM PST 23
Finished Dec 20 12:55:24 PM PST 23
Peak memory 209784 kb
Host smart-c1a2365c-7d75-4e20-a71c-21c6a790e3a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322931714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2322931714
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.1485975400
Short name T876
Test name
Test status
Simulation time 14033865 ps
CPU time 0.83 seconds
Started Dec 20 12:55:00 PM PST 23
Finished Dec 20 12:55:21 PM PST 23
Peak memory 209516 kb
Host smart-5cfb5739-b294-4874-9a71-6823178eb514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485975400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.1485975400
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.1745190369
Short name T39
Test name
Test status
Simulation time 323845377 ps
CPU time 13.47 seconds
Started Dec 20 12:55:16 PM PST 23
Finished Dec 20 12:55:46 PM PST 23
Peak memory 218300 kb
Host smart-d971ec86-8d61-419b-bb4f-26d39a59be96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745190369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1745190369
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.79107250
Short name T29
Test name
Test status
Simulation time 457255551 ps
CPU time 5.39 seconds
Started Dec 20 12:55:01 PM PST 23
Finished Dec 20 12:55:27 PM PST 23
Peak memory 209784 kb
Host smart-cc4deba8-6afb-4421-8c17-9ddb42dbbcce
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79107250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jta
g_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_acce
ss.79107250
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.577634718
Short name T50
Test name
Test status
Simulation time 5316855096 ps
CPU time 17.45 seconds
Started Dec 20 12:55:00 PM PST 23
Finished Dec 20 12:55:39 PM PST 23
Peak memory 218408 kb
Host smart-7458837d-4091-4207-80c4-50a09905f359
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577634718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_err
ors.577634718
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.2040861843
Short name T545
Test name
Test status
Simulation time 19238296158 ps
CPU time 9.58 seconds
Started Dec 20 12:55:07 PM PST 23
Finished Dec 20 12:55:38 PM PST 23
Peak memory 217980 kb
Host smart-8f13f3b2-36bf-49ca-8592-67bd83552e86
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040861843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
priority.2040861843
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.930565058
Short name T119
Test name
Test status
Simulation time 521982879 ps
CPU time 4.94 seconds
Started Dec 20 12:55:04 PM PST 23
Finished Dec 20 12:55:30 PM PST 23
Peak memory 218240 kb
Host smart-5731b443-28fe-4448-8361-233e588691ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930565058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
prog_failure.930565058
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1643551154
Short name T666
Test name
Test status
Simulation time 5132170716 ps
CPU time 10.3 seconds
Started Dec 20 12:55:07 PM PST 23
Finished Dec 20 12:55:38 PM PST 23
Peak memory 213472 kb
Host smart-e6f4cfda-7a0c-4c47-9eda-87d2fd21f8ed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643551154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.1643551154
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.966025509
Short name T624
Test name
Test status
Simulation time 709416204 ps
CPU time 3.68 seconds
Started Dec 20 12:55:00 PM PST 23
Finished Dec 20 12:55:25 PM PST 23
Peak memory 213020 kb
Host smart-c5ba90c8-cda5-477c-b0e5-10d31fd1ad5f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966025509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.966025509
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.1658351595
Short name T715
Test name
Test status
Simulation time 1046480990 ps
CPU time 47.73 seconds
Started Dec 20 12:55:15 PM PST 23
Finished Dec 20 12:56:20 PM PST 23
Peak memory 251172 kb
Host smart-0d5963ec-8815-4294-b6ed-708f32e39fed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658351595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.1658351595
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.4259813785
Short name T820
Test name
Test status
Simulation time 830149396 ps
CPU time 15.86 seconds
Started Dec 20 12:55:00 PM PST 23
Finished Dec 20 12:55:36 PM PST 23
Peak memory 250752 kb
Host smart-9be6139c-7ed1-4cfe-9826-6cfb45b5c379
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259813785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.4259813785
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.1524660656
Short name T499
Test name
Test status
Simulation time 88058864 ps
CPU time 2.97 seconds
Started Dec 20 12:55:00 PM PST 23
Finished Dec 20 12:55:23 PM PST 23
Peak memory 218364 kb
Host smart-c72bcac4-410e-4cfd-a595-a1d2c2a974c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524660656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.1524660656
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.3494781105
Short name T68
Test name
Test status
Simulation time 560412125 ps
CPU time 7.14 seconds
Started Dec 20 12:55:07 PM PST 23
Finished Dec 20 12:55:35 PM PST 23
Peak memory 217920 kb
Host smart-3f684629-68fe-4309-8783-145e3944ce4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494781105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.3494781105
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.3167209655
Short name T64
Test name
Test status
Simulation time 406631959 ps
CPU time 35.89 seconds
Started Dec 20 12:55:09 PM PST 23
Finished Dec 20 12:56:04 PM PST 23
Peak memory 281868 kb
Host smart-dbfd65f7-4ba3-4bcc-8ae1-be01f0bf5bf8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167209655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.3167209655
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.535379085
Short name T470
Test name
Test status
Simulation time 1482498739 ps
CPU time 12.77 seconds
Started Dec 20 12:55:05 PM PST 23
Finished Dec 20 12:55:39 PM PST 23
Peak memory 219300 kb
Host smart-6f6d36b3-4917-4bc0-9390-5fc1c58b0b4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535379085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.535379085
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.817384820
Short name T509
Test name
Test status
Simulation time 4353112482 ps
CPU time 10.07 seconds
Started Dec 20 12:55:12 PM PST 23
Finished Dec 20 12:55:40 PM PST 23
Peak memory 218284 kb
Host smart-3b6f3af1-5791-4140-b21c-65932a6ba2c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817384820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_dig
est.817384820
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.2845818259
Short name T580
Test name
Test status
Simulation time 1067986872 ps
CPU time 10.32 seconds
Started Dec 20 12:55:00 PM PST 23
Finished Dec 20 12:55:30 PM PST 23
Peak memory 218232 kb
Host smart-900e18c8-55d3-4679-b80a-cf6a896803f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845818259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.2
845818259
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.414631123
Short name T57
Test name
Test status
Simulation time 4481978925 ps
CPU time 7.98 seconds
Started Dec 20 12:55:01 PM PST 23
Finished Dec 20 12:55:30 PM PST 23
Peak memory 218312 kb
Host smart-3a8c569a-742b-4504-9228-c4df608f0ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414631123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.414631123
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.2353973898
Short name T47
Test name
Test status
Simulation time 37974139 ps
CPU time 1.93 seconds
Started Dec 20 12:55:02 PM PST 23
Finished Dec 20 12:55:25 PM PST 23
Peak memory 218176 kb
Host smart-448e0a12-92dd-41b2-b612-c13952c48c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353973898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.2353973898
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.1976460291
Short name T692
Test name
Test status
Simulation time 956904860 ps
CPU time 25.44 seconds
Started Dec 20 12:55:13 PM PST 23
Finished Dec 20 12:55:55 PM PST 23
Peak memory 251200 kb
Host smart-79db5fca-f985-4ee2-a2e3-458306a07f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976460291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.1976460291
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.1128250200
Short name T327
Test name
Test status
Simulation time 66289125 ps
CPU time 7.03 seconds
Started Dec 20 12:55:11 PM PST 23
Finished Dec 20 12:55:36 PM PST 23
Peak memory 251272 kb
Host smart-1eb4daa0-733f-43ae-942f-beaaf41807ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128250200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.1128250200
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.499473796
Short name T656
Test name
Test status
Simulation time 9201081880 ps
CPU time 109.13 seconds
Started Dec 20 12:55:08 PM PST 23
Finished Dec 20 12:57:17 PM PST 23
Peak memory 276284 kb
Host smart-fcaf6b2b-e5e6-49a1-8bfc-f8209c8158e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499473796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.499473796
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1406699234
Short name T681
Test name
Test status
Simulation time 11055667 ps
CPU time 0.83 seconds
Started Dec 20 12:54:57 PM PST 23
Finished Dec 20 12:55:16 PM PST 23
Peak memory 208164 kb
Host smart-7d9f17fb-77bf-42ed-97a1-8acf8702a27d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406699234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.1406699234
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.2577250981
Short name T520
Test name
Test status
Simulation time 70560628 ps
CPU time 0.89 seconds
Started Dec 20 12:57:02 PM PST 23
Finished Dec 20 12:57:19 PM PST 23
Peak memory 209664 kb
Host smart-77a23daf-bfaf-42f6-a07f-267b90637da9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577250981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.2577250981
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.1739814148
Short name T408
Test name
Test status
Simulation time 2541919707 ps
CPU time 10.4 seconds
Started Dec 20 12:56:48 PM PST 23
Finished Dec 20 12:57:04 PM PST 23
Peak memory 218300 kb
Host smart-9f2670b3-5418-4e3e-b013-e24d2af01c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739814148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.1739814148
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.3183486445
Short name T7
Test name
Test status
Simulation time 361420118 ps
CPU time 3.1 seconds
Started Dec 20 12:56:29 PM PST 23
Finished Dec 20 12:56:39 PM PST 23
Peak memory 209796 kb
Host smart-dd102895-a842-4301-b071-da715086b60f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183486445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_a
ccess.3183486445
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.1244439100
Short name T825
Test name
Test status
Simulation time 58014838 ps
CPU time 2.84 seconds
Started Dec 20 12:57:02 PM PST 23
Finished Dec 20 12:57:21 PM PST 23
Peak memory 218312 kb
Host smart-1a749b91-ef09-4a21-98d1-bc69066e9362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244439100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.1244439100
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.3852610039
Short name T896
Test name
Test status
Simulation time 1398110750 ps
CPU time 18.84 seconds
Started Dec 20 12:56:59 PM PST 23
Finished Dec 20 12:57:32 PM PST 23
Peak memory 219336 kb
Host smart-3fa9d486-920a-4729-ab01-cff1df862bb9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852610039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.3852610039
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.435451175
Short name T426
Test name
Test status
Simulation time 373045102 ps
CPU time 13.47 seconds
Started Dec 20 12:56:51 PM PST 23
Finished Dec 20 12:57:12 PM PST 23
Peak memory 218268 kb
Host smart-8c3b1546-aacd-43d7-bb5b-3fff741f176a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435451175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_di
gest.435451175
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.3077195010
Short name T773
Test name
Test status
Simulation time 162321369 ps
CPU time 6.63 seconds
Started Dec 20 12:56:36 PM PST 23
Finished Dec 20 12:56:48 PM PST 23
Peak memory 218264 kb
Host smart-20ff5878-549e-4aaa-a419-dc01b74139d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077195010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
3077195010
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.1622859392
Short name T874
Test name
Test status
Simulation time 705239945 ps
CPU time 8.57 seconds
Started Dec 20 12:56:30 PM PST 23
Finished Dec 20 12:56:44 PM PST 23
Peak memory 218260 kb
Host smart-d1d52ba0-c064-4869-835d-8d1f622cd3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622859392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.1622859392
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.1710412798
Short name T423
Test name
Test status
Simulation time 42842919 ps
CPU time 1.57 seconds
Started Dec 20 12:56:29 PM PST 23
Finished Dec 20 12:56:37 PM PST 23
Peak memory 213636 kb
Host smart-51056376-fe5f-4c44-8f3f-ab38369ecaa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710412798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.1710412798
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.1186389108
Short name T442
Test name
Test status
Simulation time 374205831 ps
CPU time 25.58 seconds
Started Dec 20 12:56:29 PM PST 23
Finished Dec 20 12:57:01 PM PST 23
Peak memory 251192 kb
Host smart-40b005dd-ac9b-47a8-ac82-834b436695c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186389108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.1186389108
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.3166507210
Short name T832
Test name
Test status
Simulation time 728959657 ps
CPU time 2.91 seconds
Started Dec 20 12:56:39 PM PST 23
Finished Dec 20 12:56:48 PM PST 23
Peak memory 222248 kb
Host smart-d819e13b-b9ba-432a-817b-1c759ecf4ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166507210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.3166507210
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.1155704100
Short name T789
Test name
Test status
Simulation time 20247735490 ps
CPU time 272.16 seconds
Started Dec 20 12:56:46 PM PST 23
Finished Dec 20 01:01:23 PM PST 23
Peak memory 284116 kb
Host smart-eb83c508-2439-4cae-9d20-ee4498ae860a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155704100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.1155704100
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1485566252
Short name T977
Test name
Test status
Simulation time 13404232 ps
CPU time 1.04 seconds
Started Dec 20 12:57:02 PM PST 23
Finished Dec 20 12:57:19 PM PST 23
Peak memory 208260 kb
Host smart-fd445e12-5f36-447d-9098-28ee9970d179
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485566252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.1485566252
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.2414593958
Short name T919
Test name
Test status
Simulation time 244597538 ps
CPU time 1.14 seconds
Started Dec 20 12:56:18 PM PST 23
Finished Dec 20 12:56:27 PM PST 23
Peak memory 208596 kb
Host smart-03fadba1-6d50-4bd8-aea4-aad00801721a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414593958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2414593958
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.3825508264
Short name T123
Test name
Test status
Simulation time 496802456 ps
CPU time 12.39 seconds
Started Dec 20 12:56:41 PM PST 23
Finished Dec 20 12:56:58 PM PST 23
Peak memory 218052 kb
Host smart-feda808b-263e-404d-9650-0ea7f7fa2ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825508264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.3825508264
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.2479451543
Short name T30
Test name
Test status
Simulation time 1529090785 ps
CPU time 18.28 seconds
Started Dec 20 12:56:39 PM PST 23
Finished Dec 20 12:57:02 PM PST 23
Peak memory 209696 kb
Host smart-ad07e5bb-772f-4d68-8132-1dfb7d7b11be
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479451543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_a
ccess.2479451543
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.23268317
Short name T973
Test name
Test status
Simulation time 124184689 ps
CPU time 1.77 seconds
Started Dec 20 12:56:23 PM PST 23
Finished Dec 20 12:56:31 PM PST 23
Peak memory 218220 kb
Host smart-2b3c99a9-962c-40a6-b30c-e770efa6fcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23268317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.23268317
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.506544700
Short name T965
Test name
Test status
Simulation time 482734393 ps
CPU time 11.11 seconds
Started Dec 20 12:56:28 PM PST 23
Finished Dec 20 12:56:45 PM PST 23
Peak memory 218292 kb
Host smart-11460f9a-1485-456e-85ea-1c81cbf5b184
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506544700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.506544700
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.393322407
Short name T626
Test name
Test status
Simulation time 490634835 ps
CPU time 11.76 seconds
Started Dec 20 12:56:46 PM PST 23
Finished Dec 20 12:57:19 PM PST 23
Peak memory 218184 kb
Host smart-4897ac48-26d0-4df4-ae65-805cad0ff361
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393322407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_di
gest.393322407
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.2385684364
Short name T466
Test name
Test status
Simulation time 2301659756 ps
CPU time 15.67 seconds
Started Dec 20 12:56:28 PM PST 23
Finished Dec 20 12:56:50 PM PST 23
Peak memory 218220 kb
Host smart-ad5dcf1e-ab6c-472e-9132-b19cdffa49dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385684364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
2385684364
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.4145362221
Short name T687
Test name
Test status
Simulation time 188648550 ps
CPU time 5.68 seconds
Started Dec 20 12:56:33 PM PST 23
Finished Dec 20 12:56:44 PM PST 23
Peak memory 218328 kb
Host smart-9b0ac453-c494-4c60-bfa8-0e3933cd1e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145362221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.4145362221
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.379192906
Short name T702
Test name
Test status
Simulation time 71761201 ps
CPU time 2.67 seconds
Started Dec 20 12:56:21 PM PST 23
Finished Dec 20 12:56:30 PM PST 23
Peak memory 214116 kb
Host smart-e2902d85-7ef8-40cf-b454-1796ceb309c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379192906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.379192906
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.2806152535
Short name T790
Test name
Test status
Simulation time 291548795 ps
CPU time 28.56 seconds
Started Dec 20 12:56:40 PM PST 23
Finished Dec 20 12:57:14 PM PST 23
Peak memory 251236 kb
Host smart-2cbb0ed5-d202-49fe-867f-c51a710118e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806152535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.2806152535
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.3332249964
Short name T525
Test name
Test status
Simulation time 304202109 ps
CPU time 6.78 seconds
Started Dec 20 12:56:20 PM PST 23
Finished Dec 20 12:56:33 PM PST 23
Peak memory 250860 kb
Host smart-0f13f644-ce06-4076-8a66-87881672fd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332249964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.3332249964
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.1136118302
Short name T467
Test name
Test status
Simulation time 8284295495 ps
CPU time 52.33 seconds
Started Dec 20 12:56:28 PM PST 23
Finished Dec 20 12:57:26 PM PST 23
Peak memory 251336 kb
Host smart-6774f6db-ed40-46fa-8e69-3c82ffb18838
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136118302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.1136118302
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3830143783
Short name T625
Test name
Test status
Simulation time 20562898 ps
CPU time 0.89 seconds
Started Dec 20 12:57:02 PM PST 23
Finished Dec 20 12:57:19 PM PST 23
Peak memory 208456 kb
Host smart-e5cb587e-cddc-4d15-9288-1a16936377ec
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830143783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.3830143783
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.2983898106
Short name T453
Test name
Test status
Simulation time 142263515 ps
CPU time 1.05 seconds
Started Dec 20 12:56:47 PM PST 23
Finished Dec 20 12:56:53 PM PST 23
Peak memory 209740 kb
Host smart-db5f1764-85a1-40c9-a878-629dca5f7c06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983898106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.2983898106
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.1894728401
Short name T523
Test name
Test status
Simulation time 375422888 ps
CPU time 14.54 seconds
Started Dec 20 12:56:30 PM PST 23
Finished Dec 20 12:56:51 PM PST 23
Peak memory 218220 kb
Host smart-fca19ec7-7459-4123-b1b6-b22a5b63ce67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894728401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.1894728401
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.424286585
Short name T387
Test name
Test status
Simulation time 331378649 ps
CPU time 2.6 seconds
Started Dec 20 12:56:27 PM PST 23
Finished Dec 20 12:56:35 PM PST 23
Peak memory 209708 kb
Host smart-02c93f32-862e-484e-bde0-de4a6e288e57
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424286585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_ac
cess.424286585
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.1812917760
Short name T329
Test name
Test status
Simulation time 46592361 ps
CPU time 2.31 seconds
Started Dec 20 12:56:24 PM PST 23
Finished Dec 20 12:56:33 PM PST 23
Peak memory 218180 kb
Host smart-e0e35591-08a2-4507-9a0d-aea5541e7b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812917760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.1812917760
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.2879834181
Short name T212
Test name
Test status
Simulation time 4044923103 ps
CPU time 15.52 seconds
Started Dec 20 12:56:44 PM PST 23
Finished Dec 20 12:57:05 PM PST 23
Peak memory 219284 kb
Host smart-85b9b2b3-25fe-4dcb-a2b0-18179bd38896
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879834181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.2879834181
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.804552571
Short name T603
Test name
Test status
Simulation time 2653990995 ps
CPU time 12.65 seconds
Started Dec 20 12:56:53 PM PST 23
Finished Dec 20 12:57:13 PM PST 23
Peak memory 218212 kb
Host smart-1a2c2bd1-299e-4834-91e3-b25b0c19ea0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804552571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_di
gest.804552571
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.1806754595
Short name T479
Test name
Test status
Simulation time 1804053527 ps
CPU time 10.74 seconds
Started Dec 20 12:56:34 PM PST 23
Finished Dec 20 12:56:51 PM PST 23
Peak memory 218344 kb
Host smart-537e8bd8-a467-4c21-a93b-918b99db866b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806754595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
1806754595
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.499066679
Short name T118
Test name
Test status
Simulation time 267519338 ps
CPU time 8.26 seconds
Started Dec 20 12:56:56 PM PST 23
Finished Dec 20 12:57:15 PM PST 23
Peak memory 218244 kb
Host smart-e9c9adc6-a957-42c2-9d20-a605aaa595fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499066679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.499066679
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.986862767
Short name T98
Test name
Test status
Simulation time 247965130 ps
CPU time 3.62 seconds
Started Dec 20 12:56:18 PM PST 23
Finished Dec 20 12:56:30 PM PST 23
Peak memory 214132 kb
Host smart-6a8ab7b5-acfd-42e6-8713-7b9dc4a1f8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986862767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.986862767
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.4266945985
Short name T755
Test name
Test status
Simulation time 221438536 ps
CPU time 18.95 seconds
Started Dec 20 12:56:32 PM PST 23
Finished Dec 20 12:56:57 PM PST 23
Peak memory 251208 kb
Host smart-1b2812ec-962a-4a19-86e3-8c73530a466b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266945985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.4266945985
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3801169686
Short name T810
Test name
Test status
Simulation time 182569896 ps
CPU time 6.48 seconds
Started Dec 20 12:56:43 PM PST 23
Finished Dec 20 12:56:54 PM PST 23
Peak memory 246852 kb
Host smart-f9ab5211-db3f-43d3-8451-d97f936bd6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801169686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3801169686
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.3371424378
Short name T389
Test name
Test status
Simulation time 29342828407 ps
CPU time 142.16 seconds
Started Dec 20 12:56:47 PM PST 23
Finished Dec 20 12:59:15 PM PST 23
Peak memory 251284 kb
Host smart-336e230e-6ec1-46a3-8ff0-f63290de5b4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371424378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.3371424378
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1403389366
Short name T347
Test name
Test status
Simulation time 11329850 ps
CPU time 0.92 seconds
Started Dec 20 12:56:39 PM PST 23
Finished Dec 20 12:56:45 PM PST 23
Peak memory 208280 kb
Host smart-f30a87a1-5878-4c28-9711-792fc807ed85
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403389366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.1403389366
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.2145282159
Short name T529
Test name
Test status
Simulation time 51597491 ps
CPU time 0.98 seconds
Started Dec 20 12:56:37 PM PST 23
Finished Dec 20 12:56:43 PM PST 23
Peak memory 209676 kb
Host smart-71d301b1-e6e4-42b1-90c9-b981c1554d7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145282159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2145282159
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.3414402997
Short name T54
Test name
Test status
Simulation time 655479885 ps
CPU time 14.17 seconds
Started Dec 20 12:56:34 PM PST 23
Finished Dec 20 12:56:54 PM PST 23
Peak memory 218180 kb
Host smart-90bdf3d0-5a80-4c1e-b1dc-a03b8b24dda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414402997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.3414402997
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.500673451
Short name T27
Test name
Test status
Simulation time 865417452 ps
CPU time 5.13 seconds
Started Dec 20 12:56:38 PM PST 23
Finished Dec 20 12:56:48 PM PST 23
Peak memory 209664 kb
Host smart-4d458d24-c076-45c0-8207-be3944f183d5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500673451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_ac
cess.500673451
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.3459774987
Short name T522
Test name
Test status
Simulation time 341630150 ps
CPU time 2.75 seconds
Started Dec 20 12:56:23 PM PST 23
Finished Dec 20 12:56:33 PM PST 23
Peak memory 218328 kb
Host smart-e1f40f61-7a74-40b4-b319-7542e1da992d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459774987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.3459774987
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.1048702246
Short name T737
Test name
Test status
Simulation time 1778257200 ps
CPU time 17.08 seconds
Started Dec 20 12:56:49 PM PST 23
Finished Dec 20 12:57:12 PM PST 23
Peak memory 219276 kb
Host smart-9afb8c44-6038-4fdf-ae1b-8b0ed9acbd54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048702246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.1048702246
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.2286847515
Short name T481
Test name
Test status
Simulation time 391744854 ps
CPU time 15.14 seconds
Started Dec 20 12:56:32 PM PST 23
Finished Dec 20 12:56:53 PM PST 23
Peak memory 218128 kb
Host smart-227ccc17-1453-4652-8ac4-ef02c249b61a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286847515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.2286847515
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2752803353
Short name T811
Test name
Test status
Simulation time 544650280 ps
CPU time 7.09 seconds
Started Dec 20 12:56:48 PM PST 23
Finished Dec 20 12:57:01 PM PST 23
Peak memory 218188 kb
Host smart-07474a0a-4a1f-43be-9e0d-a3eaa24ce9e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752803353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
2752803353
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.1800824355
Short name T906
Test name
Test status
Simulation time 323720323 ps
CPU time 12.31 seconds
Started Dec 20 12:56:46 PM PST 23
Finished Dec 20 12:57:04 PM PST 23
Peak memory 218336 kb
Host smart-eb4935ff-4548-4f07-8b32-c77b4c691baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800824355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.1800824355
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.3298090332
Short name T129
Test name
Test status
Simulation time 68595547 ps
CPU time 2.84 seconds
Started Dec 20 12:56:35 PM PST 23
Finished Dec 20 12:56:44 PM PST 23
Peak memory 214272 kb
Host smart-0619bf02-16d4-4473-85f5-14b2da6d7155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298090332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.3298090332
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.3456541326
Short name T664
Test name
Test status
Simulation time 1059442742 ps
CPU time 20.14 seconds
Started Dec 20 12:56:28 PM PST 23
Finished Dec 20 12:56:54 PM PST 23
Peak memory 251220 kb
Host smart-557c7652-ae77-438b-9672-617a6595dc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456541326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.3456541326
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.1859058821
Short name T933
Test name
Test status
Simulation time 84061402 ps
CPU time 6.54 seconds
Started Dec 20 12:56:29 PM PST 23
Finished Dec 20 12:56:42 PM PST 23
Peak memory 247004 kb
Host smart-43908d5c-6cfe-45fc-bbe0-ddfdba919706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859058821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.1859058821
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.2807450798
Short name T842
Test name
Test status
Simulation time 16114131 ps
CPU time 0.85 seconds
Started Dec 20 12:56:38 PM PST 23
Finished Dec 20 12:56:44 PM PST 23
Peak memory 208416 kb
Host smart-093a543d-f635-4e12-be0f-525acb755f78
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807450798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.2807450798
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.912781616
Short name T791
Test name
Test status
Simulation time 59356239 ps
CPU time 1.01 seconds
Started Dec 20 12:56:20 PM PST 23
Finished Dec 20 12:56:28 PM PST 23
Peak memory 209588 kb
Host smart-3fdb8053-fbad-4fb6-ad56-9cb58a169cd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912781616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.912781616
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.121960713
Short name T549
Test name
Test status
Simulation time 771700486 ps
CPU time 19.96 seconds
Started Dec 20 12:56:46 PM PST 23
Finished Dec 20 12:57:11 PM PST 23
Peak memory 218264 kb
Host smart-17ef956e-ccec-40f1-9b3a-ed1d09472e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121960713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.121960713
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.2101091549
Short name T688
Test name
Test status
Simulation time 778510621 ps
CPU time 4 seconds
Started Dec 20 12:56:38 PM PST 23
Finished Dec 20 12:56:47 PM PST 23
Peak memory 209760 kb
Host smart-66fadba1-4f12-4cac-94fb-8fb64bd28ba6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101091549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_a
ccess.2101091549
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.290553582
Short name T446
Test name
Test status
Simulation time 138955807 ps
CPU time 3.57 seconds
Started Dec 20 12:56:37 PM PST 23
Finished Dec 20 12:56:46 PM PST 23
Peak memory 218272 kb
Host smart-e4264b60-992e-467f-a725-f3c23059fe71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290553582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.290553582
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.1598406832
Short name T683
Test name
Test status
Simulation time 1341395969 ps
CPU time 15.31 seconds
Started Dec 20 12:56:33 PM PST 23
Finished Dec 20 12:56:55 PM PST 23
Peak memory 219144 kb
Host smart-eb28e040-cc4e-48a2-9567-186d6da2b082
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598406832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.1598406832
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.249808284
Short name T665
Test name
Test status
Simulation time 433015699 ps
CPU time 12.14 seconds
Started Dec 20 12:56:36 PM PST 23
Finished Dec 20 12:56:53 PM PST 23
Peak memory 218228 kb
Host smart-e1f83456-504b-4faa-9668-e39930730504
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249808284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_di
gest.249808284
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.2633242378
Short name T497
Test name
Test status
Simulation time 654296286 ps
CPU time 7.19 seconds
Started Dec 20 12:56:27 PM PST 23
Finished Dec 20 12:56:40 PM PST 23
Peak memory 218080 kb
Host smart-8ef17e77-54cd-4e86-aa42-14533e51832a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633242378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
2633242378
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.2964493402
Short name T864
Test name
Test status
Simulation time 1703020770 ps
CPU time 15.34 seconds
Started Dec 20 12:56:52 PM PST 23
Finished Dec 20 12:57:15 PM PST 23
Peak memory 218224 kb
Host smart-5a72bff0-af9b-410c-acbc-d5b349ffbc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964493402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2964493402
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.3387587481
Short name T643
Test name
Test status
Simulation time 37320364 ps
CPU time 1.25 seconds
Started Dec 20 12:56:24 PM PST 23
Finished Dec 20 12:56:32 PM PST 23
Peak memory 213528 kb
Host smart-4f48e895-b335-44c0-a432-64b3bce4f55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387587481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.3387587481
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.3993113921
Short name T339
Test name
Test status
Simulation time 313771915 ps
CPU time 33.15 seconds
Started Dec 20 12:56:23 PM PST 23
Finished Dec 20 12:57:03 PM PST 23
Peak memory 247200 kb
Host smart-e45b0c67-dfe4-4c9b-a7b1-4c3279487b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993113921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3993113921
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.2819031491
Short name T552
Test name
Test status
Simulation time 83773651 ps
CPU time 8.49 seconds
Started Dec 20 12:56:30 PM PST 23
Finished Dec 20 12:56:44 PM PST 23
Peak memory 251160 kb
Host smart-7f0737cc-f497-4225-9025-14eff4190c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819031491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.2819031491
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.2297325793
Short name T576
Test name
Test status
Simulation time 63615328693 ps
CPU time 450.86 seconds
Started Dec 20 12:56:35 PM PST 23
Finished Dec 20 01:04:12 PM PST 23
Peak memory 270716 kb
Host smart-8dbf3324-8e05-4624-9cd8-1383c6005c7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297325793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.2297325793
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.3818848625
Short name T473
Test name
Test status
Simulation time 18810043387 ps
CPU time 423.41 seconds
Started Dec 20 12:56:23 PM PST 23
Finished Dec 20 01:03:33 PM PST 23
Peak memory 448212 kb
Host smart-8d9cd2c7-7d31-47d6-896e-187a97053c7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3818848625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.3818848625
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3909320719
Short name T975
Test name
Test status
Simulation time 16190822 ps
CPU time 0.89 seconds
Started Dec 20 12:56:25 PM PST 23
Finished Dec 20 12:56:33 PM PST 23
Peak memory 208456 kb
Host smart-5d7088bd-8341-4175-8c99-2a0c3f9e39a0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909320719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.3909320719
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.1663115410
Short name T444
Test name
Test status
Simulation time 21423959 ps
CPU time 1.23 seconds
Started Dec 20 12:56:46 PM PST 23
Finished Dec 20 12:56:52 PM PST 23
Peak memory 208560 kb
Host smart-42065152-b2b2-4f0a-8bd1-e7d4184c11bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663115410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.1663115410
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.1819453858
Short name T904
Test name
Test status
Simulation time 6749561898 ps
CPU time 14.97 seconds
Started Dec 20 12:56:33 PM PST 23
Finished Dec 20 12:56:54 PM PST 23
Peak memory 218592 kb
Host smart-f83e3db2-6397-4f04-a2a7-ed2677100fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819453858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.1819453858
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.1521069524
Short name T954
Test name
Test status
Simulation time 720025945 ps
CPU time 9.25 seconds
Started Dec 20 12:56:25 PM PST 23
Finished Dec 20 12:56:41 PM PST 23
Peak memory 209840 kb
Host smart-ad39e790-c580-475b-a569-f5f7ff1bae05
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521069524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_a
ccess.1521069524
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.1860495714
Short name T758
Test name
Test status
Simulation time 48652481 ps
CPU time 2.14 seconds
Started Dec 20 12:56:32 PM PST 23
Finished Dec 20 12:56:40 PM PST 23
Peak memory 218196 kb
Host smart-264ed4ad-61da-430a-a81e-f314e8f67dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860495714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.1860495714
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.819771233
Short name T809
Test name
Test status
Simulation time 942067627 ps
CPU time 9.88 seconds
Started Dec 20 12:56:46 PM PST 23
Finished Dec 20 12:57:01 PM PST 23
Peak memory 218324 kb
Host smart-dd243ad2-861c-4358-ada3-b09d20fa7036
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819771233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.819771233
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.2354118125
Short name T722
Test name
Test status
Simulation time 1099464741 ps
CPU time 19.5 seconds
Started Dec 20 12:56:31 PM PST 23
Finished Dec 20 12:56:56 PM PST 23
Peak memory 218204 kb
Host smart-494d7267-bc88-4dfc-8557-dba346fbc625
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354118125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.2354118125
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.4174451002
Short name T675
Test name
Test status
Simulation time 1039391530 ps
CPU time 15.81 seconds
Started Dec 20 12:57:14 PM PST 23
Finished Dec 20 12:57:47 PM PST 23
Peak memory 218168 kb
Host smart-ae497b87-0334-4a9c-b1f9-f4f349801f24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174451002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
4174451002
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.964708719
Short name T519
Test name
Test status
Simulation time 1784890662 ps
CPU time 10.37 seconds
Started Dec 20 12:56:32 PM PST 23
Finished Dec 20 12:56:49 PM PST 23
Peak memory 218288 kb
Host smart-5cb62ba8-c8bc-405a-a430-bf1d0417bfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964708719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.964708719
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.3173264203
Short name T434
Test name
Test status
Simulation time 45444956 ps
CPU time 2.26 seconds
Started Dec 20 12:56:22 PM PST 23
Finished Dec 20 12:56:30 PM PST 23
Peak memory 214100 kb
Host smart-f5248f65-01a2-4793-b3ac-00f8105b189a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173264203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.3173264203
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.1481787063
Short name T768
Test name
Test status
Simulation time 429255256 ps
CPU time 27.19 seconds
Started Dec 20 12:56:25 PM PST 23
Finished Dec 20 12:56:59 PM PST 23
Peak memory 251176 kb
Host smart-41691e53-74d2-449b-a6c0-ae09ae888dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481787063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.1481787063
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.756388039
Short name T719
Test name
Test status
Simulation time 82031232 ps
CPU time 6.56 seconds
Started Dec 20 12:56:41 PM PST 23
Finished Dec 20 12:56:52 PM PST 23
Peak memory 250640 kb
Host smart-61105b2d-6367-4aba-aa05-b2d176109937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756388039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.756388039
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.2708575105
Short name T682
Test name
Test status
Simulation time 7283494405 ps
CPU time 51.9 seconds
Started Dec 20 12:56:35 PM PST 23
Finished Dec 20 12:57:32 PM PST 23
Peak memory 221696 kb
Host smart-99f51bfe-8b84-4e69-af55-eb0bf61baa82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708575105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.2708575105
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.3001216165
Short name T620
Test name
Test status
Simulation time 12065332 ps
CPU time 0.88 seconds
Started Dec 20 12:56:38 PM PST 23
Finished Dec 20 12:56:44 PM PST 23
Peak memory 208256 kb
Host smart-83019e68-7652-490a-a92c-641f398aa4b5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001216165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.3001216165
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.2249595555
Short name T112
Test name
Test status
Simulation time 18572040 ps
CPU time 1.11 seconds
Started Dec 20 12:56:29 PM PST 23
Finished Dec 20 12:56:37 PM PST 23
Peak memory 209788 kb
Host smart-f8375af0-9fae-477f-a21c-e1be23da9fef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249595555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.2249595555
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.1431463330
Short name T382
Test name
Test status
Simulation time 1711445348 ps
CPU time 12.77 seconds
Started Dec 20 12:56:30 PM PST 23
Finished Dec 20 12:56:49 PM PST 23
Peak memory 218256 kb
Host smart-154cac91-fd90-450b-b198-ff004fa64c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431463330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.1431463330
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.2582160866
Short name T421
Test name
Test status
Simulation time 1324732690 ps
CPU time 8.6 seconds
Started Dec 20 12:56:42 PM PST 23
Finished Dec 20 12:56:56 PM PST 23
Peak memory 209656 kb
Host smart-7b0b8bbb-5ac5-474c-b4d2-41b3ecab772e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582160866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_a
ccess.2582160866
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.57420415
Short name T890
Test name
Test status
Simulation time 133600515 ps
CPU time 2.56 seconds
Started Dec 20 12:56:34 PM PST 23
Finished Dec 20 12:56:43 PM PST 23
Peak memory 218256 kb
Host smart-e7f282cb-9477-4327-8e5e-21c104d32324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57420415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.57420415
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.61201665
Short name T451
Test name
Test status
Simulation time 225965203 ps
CPU time 8.91 seconds
Started Dec 20 12:57:13 PM PST 23
Finished Dec 20 12:57:40 PM PST 23
Peak memory 218360 kb
Host smart-11677381-d3c2-45c8-af79-e40bcff03a0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61201665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.61201665
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.887383551
Short name T526
Test name
Test status
Simulation time 1447896464 ps
CPU time 11.21 seconds
Started Dec 20 12:56:44 PM PST 23
Finished Dec 20 12:57:00 PM PST 23
Peak memory 218224 kb
Host smart-3d4eb189-fb22-432a-a7a5-f4a29a08f7ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887383551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_di
gest.887383551
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.1657579788
Short name T877
Test name
Test status
Simulation time 1178402694 ps
CPU time 10.12 seconds
Started Dec 20 12:56:46 PM PST 23
Finished Dec 20 12:57:01 PM PST 23
Peak memory 218224 kb
Host smart-5fbbfffc-7775-4a5f-8d88-44dc1551f8fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657579788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
1657579788
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.550532549
Short name T668
Test name
Test status
Simulation time 391393341 ps
CPU time 13 seconds
Started Dec 20 12:56:40 PM PST 23
Finished Dec 20 12:56:58 PM PST 23
Peak memory 218188 kb
Host smart-7c004978-8bba-46be-8423-fb1c4bacb7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550532549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.550532549
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.1365063518
Short name T448
Test name
Test status
Simulation time 239777463 ps
CPU time 2.81 seconds
Started Dec 20 12:56:47 PM PST 23
Finished Dec 20 12:56:54 PM PST 23
Peak memory 213968 kb
Host smart-5cbef00c-e086-4d6d-8602-47ab8d6fde91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365063518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1365063518
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.3909168444
Short name T946
Test name
Test status
Simulation time 493273508 ps
CPU time 20.75 seconds
Started Dec 20 12:56:48 PM PST 23
Finished Dec 20 12:57:14 PM PST 23
Peak memory 251060 kb
Host smart-99923bc2-d3b0-42d5-b45d-98fd065bb740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909168444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.3909168444
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.2630056611
Short name T631
Test name
Test status
Simulation time 235333262 ps
CPU time 2.59 seconds
Started Dec 20 12:56:51 PM PST 23
Finished Dec 20 12:57:00 PM PST 23
Peak memory 222152 kb
Host smart-b4ea38d9-9a45-4978-a517-bfcf66a58e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630056611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2630056611
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.131653826
Short name T594
Test name
Test status
Simulation time 39780417641 ps
CPU time 250.16 seconds
Started Dec 20 12:56:31 PM PST 23
Finished Dec 20 01:00:47 PM PST 23
Peak memory 268264 kb
Host smart-fe836307-da97-45e3-b981-51f99009054a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131653826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.131653826
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.628204740
Short name T51
Test name
Test status
Simulation time 73152649737 ps
CPU time 631.52 seconds
Started Dec 20 12:56:58 PM PST 23
Finished Dec 20 01:07:43 PM PST 23
Peak memory 387360 kb
Host smart-804ec7bd-1118-404b-a63b-ab543a0e4f06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=628204740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.628204740
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.4255989998
Short name T593
Test name
Test status
Simulation time 52095094 ps
CPU time 0.79 seconds
Started Dec 20 12:56:35 PM PST 23
Finished Dec 20 12:56:41 PM PST 23
Peak memory 208420 kb
Host smart-c04f451f-11a9-4099-9ce0-88bbe4856650
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255989998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.4255989998
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.3600258263
Short name T931
Test name
Test status
Simulation time 22491733 ps
CPU time 1.17 seconds
Started Dec 20 12:56:57 PM PST 23
Finished Dec 20 12:57:09 PM PST 23
Peak memory 208468 kb
Host smart-8b288e5a-9777-4550-9a0f-f4f643d922df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600258263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.3600258263
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.1204174313
Short name T380
Test name
Test status
Simulation time 455771886 ps
CPU time 13.91 seconds
Started Dec 20 12:57:01 PM PST 23
Finished Dec 20 12:57:31 PM PST 23
Peak memory 218188 kb
Host smart-fbd6470e-95f6-4b0c-9adf-d55ab2fa1a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204174313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1204174313
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.520905391
Short name T762
Test name
Test status
Simulation time 2140120129 ps
CPU time 3.11 seconds
Started Dec 20 12:57:08 PM PST 23
Finished Dec 20 12:57:27 PM PST 23
Peak memory 209620 kb
Host smart-754bfb83-65b2-451f-ae75-5211eb7d9021
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520905391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_ac
cess.520905391
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.574045644
Short name T655
Test name
Test status
Simulation time 33985756 ps
CPU time 1.71 seconds
Started Dec 20 12:57:11 PM PST 23
Finished Dec 20 12:57:30 PM PST 23
Peak memory 218156 kb
Host smart-13f57fcd-d419-4256-9512-f92e70399c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574045644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.574045644
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.103467878
Short name T808
Test name
Test status
Simulation time 332930160 ps
CPU time 14.82 seconds
Started Dec 20 12:57:08 PM PST 23
Finished Dec 20 12:57:38 PM PST 23
Peak memory 219328 kb
Host smart-69099e25-2eb7-44e5-8ad7-35ce2c5489d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103467878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.103467878
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.787127414
Short name T345
Test name
Test status
Simulation time 399349408 ps
CPU time 14.55 seconds
Started Dec 20 12:57:12 PM PST 23
Finished Dec 20 12:57:44 PM PST 23
Peak memory 218160 kb
Host smart-1b72621d-3384-4aed-8b20-4caa22b14aef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787127414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_di
gest.787127414
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.1352767163
Short name T542
Test name
Test status
Simulation time 2494970989 ps
CPU time 14.79 seconds
Started Dec 20 12:57:01 PM PST 23
Finished Dec 20 12:57:32 PM PST 23
Peak memory 218144 kb
Host smart-74a51916-e40f-4320-973f-d8ce2fe37bf8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352767163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
1352767163
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.1115317328
Short name T751
Test name
Test status
Simulation time 202041409 ps
CPU time 7.96 seconds
Started Dec 20 12:57:01 PM PST 23
Finished Dec 20 12:57:25 PM PST 23
Peak memory 218220 kb
Host smart-1ca9f08b-63a7-41f6-89bc-4b8252d68784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115317328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.1115317328
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.1703226249
Short name T979
Test name
Test status
Simulation time 61594827 ps
CPU time 2.31 seconds
Started Dec 20 12:57:02 PM PST 23
Finished Dec 20 12:57:20 PM PST 23
Peak memory 213912 kb
Host smart-373117f2-eafb-44d6-afc1-6ecb4c949ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703226249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.1703226249
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.3832883580
Short name T424
Test name
Test status
Simulation time 992555736 ps
CPU time 27.54 seconds
Started Dec 20 12:57:01 PM PST 23
Finished Dec 20 12:57:44 PM PST 23
Peak memory 251224 kb
Host smart-e51c94ce-b679-4287-bc37-5975160f2303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832883580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3832883580
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.858275760
Short name T694
Test name
Test status
Simulation time 76964336 ps
CPU time 4.19 seconds
Started Dec 20 12:56:55 PM PST 23
Finished Dec 20 12:57:09 PM PST 23
Peak memory 218272 kb
Host smart-eebce543-0573-4d30-984e-0a90b7976f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858275760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.858275760
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.1281377545
Short name T38
Test name
Test status
Simulation time 9898394637 ps
CPU time 82.27 seconds
Started Dec 20 12:56:54 PM PST 23
Finished Dec 20 12:58:25 PM PST 23
Peak memory 221492 kb
Host smart-50e45893-c9d5-47d3-acd0-3b4071c9f992
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281377545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.1281377545
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2680785474
Short name T534
Test name
Test status
Simulation time 46271333 ps
CPU time 0.76 seconds
Started Dec 20 12:56:52 PM PST 23
Finished Dec 20 12:57:00 PM PST 23
Peak memory 208312 kb
Host smart-bbe01007-17a8-47c4-9347-9b63e7e5ab4e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680785474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.2680785474
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.1284643361
Short name T427
Test name
Test status
Simulation time 24606227 ps
CPU time 1.26 seconds
Started Dec 20 12:56:49 PM PST 23
Finished Dec 20 12:56:56 PM PST 23
Peak memory 209808 kb
Host smart-fcb21b19-20b5-4994-bfc4-61aa869da893
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284643361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1284643361
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.2641708294
Short name T623
Test name
Test status
Simulation time 301176999 ps
CPU time 14.69 seconds
Started Dec 20 12:56:52 PM PST 23
Finished Dec 20 12:57:14 PM PST 23
Peak memory 218264 kb
Host smart-23d78671-efb0-4d64-83d1-0ba72448ea84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641708294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.2641708294
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.429452351
Short name T684
Test name
Test status
Simulation time 123007279 ps
CPU time 3.33 seconds
Started Dec 20 12:56:24 PM PST 23
Finished Dec 20 12:56:34 PM PST 23
Peak memory 209796 kb
Host smart-2fcce7e3-6e51-43d1-a8be-3694311c4240
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429452351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_ac
cess.429452351
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.2247364283
Short name T602
Test name
Test status
Simulation time 150323877 ps
CPU time 1.7 seconds
Started Dec 20 12:56:43 PM PST 23
Finished Dec 20 12:56:49 PM PST 23
Peak memory 218276 kb
Host smart-c3b8805b-0080-4fb3-ad8c-ceec9ebfd27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247364283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.2247364283
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.1375494866
Short name T386
Test name
Test status
Simulation time 3254472235 ps
CPU time 14.37 seconds
Started Dec 20 12:56:31 PM PST 23
Finished Dec 20 12:56:51 PM PST 23
Peak memory 219276 kb
Host smart-3c07a76d-209a-41b1-a463-b5225b0c16a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375494866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.1375494866
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.952820219
Short name T536
Test name
Test status
Simulation time 1326326094 ps
CPU time 10.89 seconds
Started Dec 20 12:56:30 PM PST 23
Finished Dec 20 12:56:47 PM PST 23
Peak memory 218208 kb
Host smart-7e9db947-0198-4fe3-9874-9d4c6d79ba29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952820219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_di
gest.952820219
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.1164712460
Short name T511
Test name
Test status
Simulation time 846648646 ps
CPU time 8.44 seconds
Started Dec 20 12:56:28 PM PST 23
Finished Dec 20 12:56:43 PM PST 23
Peak memory 218204 kb
Host smart-a9ed8975-52e3-436c-8794-70bd0320a6c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164712460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
1164712460
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.612147053
Short name T476
Test name
Test status
Simulation time 285419772 ps
CPU time 11 seconds
Started Dec 20 12:56:50 PM PST 23
Finished Dec 20 12:57:07 PM PST 23
Peak memory 218452 kb
Host smart-5121a43f-53fc-4cf1-a2f9-b8e18512f530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612147053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.612147053
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.1668928806
Short name T938
Test name
Test status
Simulation time 42876014 ps
CPU time 1.35 seconds
Started Dec 20 12:57:11 PM PST 23
Finished Dec 20 12:57:29 PM PST 23
Peak memory 213096 kb
Host smart-3c7a94db-00c5-4727-8041-d11129773274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668928806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.1668928806
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.2535159278
Short name T528
Test name
Test status
Simulation time 351709404 ps
CPU time 33.97 seconds
Started Dec 20 12:57:00 PM PST 23
Finished Dec 20 12:57:57 PM PST 23
Peak memory 251184 kb
Host smart-62e2dbca-2af9-4661-af7b-503486c826d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535159278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.2535159278
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.1715378613
Short name T532
Test name
Test status
Simulation time 381370624 ps
CPU time 7.56 seconds
Started Dec 20 12:56:48 PM PST 23
Finished Dec 20 12:57:01 PM PST 23
Peak memory 251228 kb
Host smart-3decad96-5768-4f43-a2df-71a1ed0326ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715378613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.1715378613
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.756224754
Short name T816
Test name
Test status
Simulation time 29779730973 ps
CPU time 121.33 seconds
Started Dec 20 12:56:33 PM PST 23
Finished Dec 20 12:58:40 PM PST 23
Peak memory 282864 kb
Host smart-109e28d3-ca04-40bf-a31b-36e6043a942c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756224754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.756224754
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2008339957
Short name T356
Test name
Test status
Simulation time 11614444 ps
CPU time 0.87 seconds
Started Dec 20 12:56:40 PM PST 23
Finished Dec 20 12:56:46 PM PST 23
Peak memory 208184 kb
Host smart-94b419ff-72ed-4b80-94fe-e15634197465
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008339957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.2008339957
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.880332110
Short name T944
Test name
Test status
Simulation time 19348067 ps
CPU time 0.93 seconds
Started Dec 20 12:56:38 PM PST 23
Finished Dec 20 12:56:44 PM PST 23
Peak memory 209756 kb
Host smart-3b4d68a4-7794-4f32-b792-f635c937edf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880332110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.880332110
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.2083388876
Short name T695
Test name
Test status
Simulation time 659225955 ps
CPU time 16.1 seconds
Started Dec 20 12:56:37 PM PST 23
Finished Dec 20 12:56:59 PM PST 23
Peak memory 218120 kb
Host smart-c3c48538-a024-44ce-bb76-7bedb1602418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083388876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.2083388876
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.232525979
Short name T710
Test name
Test status
Simulation time 697973722 ps
CPU time 4.42 seconds
Started Dec 20 12:56:40 PM PST 23
Finished Dec 20 12:56:49 PM PST 23
Peak memory 209756 kb
Host smart-fd737bb0-0b38-4618-9330-84f30fd57e3e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232525979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_ac
cess.232525979
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.3559462198
Short name T491
Test name
Test status
Simulation time 207387944 ps
CPU time 3.92 seconds
Started Dec 20 12:56:33 PM PST 23
Finished Dec 20 12:56:42 PM PST 23
Peak memory 218168 kb
Host smart-5cec915a-f5ed-409b-bdc5-c25a039f0103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559462198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.3559462198
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.4065087786
Short name T644
Test name
Test status
Simulation time 307013400 ps
CPU time 13.53 seconds
Started Dec 20 12:56:32 PM PST 23
Finished Dec 20 12:56:51 PM PST 23
Peak memory 218648 kb
Host smart-995be313-1dd7-44cd-8c58-cedb1a7c496a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065087786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.4065087786
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.587283484
Short name T788
Test name
Test status
Simulation time 1611695129 ps
CPU time 16.18 seconds
Started Dec 20 12:57:00 PM PST 23
Finished Dec 20 12:57:30 PM PST 23
Peak memory 218176 kb
Host smart-f92ac2ae-a384-4c24-adef-1db3d0e381f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587283484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_di
gest.587283484
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.2557063719
Short name T902
Test name
Test status
Simulation time 194639960 ps
CPU time 7.69 seconds
Started Dec 20 12:56:46 PM PST 23
Finished Dec 20 12:57:06 PM PST 23
Peak memory 218252 kb
Host smart-3c375295-9612-4d69-9274-a538f03f6129
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557063719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
2557063719
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.2343018294
Short name T920
Test name
Test status
Simulation time 415531816 ps
CPU time 7.87 seconds
Started Dec 20 12:56:39 PM PST 23
Finished Dec 20 12:56:53 PM PST 23
Peak memory 218212 kb
Host smart-d8d68bb3-ae8d-4c8c-b94f-da9f3533411c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343018294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.2343018294
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.3220659985
Short name T84
Test name
Test status
Simulation time 173256443 ps
CPU time 2.45 seconds
Started Dec 20 12:56:35 PM PST 23
Finished Dec 20 12:56:43 PM PST 23
Peak memory 213832 kb
Host smart-8e862d6e-4c5b-436d-a490-221a9caa4445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220659985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.3220659985
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.894478567
Short name T704
Test name
Test status
Simulation time 177459511 ps
CPU time 24.64 seconds
Started Dec 20 12:56:21 PM PST 23
Finished Dec 20 12:56:52 PM PST 23
Peak memory 251020 kb
Host smart-783c26e9-87e6-41be-8295-387e3f6c234a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894478567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.894478567
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.3937998898
Short name T527
Test name
Test status
Simulation time 374818406 ps
CPU time 6.93 seconds
Started Dec 20 12:57:05 PM PST 23
Finished Dec 20 12:57:28 PM PST 23
Peak memory 250680 kb
Host smart-1c9131fe-d8cf-47cd-8aa2-b45b79cc9630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937998898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.3937998898
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.76979419
Short name T648
Test name
Test status
Simulation time 4799005815 ps
CPU time 163.49 seconds
Started Dec 20 12:56:58 PM PST 23
Finished Dec 20 12:59:54 PM PST 23
Peak memory 267724 kb
Host smart-5936cb3d-1314-40a7-8c4e-6049a9d629aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76979419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.lc_ctrl_stress_all.76979419
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2848281929
Short name T70
Test name
Test status
Simulation time 36052799 ps
CPU time 0.96 seconds
Started Dec 20 12:57:01 PM PST 23
Finished Dec 20 12:57:17 PM PST 23
Peak memory 211436 kb
Host smart-6f6f4622-8b89-4820-933d-5b679ed662ee
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848281929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.2848281929
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.1097129936
Short name T588
Test name
Test status
Simulation time 38403473 ps
CPU time 0.87 seconds
Started Dec 20 12:55:20 PM PST 23
Finished Dec 20 12:55:36 PM PST 23
Peak memory 208264 kb
Host smart-1cc91cdf-2a99-46b2-99d1-17a0a1dc595a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097129936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1097129936
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.823648557
Short name T469
Test name
Test status
Simulation time 34466198 ps
CPU time 0.88 seconds
Started Dec 20 12:55:14 PM PST 23
Finished Dec 20 12:55:32 PM PST 23
Peak memory 209716 kb
Host smart-85c90720-f2e4-4108-8d16-8ea9c1a2de5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823648557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.823648557
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.3775755081
Short name T25
Test name
Test status
Simulation time 219286475 ps
CPU time 8.24 seconds
Started Dec 20 12:55:08 PM PST 23
Finished Dec 20 12:55:36 PM PST 23
Peak memory 218352 kb
Host smart-b28d5765-46f8-47f8-8ed9-b1c07ae0a16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775755081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.3775755081
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.101906743
Short name T827
Test name
Test status
Simulation time 1067979771 ps
CPU time 3.99 seconds
Started Dec 20 12:55:20 PM PST 23
Finished Dec 20 12:55:39 PM PST 23
Peak memory 209776 kb
Host smart-7f9217d0-75c0-48f3-ba78-296ed72584e3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101906743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_acc
ess.101906743
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.651994452
Short name T430
Test name
Test status
Simulation time 7494664353 ps
CPU time 31.54 seconds
Started Dec 20 12:55:15 PM PST 23
Finished Dec 20 12:56:03 PM PST 23
Peak memory 218476 kb
Host smart-f3cf4e2c-e509-4dc5-9bd7-a265c73a14e6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651994452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_err
ors.651994452
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.2915093642
Short name T590
Test name
Test status
Simulation time 571510525 ps
CPU time 13.31 seconds
Started Dec 20 12:55:20 PM PST 23
Finished Dec 20 12:55:48 PM PST 23
Peak memory 218040 kb
Host smart-1e2bc7d3-ae2c-46a1-853c-0630cfbbbbe1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915093642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_
priority.2915093642
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.512662737
Short name T399
Test name
Test status
Simulation time 621455767 ps
CPU time 9.83 seconds
Started Dec 20 12:55:15 PM PST 23
Finished Dec 20 12:55:42 PM PST 23
Peak memory 218024 kb
Host smart-c8848070-b121-4b71-91f7-a3fb41a374c9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512662737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_
prog_failure.512662737
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.1563664408
Short name T740
Test name
Test status
Simulation time 2366143307 ps
CPU time 35.15 seconds
Started Dec 20 12:55:25 PM PST 23
Finished Dec 20 12:56:14 PM PST 23
Peak memory 213444 kb
Host smart-e22bca54-ded1-43eb-a280-4424aa5f2c29
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563664408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.1563664408
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1922988487
Short name T597
Test name
Test status
Simulation time 1075191392 ps
CPU time 7.19 seconds
Started Dec 20 12:55:01 PM PST 23
Finished Dec 20 12:55:29 PM PST 23
Peak memory 213100 kb
Host smart-d7388e95-aff9-4d5d-884b-9b4e538d6d0e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922988487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
1922988487
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.681331263
Short name T19
Test name
Test status
Simulation time 8435415450 ps
CPU time 83.53 seconds
Started Dec 20 12:55:01 PM PST 23
Finished Dec 20 12:56:46 PM PST 23
Peak memory 267500 kb
Host smart-0dd98bd8-f0b5-4851-ad6e-66c77954d5da
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681331263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_state_failure.681331263
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.3536593288
Short name T828
Test name
Test status
Simulation time 1466447702 ps
CPU time 16.08 seconds
Started Dec 20 12:55:18 PM PST 23
Finished Dec 20 12:55:50 PM PST 23
Peak memory 224956 kb
Host smart-465f6c62-9720-483f-8efc-005511cc1130
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536593288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.3536593288
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.4048073232
Short name T805
Test name
Test status
Simulation time 34771600 ps
CPU time 1.99 seconds
Started Dec 20 12:55:24 PM PST 23
Finished Dec 20 12:55:41 PM PST 23
Peak memory 218296 kb
Host smart-70ef5ca5-c75f-46d8-9ace-0d3aac379fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048073232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.4048073232
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.1660496720
Short name T900
Test name
Test status
Simulation time 384907612 ps
CPU time 9.59 seconds
Started Dec 20 12:55:05 PM PST 23
Finished Dec 20 12:55:37 PM PST 23
Peak memory 214276 kb
Host smart-4d8a2ed0-c33e-4d74-a04b-0e22f0c59ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660496720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.1660496720
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.1896864647
Short name T475
Test name
Test status
Simulation time 1167381356 ps
CPU time 13.18 seconds
Started Dec 20 12:55:25 PM PST 23
Finished Dec 20 12:55:53 PM PST 23
Peak memory 218120 kb
Host smart-d97a4022-f691-4557-be8e-0086bea2b886
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896864647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.1896864647
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.3037466169
Short name T937
Test name
Test status
Simulation time 405831131 ps
CPU time 15.82 seconds
Started Dec 20 12:55:16 PM PST 23
Finished Dec 20 12:55:49 PM PST 23
Peak memory 218216 kb
Host smart-4879bfb5-5216-421e-887f-a3ffad451fb3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037466169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.3037466169
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.2509386
Short name T376
Test name
Test status
Simulation time 2249193911 ps
CPU time 13.28 seconds
Started Dec 20 12:55:16 PM PST 23
Finished Dec 20 12:55:46 PM PST 23
Peak memory 218300 kb
Host smart-cf4535cb-e87d-49a7-9c6c-655b2e76ac9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.2509386
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.3275761474
Short name T971
Test name
Test status
Simulation time 630521255 ps
CPU time 7.51 seconds
Started Dec 20 12:55:17 PM PST 23
Finished Dec 20 12:55:41 PM PST 23
Peak memory 214660 kb
Host smart-4c312b5b-5bdc-4f7c-9034-961317334fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275761474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.3275761474
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.1648142476
Short name T132
Test name
Test status
Simulation time 432075616 ps
CPU time 21.81 seconds
Started Dec 20 12:55:08 PM PST 23
Finished Dec 20 12:55:50 PM PST 23
Peak memory 251052 kb
Host smart-53abbe58-8cee-4001-b460-07b040ede8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648142476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.1648142476
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.1945567291
Short name T663
Test name
Test status
Simulation time 137825920 ps
CPU time 7.79 seconds
Started Dec 20 12:55:05 PM PST 23
Finished Dec 20 12:55:35 PM PST 23
Peak memory 251100 kb
Host smart-4ea3dc9f-7f02-4987-bde6-81da34952ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945567291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.1945567291
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.959444572
Short name T862
Test name
Test status
Simulation time 19940771368 ps
CPU time 146 seconds
Started Dec 20 12:55:15 PM PST 23
Finished Dec 20 12:57:59 PM PST 23
Peak memory 249924 kb
Host smart-f938e1a8-d45f-44b4-ad15-02c2767df84e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959444572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.959444572
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.453796909
Short name T77
Test name
Test status
Simulation time 14368628 ps
CPU time 0.89 seconds
Started Dec 20 12:55:17 PM PST 23
Finished Dec 20 12:55:34 PM PST 23
Peak memory 211516 kb
Host smart-c112fdf1-c7f9-4754-9f5d-786f51330e30
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453796909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctr
l_volatile_unlock_smoke.453796909
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.1904066308
Short name T815
Test name
Test status
Simulation time 32641726 ps
CPU time 1.43 seconds
Started Dec 20 12:55:24 PM PST 23
Finished Dec 20 12:55:40 PM PST 23
Peak memory 209804 kb
Host smart-265bc777-1c5c-49c4-81dd-c42fb2374eb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904066308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.1904066308
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3689899851
Short name T207
Test name
Test status
Simulation time 10876315 ps
CPU time 0.76 seconds
Started Dec 20 12:55:24 PM PST 23
Finished Dec 20 12:55:39 PM PST 23
Peak memory 209508 kb
Host smart-f6878902-c2bc-4989-ac3a-9c601d1ca8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689899851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3689899851
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.735541182
Short name T122
Test name
Test status
Simulation time 446715185 ps
CPU time 13.91 seconds
Started Dec 20 12:55:23 PM PST 23
Finished Dec 20 12:55:51 PM PST 23
Peak memory 218152 kb
Host smart-203b5511-0404-425f-87c0-0d8c036cb9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735541182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.735541182
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.2769236380
Short name T863
Test name
Test status
Simulation time 360501166 ps
CPU time 4.19 seconds
Started Dec 20 12:55:25 PM PST 23
Finished Dec 20 12:55:43 PM PST 23
Peak memory 209556 kb
Host smart-c0ae5425-0e9b-4f3f-b0e8-02c9830fcc66
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769236380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_ac
cess.2769236380
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.754594411
Short name T838
Test name
Test status
Simulation time 8138180944 ps
CPU time 56.54 seconds
Started Dec 20 12:55:16 PM PST 23
Finished Dec 20 12:56:29 PM PST 23
Peak memory 218612 kb
Host smart-ecae1da1-3df6-42ab-884e-f8cafca8e783
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754594411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_err
ors.754594411
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.2033832661
Short name T22
Test name
Test status
Simulation time 104917007 ps
CPU time 3.39 seconds
Started Dec 20 12:55:17 PM PST 23
Finished Dec 20 12:55:40 PM PST 23
Peak memory 209808 kb
Host smart-25679a84-1383-498f-ac27-58f31a9b8859
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033832661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
priority.2033832661
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.3142884864
Short name T735
Test name
Test status
Simulation time 305978806 ps
CPU time 9.56 seconds
Started Dec 20 12:55:16 PM PST 23
Finished Dec 20 12:55:43 PM PST 23
Peak memory 218224 kb
Host smart-c75b7ae3-f001-4199-a4a0-46282a6c7dc0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142884864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.3142884864
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3536679292
Short name T91
Test name
Test status
Simulation time 4621115640 ps
CPU time 27.48 seconds
Started Dec 20 12:55:16 PM PST 23
Finished Dec 20 12:56:00 PM PST 23
Peak memory 213840 kb
Host smart-6b0ea2a4-335a-4cdb-8f5d-278d25e5a219
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536679292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.3536679292
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.2048623993
Short name T493
Test name
Test status
Simulation time 527522183 ps
CPU time 5.15 seconds
Started Dec 20 12:55:15 PM PST 23
Finished Dec 20 12:55:38 PM PST 23
Peak memory 213180 kb
Host smart-0059d0f3-c85b-4728-b8dc-a74b19894eb7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048623993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
2048623993
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.1158427006
Short name T813
Test name
Test status
Simulation time 985466611 ps
CPU time 28.44 seconds
Started Dec 20 12:55:24 PM PST 23
Finished Dec 20 12:56:07 PM PST 23
Peak memory 251196 kb
Host smart-6569e317-c0f8-4209-b6c2-741b5efc06e4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158427006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.1158427006
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1938409912
Short name T435
Test name
Test status
Simulation time 776205068 ps
CPU time 18.36 seconds
Started Dec 20 12:55:24 PM PST 23
Finished Dec 20 12:55:57 PM PST 23
Peak memory 218292 kb
Host smart-85cb21a9-6b5b-4c69-87b2-aa4b42a08005
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938409912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.1938409912
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.1233212308
Short name T394
Test name
Test status
Simulation time 215621977 ps
CPU time 2.32 seconds
Started Dec 20 12:55:21 PM PST 23
Finished Dec 20 12:55:38 PM PST 23
Peak memory 218348 kb
Host smart-ac340f51-4ff4-49a6-b934-bca1dcc06371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233212308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.1233212308
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.2028327769
Short name T583
Test name
Test status
Simulation time 1349956115 ps
CPU time 8.75 seconds
Started Dec 20 12:55:28 PM PST 23
Finished Dec 20 12:55:52 PM PST 23
Peak memory 214292 kb
Host smart-021e917c-8046-4c2b-82b9-47c738a0258d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028327769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.2028327769
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.868420685
Short name T871
Test name
Test status
Simulation time 827603589 ps
CPU time 20.08 seconds
Started Dec 20 12:55:31 PM PST 23
Finished Dec 20 12:56:06 PM PST 23
Peak memory 219364 kb
Host smart-af1d6c5c-5bc1-4c20-8182-a80e479afa73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868420685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.868420685
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.1728440832
Short name T462
Test name
Test status
Simulation time 2851228328 ps
CPU time 13.02 seconds
Started Dec 20 12:55:26 PM PST 23
Finished Dec 20 12:55:53 PM PST 23
Peak memory 218300 kb
Host smart-5b44d2b2-250d-4b1c-95a8-41aecfe44a9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728440832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.1728440832
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.812164688
Short name T374
Test name
Test status
Simulation time 341357806 ps
CPU time 9.51 seconds
Started Dec 20 12:55:24 PM PST 23
Finished Dec 20 12:55:48 PM PST 23
Peak memory 218016 kb
Host smart-0e9fb372-9078-4514-8ce9-0cd72d6efb00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812164688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.812164688
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.287560987
Short name T373
Test name
Test status
Simulation time 1308980866 ps
CPU time 8.2 seconds
Started Dec 20 12:55:27 PM PST 23
Finished Dec 20 12:55:50 PM PST 23
Peak memory 218304 kb
Host smart-0dc1e51a-ba6e-4408-a708-ad1b14eb7256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287560987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.287560987
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.3481856039
Short name T761
Test name
Test status
Simulation time 81673553 ps
CPU time 2.71 seconds
Started Dec 20 12:55:19 PM PST 23
Finished Dec 20 12:55:37 PM PST 23
Peak memory 213796 kb
Host smart-53598ef2-57c8-4a6c-9296-b96000f2e948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481856039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.3481856039
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.3684787566
Short name T734
Test name
Test status
Simulation time 1023465026 ps
CPU time 22.99 seconds
Started Dec 20 12:55:27 PM PST 23
Finished Dec 20 12:56:04 PM PST 23
Peak memory 251072 kb
Host smart-8e032fae-9d7a-461c-ab7f-43c64bf04c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684787566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.3684787566
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.2837060597
Short name T332
Test name
Test status
Simulation time 584128006 ps
CPU time 3.04 seconds
Started Dec 20 12:55:24 PM PST 23
Finished Dec 20 12:55:42 PM PST 23
Peak memory 218072 kb
Host smart-9b2da11d-627e-4891-903b-24d0fd44d561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837060597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.2837060597
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.938435864
Short name T556
Test name
Test status
Simulation time 6091117412 ps
CPU time 122.64 seconds
Started Dec 20 12:55:16 PM PST 23
Finished Dec 20 12:57:35 PM PST 23
Peak memory 278136 kb
Host smart-1cdc4e16-125c-4455-814a-a6234976c1a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938435864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.938435864
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.3329071761
Short name T658
Test name
Test status
Simulation time 11999645 ps
CPU time 0.9 seconds
Started Dec 20 12:55:24 PM PST 23
Finished Dec 20 12:55:39 PM PST 23
Peak memory 208260 kb
Host smart-42ad8104-4a9a-4495-b476-792b8eb6d2f5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329071761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.3329071761
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.2786007264
Short name T398
Test name
Test status
Simulation time 36739601 ps
CPU time 1.14 seconds
Started Dec 20 12:55:19 PM PST 23
Finished Dec 20 12:55:36 PM PST 23
Peak memory 209792 kb
Host smart-d115799e-4b26-4d8a-954f-2ac19e994201
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786007264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.2786007264
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.3523989564
Short name T632
Test name
Test status
Simulation time 92228059 ps
CPU time 0.88 seconds
Started Dec 20 12:55:28 PM PST 23
Finished Dec 20 12:55:44 PM PST 23
Peak memory 208280 kb
Host smart-3721e054-25c5-4330-9742-84c96e3d1b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523989564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.3523989564
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.3037266768
Short name T901
Test name
Test status
Simulation time 2748898656 ps
CPU time 19.01 seconds
Started Dec 20 12:55:16 PM PST 23
Finished Dec 20 12:55:52 PM PST 23
Peak memory 218352 kb
Host smart-15a3882b-041c-457e-ad77-9d068e73481b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037266768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.3037266768
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.231166664
Short name T882
Test name
Test status
Simulation time 109254679 ps
CPU time 3.38 seconds
Started Dec 20 12:55:25 PM PST 23
Finished Dec 20 12:55:43 PM PST 23
Peak memory 209896 kb
Host smart-196bd55c-c519-4a0b-8985-3f81ea3d52a0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231166664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_acc
ess.231166664
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.2720845279
Short name T109
Test name
Test status
Simulation time 5595676290 ps
CPU time 41.47 seconds
Started Dec 20 12:55:16 PM PST 23
Finished Dec 20 12:56:15 PM PST 23
Peak memory 218228 kb
Host smart-f34a75c8-6684-4aca-9e25-88358782df8f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720845279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.2720845279
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.2548142421
Short name T592
Test name
Test status
Simulation time 520034165 ps
CPU time 5.97 seconds
Started Dec 20 12:55:21 PM PST 23
Finished Dec 20 12:55:42 PM PST 23
Peak memory 209824 kb
Host smart-e731da61-c864-4278-bd7f-59f8999f2b43
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548142421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
priority.2548142421
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.477810812
Short name T736
Test name
Test status
Simulation time 154514920 ps
CPU time 4.58 seconds
Started Dec 20 12:55:30 PM PST 23
Finished Dec 20 12:55:50 PM PST 23
Peak memory 218100 kb
Host smart-7ae33666-af29-4c1a-a7bc-5f7f4925a475
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477810812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
prog_failure.477810812
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.3922236367
Short name T697
Test name
Test status
Simulation time 5443983345 ps
CPU time 13.76 seconds
Started Dec 20 12:55:22 PM PST 23
Finished Dec 20 12:55:50 PM PST 23
Peak memory 213804 kb
Host smart-2dfe6fcb-454f-4151-9a0c-bf8964cd9b5e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922236367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.3922236367
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.3077539938
Short name T771
Test name
Test status
Simulation time 341800474 ps
CPU time 1.85 seconds
Started Dec 20 12:55:17 PM PST 23
Finished Dec 20 12:55:35 PM PST 23
Peak memory 212896 kb
Host smart-748d3a1b-0994-4614-bbb2-691586fdfd88
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077539938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
3077539938
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.172391651
Short name T331
Test name
Test status
Simulation time 1734339239 ps
CPU time 52.91 seconds
Started Dec 20 12:55:25 PM PST 23
Finished Dec 20 12:56:33 PM PST 23
Peak memory 275744 kb
Host smart-97aff333-2bd4-47d2-81b9-875399bde4fe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172391651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_state_failure.172391651
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.638140452
Short name T362
Test name
Test status
Simulation time 800537999 ps
CPU time 11.98 seconds
Started Dec 20 12:55:19 PM PST 23
Finished Dec 20 12:55:46 PM PST 23
Peak memory 251220 kb
Host smart-7cdf0308-2c1a-43e5-9492-a218d93d6ed9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638140452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_state_post_trans.638140452
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.189496681
Short name T844
Test name
Test status
Simulation time 271614848 ps
CPU time 3.45 seconds
Started Dec 20 12:55:23 PM PST 23
Finished Dec 20 12:55:41 PM PST 23
Peak memory 218168 kb
Host smart-53213410-4fa7-45ca-964b-2d051c260caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189496681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.189496681
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3157133025
Short name T978
Test name
Test status
Simulation time 342351371 ps
CPU time 18.7 seconds
Started Dec 20 12:55:16 PM PST 23
Finished Dec 20 12:55:52 PM PST 23
Peak memory 214432 kb
Host smart-72eacaaa-de8d-42d2-9a91-6bcb0daba951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157133025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3157133025
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.1912090735
Short name T73
Test name
Test status
Simulation time 2370513802 ps
CPU time 15.67 seconds
Started Dec 20 12:55:16 PM PST 23
Finished Dec 20 12:55:48 PM PST 23
Peak memory 218340 kb
Host smart-a58e9ada-2611-4bc4-b2c9-133259adab24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912090735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.1912090735
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.2197575086
Short name T797
Test name
Test status
Simulation time 1127670164 ps
CPU time 7.84 seconds
Started Dec 20 12:55:26 PM PST 23
Finished Dec 20 12:55:49 PM PST 23
Peak memory 217992 kb
Host smart-6b2eed9e-e987-4e68-b1bc-c4101c0299c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197575086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.2197575086
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1201975729
Short name T437
Test name
Test status
Simulation time 9538549922 ps
CPU time 12.94 seconds
Started Dec 20 12:55:18 PM PST 23
Finished Dec 20 12:55:47 PM PST 23
Peak memory 218044 kb
Host smart-b7fcf260-0a36-474c-a384-68cc57a0451b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201975729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
201975729
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.1383976922
Short name T807
Test name
Test status
Simulation time 318058052 ps
CPU time 5.78 seconds
Started Dec 20 12:55:30 PM PST 23
Finished Dec 20 12:55:51 PM PST 23
Peak memory 218156 kb
Host smart-da043faf-efb4-478e-a657-e583fe74e827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383976922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.1383976922
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.1518615581
Short name T823
Test name
Test status
Simulation time 146514814 ps
CPU time 3.93 seconds
Started Dec 20 12:55:28 PM PST 23
Finished Dec 20 12:55:47 PM PST 23
Peak memory 214180 kb
Host smart-001ae95f-47ba-49ca-90f5-0823ff8d0150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518615581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.1518615581
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.792007424
Short name T837
Test name
Test status
Simulation time 288017827 ps
CPU time 35.97 seconds
Started Dec 20 12:55:15 PM PST 23
Finished Dec 20 12:56:08 PM PST 23
Peak memory 251172 kb
Host smart-978f1ec0-b043-4c6c-9dab-5c68203d972e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792007424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.792007424
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.2340856822
Short name T857
Test name
Test status
Simulation time 201129104 ps
CPU time 6.49 seconds
Started Dec 20 12:55:21 PM PST 23
Finished Dec 20 12:55:42 PM PST 23
Peak memory 246488 kb
Host smart-031e8445-e817-4b48-adaf-29436d8339c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340856822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.2340856822
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.1321875596
Short name T909
Test name
Test status
Simulation time 8154610409 ps
CPU time 59.37 seconds
Started Dec 20 12:55:36 PM PST 23
Finished Dec 20 12:56:49 PM PST 23
Peak memory 250628 kb
Host smart-72e241e9-633c-4f35-b036-2fbd1d35a865
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321875596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.1321875596
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1662977622
Short name T774
Test name
Test status
Simulation time 160169122 ps
CPU time 1.11 seconds
Started Dec 20 12:55:16 PM PST 23
Finished Dec 20 12:55:34 PM PST 23
Peak memory 212660 kb
Host smart-ac4051db-094f-4361-8f99-94d4558d23d1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662977622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.1662977622
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.951644403
Short name T384
Test name
Test status
Simulation time 64020344 ps
CPU time 1.09 seconds
Started Dec 20 12:55:16 PM PST 23
Finished Dec 20 12:55:34 PM PST 23
Peak memory 209864 kb
Host smart-e4a9d37e-93f7-4f9f-a619-7f650563e14b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951644403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.951644403
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.665136604
Short name T589
Test name
Test status
Simulation time 1578880423 ps
CPU time 27.38 seconds
Started Dec 20 12:55:16 PM PST 23
Finished Dec 20 12:56:00 PM PST 23
Peak memory 218276 kb
Host smart-a51176fa-d1ac-4ad2-bdac-25bb224238e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665136604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.665136604
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.2315513817
Short name T31
Test name
Test status
Simulation time 314438070 ps
CPU time 4.73 seconds
Started Dec 20 12:55:30 PM PST 23
Finished Dec 20 12:55:50 PM PST 23
Peak memory 209768 kb
Host smart-64431a60-ca25-48dc-ad24-569b21583b3a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315513817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_ac
cess.2315513817
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.2176736084
Short name T472
Test name
Test status
Simulation time 3645581103 ps
CPU time 18.14 seconds
Started Dec 20 12:55:17 PM PST 23
Finished Dec 20 12:55:55 PM PST 23
Peak memory 218296 kb
Host smart-2ced4051-bc8a-419f-81ec-a279ee0bcf08
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176736084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.2176736084
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.4029357529
Short name T650
Test name
Test status
Simulation time 100919925 ps
CPU time 3.22 seconds
Started Dec 20 12:55:29 PM PST 23
Finished Dec 20 12:55:47 PM PST 23
Peak memory 218032 kb
Host smart-c8a5b317-d920-4735-81b1-d5fb33dd3588
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029357529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
priority.4029357529
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.506235458
Short name T515
Test name
Test status
Simulation time 9062668481 ps
CPU time 20.35 seconds
Started Dec 20 12:55:17 PM PST 23
Finished Dec 20 12:56:00 PM PST 23
Peak memory 218280 kb
Host smart-ad4afa79-9edd-448d-9ffd-f3d1fc8878b6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506235458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
prog_failure.506235458
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3586440496
Short name T33
Test name
Test status
Simulation time 2126933381 ps
CPU time 15.68 seconds
Started Dec 20 12:55:23 PM PST 23
Finished Dec 20 12:55:53 PM PST 23
Peak memory 213124 kb
Host smart-a492b595-d787-42f8-a567-2d0cce040c27
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586440496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.3586440496
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.1833662187
Short name T95
Test name
Test status
Simulation time 1763131141 ps
CPU time 2.63 seconds
Started Dec 20 12:55:22 PM PST 23
Finished Dec 20 12:55:39 PM PST 23
Peak memory 213012 kb
Host smart-26170e9b-78ce-45ff-b26e-9f96ef3a07bb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833662187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
1833662187
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.196961550
Short name T18
Test name
Test status
Simulation time 2350993564 ps
CPU time 73.62 seconds
Started Dec 20 12:55:28 PM PST 23
Finished Dec 20 12:56:57 PM PST 23
Peak memory 275864 kb
Host smart-10219350-da27-4661-ab01-c5c2b1980565
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196961550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_state_failure.196961550
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.2706785122
Short name T415
Test name
Test status
Simulation time 1029116605 ps
CPU time 8.65 seconds
Started Dec 20 12:55:17 PM PST 23
Finished Dec 20 12:55:42 PM PST 23
Peak memory 218216 kb
Host smart-fa81eceb-6998-4625-b9a4-b648315853fd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706785122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.2706785122
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.2669397452
Short name T72
Test name
Test status
Simulation time 295008016 ps
CPU time 2.73 seconds
Started Dec 20 12:55:23 PM PST 23
Finished Dec 20 12:55:40 PM PST 23
Peak memory 218348 kb
Host smart-f4ee3dfb-2905-4383-bd81-120ad6bc5dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669397452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.2669397452
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.715021631
Short name T11
Test name
Test status
Simulation time 911148397 ps
CPU time 9.76 seconds
Started Dec 20 12:55:30 PM PST 23
Finished Dec 20 12:55:55 PM PST 23
Peak memory 214140 kb
Host smart-4245f8a3-8a43-4d49-94c0-e17b250a26b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715021631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.715021631
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.3562904199
Short name T980
Test name
Test status
Simulation time 317244990 ps
CPU time 11.14 seconds
Started Dec 20 12:55:16 PM PST 23
Finished Dec 20 12:55:44 PM PST 23
Peak memory 218232 kb
Host smart-a2fda0e9-063f-4cb5-87d3-389f284b1026
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562904199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.3562904199
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2461602528
Short name T923
Test name
Test status
Simulation time 350874579 ps
CPU time 13.64 seconds
Started Dec 20 12:55:30 PM PST 23
Finished Dec 20 12:55:58 PM PST 23
Peak memory 218240 kb
Host smart-047bdbd3-f82c-441a-b074-b477c558cb43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461602528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2461602528
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3572894148
Short name T950
Test name
Test status
Simulation time 683104165 ps
CPU time 9.45 seconds
Started Dec 20 12:55:16 PM PST 23
Finished Dec 20 12:55:43 PM PST 23
Peak memory 218156 kb
Host smart-ac00d0d2-94cb-4174-b91c-e62bae12e108
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572894148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.3
572894148
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.2895210636
Short name T903
Test name
Test status
Simulation time 629075273 ps
CPU time 7.63 seconds
Started Dec 20 12:55:30 PM PST 23
Finished Dec 20 12:55:53 PM PST 23
Peak memory 218264 kb
Host smart-89d05ada-7884-4659-bf41-2ef5a9471b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895210636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.2895210636
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.854070316
Short name T90
Test name
Test status
Simulation time 36925620 ps
CPU time 2.54 seconds
Started Dec 20 12:55:16 PM PST 23
Finished Dec 20 12:55:35 PM PST 23
Peak memory 214244 kb
Host smart-a47bb407-9035-4bfe-87d6-a44872a3a4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854070316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.854070316
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.3023852993
Short name T657
Test name
Test status
Simulation time 1496231457 ps
CPU time 34.63 seconds
Started Dec 20 12:55:16 PM PST 23
Finished Dec 20 12:56:08 PM PST 23
Peak memory 251220 kb
Host smart-7b84114c-ce0c-42ef-bd8a-00375f4cb7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023852993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.3023852993
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.2775632721
Short name T817
Test name
Test status
Simulation time 59919719 ps
CPU time 6.44 seconds
Started Dec 20 12:55:25 PM PST 23
Finished Dec 20 12:55:45 PM PST 23
Peak memory 246048 kb
Host smart-f38e84d2-d409-4f52-80fe-c5c56e5d9658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775632721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.2775632721
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.1456586126
Short name T835
Test name
Test status
Simulation time 47155075073 ps
CPU time 205.66 seconds
Started Dec 20 12:55:24 PM PST 23
Finished Dec 20 12:59:04 PM PST 23
Peak memory 251348 kb
Host smart-8031dbd0-d20d-4bf6-a20a-7fbae9671cdd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456586126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.1456586126
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3799717922
Short name T93
Test name
Test status
Simulation time 15933015 ps
CPU time 1.12 seconds
Started Dec 20 12:55:21 PM PST 23
Finished Dec 20 12:55:37 PM PST 23
Peak memory 212588 kb
Host smart-9aa90c36-6c9a-45de-ab20-6b259b29c39d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799717922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.3799717922
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.1835679468
Short name T608
Test name
Test status
Simulation time 20086660 ps
CPU time 1.2 seconds
Started Dec 20 12:55:16 PM PST 23
Finished Dec 20 12:55:34 PM PST 23
Peak memory 209844 kb
Host smart-9ea8dfe4-7cf4-4f9d-957f-94ce8780285d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835679468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.1835679468
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.3511808295
Short name T846
Test name
Test status
Simulation time 26729539 ps
CPU time 0.85 seconds
Started Dec 20 12:55:30 PM PST 23
Finished Dec 20 12:55:46 PM PST 23
Peak memory 209520 kb
Host smart-5ab433ef-3d2e-4857-8fe5-a1fa36ad6ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511808295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.3511808295
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.1237077806
Short name T834
Test name
Test status
Simulation time 2043481954 ps
CPU time 13.41 seconds
Started Dec 20 12:55:22 PM PST 23
Finished Dec 20 12:55:50 PM PST 23
Peak memory 218304 kb
Host smart-039e7f90-4892-4caa-b5da-17f69ccf6a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237077806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1237077806
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.3922883810
Short name T956
Test name
Test status
Simulation time 1544165393 ps
CPU time 7.49 seconds
Started Dec 20 12:55:34 PM PST 23
Finished Dec 20 12:55:55 PM PST 23
Peak memory 209760 kb
Host smart-655998e9-e5d0-4c7d-b409-41e392942dbe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922883810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_ac
cess.3922883810
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.279351522
Short name T369
Test name
Test status
Simulation time 5680798557 ps
CPU time 57.9 seconds
Started Dec 20 12:55:17 PM PST 23
Finished Dec 20 12:56:31 PM PST 23
Peak memory 217988 kb
Host smart-f85866d9-0d54-445c-a8b6-3aec0500ee26
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279351522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_err
ors.279351522
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.392434270
Short name T921
Test name
Test status
Simulation time 352476657 ps
CPU time 4.48 seconds
Started Dec 20 12:55:21 PM PST 23
Finished Dec 20 12:55:40 PM PST 23
Peak memory 209840 kb
Host smart-53960b83-6462-4b9c-901d-967e7220f5cd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392434270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_p
riority.392434270
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.4160639664
Short name T678
Test name
Test status
Simulation time 1242854166 ps
CPU time 5.23 seconds
Started Dec 20 12:55:24 PM PST 23
Finished Dec 20 12:55:43 PM PST 23
Peak memory 218228 kb
Host smart-ec82ba2c-50c5-493a-b61e-33c85ba57115
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160639664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.4160639664
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.98268506
Short name T100
Test name
Test status
Simulation time 1178010780 ps
CPU time 32.74 seconds
Started Dec 20 12:55:17 PM PST 23
Finished Dec 20 12:56:06 PM PST 23
Peak memory 213424 kb
Host smart-55ccf7b0-4a63-4c80-af53-645b03a9e8bc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98268506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jt
ag_regwen_during_op.98268506
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2873277184
Short name T83
Test name
Test status
Simulation time 1193840722 ps
CPU time 4.35 seconds
Started Dec 20 12:55:17 PM PST 23
Finished Dec 20 12:55:38 PM PST 23
Peak memory 213260 kb
Host smart-a31d4936-03c6-4579-b86c-8e47b6fa00f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873277184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
2873277184
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1252315493
Short name T875
Test name
Test status
Simulation time 1609485908 ps
CPU time 43.46 seconds
Started Dec 20 12:55:16 PM PST 23
Finished Dec 20 12:56:16 PM PST 23
Peak memory 267808 kb
Host smart-833965fe-b1de-4b2b-a4a0-b945b743185c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252315493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.1252315493
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.868955463
Short name T562
Test name
Test status
Simulation time 2026150737 ps
CPU time 9.17 seconds
Started Dec 20 12:55:18 PM PST 23
Finished Dec 20 12:55:43 PM PST 23
Peak memory 222764 kb
Host smart-4fc8958e-de3d-4ad1-9e0f-53d09eb53de6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868955463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_state_post_trans.868955463
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.3665947237
Short name T543
Test name
Test status
Simulation time 269774532 ps
CPU time 4.11 seconds
Started Dec 20 12:55:18 PM PST 23
Finished Dec 20 12:55:38 PM PST 23
Peak memory 218216 kb
Host smart-df72d5a5-8c2a-465b-9274-4bef18a6ca1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665947237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.3665947237
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.1162720907
Short name T80
Test name
Test status
Simulation time 681150355 ps
CPU time 6.44 seconds
Started Dec 20 12:55:32 PM PST 23
Finished Dec 20 12:55:52 PM PST 23
Peak memory 213524 kb
Host smart-556fc2f9-d251-476a-8abb-6df751d8ab2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162720907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.1162720907
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.3784905530
Short name T636
Test name
Test status
Simulation time 344349368 ps
CPU time 13.1 seconds
Started Dec 20 12:55:17 PM PST 23
Finished Dec 20 12:55:46 PM PST 23
Peak memory 217808 kb
Host smart-f1f96ddc-0b45-4175-a9c4-8b5b20af3a60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784905530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.3784905530
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.1397952326
Short name T961
Test name
Test status
Simulation time 315492413 ps
CPU time 11.36 seconds
Started Dec 20 12:55:30 PM PST 23
Finished Dec 20 12:55:56 PM PST 23
Peak memory 218236 kb
Host smart-bfe37116-5919-43c5-8aa0-2145e0b20bbb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397952326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.1
397952326
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.521784655
Short name T531
Test name
Test status
Simulation time 284765021 ps
CPU time 7.05 seconds
Started Dec 20 12:55:22 PM PST 23
Finished Dec 20 12:55:43 PM PST 23
Peak memory 218296 kb
Host smart-7e877728-347f-4636-99df-31ed57798b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521784655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.521784655
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.1841545772
Short name T409
Test name
Test status
Simulation time 27599026 ps
CPU time 2.02 seconds
Started Dec 20 12:55:17 PM PST 23
Finished Dec 20 12:55:35 PM PST 23
Peak memory 213632 kb
Host smart-69997c30-c55c-41ec-9c2e-2e50006bc2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841545772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1841545772
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.577925282
Short name T535
Test name
Test status
Simulation time 1222954319 ps
CPU time 22.06 seconds
Started Dec 20 12:55:18 PM PST 23
Finished Dec 20 12:55:56 PM PST 23
Peak memory 251172 kb
Host smart-57d22a69-fbbc-4c5d-8f54-12475b11222f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577925282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.577925282
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.3788225764
Short name T411
Test name
Test status
Simulation time 452800455 ps
CPU time 8.59 seconds
Started Dec 20 12:55:34 PM PST 23
Finished Dec 20 12:55:56 PM PST 23
Peak memory 251232 kb
Host smart-72576ec2-b935-4e2c-9c7e-dc4c63c27f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788225764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.3788225764
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.1516045610
Short name T949
Test name
Test status
Simulation time 3524272817 ps
CPU time 88.69 seconds
Started Dec 20 12:55:30 PM PST 23
Finished Dec 20 12:57:14 PM PST 23
Peak memory 284112 kb
Host smart-b1ed9433-a78c-499e-bcbb-d82b5a06d814
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516045610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.1516045610
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.4088951714
Short name T700
Test name
Test status
Simulation time 18356534 ps
CPU time 0.7 seconds
Started Dec 20 12:55:23 PM PST 23
Finished Dec 20 12:55:38 PM PST 23
Peak memory 207088 kb
Host smart-e092629f-43cf-4b86-8bd5-dd1b34af3d8d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088951714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.4088951714
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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