LC_CTRL Simulation Results

Wednesday December 20 2023 20:02:55 UTC

GitHub Revision: 9601d3bbdd

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 30104064247514112511662306974640835321092728874679524971043777466318536599043

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	12.160s	849.453us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.300s	39.240us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.030s	58.938us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.050s	97.002us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.690s	165.915us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.770s	32.496us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.030s	58.938us	20	20	100.00
		lc_ctrl_csr_aliasing	1.690s	165.915us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.190s	128.062us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	18.990s	299.506us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.960s	13.146us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.110s	269.775us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	35.970s	288.018us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	27.380s	1.579ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	35.970s	288.018us	50	50	100.00
		lc_ctrl_prog_failure	4.110s	269.775us	50	50	100.00
		lc_ctrl_errors	27.380s	1.579ms	50	50	100.00
		lc_ctrl_security_escalation	17.930s	1.821ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.393m	9.824ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.350s	9.063ms	20	20	100.00
		lc_ctrl_jtag_errors	1.255m	2.828ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	8.780s	330.742us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	34.060s	1.115ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.350s	9.063ms	20	20	100.00
		lc_ctrl_jtag_errors	1.255m	2.828ms	20	20	100.00
		lc_ctrl_jtag_access	18.280s	1.529ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	35.150s	2.366ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	2.780s	92.991us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.830s	701.471us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	41.000s	2.004ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	22.360s	988.708us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.750s	79.994us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.010s	98.419us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.780s	100.706us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	13.310s	571.511us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.410s	24.237us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	7.514m	63.615ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.430s	32.642us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.140s	297.594us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.140s	297.594us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.300s	39.240us	5	5	100.00
		lc_ctrl_csr_rw	1.030s	58.938us	20	20	100.00
		lc_ctrl_csr_aliasing	1.690s	165.915us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.690s	37.302us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.300s	39.240us	5	5	100.00
		lc_ctrl_csr_rw	1.030s	58.938us	20	20	100.00
		lc_ctrl_csr_aliasing	1.690s	165.915us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.690s	37.302us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	38.570s	939.450us	5	5	100.00
		lc_ctrl_tl_intg_err	3.950s	218.051us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.950s	218.051us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	18.990s	299.506us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	35.970s	288.018us	50	50	100.00
		lc_ctrl_sec_cm	38.570s	939.450us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	35.970s	288.018us	50	50	100.00
		lc_ctrl_sec_cm	38.570s	939.450us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	35.970s	288.018us	50	50	100.00
		lc_ctrl_sec_cm	38.570s	939.450us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	35.970s	288.018us	50	50	100.00
		lc_ctrl_sec_cm	38.570s	939.450us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	35.970s	288.018us	50	50	100.00
		lc_ctrl_sec_cm	38.570s	939.450us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	35.970s	288.018us	50	50	100.00
		lc_ctrl_sec_cm	38.570s	939.450us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	35.970s	288.018us	50	50	100.00
		lc_ctrl_sec_cm	38.570s	939.450us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	35.970s	288.018us	50	50	100.00
		lc_ctrl_sec_cm	38.570s	939.450us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	17.930s	1.821ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.190s	128.062us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	34.060s	1.115ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	20.080s	827.604us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	20.080s	827.604us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	19.500s	1.099ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	21.560s	630.313us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	21.560s	630.313us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	10.525m	73.153ms	9	50	18.00
V3		TOTAL			9	50	18.00
		TOTAL			989	1030	96.02

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.30	97.29	95.52	91.98	100.00	95.93	98.73	94.64

Failure Buckets

• Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 25 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 25 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.97227834857795092392027765220135496085497866061515388473714879736579664216684
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:f01a2909-a380-4169-b538-bbf398891df3
      

    • 3.lc_ctrl_stress_all_with_rand_reset.45978869952314885706907912059517458030343089972087388452590393697135897423308
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:b12eda82-5436-40ee-a7ca-12c376fc9875
      

    • ... and 23 more failures.

• Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 7 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 7 failures.

    • 4.lc_ctrl_stress_all_with_rand_reset.16372304983587735981460398198921917129638515518182135252146117815789537521019
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:8461bee5-c065-4c9f-888e-8620b44c2bc8
      

    • 6.lc_ctrl_stress_all_with_rand_reset.53319167261267344876799961206837395962961983469993982501052282632820515817261
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:aa160f46-68aa-4309-8b56-bc23e45b698e
      

    • ... and 5 more failures.

• UVM_FATAL (lc_ctrl_scoreboard.sv:265) scoreboard [scoreboard] Access unexpected addr * has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 8.lc_ctrl_stress_all_with_rand_reset.101404561697893539201331402365312137476788771104488708631660072930934402748158
      Line 18342, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 42809377784 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0xa4851600
        UVM_INFO @ 42809377784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 21.lc_ctrl_stress_all_with_rand_reset.31414557309881928629754881988194338450259176095228754663821566194372255205127
      Line 13606, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 93278323349 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x344d5000
        UVM_INFO @ 93278323349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_vseq.sv:519) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 5.lc_ctrl_stress_all_with_rand_reset.108852258114839796157408040672634952861366317575229003111871310281969736581429
      Line 18713, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 76632089695 ps: (cip_base_vseq.sv:519) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 76632089695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:239) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 9.lc_ctrl_stress_all_with_rand_reset.53169400527233265867157350596728594114629599421041212347707623200269147686146
      Line 6337, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4922698281 ps: (lc_ctrl_scoreboard.sv:239) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 97, LC_St DecLcStTestLocked3
        UVM_INFO @ 4922698281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.status.ready reset value: * called from ../src/lowrisc_dv_lc_ctrl_env_*/seq_lib/lc_ctrl_errors_vseq.sv: * has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 29.lc_ctrl_stress_all_with_rand_reset.56100497212604881255463556249456264240379457249265089049852007326496161766628
      Line 2182, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/29.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 628898400 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0 called from ../src/lowrisc_dv_lc_ctrl_env_0.1/seq_lib/lc_ctrl_errors_vseq.sv: 288
        UVM_INFO @ 628898400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (jtag_riscv_monitor.sv:80) monitor [monitor] Bad status - DmiReserved(*) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 31.lc_ctrl_stress_all_with_rand_reset.75889747178917522779581170497984022434449418442043043391021630347975378894712
      Line 4620, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/31.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 65803625698 ps: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
        UVM_INFO @ 65803625698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.status.ready reset value: * has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 34.lc_ctrl_stress_all_with_rand_reset.17597871619691490274551425565156961778981902228018288336766509920537939385568
      Line 15580, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14705984054 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0
        UVM_INFO @ 14705984054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:234) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 38.lc_ctrl_stress_all_with_rand_reset.25997805446397276594872955530579080632159822742694748015722767216023408930524
      Line 20550, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/38.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 47056944548 ps: (lc_ctrl_scoreboard.sv:234) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (5 [0x5] vs 10 [0xa]) Called from line: 97, LC_St DecLcStTestUnlocked2
        UVM_INFO @ 47056944548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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• 2023.11.23_02.09.59
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• 2023.10.30_18.19.21
• 2023.10.26_03.01.18
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