Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41305 |
1 |
|
|
T1 |
73 |
|
T2 |
781 |
|
T3 |
73 |
auto[1] |
1505 |
1 |
|
|
T1 |
12 |
|
T2 |
36 |
|
T5 |
5 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
42002 |
1 |
|
|
T1 |
85 |
|
T2 |
817 |
|
T3 |
73 |
auto[1] |
808 |
1 |
|
|
T45 |
16 |
|
T64 |
16 |
|
T65 |
15 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41645 |
1 |
|
|
T1 |
85 |
|
T2 |
765 |
|
T3 |
73 |
auto[1] |
1165 |
1 |
|
|
T2 |
52 |
|
T9 |
5 |
|
T5 |
15 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41611 |
1 |
|
|
T1 |
85 |
|
T2 |
773 |
|
T3 |
73 |
auto[1] |
1199 |
1 |
|
|
T2 |
44 |
|
T9 |
7 |
|
T5 |
17 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41585 |
1 |
|
|
T1 |
85 |
|
T2 |
755 |
|
T3 |
73 |
auto[1] |
1225 |
1 |
|
|
T2 |
62 |
|
T9 |
5 |
|
T11 |
2 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
39653 |
1 |
|
|
T1 |
85 |
|
T2 |
782 |
|
T3 |
73 |
no_err_inj |
3157 |
1 |
|
|
T2 |
35 |
|
T4 |
9 |
|
T10 |
13 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41403 |
1 |
|
|
T1 |
73 |
|
T2 |
780 |
|
T3 |
73 |
auto[1] |
1407 |
1 |
|
|
T1 |
12 |
|
T2 |
37 |
|
T5 |
6 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
42040 |
1 |
|
|
T1 |
85 |
|
T2 |
817 |
|
T3 |
73 |
auto[1] |
770 |
1 |
|
|
T45 |
8 |
|
T64 |
16 |
|
T65 |
7 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
31069 |
1 |
|
|
T1 |
85 |
|
T2 |
535 |
|
T3 |
73 |
auto[1] |
11741 |
1 |
|
|
T2 |
282 |
|
T4 |
9 |
|
T5 |
182 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41581 |
1 |
|
|
T1 |
85 |
|
T2 |
759 |
|
T3 |
73 |
auto[1] |
1229 |
1 |
|
|
T2 |
58 |
|
T9 |
2 |
|
T5 |
12 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41589 |
1 |
|
|
T1 |
85 |
|
T2 |
756 |
|
T3 |
73 |
auto[1] |
1221 |
1 |
|
|
T2 |
61 |
|
T9 |
8 |
|
T11 |
1 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41622 |
1 |
|
|
T1 |
85 |
|
T2 |
760 |
|
T3 |
73 |
auto[1] |
1188 |
1 |
|
|
T2 |
57 |
|
T9 |
3 |
|
T11 |
1 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41349 |
1 |
|
|
T1 |
77 |
|
T2 |
795 |
|
T3 |
73 |
auto[1] |
1461 |
1 |
|
|
T1 |
8 |
|
T2 |
22 |
|
T5 |
5 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41184 |
1 |
|
|
T1 |
85 |
|
T2 |
785 |
|
T3 |
73 |
auto[1] |
1626 |
1 |
|
|
T2 |
32 |
|
T13 |
61 |
|
T18 |
5 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
42075 |
1 |
|
|
T1 |
85 |
|
T2 |
817 |
|
T3 |
73 |
auto[1] |
735 |
1 |
|
|
T45 |
13 |
|
T64 |
27 |
|
T65 |
9 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
42046 |
1 |
|
|
T1 |
85 |
|
T2 |
817 |
|
T3 |
73 |
auto[1] |
764 |
1 |
|
|
T45 |
16 |
|
T64 |
22 |
|
T65 |
11 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
42070 |
1 |
|
|
T1 |
85 |
|
T2 |
817 |
|
T3 |
73 |
auto[1] |
740 |
1 |
|
|
T45 |
14 |
|
T64 |
19 |
|
T65 |
14 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40981 |
1 |
|
|
T1 |
85 |
|
T2 |
803 |
|
T3 |
73 |
auto[1] |
1829 |
1 |
|
|
T2 |
14 |
|
T11 |
12 |
|
T5 |
25 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39135 |
1 |
|
|
T1 |
85 |
|
T2 |
817 |
|
T3 |
73 |
auto[1] |
3675 |
1 |
|
|
T41 |
50 |
|
T51 |
67 |
|
T54 |
88 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41516 |
1 |
|
|
T1 |
85 |
|
T2 |
751 |
|
T3 |
73 |
auto[1] |
1294 |
1 |
|
|
T2 |
66 |
|
T9 |
9 |
|
T5 |
13 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41586 |
1 |
|
|
T1 |
85 |
|
T2 |
769 |
|
T3 |
73 |
auto[1] |
1224 |
1 |
|
|
T2 |
48 |
|
T9 |
9 |
|
T11 |
1 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41529 |
1 |
|
|
T1 |
85 |
|
T2 |
767 |
|
T3 |
73 |
auto[1] |
1281 |
1 |
|
|
T2 |
50 |
|
T9 |
2 |
|
T5 |
15 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41356 |
1 |
|
|
T1 |
76 |
|
T2 |
788 |
|
T3 |
73 |
auto[1] |
1454 |
1 |
|
|
T1 |
9 |
|
T2 |
29 |
|
T5 |
7 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
37421 |
1 |
|
|
T1 |
77 |
|
T2 |
785 |
|
T9 |
50 |
auto[1] |
5389 |
1 |
|
|
T1 |
8 |
|
T2 |
32 |
|
T3 |
73 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38921 |
1 |
|
|
T1 |
85 |
|
T2 |
817 |
|
T3 |
73 |
auto[1] |
3889 |
1 |
|
|
T14 |
86 |
|
T29 |
72 |
|
T63 |
83 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
42810 |
1 |
|
|
T1 |
85 |
|
T2 |
817 |
|
T3 |
73 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41373 |
1 |
|
|
T1 |
75 |
|
T2 |
776 |
|
T3 |
73 |
auto[1] |
1437 |
1 |
|
|
T1 |
10 |
|
T2 |
41 |
|
T5 |
2 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41347 |
1 |
|
|
T1 |
72 |
|
T2 |
793 |
|
T3 |
73 |
auto[1] |
1463 |
1 |
|
|
T1 |
13 |
|
T2 |
24 |
|
T5 |
3 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41306 |
1 |
|
|
T1 |
72 |
|
T2 |
786 |
|
T3 |
73 |
auto[1] |
1504 |
1 |
|
|
T1 |
13 |
|
T2 |
31 |
|
T5 |
7 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
38748 |
1 |
|
|
T1 |
85 |
|
T2 |
775 |
|
T3 |
73 |
auto[0] |
no_err_inj |
2233 |
1 |
|
|
T2 |
28 |
|
T4 |
9 |
|
T10 |
13 |
auto[1] |
err_inj |
905 |
1 |
|
|
T2 |
7 |
|
T11 |
5 |
|
T5 |
14 |
auto[1] |
no_err_inj |
924 |
1 |
|
|
T2 |
7 |
|
T11 |
7 |
|
T5 |
11 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39870 |
1 |
|
|
T1 |
85 |
|
T2 |
755 |
|
T3 |
73 |
auto[0] |
auto[1] |
1111 |
1 |
|
|
T2 |
48 |
|
T9 |
9 |
|
T5 |
12 |
auto[1] |
auto[0] |
1716 |
1 |
|
|
T2 |
14 |
|
T11 |
11 |
|
T5 |
25 |
auto[1] |
auto[1] |
113 |
1 |
|
|
T11 |
1 |
|
T13 |
2 |
|
T185 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39854 |
1 |
|
|
T1 |
85 |
|
T2 |
743 |
|
T3 |
73 |
auto[0] |
auto[1] |
1127 |
1 |
|
|
T2 |
60 |
|
T9 |
8 |
|
T5 |
10 |
auto[1] |
auto[0] |
1735 |
1 |
|
|
T2 |
13 |
|
T11 |
11 |
|
T5 |
23 |
auto[1] |
auto[1] |
94 |
1 |
|
|
T2 |
1 |
|
T11 |
1 |
|
T5 |
2 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39817 |
1 |
|
|
T1 |
85 |
|
T2 |
754 |
|
T3 |
73 |
auto[0] |
auto[1] |
1164 |
1 |
|
|
T2 |
49 |
|
T9 |
2 |
|
T5 |
13 |
auto[1] |
auto[0] |
1712 |
1 |
|
|
T2 |
13 |
|
T11 |
12 |
|
T5 |
23 |
auto[1] |
auto[1] |
117 |
1 |
|
|
T2 |
1 |
|
T5 |
2 |
|
T13 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39874 |
1 |
|
|
T1 |
85 |
|
T2 |
759 |
|
T3 |
73 |
auto[0] |
auto[1] |
1107 |
1 |
|
|
T2 |
44 |
|
T9 |
7 |
|
T5 |
15 |
auto[1] |
auto[0] |
1737 |
1 |
|
|
T2 |
14 |
|
T11 |
12 |
|
T5 |
23 |
auto[1] |
auto[1] |
92 |
1 |
|
|
T5 |
2 |
|
T17 |
2 |
|
T101 |
2 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39873 |
1 |
|
|
T1 |
85 |
|
T2 |
741 |
|
T3 |
73 |
auto[0] |
auto[1] |
1108 |
1 |
|
|
T2 |
62 |
|
T9 |
5 |
|
T5 |
5 |
auto[1] |
auto[0] |
1712 |
1 |
|
|
T2 |
14 |
|
T11 |
10 |
|
T5 |
23 |
auto[1] |
auto[1] |
117 |
1 |
|
|
T11 |
2 |
|
T5 |
2 |
|
T13 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39902 |
1 |
|
|
T1 |
85 |
|
T2 |
751 |
|
T3 |
73 |
auto[0] |
auto[1] |
1079 |
1 |
|
|
T2 |
52 |
|
T9 |
5 |
|
T5 |
12 |
auto[1] |
auto[0] |
1743 |
1 |
|
|
T2 |
14 |
|
T11 |
12 |
|
T5 |
22 |
auto[1] |
auto[1] |
86 |
1 |
|
|
T5 |
3 |
|
T13 |
1 |
|
T101 |
2 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30162 |
1 |
|
|
T1 |
73 |
|
T2 |
506 |
|
T3 |
73 |
auto[0] |
auto[1] |
907 |
1 |
|
|
T1 |
12 |
|
T2 |
29 |
|
T13 |
20 |
auto[1] |
auto[0] |
11143 |
1 |
|
|
T2 |
275 |
|
T4 |
9 |
|
T5 |
177 |
auto[1] |
auto[1] |
598 |
1 |
|
|
T2 |
7 |
|
T5 |
5 |
|
T13 |
9 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30242 |
1 |
|
|
T1 |
73 |
|
T2 |
507 |
|
T3 |
73 |
auto[0] |
auto[1] |
827 |
1 |
|
|
T1 |
12 |
|
T2 |
28 |
|
T13 |
22 |
auto[1] |
auto[0] |
11161 |
1 |
|
|
T2 |
273 |
|
T4 |
9 |
|
T5 |
176 |
auto[1] |
auto[1] |
580 |
1 |
|
|
T2 |
9 |
|
T5 |
6 |
|
T13 |
4 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30113 |
1 |
|
|
T1 |
85 |
|
T2 |
516 |
|
T3 |
73 |
auto[0] |
auto[1] |
956 |
1 |
|
|
T2 |
19 |
|
T13 |
25 |
|
T101 |
17 |
auto[1] |
auto[0] |
11071 |
1 |
|
|
T2 |
269 |
|
T4 |
9 |
|
T5 |
182 |
auto[1] |
auto[1] |
670 |
1 |
|
|
T2 |
13 |
|
T13 |
36 |
|
T18 |
5 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30228 |
1 |
|
|
T1 |
77 |
|
T2 |
519 |
|
T3 |
73 |
auto[0] |
auto[1] |
841 |
1 |
|
|
T1 |
8 |
|
T2 |
16 |
|
T13 |
21 |
auto[1] |
auto[0] |
11121 |
1 |
|
|
T2 |
276 |
|
T4 |
9 |
|
T5 |
177 |
auto[1] |
auto[1] |
620 |
1 |
|
|
T2 |
6 |
|
T5 |
5 |
|
T13 |
6 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
26265 |
1 |
|
|
T1 |
77 |
|
T2 |
511 |
|
T9 |
50 |
auto[0] |
auto[1] |
4804 |
1 |
|
|
T1 |
8 |
|
T2 |
24 |
|
T3 |
73 |
auto[1] |
auto[0] |
11156 |
1 |
|
|
T2 |
274 |
|
T4 |
9 |
|
T5 |
165 |
auto[1] |
auto[1] |
585 |
1 |
|
|
T2 |
8 |
|
T5 |
17 |
|
T13 |
5 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30395 |
1 |
|
|
T1 |
85 |
|
T2 |
506 |
|
T3 |
73 |
auto[0] |
auto[1] |
674 |
1 |
|
|
T2 |
29 |
|
T9 |
9 |
|
T11 |
1 |
auto[1] |
auto[0] |
11191 |
1 |
|
|
T2 |
263 |
|
T4 |
9 |
|
T5 |
170 |
auto[1] |
auto[1] |
550 |
1 |
|
|
T2 |
19 |
|
T5 |
12 |
|
T13 |
3 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30373 |
1 |
|
|
T1 |
85 |
|
T2 |
501 |
|
T3 |
73 |
auto[0] |
auto[1] |
696 |
1 |
|
|
T2 |
34 |
|
T9 |
9 |
|
T85 |
15 |
auto[1] |
auto[0] |
11143 |
1 |
|
|
T2 |
250 |
|
T4 |
9 |
|
T5 |
169 |
auto[1] |
auto[1] |
598 |
1 |
|
|
T2 |
32 |
|
T5 |
13 |
|
T13 |
4 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30403 |
1 |
|
|
T1 |
85 |
|
T2 |
498 |
|
T3 |
73 |
auto[0] |
auto[1] |
666 |
1 |
|
|
T2 |
37 |
|
T9 |
8 |
|
T11 |
1 |
auto[1] |
auto[0] |
11186 |
1 |
|
|
T2 |
258 |
|
T4 |
9 |
|
T5 |
172 |
auto[1] |
auto[1] |
555 |
1 |
|
|
T2 |
24 |
|
T5 |
10 |
|
T13 |
12 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30392 |
1 |
|
|
T1 |
85 |
|
T2 |
500 |
|
T3 |
73 |
auto[0] |
auto[1] |
677 |
1 |
|
|
T2 |
35 |
|
T9 |
2 |
|
T5 |
2 |
auto[1] |
auto[0] |
11189 |
1 |
|
|
T2 |
259 |
|
T4 |
9 |
|
T5 |
172 |
auto[1] |
auto[1] |
552 |
1 |
|
|
T2 |
23 |
|
T5 |
10 |
|
T13 |
12 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30377 |
1 |
|
|
T1 |
85 |
|
T2 |
512 |
|
T3 |
73 |
auto[0] |
auto[1] |
692 |
1 |
|
|
T2 |
23 |
|
T9 |
7 |
|
T5 |
2 |
auto[1] |
auto[0] |
11234 |
1 |
|
|
T2 |
261 |
|
T4 |
9 |
|
T5 |
167 |
auto[1] |
auto[1] |
507 |
1 |
|
|
T2 |
21 |
|
T5 |
15 |
|
T13 |
11 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30396 |
1 |
|
|
T1 |
85 |
|
T2 |
502 |
|
T3 |
73 |
auto[0] |
auto[1] |
673 |
1 |
|
|
T2 |
33 |
|
T9 |
5 |
|
T5 |
3 |
auto[1] |
auto[0] |
11249 |
1 |
|
|
T2 |
263 |
|
T4 |
9 |
|
T5 |
170 |
auto[1] |
auto[1] |
492 |
1 |
|
|
T2 |
19 |
|
T5 |
12 |
|
T13 |
4 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30183 |
1 |
|
|
T1 |
72 |
|
T2 |
510 |
|
T3 |
73 |
auto[0] |
auto[1] |
886 |
1 |
|
|
T1 |
13 |
|
T2 |
25 |
|
T13 |
21 |
auto[1] |
auto[0] |
11123 |
1 |
|
|
T2 |
276 |
|
T4 |
9 |
|
T5 |
175 |
auto[1] |
auto[1] |
618 |
1 |
|
|
T2 |
6 |
|
T5 |
7 |
|
T13 |
7 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30202 |
1 |
|
|
T1 |
72 |
|
T2 |
515 |
|
T3 |
73 |
auto[0] |
auto[1] |
867 |
1 |
|
|
T1 |
13 |
|
T2 |
20 |
|
T13 |
27 |
auto[1] |
auto[0] |
11145 |
1 |
|
|
T2 |
278 |
|
T4 |
9 |
|
T5 |
179 |
auto[1] |
auto[1] |
596 |
1 |
|
|
T2 |
4 |
|
T5 |
3 |
|
T13 |
5 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30033 |
1 |
|
|
T1 |
85 |
|
T2 |
535 |
|
T3 |
73 |
auto[0] |
auto[1] |
1036 |
1 |
|
|
T11 |
12 |
|
T5 |
25 |
|
T13 |
10 |
auto[1] |
auto[0] |
10948 |
1 |
|
|
T2 |
268 |
|
T4 |
9 |
|
T5 |
182 |
auto[1] |
auto[1] |
793 |
1 |
|
|
T2 |
14 |
|
T13 |
13 |
|
T17 |
13 |