Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

69450322

1

T1

33516

T2

113813

T88

6418

auto[1]

1187407

1

T1

792

T2

25248

T9

2178

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

69465325

1

T1

33912

T2

113843

T88

6418

auto[1]

1172404

1

T1

396

T2

24956

T9

2475

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5490297	1			T1	7980		T2	107034		T88	88
auto[IdleSt]	18121861	1			T1	7542		T2	129020		T88	6330
auto[ClkMuxSt]	30532	1			T1	85		T2	319		T3	73
auto[CntIncrSt]	30247	1			T1	85		T2	314		T3	73
auto[CntProgSt]	1194802	1			T1	1894		T2	545		T3	888
auto[TransCheckSt]	23771	1			T1	60		T2	223		T3	73
auto[TokenHashSt]	21352047	1			T1	1030		T2	484065		T3	1449
auto[FlashRmaSt]	23055	1			T1	33		T2	169		T4	31
auto[TokenCheck0St]	10212	1			T1	20		T2	87		T4	9
auto[TokenCheck1St]	7253	1			T1	10		T2	53		T4	9
auto[TransProgSt]	269206	1			T1	213		T2	100		T4	3076
auto[PostTransSt]	10854760	1			T1	13651		T2	97399		T3	11134
auto[ScrapSt]	230125	1			T2	945		T90	393		T114	157
auto[EscalateSt]	5215058	1			T1	1705		T2	122331		T9	6883
auto[InvalidSt]	7783222	1			T2	220721		T9	8502		T11	579

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1281	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	7783222	1			T2	220721		T9	8502		T11	579
EscalateSt	5215058	1			T1	1705		T2	122331		T9	6883
ScrapSt	230125	1			T2	945		T90	393		T114	157
PostTransSt	10854760	1			T1	13651		T2	97399		T3	11134
TransProgSt	269206	1			T1	213		T2	100		T4	3076
TokenCheck1St	7253	1			T1	10		T2	53		T4	9
TokenCheck0St	10212	1			T1	20		T2	87		T4	9
FlashRmaSt	23055	1			T1	33		T2	169		T4	31
TokenHashSt	21352047	1			T1	1030		T2	484065		T3	1449
TransCheckSt	23771	1			T1	60		T2	223		T3	73
CntProgSt	1194802	1			T1	1894		T2	545		T3	888
CntIncrSt	30247	1			T1	85		T2	314		T3	73
ClkMuxSt	30532	1			T1	85		T2	319		T3	73
IdleSt	18121861	1			T1	7542		T2	129020		T88	6330
ResetSt	5490297	1			T1	7980		T2	107034		T88	88
arcs[ResetSt=>IdleSt]	43336	1			T1	86		T2	781		T88	1
arcs[IdleSt=>ScrapSt]	241	1			T2	3		T90	1		T114	1
arcs[IdleSt=>ClkMuxSt]	30310	1			T1	85		T2	314		T3	73
arcs[ClkMuxSt=>CntIncrSt]	30247	1			T1	85		T2	314		T3	73
arcs[CntIncrSt=>PostTransSt]	1463	1			T1	13		T2	24		T5	3
arcs[CntIncrSt=>CntProgSt]	28723	1			T1	72		T2	290		T3	73
arcs[CntProgSt=>PostTransSt]	3892	1			T1	12		T2	67		T5	5
arcs[CntProgSt=>TransCheckSt]	23771	1			T1	60		T2	223		T3	73
arcs[TransCheckSt=>PostTransSt]	3462	1			T1	13		T2	31		T5	7
arcs[TransCheckSt=>TokenHashSt]	20170	1			T1	47		T2	192		T3	73
arcs[TokenHashSt=>PostTransSt]	9185	1			T1	27		T2	103		T3	73
arcs[TokenHashSt=>FlashRmaSt]	10296	1			T1	20		T2	87		T4	9
arcs[FlashRmaSt=>TokenCheck0St]	10212	1			T1	20		T2	87		T4	9
arcs[TokenCheck0St=>PostTransSt]	2933	1			T1	10		T2	34		T5	6
arcs[TokenCheck0St=>TokenCheck1St]	7253	1			T1	10		T2	53		T4	9
arcs[TokenCheck1St=>PostTransSt]	637	1			T1	2		T2	3		T14	8
arcs[TransProgSt=>PostTransSt]	5772	1			T1	8		T2	50		T4	9
arcs[IdleSt=>EscalateSt]	194	1			T52	5		T53	7		T55	9
arcs[ClkMuxSt=>EscalateSt]	63	1			T51	2		T52	2		T53	2
arcs[CntIncrSt=>EscalateSt]	61	1			T41	1		T51	2		T54	1
arcs[CntProgSt=>EscalateSt]	1060	1			T41	18		T51	8		T54	47
arcs[TransCheckSt=>EscalateSt]	139	1			T51	4		T52	6		T55	6
arcs[TokenHashSt=>EscalateSt]	676	1			T2	1		T13	1		T41	7
arcs[FlashRmaSt=>EscalateSt]	84	1			T41	1		T51	2		T54	2
arcs[TokenCheck0St=>EscalateSt]	26	1			T52	1		T55	1		T59	1
arcs[TokenCheck1St=>EscalateSt]	167	1			T41	3		T51	3		T54	3
arcs[TransProgSt=>EscalateSt]	677	1			T41	16		T51	7		T54	13
arcs[PostTransSt=>EscalateSt]	4132	1			T1	12		T2	67		T5	5
arcs[InvalidSt=>EscalateSt]	10603	1			T2	441		T9	47		T11	4

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5490131	1			T1	7980		T2	107034		T88	88
auto[0]	auto[IdleSt]	18121733	1			T1	7542		T2	129020		T88	6330
auto[0]	auto[ClkMuxSt]	30493	1			T1	85		T2	319		T3	73
auto[0]	auto[CntIncrSt]	30207	1			T1	85		T2	314		T3	73
auto[0]	auto[CntProgSt]	1194054	1			T1	1894		T2	545		T3	888
auto[0]	auto[TransCheckSt]	23674	1			T1	60		T2	223		T3	73
auto[0]	auto[TokenHashSt]	21351603	1			T1	1030		T2	484065		T3	1449
auto[0]	auto[FlashRmaSt]	22998	1			T1	33		T2	169		T4	31
auto[0]	auto[TokenCheck0St]	10196	1			T1	20		T2	87		T4	9
auto[0]	auto[TokenCheck1St]	7136	1			T1	10		T2	53		T4	9
auto[0]	auto[TransProgSt]	268753	1			T1	213		T2	100		T4	3076
auto[0]	auto[PostTransSt]	10852677	1			T1	13643		T2	97368		T3	11134
auto[0]	auto[ScrapSt]	230080	1			T2	945		T90	393		T114	157
auto[0]	auto[EscalateSt]	4037419	1			T1	921		T2	97339		T9	4727
auto[0]	auto[InvalidSt]	7777887	1			T2	220496		T9	8480		T11	577
auto[1]	auto[ResetSt]	166	1			T41	2		T54	7		T52	4
auto[1]	auto[IdleSt]	128	1			T52	3		T53	4		T55	4
auto[1]	auto[ClkMuxSt]	39	1			T51	1		T52	2		T53	2
auto[1]	auto[CntIncrSt]	40	1			T41	1		T51	2		T52	1
auto[1]	auto[CntProgSt]	748	1			T41	14		T51	4		T54	34
auto[1]	auto[TransCheckSt]	97	1			T51	1		T52	5		T55	5
auto[1]	auto[TokenHashSt]	444	1			T13	1		T41	3		T51	18
auto[1]	auto[FlashRmaSt]	57	1			T51	1		T54	2		T52	1
auto[1]	auto[TokenCheck0St]	16	1			T52	1		T59	1		T181	1
auto[1]	auto[TokenCheck1St]	117	1			T41	1		T51	2		T54	2
auto[1]	auto[TransProgSt]	453	1			T41	11		T51	5		T54	8
auto[1]	auto[PostTransSt]	2083	1			T1	8		T2	31		T5	2
auto[1]	auto[ScrapSt]	45	1			T41	1		T51	1		T54	1
auto[1]	auto[EscalateSt]	1177639	1			T1	784		T2	24992		T9	2156
auto[1]	auto[InvalidSt]	5335	1			T2	225		T9	22		T11	2

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5490120	1			T1	7980		T2	107034		T88	88
auto[0]	auto[IdleSt]	18121728	1			T1	7542		T2	129020		T88	6330
auto[0]	auto[ClkMuxSt]	30487	1			T1	85		T2	319		T3	73
auto[0]	auto[CntIncrSt]	30205	1			T1	85		T2	314		T3	73
auto[0]	auto[CntProgSt]	1194125	1			T1	1894		T2	545		T3	888
auto[0]	auto[TransCheckSt]	23679	1			T1	60		T2	223		T3	73
auto[0]	auto[TokenHashSt]	21351600	1			T1	1030		T2	484064		T3	1449
auto[0]	auto[FlashRmaSt]	23001	1			T1	33		T2	169		T4	31
auto[0]	auto[TokenCheck0St]	10192	1			T1	20		T2	87		T4	9
auto[0]	auto[TokenCheck1St]	7145	1			T1	10		T2	53		T4	9
auto[0]	auto[TransProgSt]	268757	1			T1	213		T2	100		T4	3076
auto[0]	auto[PostTransSt]	10852638	1			T1	13647		T2	97363		T3	11134
auto[0]	auto[ScrapSt]	230080	1			T2	945		T90	393		T114	157
auto[0]	auto[EscalateSt]	4052333	1			T1	1313		T2	97628		T9	4433
auto[0]	auto[InvalidSt]	7777954	1			T2	220505		T9	8477		T11	577
auto[1]	auto[ResetSt]	177	1			T41	3		T51	2		T54	4
auto[1]	auto[IdleSt]	133	1			T52	5		T53	6		T55	8
auto[1]	auto[ClkMuxSt]	45	1			T51	2		T53	2		T182	1
auto[1]	auto[CntIncrSt]	42	1			T51	2		T54	1		T52	1
auto[1]	auto[CntProgSt]	677	1			T41	9		T51	7		T54	34
auto[1]	auto[TransCheckSt]	92	1			T51	4		T52	4		T55	3
auto[1]	auto[TokenHashSt]	447	1			T2	1		T41	5		T51	19
auto[1]	auto[FlashRmaSt]	54	1			T41	1		T51	2		T54	2
auto[1]	auto[TokenCheck0St]	20	1			T52	1		T55	1		T183	1
auto[1]	auto[TokenCheck1St]	108	1			T41	3		T51	2		T54	1
auto[1]	auto[TransProgSt]	449	1			T41	14		T51	4		T54	9
auto[1]	auto[PostTransSt]	2122	1			T1	4		T2	36		T5	3
auto[1]	auto[ScrapSt]	45	1			T51	1		T54	3		T184	1
auto[1]	auto[EscalateSt]	1162725	1			T1	392		T2	24703		T9	2450
auto[1]	auto[InvalidSt]	5268	1			T2	216		T9	25		T11	2