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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 97.29 95.79 91.98 97.67 95.93 98.48 95.36


Total test records in report: 987
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T759 /workspace/coverage/default/6.lc_ctrl_jtag_access.172494639 Dec 24 01:06:35 PM PST 23 Dec 24 01:06:49 PM PST 23 2052110546 ps
T760 /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.497657447 Dec 24 01:06:55 PM PST 23 Dec 24 01:07:00 PM PST 23 14157774 ps
T761 /workspace/coverage/default/48.lc_ctrl_state_post_trans.3365306674 Dec 24 01:09:01 PM PST 23 Dec 24 01:09:12 PM PST 23 228412744 ps
T762 /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2649853138 Dec 24 01:08:41 PM PST 23 Dec 24 01:08:49 PM PST 23 15474282 ps
T763 /workspace/coverage/default/7.lc_ctrl_state_post_trans.1639848348 Dec 24 01:06:50 PM PST 23 Dec 24 01:07:02 PM PST 23 88637529 ps
T82 /workspace/coverage/default/3.lc_ctrl_jtag_smoke.2904944442 Dec 24 01:06:44 PM PST 23 Dec 24 01:06:49 PM PST 23 379767260 ps
T764 /workspace/coverage/default/48.lc_ctrl_sec_token_mux.3429637867 Dec 24 01:08:55 PM PST 23 Dec 24 01:09:15 PM PST 23 361196589 ps
T765 /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2026581253 Dec 24 01:05:47 PM PST 23 Dec 24 01:05:57 PM PST 23 16080924 ps
T766 /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3430376511 Dec 24 01:08:09 PM PST 23 Dec 24 01:08:30 PM PST 23 24170370 ps
T767 /workspace/coverage/default/45.lc_ctrl_prog_failure.1061923349 Dec 24 01:08:53 PM PST 23 Dec 24 01:09:03 PM PST 23 149069617 ps
T768 /workspace/coverage/default/26.lc_ctrl_sec_token_digest.3280901026 Dec 24 01:08:03 PM PST 23 Dec 24 01:08:27 PM PST 23 534840910 ps
T769 /workspace/coverage/default/23.lc_ctrl_sec_token_digest.2335631289 Dec 24 01:08:04 PM PST 23 Dec 24 01:08:27 PM PST 23 1585607379 ps
T770 /workspace/coverage/default/30.lc_ctrl_security_escalation.1009526725 Dec 24 01:08:11 PM PST 23 Dec 24 01:08:42 PM PST 23 1227188360 ps
T771 /workspace/coverage/default/47.lc_ctrl_prog_failure.1665023118 Dec 24 01:08:44 PM PST 23 Dec 24 01:08:53 PM PST 23 90447372 ps
T772 /workspace/coverage/default/19.lc_ctrl_sec_token_digest.473047384 Dec 24 01:08:08 PM PST 23 Dec 24 01:08:43 PM PST 23 1222621823 ps
T773 /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.4136695262 Dec 24 01:05:49 PM PST 23 Dec 24 01:06:13 PM PST 23 1893773109 ps
T774 /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2110410000 Dec 24 01:07:04 PM PST 23 Dec 24 01:07:17 PM PST 23 2567767743 ps
T775 /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2156125011 Dec 24 01:06:50 PM PST 23 Dec 24 01:07:38 PM PST 23 3912009183 ps
T776 /workspace/coverage/default/23.lc_ctrl_alert_test.7065566 Dec 24 01:08:08 PM PST 23 Dec 24 01:08:30 PM PST 23 40775919 ps
T777 /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3267669641 Dec 24 01:08:13 PM PST 23 Dec 24 01:09:36 PM PST 23 5719904772 ps
T778 /workspace/coverage/default/3.lc_ctrl_alert_test.1698422254 Dec 24 01:06:22 PM PST 23 Dec 24 01:06:24 PM PST 23 34212220 ps
T779 /workspace/coverage/default/19.lc_ctrl_alert_test.2158327716 Dec 24 01:08:03 PM PST 23 Dec 24 01:08:16 PM PST 23 14669958 ps
T780 /workspace/coverage/default/41.lc_ctrl_prog_failure.1175992850 Dec 24 01:08:55 PM PST 23 Dec 24 01:09:04 PM PST 23 128751281 ps
T781 /workspace/coverage/default/16.lc_ctrl_state_failure.2364293178 Dec 24 01:07:07 PM PST 23 Dec 24 01:07:35 PM PST 23 1283202394 ps
T782 /workspace/coverage/default/12.lc_ctrl_jtag_errors.1564720306 Dec 24 01:06:46 PM PST 23 Dec 24 01:07:34 PM PST 23 6378923347 ps
T783 /workspace/coverage/default/44.lc_ctrl_security_escalation.664828281 Dec 24 01:08:37 PM PST 23 Dec 24 01:08:58 PM PST 23 1016975289 ps
T49 /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.3087520841 Dec 24 01:06:17 PM PST 23 Dec 24 01:14:04 PM PST 23 11341559892 ps
T784 /workspace/coverage/default/20.lc_ctrl_jtag_access.3581663736 Dec 24 01:07:45 PM PST 23 Dec 24 01:08:01 PM PST 23 6529648322 ps
T785 /workspace/coverage/default/31.lc_ctrl_smoke.2898824586 Dec 24 01:08:36 PM PST 23 Dec 24 01:08:48 PM PST 23 55817262 ps
T786 /workspace/coverage/default/3.lc_ctrl_sec_mubi.1251658317 Dec 24 01:06:19 PM PST 23 Dec 24 01:06:34 PM PST 23 1672901393 ps
T787 /workspace/coverage/default/42.lc_ctrl_jtag_access.3564319281 Dec 24 01:08:47 PM PST 23 Dec 24 01:09:02 PM PST 23 1622585958 ps
T788 /workspace/coverage/default/25.lc_ctrl_sec_token_digest.2555491436 Dec 24 01:08:06 PM PST 23 Dec 24 01:08:36 PM PST 23 322770248 ps
T789 /workspace/coverage/default/24.lc_ctrl_state_failure.837750235 Dec 24 01:08:10 PM PST 23 Dec 24 01:09:08 PM PST 23 1344265995 ps
T790 /workspace/coverage/default/24.lc_ctrl_prog_failure.3818366377 Dec 24 01:08:07 PM PST 23 Dec 24 01:08:29 PM PST 23 74662699 ps
T791 /workspace/coverage/default/2.lc_ctrl_jtag_errors.4204292764 Dec 24 01:06:28 PM PST 23 Dec 24 01:07:07 PM PST 23 2721503265 ps
T792 /workspace/coverage/default/4.lc_ctrl_sec_token_mux.3341566643 Dec 24 01:06:46 PM PST 23 Dec 24 01:06:57 PM PST 23 869370947 ps
T793 /workspace/coverage/default/44.lc_ctrl_prog_failure.524659699 Dec 24 01:08:50 PM PST 23 Dec 24 01:08:59 PM PST 23 185852815 ps
T794 /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.917885936 Dec 24 01:06:45 PM PST 23 Dec 24 01:06:52 PM PST 23 274308116 ps
T795 /workspace/coverage/default/34.lc_ctrl_jtag_access.141744819 Dec 24 01:08:30 PM PST 23 Dec 24 01:08:52 PM PST 23 1195219986 ps
T796 /workspace/coverage/default/30.lc_ctrl_sec_token_digest.2437343564 Dec 24 01:08:11 PM PST 23 Dec 24 01:08:38 PM PST 23 5027316963 ps
T797 /workspace/coverage/default/16.lc_ctrl_prog_failure.2150999892 Dec 24 01:06:56 PM PST 23 Dec 24 01:07:02 PM PST 23 27870243 ps
T798 /workspace/coverage/default/2.lc_ctrl_jtag_smoke.18008622 Dec 24 01:06:11 PM PST 23 Dec 24 01:06:18 PM PST 23 358310670 ps
T799 /workspace/coverage/default/16.lc_ctrl_security_escalation.1160583148 Dec 24 01:07:09 PM PST 23 Dec 24 01:07:26 PM PST 23 278626059 ps
T800 /workspace/coverage/default/44.lc_ctrl_sec_token_digest.743923563 Dec 24 01:08:51 PM PST 23 Dec 24 01:09:08 PM PST 23 246357210 ps
T801 /workspace/coverage/default/4.lc_ctrl_jtag_priority.2361614554 Dec 24 01:06:52 PM PST 23 Dec 24 01:08:23 PM PST 23 3631596430 ps
T802 /workspace/coverage/default/9.lc_ctrl_smoke.3387019312 Dec 24 01:06:41 PM PST 23 Dec 24 01:06:43 PM PST 23 38682548 ps
T803 /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.16718714 Dec 24 01:08:53 PM PST 23 Dec 24 01:09:00 PM PST 23 10816765 ps
T804 /workspace/coverage/default/26.lc_ctrl_state_failure.3021732590 Dec 24 01:07:59 PM PST 23 Dec 24 01:08:28 PM PST 23 496960780 ps
T805 /workspace/coverage/default/8.lc_ctrl_errors.3313928664 Dec 24 01:07:09 PM PST 23 Dec 24 01:07:25 PM PST 23 433573270 ps
T806 /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3040322309 Dec 24 01:08:40 PM PST 23 Dec 24 01:08:49 PM PST 23 40146331 ps
T807 /workspace/coverage/default/44.lc_ctrl_sec_mubi.2044244041 Dec 24 01:08:49 PM PST 23 Dec 24 01:09:06 PM PST 23 846571555 ps
T808 /workspace/coverage/default/33.lc_ctrl_jtag_access.4167801062 Dec 24 01:08:35 PM PST 23 Dec 24 01:08:50 PM PST 23 558062110 ps
T809 /workspace/coverage/default/0.lc_ctrl_sec_mubi.2236501067 Dec 24 01:05:52 PM PST 23 Dec 24 01:06:15 PM PST 23 2822706555 ps
T57 /workspace/coverage/default/4.lc_ctrl_sec_cm.1065375987 Dec 24 01:06:30 PM PST 23 Dec 24 01:07:07 PM PST 23 209886699 ps
T810 /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.226967734 Dec 24 01:06:35 PM PST 23 Dec 24 01:07:31 PM PST 23 2684172145 ps
T811 /workspace/coverage/default/27.lc_ctrl_security_escalation.1280228154 Dec 24 01:08:01 PM PST 23 Dec 24 01:08:23 PM PST 23 2600778801 ps
T812 /workspace/coverage/default/29.lc_ctrl_sec_mubi.303404489 Dec 24 01:08:08 PM PST 23 Dec 24 01:08:43 PM PST 23 1663746365 ps
T813 /workspace/coverage/default/49.lc_ctrl_security_escalation.3219364376 Dec 24 01:08:56 PM PST 23 Dec 24 01:09:10 PM PST 23 295279143 ps
T814 /workspace/coverage/default/26.lc_ctrl_sec_mubi.1696023879 Dec 24 01:08:06 PM PST 23 Dec 24 01:08:35 PM PST 23 419244493 ps
T815 /workspace/coverage/default/2.lc_ctrl_state_post_trans.2183563324 Dec 24 01:05:47 PM PST 23 Dec 24 01:05:59 PM PST 23 195821026 ps
T816 /workspace/coverage/default/19.lc_ctrl_errors.1944962155 Dec 24 01:08:08 PM PST 23 Dec 24 01:08:40 PM PST 23 1113709305 ps
T817 /workspace/coverage/default/17.lc_ctrl_sec_token_digest.4120906325 Dec 24 01:07:47 PM PST 23 Dec 24 01:08:04 PM PST 23 192997961 ps
T818 /workspace/coverage/default/32.lc_ctrl_errors.791048705 Dec 24 01:08:29 PM PST 23 Dec 24 01:09:00 PM PST 23 376452928 ps
T819 /workspace/coverage/default/45.lc_ctrl_security_escalation.1711388137 Dec 24 01:08:53 PM PST 23 Dec 24 01:09:11 PM PST 23 2161009724 ps
T820 /workspace/coverage/default/6.lc_ctrl_state_failure.1733174606 Dec 24 01:06:32 PM PST 23 Dec 24 01:06:51 PM PST 23 728534873 ps
T821 /workspace/coverage/default/9.lc_ctrl_state_post_trans.935993333 Dec 24 01:06:34 PM PST 23 Dec 24 01:06:39 PM PST 23 227925572 ps
T822 /workspace/coverage/default/40.lc_ctrl_sec_mubi.772560621 Dec 24 01:08:57 PM PST 23 Dec 24 01:09:14 PM PST 23 226346652 ps
T823 /workspace/coverage/default/3.lc_ctrl_errors.340685017 Dec 24 01:06:47 PM PST 23 Dec 24 01:07:01 PM PST 23 524207924 ps
T824 /workspace/coverage/default/1.lc_ctrl_state_failure.1570697246 Dec 24 01:05:46 PM PST 23 Dec 24 01:06:19 PM PST 23 156164228 ps
T825 /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3898255805 Dec 24 01:06:51 PM PST 23 Dec 24 01:06:57 PM PST 23 13607973 ps
T826 /workspace/coverage/default/9.lc_ctrl_security_escalation.711267766 Dec 24 01:06:41 PM PST 23 Dec 24 01:06:54 PM PST 23 571686849 ps
T827 /workspace/coverage/default/27.lc_ctrl_jtag_access.739984130 Dec 24 01:08:00 PM PST 23 Dec 24 01:08:15 PM PST 23 906358714 ps
T828 /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.786631102 Dec 24 01:08:25 PM PST 23 Dec 24 01:08:44 PM PST 23 46095527 ps
T829 /workspace/coverage/default/22.lc_ctrl_sec_mubi.1048611249 Dec 24 01:08:04 PM PST 23 Dec 24 01:08:34 PM PST 23 2324547419 ps
T830 /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.659145859 Dec 24 01:06:55 PM PST 23 Dec 24 01:07:14 PM PST 23 4544663917 ps
T831 /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.858814478 Dec 24 01:07:05 PM PST 23 Dec 24 01:07:17 PM PST 23 983750890 ps
T832 /workspace/coverage/default/13.lc_ctrl_jtag_errors.1414888889 Dec 24 01:07:17 PM PST 23 Dec 24 01:08:00 PM PST 23 5779294910 ps
T833 /workspace/coverage/default/8.lc_ctrl_state_post_trans.2921406997 Dec 24 01:07:09 PM PST 23 Dec 24 01:07:25 PM PST 23 60165538 ps
T834 /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3828613606 Dec 24 01:07:24 PM PST 23 Dec 24 01:07:29 PM PST 23 45813186 ps
T835 /workspace/coverage/default/36.lc_ctrl_smoke.3309747878 Dec 24 01:08:32 PM PST 23 Dec 24 01:08:48 PM PST 23 827460141 ps
T836 /workspace/coverage/default/23.lc_ctrl_stress_all.3359837680 Dec 24 01:08:09 PM PST 23 Dec 24 01:09:51 PM PST 23 31093191320 ps
T837 /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.955787800 Dec 24 01:08:34 PM PST 23 Dec 24 01:08:46 PM PST 23 24485205 ps
T838 /workspace/coverage/default/15.lc_ctrl_smoke.167959006 Dec 24 01:07:15 PM PST 23 Dec 24 01:07:23 PM PST 23 88431404 ps
T839 /workspace/coverage/default/46.lc_ctrl_prog_failure.4197661928 Dec 24 01:08:49 PM PST 23 Dec 24 01:08:57 PM PST 23 29227196 ps
T840 /workspace/coverage/default/35.lc_ctrl_state_failure.1460899295 Dec 24 01:08:34 PM PST 23 Dec 24 01:09:11 PM PST 23 282162982 ps
T841 /workspace/coverage/default/23.lc_ctrl_sec_mubi.3975139090 Dec 24 01:08:09 PM PST 23 Dec 24 01:08:38 PM PST 23 223482131 ps
T842 /workspace/coverage/default/26.lc_ctrl_prog_failure.1015625746 Dec 24 01:08:06 PM PST 23 Dec 24 01:08:26 PM PST 23 161583876 ps
T843 /workspace/coverage/default/40.lc_ctrl_stress_all.2740548844 Dec 24 01:08:48 PM PST 23 Dec 24 01:14:31 PM PST 23 91289321404 ps
T844 /workspace/coverage/default/11.lc_ctrl_errors.74223584 Dec 24 01:06:50 PM PST 23 Dec 24 01:07:06 PM PST 23 225958981 ps
T845 /workspace/coverage/default/36.lc_ctrl_prog_failure.96141649 Dec 24 01:08:33 PM PST 23 Dec 24 01:08:48 PM PST 23 100836985 ps
T846 /workspace/coverage/default/11.lc_ctrl_state_post_trans.3073965160 Dec 24 01:06:56 PM PST 23 Dec 24 01:07:10 PM PST 23 91269764 ps
T847 /workspace/coverage/default/23.lc_ctrl_jtag_access.2269748325 Dec 24 01:08:06 PM PST 23 Dec 24 01:08:28 PM PST 23 496505350 ps
T848 /workspace/coverage/default/25.lc_ctrl_jtag_access.953116817 Dec 24 01:08:08 PM PST 23 Dec 24 01:08:32 PM PST 23 844452493 ps
T849 /workspace/coverage/default/10.lc_ctrl_sec_mubi.3848860629 Dec 24 01:07:06 PM PST 23 Dec 24 01:07:25 PM PST 23 6693489070 ps
T850 /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.493338961 Dec 24 01:08:16 PM PST 23 Dec 24 01:08:39 PM PST 23 29532218 ps
T851 /workspace/coverage/default/7.lc_ctrl_sec_mubi.1545411555 Dec 24 01:07:08 PM PST 23 Dec 24 01:07:27 PM PST 23 238742398 ps
T852 /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.3844719560 Dec 24 01:06:47 PM PST 23 Dec 24 01:06:52 PM PST 23 28576395 ps
T853 /workspace/coverage/default/45.lc_ctrl_sec_mubi.1980765483 Dec 24 01:08:51 PM PST 23 Dec 24 01:09:11 PM PST 23 835834666 ps
T854 /workspace/coverage/default/24.lc_ctrl_state_post_trans.2981970643 Dec 24 01:08:10 PM PST 23 Dec 24 01:08:37 PM PST 23 318727479 ps
T855 /workspace/coverage/default/7.lc_ctrl_stress_all.3279310780 Dec 24 01:07:09 PM PST 23 Dec 24 01:09:35 PM PST 23 15467886536 ps
T856 /workspace/coverage/default/35.lc_ctrl_sec_mubi.475169446 Dec 24 01:08:42 PM PST 23 Dec 24 01:09:03 PM PST 23 3504047448 ps
T857 /workspace/coverage/default/9.lc_ctrl_stress_all.3806072779 Dec 24 01:07:17 PM PST 23 Dec 24 01:08:20 PM PST 23 2590826914 ps
T858 /workspace/coverage/default/22.lc_ctrl_sec_token_digest.343337767 Dec 24 01:08:07 PM PST 23 Dec 24 01:08:38 PM PST 23 546166811 ps
T110 /workspace/coverage/default/26.lc_ctrl_stress_all.891814323 Dec 24 01:08:04 PM PST 23 Dec 24 01:10:10 PM PST 23 10523555393 ps
T859 /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.2392891043 Dec 24 01:08:06 PM PST 23 Dec 24 01:08:44 PM PST 23 1477068542 ps
T860 /workspace/coverage/default/7.lc_ctrl_jtag_priority.3913381391 Dec 24 01:06:57 PM PST 23 Dec 24 01:07:03 PM PST 23 396374049 ps
T861 /workspace/coverage/default/0.lc_ctrl_jtag_priority.2697632297 Dec 24 01:05:51 PM PST 23 Dec 24 01:06:05 PM PST 23 498396617 ps
T862 /workspace/coverage/default/27.lc_ctrl_stress_all.701899202 Dec 24 01:08:07 PM PST 23 Dec 24 01:11:42 PM PST 23 6386088625 ps
T74 /workspace/coverage/default/17.lc_ctrl_stress_all.1063320783 Dec 24 01:08:05 PM PST 23 Dec 24 01:09:22 PM PST 23 2240718044 ps
T863 /workspace/coverage/default/10.lc_ctrl_sec_token_digest.2961712189 Dec 24 01:07:23 PM PST 23 Dec 24 01:07:38 PM PST 23 1024960390 ps
T864 /workspace/coverage/default/8.lc_ctrl_regwen_during_op.3509570232 Dec 24 01:07:23 PM PST 23 Dec 24 01:07:40 PM PST 23 245975739 ps
T865 /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1012424280 Dec 24 01:07:29 PM PST 23 Dec 24 01:07:40 PM PST 23 340288443 ps
T866 /workspace/coverage/default/23.lc_ctrl_security_escalation.2146344707 Dec 24 01:08:09 PM PST 23 Dec 24 01:08:39 PM PST 23 251480041 ps
T867 /workspace/coverage/default/8.lc_ctrl_security_escalation.3738185551 Dec 24 01:07:28 PM PST 23 Dec 24 01:07:39 PM PST 23 323453820 ps
T868 /workspace/coverage/default/4.lc_ctrl_jtag_errors.2913045280 Dec 24 01:06:51 PM PST 23 Dec 24 01:07:43 PM PST 23 1927446339 ps
T869 /workspace/coverage/default/34.lc_ctrl_sec_token_digest.815488874 Dec 24 01:08:36 PM PST 23 Dec 24 01:09:00 PM PST 23 703853585 ps
T870 /workspace/coverage/default/10.lc_ctrl_state_post_trans.1180485749 Dec 24 01:07:26 PM PST 23 Dec 24 01:07:37 PM PST 23 435272590 ps
T871 /workspace/coverage/default/9.lc_ctrl_sec_token_mux.3579877582 Dec 24 01:07:05 PM PST 23 Dec 24 01:07:23 PM PST 23 378959323 ps
T872 /workspace/coverage/default/40.lc_ctrl_jtag_access.1330594274 Dec 24 01:08:52 PM PST 23 Dec 24 01:09:02 PM PST 23 285108240 ps
T873 /workspace/coverage/default/45.lc_ctrl_errors.784902216 Dec 24 01:08:50 PM PST 23 Dec 24 01:09:06 PM PST 23 243121150 ps
T874 /workspace/coverage/default/34.lc_ctrl_stress_all.494544399 Dec 24 01:08:30 PM PST 23 Dec 24 01:10:41 PM PST 23 5448376984 ps
T875 /workspace/coverage/default/24.lc_ctrl_smoke.126953378 Dec 24 01:08:11 PM PST 23 Dec 24 01:08:33 PM PST 23 132911346 ps
T876 /workspace/coverage/default/4.lc_ctrl_regwen_during_op.551911479 Dec 24 01:06:22 PM PST 23 Dec 24 01:06:47 PM PST 23 360837352 ps
T877 /workspace/coverage/default/37.lc_ctrl_alert_test.3654934530 Dec 24 01:08:42 PM PST 23 Dec 24 01:08:50 PM PST 23 60027713 ps
T878 /workspace/coverage/default/41.lc_ctrl_errors.4064317810 Dec 24 01:08:41 PM PST 23 Dec 24 01:08:59 PM PST 23 764242792 ps
T879 /workspace/coverage/default/49.lc_ctrl_jtag_access.1696051390 Dec 24 01:09:11 PM PST 23 Dec 24 01:09:16 PM PST 23 199111917 ps
T880 /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.163412197 Dec 24 01:08:55 PM PST 23 Dec 24 01:09:03 PM PST 23 15798160 ps
T881 /workspace/coverage/default/45.lc_ctrl_stress_all.1110160561 Dec 24 01:08:46 PM PST 23 Dec 24 01:11:50 PM PST 23 51428152325 ps
T882 /workspace/coverage/default/46.lc_ctrl_sec_token_digest.4126086587 Dec 24 01:08:52 PM PST 23 Dec 24 01:09:11 PM PST 23 288596227 ps
T883 /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1992392 Dec 24 01:07:06 PM PST 23 Dec 24 01:07:12 PM PST 23 23771611 ps
T884 /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.882269542 Dec 24 01:07:05 PM PST 23 Dec 24 01:07:23 PM PST 23 1005766312 ps
T885 /workspace/coverage/default/9.lc_ctrl_jtag_errors.494621613 Dec 24 01:06:48 PM PST 23 Dec 24 01:07:44 PM PST 23 7121308188 ps
T886 /workspace/coverage/default/17.lc_ctrl_jtag_errors.412913369 Dec 24 01:07:59 PM PST 23 Dec 24 01:10:00 PM PST 23 19031138658 ps
T887 /workspace/coverage/default/41.lc_ctrl_alert_test.1324477710 Dec 24 01:08:53 PM PST 23 Dec 24 01:09:00 PM PST 23 59757966 ps
T888 /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.121126050 Dec 24 01:06:41 PM PST 23 Dec 24 01:06:56 PM PST 23 479816296 ps
T889 /workspace/coverage/default/13.lc_ctrl_prog_failure.1444043218 Dec 24 01:07:19 PM PST 23 Dec 24 01:07:25 PM PST 23 31031040 ps
T890 /workspace/coverage/default/1.lc_ctrl_alert_test.3723810969 Dec 24 01:05:44 PM PST 23 Dec 24 01:05:54 PM PST 23 21825733 ps
T891 /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1141364748 Dec 24 01:07:05 PM PST 23 Dec 24 01:09:03 PM PST 23 7856663287 ps
T892 /workspace/coverage/default/18.lc_ctrl_errors.2842057590 Dec 24 01:08:05 PM PST 23 Dec 24 01:08:35 PM PST 23 1439958350 ps
T893 /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.557621319 Dec 24 01:08:10 PM PST 23 Dec 24 01:08:30 PM PST 23 23640638 ps
T894 /workspace/coverage/default/4.lc_ctrl_smoke.3658633185 Dec 24 01:06:49 PM PST 23 Dec 24 01:06:55 PM PST 23 36191714 ps
T895 /workspace/coverage/default/47.lc_ctrl_jtag_access.1357396894 Dec 24 01:08:52 PM PST 23 Dec 24 01:09:02 PM PST 23 786443818 ps
T896 /workspace/coverage/default/19.lc_ctrl_sec_mubi.2881806362 Dec 24 01:08:05 PM PST 23 Dec 24 01:08:36 PM PST 23 273478688 ps
T897 /workspace/coverage/default/38.lc_ctrl_sec_mubi.1775561582 Dec 24 01:08:53 PM PST 23 Dec 24 01:09:14 PM PST 23 436314740 ps
T898 /workspace/coverage/default/14.lc_ctrl_alert_test.1859942487 Dec 24 01:07:14 PM PST 23 Dec 24 01:07:21 PM PST 23 69673022 ps
T899 /workspace/coverage/default/21.lc_ctrl_jtag_access.2637077801 Dec 24 01:08:03 PM PST 23 Dec 24 01:08:19 PM PST 23 301692149 ps
T900 /workspace/coverage/default/43.lc_ctrl_sec_token_digest.4086460172 Dec 24 01:08:46 PM PST 23 Dec 24 01:09:01 PM PST 23 565642871 ps
T901 /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1531685951 Dec 24 01:07:06 PM PST 23 Dec 24 01:07:18 PM PST 23 958267738 ps
T902 /workspace/coverage/default/16.lc_ctrl_smoke.3274155851 Dec 24 01:07:07 PM PST 23 Dec 24 01:07:20 PM PST 23 779046555 ps
T903 /workspace/coverage/default/32.lc_ctrl_stress_all.762706522 Dec 24 01:08:13 PM PST 23 Dec 24 01:10:13 PM PST 23 5039128134 ps
T904 /workspace/coverage/default/17.lc_ctrl_state_post_trans.3642517546 Dec 24 01:07:00 PM PST 23 Dec 24 01:07:12 PM PST 23 262476819 ps
T905 /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3917750754 Dec 24 01:07:08 PM PST 23 Dec 24 01:09:12 PM PST 23 3506080249 ps
T906 /workspace/coverage/default/14.lc_ctrl_state_failure.1614382949 Dec 24 01:07:20 PM PST 23 Dec 24 01:08:00 PM PST 23 854440944 ps
T907 /workspace/coverage/default/10.lc_ctrl_state_failure.4130523144 Dec 24 01:07:15 PM PST 23 Dec 24 01:07:56 PM PST 23 1758119471 ps
T908 /workspace/coverage/default/19.lc_ctrl_security_escalation.3665660801 Dec 24 01:08:08 PM PST 23 Dec 24 01:08:36 PM PST 23 1061611379 ps
T909 /workspace/coverage/default/0.lc_ctrl_jtag_errors.357906932 Dec 24 01:05:49 PM PST 23 Dec 24 01:06:29 PM PST 23 1705881992 ps
T910 /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1088171647 Dec 24 01:08:07 PM PST 23 Dec 24 01:08:27 PM PST 23 25937657 ps
T911 /workspace/coverage/default/41.lc_ctrl_sec_token_mux.2694701246 Dec 24 01:08:53 PM PST 23 Dec 24 01:09:10 PM PST 23 495913998 ps
T912 /workspace/coverage/default/37.lc_ctrl_prog_failure.1332117160 Dec 24 01:08:31 PM PST 23 Dec 24 01:08:50 PM PST 23 208843165 ps
T913 /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.1227184835 Dec 24 01:07:15 PM PST 23 Dec 24 01:07:36 PM PST 23 381784142 ps
T914 /workspace/coverage/default/44.lc_ctrl_errors.845932288 Dec 24 01:08:50 PM PST 23 Dec 24 01:09:09 PM PST 23 233180806 ps
T915 /workspace/coverage/default/31.lc_ctrl_jtag_access.2609385570 Dec 24 01:08:26 PM PST 23 Dec 24 01:08:49 PM PST 23 341618648 ps
T916 /workspace/coverage/default/42.lc_ctrl_stress_all.1447833785 Dec 24 01:08:54 PM PST 23 Dec 24 01:12:01 PM PST 23 5467479463 ps
T917 /workspace/coverage/default/26.lc_ctrl_errors.1501002838 Dec 24 01:08:05 PM PST 23 Dec 24 01:08:35 PM PST 23 1324606697 ps
T75 /workspace/coverage/default/40.lc_ctrl_alert_test.1395065625 Dec 24 01:08:41 PM PST 23 Dec 24 01:08:49 PM PST 23 18091092 ps
T918 /workspace/coverage/default/49.lc_ctrl_smoke.1305090817 Dec 24 01:09:12 PM PST 23 Dec 24 01:09:15 PM PST 23 23814061 ps
T919 /workspace/coverage/default/22.lc_ctrl_smoke.758075549 Dec 24 01:08:06 PM PST 23 Dec 24 01:08:25 PM PST 23 186279105 ps
T920 /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2326515895 Dec 24 01:08:34 PM PST 23 Dec 24 01:08:55 PM PST 23 333967953 ps
T921 /workspace/coverage/default/13.lc_ctrl_sec_mubi.2552520348 Dec 24 01:07:10 PM PST 23 Dec 24 01:07:30 PM PST 23 1339668705 ps
T922 /workspace/coverage/default/5.lc_ctrl_prog_failure.1150971493 Dec 24 01:06:26 PM PST 23 Dec 24 01:06:29 PM PST 23 732619879 ps
T923 /workspace/coverage/default/2.lc_ctrl_sec_token_mux.547764396 Dec 24 01:06:31 PM PST 23 Dec 24 01:06:48 PM PST 23 508386989 ps
T924 /workspace/coverage/default/18.lc_ctrl_security_escalation.2636131066 Dec 24 01:08:01 PM PST 23 Dec 24 01:08:23 PM PST 23 308316309 ps
T925 /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.2797063545 Dec 24 01:06:51 PM PST 23 Dec 24 01:07:06 PM PST 23 302303384 ps
T926 /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1717677890 Dec 24 01:07:04 PM PST 23 Dec 24 01:07:07 PM PST 23 28820507 ps
T927 /workspace/coverage/default/44.lc_ctrl_state_post_trans.413267032 Dec 24 01:08:44 PM PST 23 Dec 24 01:09:00 PM PST 23 297628875 ps
T928 /workspace/coverage/default/18.lc_ctrl_state_failure.642065449 Dec 24 01:07:56 PM PST 23 Dec 24 01:08:27 PM PST 23 1858294892 ps
T929 /workspace/coverage/default/22.lc_ctrl_jtag_access.1501804771 Dec 24 01:08:10 PM PST 23 Dec 24 01:08:35 PM PST 23 1004184260 ps
T930 /workspace/coverage/default/28.lc_ctrl_sec_token_digest.3652904484 Dec 24 01:08:19 PM PST 23 Dec 24 01:08:50 PM PST 23 346237716 ps
T931 /workspace/coverage/default/31.lc_ctrl_errors.3171387492 Dec 24 01:08:28 PM PST 23 Dec 24 01:08:56 PM PST 23 1152045224 ps
T932 /workspace/coverage/default/36.lc_ctrl_stress_all.1182476149 Dec 24 01:08:23 PM PST 23 Dec 24 01:12:34 PM PST 23 25414819792 ps
T933 /workspace/coverage/default/25.lc_ctrl_security_escalation.2206994486 Dec 24 01:08:05 PM PST 23 Dec 24 01:08:29 PM PST 23 969284406 ps
T934 /workspace/coverage/default/17.lc_ctrl_security_escalation.4195052809 Dec 24 01:07:03 PM PST 23 Dec 24 01:07:14 PM PST 23 1091012174 ps
T935 /workspace/coverage/default/13.lc_ctrl_state_post_trans.1366685485 Dec 24 01:07:06 PM PST 23 Dec 24 01:07:19 PM PST 23 65676504 ps
T936 /workspace/coverage/default/27.lc_ctrl_prog_failure.3688581079 Dec 24 01:08:03 PM PST 23 Dec 24 01:08:19 PM PST 23 69528588 ps
T937 /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.837073282 Dec 24 01:07:22 PM PST 23 Dec 24 01:07:40 PM PST 23 514855102 ps
T938 /workspace/coverage/default/31.lc_ctrl_state_failure.3560141722 Dec 24 01:08:29 PM PST 23 Dec 24 01:09:07 PM PST 23 276525210 ps
T939 /workspace/coverage/default/32.lc_ctrl_sec_mubi.54818026 Dec 24 01:08:13 PM PST 23 Dec 24 01:08:41 PM PST 23 232850637 ps
T940 /workspace/coverage/default/6.lc_ctrl_prog_failure.115732513 Dec 24 01:06:49 PM PST 23 Dec 24 01:06:57 PM PST 23 82868979 ps
T941 /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.2952439080 Dec 24 01:06:33 PM PST 23 Dec 24 01:07:11 PM PST 23 17579791091 ps
T942 /workspace/coverage/default/29.lc_ctrl_sec_token_digest.1858151500 Dec 24 01:08:10 PM PST 23 Dec 24 01:08:38 PM PST 23 202697887 ps
T943 /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2412672438 Dec 24 01:07:04 PM PST 23 Dec 24 01:07:15 PM PST 23 1566280093 ps
T944 /workspace/coverage/default/38.lc_ctrl_state_failure.1279236838 Dec 24 01:08:44 PM PST 23 Dec 24 01:09:19 PM PST 23 426591001 ps
T945 /workspace/coverage/default/37.lc_ctrl_smoke.920570417 Dec 24 01:08:46 PM PST 23 Dec 24 01:08:57 PM PST 23 455129936 ps
T946 /workspace/coverage/default/7.lc_ctrl_jtag_access.1838234426 Dec 24 01:07:06 PM PST 23 Dec 24 01:07:37 PM PST 23 1244506533 ps
T947 /workspace/coverage/default/28.lc_ctrl_alert_test.4236514351 Dec 24 01:08:07 PM PST 23 Dec 24 01:08:25 PM PST 23 16742345 ps
T948 /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2331103318 Dec 24 01:08:40 PM PST 23 Dec 24 01:08:48 PM PST 23 22994980 ps
T949 /workspace/coverage/default/36.lc_ctrl_sec_token_digest.1724036653 Dec 24 01:08:30 PM PST 23 Dec 24 01:08:55 PM PST 23 281208310 ps
T950 /workspace/coverage/default/5.lc_ctrl_jtag_errors.2075149686 Dec 24 01:06:28 PM PST 23 Dec 24 01:07:12 PM PST 23 3088158041 ps
T951 /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2202373569 Dec 24 01:07:14 PM PST 23 Dec 24 01:07:31 PM PST 23 659881371 ps
T952 /workspace/coverage/default/26.lc_ctrl_jtag_access.1715039064 Dec 24 01:08:02 PM PST 23 Dec 24 01:08:22 PM PST 23 3559891480 ps
T953 /workspace/coverage/default/38.lc_ctrl_stress_all.2373477967 Dec 24 01:08:28 PM PST 23 Dec 24 01:11:21 PM PST 23 19018502824 ps
T954 /workspace/coverage/default/0.lc_ctrl_sec_token_digest.1689299776 Dec 24 01:05:49 PM PST 23 Dec 24 01:06:13 PM PST 23 795475576 ps
T955 /workspace/coverage/default/24.lc_ctrl_stress_all.2756337430 Dec 24 01:08:05 PM PST 23 Dec 24 01:11:18 PM PST 23 11115885972 ps
T956 /workspace/coverage/default/44.lc_ctrl_state_failure.2065035104 Dec 24 01:08:35 PM PST 23 Dec 24 01:09:00 PM PST 23 190885410 ps
T957 /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.2983283514 Dec 24 01:07:09 PM PST 23 Dec 24 01:07:17 PM PST 23 12540093 ps
T958 /workspace/coverage/default/19.lc_ctrl_state_failure.2424504866 Dec 24 01:08:20 PM PST 23 Dec 24 01:09:04 PM PST 23 714855549 ps
T959 /workspace/coverage/default/2.lc_ctrl_security_escalation.1560342600 Dec 24 01:06:10 PM PST 23 Dec 24 01:06:23 PM PST 23 448661641 ps
T960 /workspace/coverage/default/1.lc_ctrl_regwen_during_op.377314872 Dec 24 01:05:55 PM PST 23 Dec 24 01:06:19 PM PST 23 1198835613 ps
T50 /workspace/coverage/default/2.lc_ctrl_stress_all.3239130013 Dec 24 01:06:25 PM PST 23 Dec 24 01:09:20 PM PST 23 44584007349 ps
T961 /workspace/coverage/default/6.lc_ctrl_stress_all.288048981 Dec 24 01:06:56 PM PST 23 Dec 24 01:08:03 PM PST 23 1593325028 ps
T962 /workspace/coverage/default/4.lc_ctrl_prog_failure.2759820727 Dec 24 01:06:47 PM PST 23 Dec 24 01:06:52 PM PST 23 58280483 ps
T963 /workspace/coverage/default/46.lc_ctrl_jtag_access.768415495 Dec 24 01:08:54 PM PST 23 Dec 24 01:09:11 PM PST 23 4591488241 ps
T964 /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.1151999110 Dec 24 01:06:47 PM PST 23 Dec 24 01:06:57 PM PST 23 4939735108 ps
T965 /workspace/coverage/default/17.lc_ctrl_sec_token_mux.3079969948 Dec 24 01:07:39 PM PST 23 Dec 24 01:08:01 PM PST 23 3113661809 ps
T966 /workspace/coverage/default/42.lc_ctrl_sec_mubi.2661560575 Dec 24 01:08:53 PM PST 23 Dec 24 01:09:12 PM PST 23 703120553 ps
T967 /workspace/coverage/default/30.lc_ctrl_sec_mubi.4098399312 Dec 24 01:08:36 PM PST 23 Dec 24 01:08:55 PM PST 23 214985097 ps
T968 /workspace/coverage/default/18.lc_ctrl_jtag_access.3108975286 Dec 24 01:08:06 PM PST 23 Dec 24 01:08:38 PM PST 23 2360870410 ps
T969 /workspace/coverage/default/33.lc_ctrl_sec_token_digest.618952897 Dec 24 01:08:26 PM PST 23 Dec 24 01:08:56 PM PST 23 4255797347 ps
T970 /workspace/coverage/default/44.lc_ctrl_smoke.501518350 Dec 24 01:08:50 PM PST 23 Dec 24 01:08:59 PM PST 23 75098259 ps
T971 /workspace/coverage/default/25.lc_ctrl_errors.3180230792 Dec 24 01:08:06 PM PST 23 Dec 24 01:08:33 PM PST 23 938386842 ps
T58 /workspace/coverage/default/2.lc_ctrl_sec_cm.1208263048 Dec 24 01:06:46 PM PST 23 Dec 24 01:07:10 PM PST 23 107702328 ps
T972 /workspace/coverage/default/32.lc_ctrl_state_failure.3399841227 Dec 24 01:08:29 PM PST 23 Dec 24 01:09:11 PM PST 23 233462800 ps
T973 /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.2942891084 Dec 24 01:08:24 PM PST 23 Dec 24 01:08:43 PM PST 23 27870858 ps
T974 /workspace/coverage/default/34.lc_ctrl_sec_mubi.1716256554 Dec 24 01:08:34 PM PST 23 Dec 24 01:09:05 PM PST 23 462442427 ps
T975 /workspace/coverage/default/29.lc_ctrl_stress_all.1795248890 Dec 24 01:08:11 PM PST 23 Dec 24 01:09:01 PM PST 23 985718137 ps
T976 /workspace/coverage/default/7.lc_ctrl_prog_failure.3744730019 Dec 24 01:06:56 PM PST 23 Dec 24 01:07:05 PM PST 23 510781089 ps
T977 /workspace/coverage/default/0.lc_ctrl_jtag_smoke.2305513592 Dec 24 01:05:56 PM PST 23 Dec 24 01:06:06 PM PST 23 1544593891 ps
T978 /workspace/coverage/default/16.lc_ctrl_sec_mubi.1743700580 Dec 24 01:07:08 PM PST 23 Dec 24 01:07:25 PM PST 23 247340134 ps
T979 /workspace/coverage/default/32.lc_ctrl_smoke.438526929 Dec 24 01:08:31 PM PST 23 Dec 24 01:08:47 PM PST 23 43792639 ps
T980 /workspace/coverage/default/46.lc_ctrl_smoke.2105403927 Dec 24 01:08:52 PM PST 23 Dec 24 01:09:03 PM PST 23 144305784 ps
T981 /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3359620432 Dec 24 01:06:23 PM PST 23 Dec 24 01:06:38 PM PST 23 1108494081 ps
T982 /workspace/coverage/default/21.lc_ctrl_stress_all.3648232762 Dec 24 01:07:59 PM PST 23 Dec 24 01:09:36 PM PST 23 16244978757 ps
T983 /workspace/coverage/default/38.lc_ctrl_smoke.3272577719 Dec 24 01:08:39 PM PST 23 Dec 24 01:08:54 PM PST 23 106750213 ps
T984 /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.1069318823 Dec 24 01:07:15 PM PST 23 Dec 24 01:07:27 PM PST 23 358372622 ps
T985 /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.2470717576 Dec 24 01:07:11 PM PST 23 Dec 24 01:07:30 PM PST 23 790851026 ps
T986 /workspace/coverage/default/35.lc_ctrl_stress_all.851786507 Dec 24 01:08:45 PM PST 23 Dec 24 01:09:57 PM PST 23 14619777468 ps
T987 /workspace/coverage/default/36.lc_ctrl_sec_mubi.3080134581 Dec 24 01:08:35 PM PST 23 Dec 24 01:09:00 PM PST 23 595924999 ps

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.2422362113
Short name T2
Test name
Test status
Simulation time 11871208233 ps
CPU time 507.39 seconds
Started Dec 24 01:07:11 PM PST 23
Finished Dec 24 01:15:46 PM PST 23
Peak memory 464268 kb
Host smart-734d9656-ec3e-421b-8d04-9ea1bd3e9ebe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2422362113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.2422362113
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.1841444767
Short name T55
Test name
Test status
Simulation time 630822598 ps
CPU time 11.82 seconds
Started Dec 24 01:08:19 PM PST 23
Finished Dec 24 01:08:53 PM PST 23
Peak memory 218280 kb
Host smart-5d3a7f52-da0f-421c-a223-fa4bed4c1122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841444767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.1841444767
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2340773408
Short name T90
Test name
Test status
Simulation time 101309846 ps
CPU time 2.86 seconds
Started Dec 24 01:09:26 PM PST 23
Finished Dec 24 01:09:33 PM PST 23
Peak memory 221888 kb
Host smart-0208832a-df8e-47e1-af64-166a9a71ac7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340773408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.2340773408
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.1206721822
Short name T64
Test name
Test status
Simulation time 820800252 ps
CPU time 15.02 seconds
Started Dec 24 01:08:10 PM PST 23
Finished Dec 24 01:08:44 PM PST 23
Peak memory 218108 kb
Host smart-b15082a9-2acb-4288-a1d6-831ea7b44ea6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206721822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.1206721822
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1007171748
Short name T112
Test name
Test status
Simulation time 144188873 ps
CPU time 2.62 seconds
Started Dec 24 01:09:31 PM PST 23
Finished Dec 24 01:09:38 PM PST 23
Peak memory 218128 kb
Host smart-cabf3dda-1d69-49d8-8ac6-8009c1f2aae8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007171748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.1007171748
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.4243540212
Short name T36
Test name
Test status
Simulation time 12160846 ps
CPU time 0.88 seconds
Started Dec 24 01:06:49 PM PST 23
Finished Dec 24 01:06:54 PM PST 23
Peak memory 208392 kb
Host smart-9044bf08-59ae-4d91-82e1-b151c5525040
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243540212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.4243540212
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.1208263048
Short name T58
Test name
Test status
Simulation time 107702328 ps
CPU time 22.35 seconds
Started Dec 24 01:06:46 PM PST 23
Finished Dec 24 01:07:10 PM PST 23
Peak memory 284448 kb
Host smart-37b87985-414b-4d2b-8007-5bc9c7d48997
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208263048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.1208263048
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3374317370
Short name T111
Test name
Test status
Simulation time 47148071 ps
CPU time 1.54 seconds
Started Dec 24 01:09:15 PM PST 23
Finished Dec 24 01:09:22 PM PST 23
Peak memory 211316 kb
Host smart-ad005d7b-8477-4709-919d-f4012d72361c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374317370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.3374317370
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.3963460100
Short name T14
Test name
Test status
Simulation time 362121279 ps
CPU time 13.58 seconds
Started Dec 24 01:05:52 PM PST 23
Finished Dec 24 01:06:14 PM PST 23
Peak memory 217928 kb
Host smart-5a9426a9-4c62-4085-a891-b60186857dba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963460100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.3
963460100
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.2277817350
Short name T539
Test name
Test status
Simulation time 452606195 ps
CPU time 10.6 seconds
Started Dec 24 01:07:07 PM PST 23
Finished Dec 24 01:07:23 PM PST 23
Peak memory 218220 kb
Host smart-850bb41b-eb9b-4958-b139-6c5d519b497c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277817350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.2277817350
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1158434040
Short name T89
Test name
Test status
Simulation time 522286060 ps
CPU time 2.64 seconds
Started Dec 24 01:09:06 PM PST 23
Finished Dec 24 01:09:11 PM PST 23
Peak memory 210912 kb
Host smart-480c0942-ca27-436b-8532-d3d62408ad90
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158434040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.1158434040
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.4082245437
Short name T13
Test name
Test status
Simulation time 19481355459 ps
CPU time 378.87 seconds
Started Dec 24 01:08:40 PM PST 23
Finished Dec 24 01:15:06 PM PST 23
Peak memory 273336 kb
Host smart-a44506ba-2b27-47bc-bb6c-28f845fd4994
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4082245437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.4082245437
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.4246570675
Short name T119
Test name
Test status
Simulation time 75425977 ps
CPU time 1.23 seconds
Started Dec 24 01:09:15 PM PST 23
Finished Dec 24 01:09:20 PM PST 23
Peak memory 211440 kb
Host smart-3b70cf96-40c9-4e06-adb4-eab05461453d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246570675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.4246570675
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.31126514
Short name T114
Test name
Test status
Simulation time 305755765 ps
CPU time 2.7 seconds
Started Dec 24 01:09:34 PM PST 23
Finished Dec 24 01:09:44 PM PST 23
Peak memory 222036 kb
Host smart-42132938-5947-4b69-917d-966a00d15933
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31126514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_e
rr.31126514
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.2113446114
Short name T20
Test name
Test status
Simulation time 403601115 ps
CPU time 1.2 seconds
Started Dec 24 01:07:21 PM PST 23
Finished Dec 24 01:07:25 PM PST 23
Peak memory 209632 kb
Host smart-90896a38-39e6-4552-a2dc-6e1e2d32ad04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113446114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.2113446114
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3598374362
Short name T120
Test name
Test status
Simulation time 558578865 ps
CPU time 3.94 seconds
Started Dec 24 01:09:32 PM PST 23
Finished Dec 24 01:09:42 PM PST 23
Peak memory 217696 kb
Host smart-82ae55d4-2c6d-498b-b48c-d5be8ab66f94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598374362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.3598374362
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.1985481719
Short name T44
Test name
Test status
Simulation time 12849822144 ps
CPU time 204.22 seconds
Started Dec 24 01:08:53 PM PST 23
Finished Dec 24 01:12:23 PM PST 23
Peak memory 283984 kb
Host smart-991e6ae7-895c-4f6a-8a45-ec8d3da211f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985481719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.1985481719
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.931187146
Short name T109
Test name
Test status
Simulation time 62985566106 ps
CPU time 319.94 seconds
Started Dec 24 01:08:34 PM PST 23
Finished Dec 24 01:14:06 PM PST 23
Peak memory 333172 kb
Host smart-3f9517b4-3dce-411c-8933-ab78dea12940
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=931187146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.931187146
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.3325290701
Short name T6
Test name
Test status
Simulation time 1462472437 ps
CPU time 5.39 seconds
Started Dec 24 01:08:39 PM PST 23
Finished Dec 24 01:08:52 PM PST 23
Peak memory 209640 kb
Host smart-158d3d73-e3c5-4a6a-932d-bb715adceed8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325290701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_a
ccess.3325290701
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.177283850
Short name T117
Test name
Test status
Simulation time 46310319 ps
CPU time 1.36 seconds
Started Dec 24 01:09:15 PM PST 23
Finished Dec 24 01:09:21 PM PST 23
Peak memory 209404 kb
Host smart-73daa028-81f2-4f82-8d99-e0343d2d7c43
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177283850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasing
.177283850
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1183192416
Short name T121
Test name
Test status
Simulation time 166124779 ps
CPU time 1.88 seconds
Started Dec 24 01:09:33 PM PST 23
Finished Dec 24 01:09:41 PM PST 23
Peak memory 221592 kb
Host smart-8d01f34a-c2ce-4a83-98a0-450c8d222e67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183192416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.1183192416
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2535591403
Short name T132
Test name
Test status
Simulation time 273291858 ps
CPU time 2.49 seconds
Started Dec 24 01:09:29 PM PST 23
Finished Dec 24 01:09:34 PM PST 23
Peak memory 221812 kb
Host smart-eebece0d-c824-40d2-87fd-55f620b6a732
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535591403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.2535591403
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.328176538
Short name T576
Test name
Test status
Simulation time 29485995 ps
CPU time 0.84 seconds
Started Dec 24 01:05:53 PM PST 23
Finished Dec 24 01:06:01 PM PST 23
Peak memory 208196 kb
Host smart-62dcca07-4941-438b-a671-dd0948293a5d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328176538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctr
l_volatile_unlock_smoke.328176538
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1963060730
Short name T122
Test name
Test status
Simulation time 223784496 ps
CPU time 2.05 seconds
Started Dec 24 01:09:29 PM PST 23
Finished Dec 24 01:09:34 PM PST 23
Peak memory 221760 kb
Host smart-1d6fb744-8b38-452d-9713-a9ee5807fa78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963060730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.1963060730
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2993100819
Short name T99
Test name
Test status
Simulation time 262971744 ps
CPU time 3.33 seconds
Started Dec 24 01:09:29 PM PST 23
Finished Dec 24 01:09:35 PM PST 23
Peak memory 217708 kb
Host smart-ecfcad88-50bb-402f-ab84-75a02a888f5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993100819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.2993100819
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.4066073564
Short name T174
Test name
Test status
Simulation time 37234683 ps
CPU time 0.86 seconds
Started Dec 24 01:05:50 PM PST 23
Finished Dec 24 01:06:00 PM PST 23
Peak memory 209476 kb
Host smart-0e3e83da-65d0-44af-80ee-a8cd64812625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066073564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.4066073564
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.712107183
Short name T700
Test name
Test status
Simulation time 380581006 ps
CPU time 9.21 seconds
Started Dec 24 01:06:58 PM PST 23
Finished Dec 24 01:07:12 PM PST 23
Peak memory 218240 kb
Host smart-543312a6-6bb2-4404-8e6a-a78792c28b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712107183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.712107183
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.3181146820
Short name T176
Test name
Test status
Simulation time 11806664 ps
CPU time 0.97 seconds
Started Dec 24 01:06:30 PM PST 23
Finished Dec 24 01:06:33 PM PST 23
Peak memory 209640 kb
Host smart-ef6436d7-6e79-409b-b505-0176d79f1dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181146820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.3181146820
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.377459307
Short name T178
Test name
Test status
Simulation time 12674897 ps
CPU time 0.81 seconds
Started Dec 24 01:06:23 PM PST 23
Finished Dec 24 01:06:25 PM PST 23
Peak memory 209384 kb
Host smart-54cb1646-f36d-480a-89e0-16656a50047d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377459307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.377459307
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.1839600232
Short name T179
Test name
Test status
Simulation time 14027036 ps
CPU time 0.82 seconds
Started Dec 24 01:06:20 PM PST 23
Finished Dec 24 01:06:23 PM PST 23
Peak memory 209352 kb
Host smart-05d259a0-76da-4602-b177-3845610b8540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839600232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.1839600232
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.3598995401
Short name T177
Test name
Test status
Simulation time 11280685 ps
CPU time 0.78 seconds
Started Dec 24 01:06:50 PM PST 23
Finished Dec 24 01:06:55 PM PST 23
Peak memory 209432 kb
Host smart-33c25ac3-d1bc-42ff-b4c1-60db3d1745a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598995401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.3598995401
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.103660592
Short name T180
Test name
Test status
Simulation time 29456811 ps
CPU time 0.78 seconds
Started Dec 24 01:06:45 PM PST 23
Finished Dec 24 01:06:48 PM PST 23
Peak memory 208064 kb
Host smart-4bebd5b1-791c-47d9-9ef1-136cda009538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103660592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.103660592
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3467312239
Short name T115
Test name
Test status
Simulation time 284756235 ps
CPU time 2.18 seconds
Started Dec 24 01:09:15 PM PST 23
Finished Dec 24 01:09:21 PM PST 23
Peak memory 217628 kb
Host smart-fdd85f71-57ad-41c7-bd08-a7fea5e51896
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467312239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.3467312239
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3744445394
Short name T136
Test name
Test status
Simulation time 111931979 ps
CPU time 3.16 seconds
Started Dec 24 01:09:01 PM PST 23
Finished Dec 24 01:09:11 PM PST 23
Peak memory 222004 kb
Host smart-72eabd66-8d97-4580-9a21-7f7aff4bba4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744445394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.3744445394
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.391251366
Short name T127
Test name
Test status
Simulation time 233355938 ps
CPU time 2.18 seconds
Started Dec 24 01:09:17 PM PST 23
Finished Dec 24 01:09:24 PM PST 23
Peak memory 217740 kb
Host smart-a89ddb66-4076-41ed-a8bf-8eb24adb997c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391251366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_e
rr.391251366
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.63037676
Short name T126
Test name
Test status
Simulation time 107455161 ps
CPU time 2.37 seconds
Started Dec 24 01:09:18 PM PST 23
Finished Dec 24 01:09:26 PM PST 23
Peak memory 217772 kb
Host smart-1f20d158-028b-4fe6-b515-7edfd46d9997
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63037676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_er
r.63037676
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.545516593
Short name T137
Test name
Test status
Simulation time 101750305 ps
CPU time 4.01 seconds
Started Dec 24 01:09:30 PM PST 23
Finished Dec 24 01:09:39 PM PST 23
Peak memory 217872 kb
Host smart-452cd166-4fad-4f7f-9bb4-cd73003cd945
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545516593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_e
rr.545516593
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3169679650
Short name T131
Test name
Test status
Simulation time 133452294 ps
CPU time 2.58 seconds
Started Dec 24 01:09:34 PM PST 23
Finished Dec 24 01:09:44 PM PST 23
Peak memory 217724 kb
Host smart-8293c9a4-4cb4-4a8a-80e9-fb362c366f9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169679650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.3169679650
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.4104986189
Short name T47
Test name
Test status
Simulation time 772390043 ps
CPU time 16.69 seconds
Started Dec 24 01:05:56 PM PST 23
Finished Dec 24 01:06:19 PM PST 23
Peak memory 218196 kb
Host smart-ed2e35fb-807f-46e0-92a1-852392a1a071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104986189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.4104986189
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.3239130013
Short name T50
Test name
Test status
Simulation time 44584007349 ps
CPU time 173.05 seconds
Started Dec 24 01:06:25 PM PST 23
Finished Dec 24 01:09:20 PM PST 23
Peak memory 284008 kb
Host smart-afd99d1a-bbe0-4006-aba2-0331e7e59cb2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239130013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.3239130013
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3946344356
Short name T190
Test name
Test status
Simulation time 19703332 ps
CPU time 1.41 seconds
Started Dec 24 01:09:40 PM PST 23
Finished Dec 24 01:09:49 PM PST 23
Peak memory 219752 kb
Host smart-b46c2c00-f4ea-4ba5-a3d9-199638de7ac1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946344356 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.3946344356
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2673683218
Short name T196
Test name
Test status
Simulation time 26068628 ps
CPU time 1.41 seconds
Started Dec 24 01:09:16 PM PST 23
Finished Dec 24 01:09:23 PM PST 23
Peak memory 209512 kb
Host smart-9016a42e-ecd9-499b-b5e6-e8d3454b3aa7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673683218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.2673683218
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.813143208
Short name T234
Test name
Test status
Simulation time 19777317 ps
CPU time 1.1 seconds
Started Dec 24 01:09:17 PM PST 23
Finished Dec 24 01:09:23 PM PST 23
Peak memory 211284 kb
Host smart-250b7e9b-e402-4d7f-b4f0-5b4a9c0829ff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813143208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_reset
.813143208
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2341550546
Short name T128
Test name
Test status
Simulation time 44070810 ps
CPU time 1.88 seconds
Started Dec 24 01:09:20 PM PST 23
Finished Dec 24 01:09:29 PM PST 23
Peak memory 221744 kb
Host smart-98702b89-13ee-4130-b6b7-f9856a580033
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341550546 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.2341550546
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.82943533
Short name T139
Test name
Test status
Simulation time 36854235 ps
CPU time 1.13 seconds
Started Dec 24 01:09:13 PM PST 23
Finished Dec 24 01:09:17 PM PST 23
Peak memory 209556 kb
Host smart-082a98af-1a2f-4119-92f9-1504c82df326
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82943533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.82943533
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1590565615
Short name T237
Test name
Test status
Simulation time 175178287 ps
CPU time 1.03 seconds
Started Dec 24 01:09:10 PM PST 23
Finished Dec 24 01:09:14 PM PST 23
Peak memory 207820 kb
Host smart-9a99a58a-4348-41f5-a72b-aac79ee5d7b9
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590565615 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.1590565615
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3239901476
Short name T143
Test name
Test status
Simulation time 10753568209 ps
CPU time 12.77 seconds
Started Dec 24 01:09:17 PM PST 23
Finished Dec 24 01:09:36 PM PST 23
Peak memory 209532 kb
Host smart-60193e70-e4ab-4889-b4f0-3a0c097031e7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239901476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.3239901476
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3673238546
Short name T191
Test name
Test status
Simulation time 6563091956 ps
CPU time 17.27 seconds
Started Dec 24 01:09:11 PM PST 23
Finished Dec 24 01:09:31 PM PST 23
Peak memory 209536 kb
Host smart-3f36e782-37c8-40f2-af58-edef75c9b163
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673238546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.3673238546
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3446784589
Short name T283
Test name
Test status
Simulation time 194732409 ps
CPU time 2.55 seconds
Started Dec 24 01:09:14 PM PST 23
Finished Dec 24 01:09:20 PM PST 23
Peak memory 219204 kb
Host smart-5b37c2dc-0df0-4843-afb6-9c9a118a9080
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344678
4589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3446784589
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3448708412
Short name T150
Test name
Test status
Simulation time 271747377 ps
CPU time 2.74 seconds
Started Dec 24 01:09:15 PM PST 23
Finished Dec 24 01:09:21 PM PST 23
Peak memory 209432 kb
Host smart-bc2372a3-bb5f-40f1-ab8c-1b8de970d850
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448708412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.3448708412
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1179922878
Short name T243
Test name
Test status
Simulation time 46791084 ps
CPU time 2.01 seconds
Started Dec 24 01:08:57 PM PST 23
Finished Dec 24 01:09:06 PM PST 23
Peak memory 209544 kb
Host smart-63f2269c-4612-4f6c-b707-9962495dd995
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179922878 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.1179922878
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3744900226
Short name T289
Test name
Test status
Simulation time 79470469 ps
CPU time 1.92 seconds
Started Dec 24 01:09:08 PM PST 23
Finished Dec 24 01:09:11 PM PST 23
Peak memory 209592 kb
Host smart-13457515-5cfb-45a3-8a49-b488701750f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744900226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.3744900226
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3701396303
Short name T219
Test name
Test status
Simulation time 35979639 ps
CPU time 2.23 seconds
Started Dec 24 01:09:11 PM PST 23
Finished Dec 24 01:09:16 PM PST 23
Peak memory 217880 kb
Host smart-860242ce-1c34-47de-83fc-a6dce4d744dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701396303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.3701396303
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.752773694
Short name T169
Test name
Test status
Simulation time 33641784 ps
CPU time 1.17 seconds
Started Dec 24 01:09:10 PM PST 23
Finished Dec 24 01:09:14 PM PST 23
Peak memory 209660 kb
Host smart-7807e312-e163-4af4-886f-61e13cbdb9e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752773694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasing
.752773694
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.591620018
Short name T239
Test name
Test status
Simulation time 40027359 ps
CPU time 1.82 seconds
Started Dec 24 01:09:09 PM PST 23
Finished Dec 24 01:09:14 PM PST 23
Peak memory 209560 kb
Host smart-66c5b458-98e9-4641-b09d-90df36240b0a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591620018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bash
.591620018
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1940144033
Short name T213
Test name
Test status
Simulation time 15978911 ps
CPU time 1.27 seconds
Started Dec 24 01:09:05 PM PST 23
Finished Dec 24 01:09:10 PM PST 23
Peak memory 217840 kb
Host smart-354d34f4-5332-4236-b42c-3fedbbfa939f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940144033 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.1940144033
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3431976376
Short name T296
Test name
Test status
Simulation time 77115566 ps
CPU time 1.01 seconds
Started Dec 24 01:09:05 PM PST 23
Finished Dec 24 01:09:09 PM PST 23
Peak memory 209552 kb
Host smart-a2c37cf0-b277-445c-a35d-f5010d0f5e22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431976376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.3431976376
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1310907211
Short name T198
Test name
Test status
Simulation time 21015408 ps
CPU time 0.98 seconds
Started Dec 24 01:09:19 PM PST 23
Finished Dec 24 01:09:27 PM PST 23
Peak memory 209340 kb
Host smart-b111c3ae-784d-46c7-a6ce-297c345c00b5
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310907211 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1310907211
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1877933551
Short name T142
Test name
Test status
Simulation time 7956407260 ps
CPU time 13.75 seconds
Started Dec 24 01:09:16 PM PST 23
Finished Dec 24 01:09:35 PM PST 23
Peak memory 209528 kb
Host smart-eb723b1e-abf9-4b7d-b8d7-1f0c1e047e2a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877933551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.1877933551
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3635739804
Short name T276
Test name
Test status
Simulation time 1349424466 ps
CPU time 16.41 seconds
Started Dec 24 01:08:58 PM PST 23
Finished Dec 24 01:09:21 PM PST 23
Peak memory 208436 kb
Host smart-72581685-b2e6-4263-9eb4-b4279d7ca86d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635739804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.3635739804
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.609443586
Short name T254
Test name
Test status
Simulation time 105265037 ps
CPU time 2.85 seconds
Started Dec 24 01:09:10 PM PST 23
Finished Dec 24 01:09:16 PM PST 23
Peak memory 210920 kb
Host smart-38ead253-d14e-4e46-9ec7-fa4ed4e0f223
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609443586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.609443586
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.668654770
Short name T246
Test name
Test status
Simulation time 256379204 ps
CPU time 2.13 seconds
Started Dec 24 01:09:14 PM PST 23
Finished Dec 24 01:09:20 PM PST 23
Peak memory 218856 kb
Host smart-8e236e69-230d-4322-a33c-788a58b12dfb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668654
770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.668654770
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.539978543
Short name T280
Test name
Test status
Simulation time 556233631 ps
CPU time 2.02 seconds
Started Dec 24 01:09:08 PM PST 23
Finished Dec 24 01:09:11 PM PST 23
Peak memory 209384 kb
Host smart-fa625ff9-ee19-49b5-baf5-0ed74c9f7307
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539978543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.539978543
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1770243535
Short name T149
Test name
Test status
Simulation time 99755907 ps
CPU time 1.1 seconds
Started Dec 24 01:08:58 PM PST 23
Finished Dec 24 01:09:06 PM PST 23
Peak memory 209452 kb
Host smart-a2a629cf-285e-40bb-9df1-d47924ab5679
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770243535 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.1770243535
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1254496286
Short name T202
Test name
Test status
Simulation time 248991985 ps
CPU time 1.38 seconds
Started Dec 24 01:09:15 PM PST 23
Finished Dec 24 01:09:21 PM PST 23
Peak memory 209640 kb
Host smart-cc18b937-e12d-4dd2-8aeb-494a25b75ac4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254496286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.1254496286
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2778782667
Short name T123
Test name
Test status
Simulation time 69336827 ps
CPU time 1.52 seconds
Started Dec 24 01:09:13 PM PST 23
Finished Dec 24 01:09:17 PM PST 23
Peak memory 217680 kb
Host smart-1d585b82-e9f3-4fd7-9332-104ce1f5affa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778782667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.2778782667
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2639914294
Short name T129
Test name
Test status
Simulation time 352367782 ps
CPU time 2.66 seconds
Started Dec 24 01:09:15 PM PST 23
Finished Dec 24 01:09:22 PM PST 23
Peak memory 221576 kb
Host smart-cea22ea5-fed9-4b0b-bdcd-e3e1b0ba610c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639914294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2639914294
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2270484730
Short name T286
Test name
Test status
Simulation time 58462469 ps
CPU time 1.53 seconds
Started Dec 24 01:09:29 PM PST 23
Finished Dec 24 01:09:33 PM PST 23
Peak memory 219124 kb
Host smart-c20ece90-5089-4a7e-acec-e2479de6b73e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270484730 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.2270484730
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.550102023
Short name T259
Test name
Test status
Simulation time 65209381 ps
CPU time 1.1 seconds
Started Dec 24 01:09:36 PM PST 23
Finished Dec 24 01:09:45 PM PST 23
Peak memory 209492 kb
Host smart-e302919a-2d03-44e2-ad9a-4c671f031479
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550102023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.550102023
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.883116054
Short name T285
Test name
Test status
Simulation time 33263372 ps
CPU time 1.48 seconds
Started Dec 24 01:09:34 PM PST 23
Finished Dec 24 01:09:43 PM PST 23
Peak memory 211452 kb
Host smart-33d24c35-6f90-4265-bf2f-c0d6951a3b9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883116054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_same_csr_outstanding.883116054
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.268470377
Short name T207
Test name
Test status
Simulation time 127101818 ps
CPU time 4.18 seconds
Started Dec 24 01:09:33 PM PST 23
Finished Dec 24 01:09:44 PM PST 23
Peak memory 217704 kb
Host smart-f49978bb-8502-4177-99a3-5ee5018f20de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268470377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.268470377
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.947613113
Short name T269
Test name
Test status
Simulation time 71156903 ps
CPU time 3.01 seconds
Started Dec 24 01:09:39 PM PST 23
Finished Dec 24 01:09:50 PM PST 23
Peak memory 217680 kb
Host smart-14b56d5b-b2a2-4cae-b290-dddd29b7f134
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947613113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg_
err.947613113
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3190523756
Short name T144
Test name
Test status
Simulation time 71665655 ps
CPU time 0.83 seconds
Started Dec 24 01:09:32 PM PST 23
Finished Dec 24 01:09:39 PM PST 23
Peak memory 209360 kb
Host smart-4c71aa6f-a1a1-4b28-9345-0d64e6181c2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190523756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3190523756
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.415410538
Short name T270
Test name
Test status
Simulation time 19193675 ps
CPU time 1.14 seconds
Started Dec 24 01:09:35 PM PST 23
Finished Dec 24 01:09:44 PM PST 23
Peak memory 209548 kb
Host smart-fd4028b9-256e-4c51-b984-33f6d9903f5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415410538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_same_csr_outstanding.415410538
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.183631486
Short name T215
Test name
Test status
Simulation time 87185679 ps
CPU time 2.43 seconds
Started Dec 24 01:09:30 PM PST 23
Finished Dec 24 01:09:37 PM PST 23
Peak memory 217632 kb
Host smart-d39311d3-bd3a-4f4e-8749-8152d123d8e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183631486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.183631486
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3777297119
Short name T148
Test name
Test status
Simulation time 70959171 ps
CPU time 1.16 seconds
Started Dec 24 01:09:32 PM PST 23
Finished Dec 24 01:09:40 PM PST 23
Peak memory 219464 kb
Host smart-5cf22513-7a52-4418-9874-5352ddebee09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777297119 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.3777297119
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.510298623
Short name T159
Test name
Test status
Simulation time 28929964 ps
CPU time 0.88 seconds
Started Dec 24 01:09:31 PM PST 23
Finished Dec 24 01:09:36 PM PST 23
Peak memory 208876 kb
Host smart-078decf0-5257-4f1a-aaa4-79d27be36a7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510298623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.510298623
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.4136911579
Short name T273
Test name
Test status
Simulation time 48848316 ps
CPU time 1.15 seconds
Started Dec 24 01:09:33 PM PST 23
Finished Dec 24 01:09:40 PM PST 23
Peak memory 209568 kb
Host smart-0166c861-c633-4452-8944-eade8d7deb60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136911579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.4136911579
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.963097162
Short name T279
Test name
Test status
Simulation time 122780845 ps
CPU time 1.89 seconds
Started Dec 24 01:09:31 PM PST 23
Finished Dec 24 01:09:38 PM PST 23
Peak memory 217624 kb
Host smart-1dbe8099-80aa-4b31-a73f-9ec79ecfddb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963097162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.963097162
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2551761434
Short name T98
Test name
Test status
Simulation time 111129107 ps
CPU time 4.3 seconds
Started Dec 24 01:09:31 PM PST 23
Finished Dec 24 01:09:40 PM PST 23
Peak memory 217776 kb
Host smart-a17d0e57-81b9-42ca-9c25-84a2138bc4cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551761434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.2551761434
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3406865728
Short name T278
Test name
Test status
Simulation time 87828257 ps
CPU time 2.06 seconds
Started Dec 24 01:09:35 PM PST 23
Finished Dec 24 01:09:45 PM PST 23
Peak memory 218952 kb
Host smart-874bf058-a60c-41e3-aaaa-908cf8041977
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406865728 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.3406865728
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2698794011
Short name T214
Test name
Test status
Simulation time 12620432 ps
CPU time 1.03 seconds
Started Dec 24 01:09:32 PM PST 23
Finished Dec 24 01:09:39 PM PST 23
Peak memory 209448 kb
Host smart-18ad7b27-22c2-41c6-9e67-98acf2da34ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698794011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.2698794011
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3402588202
Short name T118
Test name
Test status
Simulation time 45265928 ps
CPU time 1.01 seconds
Started Dec 24 01:09:29 PM PST 23
Finished Dec 24 01:09:33 PM PST 23
Peak memory 208256 kb
Host smart-9b58a199-c085-4527-a853-56cd0f4f8215
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402588202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.3402588202
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.989500011
Short name T275
Test name
Test status
Simulation time 192493766 ps
CPU time 3.63 seconds
Started Dec 24 01:09:35 PM PST 23
Finished Dec 24 01:09:45 PM PST 23
Peak memory 218296 kb
Host smart-3465bf90-f59a-4ff8-a732-d70fab8addfa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989500011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.989500011
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3199808741
Short name T291
Test name
Test status
Simulation time 55005931 ps
CPU time 1.22 seconds
Started Dec 24 01:09:29 PM PST 23
Finished Dec 24 01:09:33 PM PST 23
Peak memory 219684 kb
Host smart-287ac211-5046-45cb-bb7c-8ca0289ff56a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199808741 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.3199808741
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.4161878523
Short name T160
Test name
Test status
Simulation time 20497157 ps
CPU time 0.82 seconds
Started Dec 24 01:09:35 PM PST 23
Finished Dec 24 01:09:44 PM PST 23
Peak memory 209336 kb
Host smart-3dee3beb-583e-49a0-80d3-1734a5efa561
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161878523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.4161878523
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2896083407
Short name T153
Test name
Test status
Simulation time 325643567 ps
CPU time 1.43 seconds
Started Dec 24 01:09:28 PM PST 23
Finished Dec 24 01:09:32 PM PST 23
Peak memory 209556 kb
Host smart-a458ddcd-b5c1-4f5b-948b-62c3c860b836
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896083407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.2896083407
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2486826746
Short name T260
Test name
Test status
Simulation time 193998354 ps
CPU time 3.74 seconds
Started Dec 24 01:09:40 PM PST 23
Finished Dec 24 01:09:51 PM PST 23
Peak memory 217600 kb
Host smart-4b76a4c9-5fc5-4e08-b61e-977e1b57a32e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486826746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.2486826746
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1040531566
Short name T274
Test name
Test status
Simulation time 60479513 ps
CPU time 2.68 seconds
Started Dec 24 01:09:58 PM PST 23
Finished Dec 24 01:10:04 PM PST 23
Peak memory 217752 kb
Host smart-38fb6239-328f-4ed6-acbd-a5fb72645131
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040531566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.1040531566
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1132673190
Short name T249
Test name
Test status
Simulation time 16159701 ps
CPU time 1.22 seconds
Started Dec 24 01:09:30 PM PST 23
Finished Dec 24 01:09:36 PM PST 23
Peak memory 219160 kb
Host smart-52ed9992-e3d0-43b1-8468-d22d63902661
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132673190 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.1132673190
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1848531524
Short name T255
Test name
Test status
Simulation time 43494913 ps
CPU time 0.85 seconds
Started Dec 24 01:09:56 PM PST 23
Finished Dec 24 01:10:01 PM PST 23
Peak memory 209536 kb
Host smart-ba3af4c9-ab60-43c5-b9f7-0c652f3cae9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848531524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.1848531524
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.143023476
Short name T200
Test name
Test status
Simulation time 76684072 ps
CPU time 1.42 seconds
Started Dec 24 01:09:28 PM PST 23
Finished Dec 24 01:09:33 PM PST 23
Peak memory 211576 kb
Host smart-d4f1048f-ee9f-4fca-a7b2-5d8ed0e7ea29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143023476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_same_csr_outstanding.143023476
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.7639316
Short name T247
Test name
Test status
Simulation time 128604596 ps
CPU time 2.17 seconds
Started Dec 24 01:09:19 PM PST 23
Finished Dec 24 01:09:28 PM PST 23
Peak memory 218908 kb
Host smart-ae35790d-3422-44d7-9116-21ee0bf78d93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7639316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.7639316
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.598739865
Short name T91
Test name
Test status
Simulation time 20101726 ps
CPU time 1.23 seconds
Started Dec 24 01:09:32 PM PST 23
Finished Dec 24 01:09:40 PM PST 23
Peak memory 217804 kb
Host smart-d9716650-8b71-4efa-a604-3dd3538a7b5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598739865 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.598739865
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1314894611
Short name T188
Test name
Test status
Simulation time 32073518 ps
CPU time 1.18 seconds
Started Dec 24 01:09:30 PM PST 23
Finished Dec 24 01:09:36 PM PST 23
Peak memory 209104 kb
Host smart-ddb7a6e4-5bc4-4343-9905-bfa878d54fd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314894611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1314894611
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1563501096
Short name T208
Test name
Test status
Simulation time 80518679 ps
CPU time 0.98 seconds
Started Dec 24 01:09:28 PM PST 23
Finished Dec 24 01:09:32 PM PST 23
Peak memory 209524 kb
Host smart-26f00cc2-9233-40e6-b584-18662ab52efc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563501096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.1563501096
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.345579494
Short name T116
Test name
Test status
Simulation time 41927783 ps
CPU time 1.49 seconds
Started Dec 24 01:09:21 PM PST 23
Finished Dec 24 01:09:29 PM PST 23
Peak memory 218884 kb
Host smart-c53b5ca0-8ff0-4735-b257-9e553071dba3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345579494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.345579494
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3697246696
Short name T231
Test name
Test status
Simulation time 19078645 ps
CPU time 1.29 seconds
Started Dec 24 01:09:30 PM PST 23
Finished Dec 24 01:09:36 PM PST 23
Peak memory 217744 kb
Host smart-ade78b03-76e2-4ded-94a9-ba3735d3affd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697246696 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.3697246696
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.188978800
Short name T157
Test name
Test status
Simulation time 18399350 ps
CPU time 0.91 seconds
Started Dec 24 01:09:32 PM PST 23
Finished Dec 24 01:09:39 PM PST 23
Peak memory 209648 kb
Host smart-99cae045-fac4-4e5c-9840-1a2339897c8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188978800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.188978800
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2725084617
Short name T172
Test name
Test status
Simulation time 21925949 ps
CPU time 1.47 seconds
Started Dec 24 01:09:33 PM PST 23
Finished Dec 24 01:09:41 PM PST 23
Peak memory 209568 kb
Host smart-2d27836f-2af9-42c0-85a1-986153de8f0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725084617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.2725084617
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1742806908
Short name T268
Test name
Test status
Simulation time 94299352 ps
CPU time 2.06 seconds
Started Dec 24 01:09:58 PM PST 23
Finished Dec 24 01:10:04 PM PST 23
Peak memory 217772 kb
Host smart-329fd670-0331-4372-96e9-6e6fad530e9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742806908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.1742806908
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2627777822
Short name T258
Test name
Test status
Simulation time 458052158 ps
CPU time 1.61 seconds
Started Dec 24 01:09:28 PM PST 23
Finished Dec 24 01:09:33 PM PST 23
Peak memory 219148 kb
Host smart-0fb2bdc8-270a-4ee9-b456-65a439549b64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627777822 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.2627777822
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3816352422
Short name T154
Test name
Test status
Simulation time 11964856 ps
CPU time 0.78 seconds
Started Dec 24 01:09:33 PM PST 23
Finished Dec 24 01:09:40 PM PST 23
Peak memory 209336 kb
Host smart-19e39cad-6ef6-43c1-852f-7d2e2e56fbe8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816352422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.3816352422
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.4136672746
Short name T220
Test name
Test status
Simulation time 99721942 ps
CPU time 1.45 seconds
Started Dec 24 01:09:37 PM PST 23
Finished Dec 24 01:09:46 PM PST 23
Peak memory 209588 kb
Host smart-c38ba1a8-845a-42a3-8ffe-1c52b8c48f4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136672746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.4136672746
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.767134764
Short name T130
Test name
Test status
Simulation time 187164732 ps
CPU time 2.79 seconds
Started Dec 24 01:09:29 PM PST 23
Finished Dec 24 01:09:35 PM PST 23
Peak memory 216552 kb
Host smart-212aadb0-05a7-4419-9713-879a4bebdfc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767134764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.767134764
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2354626656
Short name T295
Test name
Test status
Simulation time 60004551 ps
CPU time 1.23 seconds
Started Dec 24 01:09:30 PM PST 23
Finished Dec 24 01:09:35 PM PST 23
Peak memory 218628 kb
Host smart-6f228b8c-3ab2-49ce-85d6-d1df98c6a074
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354626656 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2354626656
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.28028202
Short name T158
Test name
Test status
Simulation time 52845241 ps
CPU time 0.83 seconds
Started Dec 24 01:09:32 PM PST 23
Finished Dec 24 01:09:39 PM PST 23
Peak memory 208680 kb
Host smart-3af3be38-4a62-4f14-9788-735a6722bf0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28028202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.28028202
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3868052040
Short name T241
Test name
Test status
Simulation time 82502000 ps
CPU time 1.36 seconds
Started Dec 24 01:09:29 PM PST 23
Finished Dec 24 01:09:34 PM PST 23
Peak memory 209692 kb
Host smart-266d29ab-0530-4387-a2bd-c755b01de3c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868052040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.3868052040
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.284005676
Short name T232
Test name
Test status
Simulation time 41703166 ps
CPU time 2.62 seconds
Started Dec 24 01:09:37 PM PST 23
Finished Dec 24 01:09:47 PM PST 23
Peak memory 218872 kb
Host smart-ba058ac4-34e9-40e4-8869-305e7bf0a80c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284005676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.284005676
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.796843335
Short name T93
Test name
Test status
Simulation time 64628393 ps
CPU time 2.49 seconds
Started Dec 24 01:09:39 PM PST 23
Finished Dec 24 01:09:50 PM PST 23
Peak memory 217856 kb
Host smart-f1adaaac-958a-4975-bf9b-fd6c0c9bc0e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796843335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg_
err.796843335
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3886210950
Short name T161
Test name
Test status
Simulation time 155457045 ps
CPU time 1.33 seconds
Started Dec 24 01:09:16 PM PST 23
Finished Dec 24 01:09:22 PM PST 23
Peak memory 209464 kb
Host smart-c4c3c90e-5579-424a-b178-00defaf5ae7a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886210950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.3886210950
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.235960051
Short name T192
Test name
Test status
Simulation time 185240353 ps
CPU time 1.9 seconds
Started Dec 24 01:09:21 PM PST 23
Finished Dec 24 01:09:29 PM PST 23
Peak memory 208092 kb
Host smart-92e8427f-541f-4b75-a485-8bf13068733d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235960051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bash
.235960051
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.737351412
Short name T171
Test name
Test status
Simulation time 45612524 ps
CPU time 1.03 seconds
Started Dec 24 01:09:16 PM PST 23
Finished Dec 24 01:09:23 PM PST 23
Peak memory 209740 kb
Host smart-80ab6d2d-02a1-4368-949a-d9d89e383d0e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737351412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_reset
.737351412
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2394374647
Short name T292
Test name
Test status
Simulation time 22033715 ps
CPU time 1.04 seconds
Started Dec 24 01:09:10 PM PST 23
Finished Dec 24 01:09:14 PM PST 23
Peak memory 217940 kb
Host smart-fe213eb2-1bb3-4336-9955-4fa51de4d306
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394374647 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.2394374647
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.4051926361
Short name T155
Test name
Test status
Simulation time 11615180 ps
CPU time 0.85 seconds
Started Dec 24 01:09:13 PM PST 23
Finished Dec 24 01:09:16 PM PST 23
Peak memory 208564 kb
Host smart-7d4fb86d-12e5-4539-9fc0-acd12e28908c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051926361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.4051926361
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.294956515
Short name T212
Test name
Test status
Simulation time 92648282 ps
CPU time 1.86 seconds
Started Dec 24 01:09:19 PM PST 23
Finished Dec 24 01:09:28 PM PST 23
Peak memory 209412 kb
Host smart-45848963-4f2d-4f90-9c1e-bb4e0e826572
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294956515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.lc_ctrl_jtag_alert_test.294956515
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.4263972781
Short name T262
Test name
Test status
Simulation time 6275835433 ps
CPU time 6.78 seconds
Started Dec 24 01:09:10 PM PST 23
Finished Dec 24 01:09:20 PM PST 23
Peak memory 209484 kb
Host smart-03ea96c5-a1fd-4238-a1ee-3dcf06029443
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263972781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.4263972781
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2512980335
Short name T193
Test name
Test status
Simulation time 3628695150 ps
CPU time 17.91 seconds
Started Dec 24 01:09:17 PM PST 23
Finished Dec 24 01:09:41 PM PST 23
Peak memory 209508 kb
Host smart-951e60e3-360d-436d-a4dc-5581bce068a4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512980335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.2512980335
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1040604376
Short name T138
Test name
Test status
Simulation time 422689479 ps
CPU time 2.61 seconds
Started Dec 24 01:09:18 PM PST 23
Finished Dec 24 01:09:26 PM PST 23
Peak memory 210740 kb
Host smart-e460837c-688b-4df6-8fe9-a52f8ec05e91
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040604376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.1040604376
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4102227741
Short name T263
Test name
Test status
Simulation time 207794198 ps
CPU time 1.26 seconds
Started Dec 24 01:09:10 PM PST 23
Finished Dec 24 01:09:14 PM PST 23
Peak memory 218204 kb
Host smart-814a4ed4-fac2-4860-ade1-59f36ea8e6b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410222
7741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4102227741
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3300329643
Short name T88
Test name
Test status
Simulation time 641877002 ps
CPU time 1.79 seconds
Started Dec 24 01:09:17 PM PST 23
Finished Dec 24 01:09:24 PM PST 23
Peak memory 209404 kb
Host smart-42ef3cc1-1edb-460e-b09c-5b3f4a5ae6ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300329643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.3300329643
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3364194348
Short name T224
Test name
Test status
Simulation time 35658694 ps
CPU time 1.19 seconds
Started Dec 24 01:09:15 PM PST 23
Finished Dec 24 01:09:20 PM PST 23
Peak memory 209600 kb
Host smart-79d1e4ec-f2e6-4fb5-be6f-6ec39f8882b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364194348 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.3364194348
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3465210882
Short name T147
Test name
Test status
Simulation time 29050269 ps
CPU time 1.49 seconds
Started Dec 24 01:09:16 PM PST 23
Finished Dec 24 01:09:23 PM PST 23
Peak memory 209624 kb
Host smart-14a966c5-4dea-405f-a00c-c97369722ea9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465210882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.3465210882
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3667617665
Short name T205
Test name
Test status
Simulation time 77148128 ps
CPU time 1.15 seconds
Started Dec 24 01:09:17 PM PST 23
Finished Dec 24 01:09:23 PM PST 23
Peak memory 209584 kb
Host smart-865407f9-58ad-43c9-a101-f3081c1358ea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667617665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.3667617665
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3176266727
Short name T187
Test name
Test status
Simulation time 119793489 ps
CPU time 1.8 seconds
Started Dec 24 01:09:20 PM PST 23
Finished Dec 24 01:09:29 PM PST 23
Peak memory 208452 kb
Host smart-1392cbd3-c16d-45ae-8f43-5bf6bfb8b68a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176266727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.3176266727
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.838741773
Short name T287
Test name
Test status
Simulation time 17789646 ps
CPU time 1.18 seconds
Started Dec 24 01:09:07 PM PST 23
Finished Dec 24 01:09:10 PM PST 23
Peak memory 209968 kb
Host smart-fbc43153-1f1d-4e61-8d9c-a08d616342a6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838741773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_reset
.838741773
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1830592427
Short name T152
Test name
Test status
Simulation time 42640989 ps
CPU time 1.56 seconds
Started Dec 24 01:09:23 PM PST 23
Finished Dec 24 01:09:30 PM PST 23
Peak memory 218992 kb
Host smart-b4481ea2-dd62-4844-a072-79fecb24d704
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830592427 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.1830592427
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1542570238
Short name T156
Test name
Test status
Simulation time 60818499 ps
CPU time 0.9 seconds
Started Dec 24 01:09:09 PM PST 23
Finished Dec 24 01:09:13 PM PST 23
Peak memory 209132 kb
Host smart-dbe2a094-6756-4292-8373-ddcd96d06ce2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542570238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.1542570238
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.88481020
Short name T253
Test name
Test status
Simulation time 403900746 ps
CPU time 1.4 seconds
Started Dec 24 01:09:21 PM PST 23
Finished Dec 24 01:09:29 PM PST 23
Peak memory 207724 kb
Host smart-54bf9d55-6ebf-46f3-8a8c-dd018a8459d5
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88481020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_alert_test.88481020
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1447845662
Short name T235
Test name
Test status
Simulation time 2056328105 ps
CPU time 11.78 seconds
Started Dec 24 01:09:18 PM PST 23
Finished Dec 24 01:09:36 PM PST 23
Peak memory 208492 kb
Host smart-61124c7d-2406-4246-b7e6-21e23196ec32
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447845662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.1447845662
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2881861051
Short name T250
Test name
Test status
Simulation time 3455203060 ps
CPU time 12.04 seconds
Started Dec 24 01:09:17 PM PST 23
Finished Dec 24 01:09:34 PM PST 23
Peak memory 209124 kb
Host smart-0a1211f2-bffc-4b66-a0cb-38f47bcad855
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881861051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.2881861051
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1021770173
Short name T245
Test name
Test status
Simulation time 77477029 ps
CPU time 1.32 seconds
Started Dec 24 01:09:10 PM PST 23
Finished Dec 24 01:09:14 PM PST 23
Peak memory 210216 kb
Host smart-066397a6-0ca0-4850-b155-1ade23944e4e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021770173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.1021770173
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1450976299
Short name T165
Test name
Test status
Simulation time 93821792 ps
CPU time 1.97 seconds
Started Dec 24 01:09:16 PM PST 23
Finished Dec 24 01:09:22 PM PST 23
Peak memory 219228 kb
Host smart-4bd96bba-4f83-46a1-88ab-0f273e73f9c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145097
6299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1450976299
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.986532889
Short name T206
Test name
Test status
Simulation time 253291462 ps
CPU time 2.1 seconds
Started Dec 24 01:09:18 PM PST 23
Finished Dec 24 01:09:26 PM PST 23
Peak memory 209472 kb
Host smart-41ffc438-e42e-4a72-9cd8-6661c0892df0
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986532889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.986532889
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1733812924
Short name T233
Test name
Test status
Simulation time 26666350 ps
CPU time 1.37 seconds
Started Dec 24 01:09:15 PM PST 23
Finished Dec 24 01:09:20 PM PST 23
Peak memory 209544 kb
Host smart-6357f12d-c9a3-42e5-92ad-b18a72a873f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733812924 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.1733812924
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.4249680712
Short name T226
Test name
Test status
Simulation time 29026338 ps
CPU time 1.94 seconds
Started Dec 24 01:09:19 PM PST 23
Finished Dec 24 01:09:28 PM PST 23
Peak memory 218808 kb
Host smart-973845b2-273f-49ed-af04-f5b64b11384a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249680712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.4249680712
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1315956974
Short name T173
Test name
Test status
Simulation time 40110199 ps
CPU time 1.02 seconds
Started Dec 24 01:09:17 PM PST 23
Finished Dec 24 01:09:23 PM PST 23
Peak memory 208916 kb
Host smart-00f6c8cf-c37f-4f10-a731-797b32825601
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315956974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.1315956974
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.551050164
Short name T163
Test name
Test status
Simulation time 66203505 ps
CPU time 1.27 seconds
Started Dec 24 01:09:22 PM PST 23
Finished Dec 24 01:09:29 PM PST 23
Peak memory 209556 kb
Host smart-7b3c80ff-c7c0-4c40-97c6-3281cd9aff21
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551050164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bash
.551050164
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1625325358
Short name T170
Test name
Test status
Simulation time 23337959 ps
CPU time 1.08 seconds
Started Dec 24 01:09:19 PM PST 23
Finished Dec 24 01:09:27 PM PST 23
Peak memory 219736 kb
Host smart-587851e2-b759-4a16-be78-a3d8696fc814
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625325358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.1625325358
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1359308515
Short name T297
Test name
Test status
Simulation time 15348586 ps
CPU time 1.11 seconds
Started Dec 24 01:09:14 PM PST 23
Finished Dec 24 01:09:18 PM PST 23
Peak memory 217780 kb
Host smart-41c4eb68-e189-4559-b1c7-39d2d08331fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359308515 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.1359308515
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3514428839
Short name T203
Test name
Test status
Simulation time 16845918 ps
CPU time 0.89 seconds
Started Dec 24 01:09:07 PM PST 23
Finished Dec 24 01:09:10 PM PST 23
Peak memory 209616 kb
Host smart-37327240-44c3-4bcb-acb0-1907354a9b25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514428839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3514428839
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.520569516
Short name T294
Test name
Test status
Simulation time 39728045 ps
CPU time 1.64 seconds
Started Dec 24 01:09:08 PM PST 23
Finished Dec 24 01:09:11 PM PST 23
Peak memory 209444 kb
Host smart-e68ed2fe-44e5-48d1-8ebb-a0ecb571dd8f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520569516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.lc_ctrl_jtag_alert_test.520569516
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2093849656
Short name T194
Test name
Test status
Simulation time 668115374 ps
CPU time 8.26 seconds
Started Dec 24 01:09:21 PM PST 23
Finished Dec 24 01:09:36 PM PST 23
Peak memory 209504 kb
Host smart-6b8b3356-048c-4077-a5a4-23c54c38f495
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093849656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.2093849656
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3420769168
Short name T113
Test name
Test status
Simulation time 8711528744 ps
CPU time 18.53 seconds
Started Dec 24 01:09:14 PM PST 23
Finished Dec 24 01:09:36 PM PST 23
Peak memory 209212 kb
Host smart-c748a141-2ac4-448e-ae2b-cd11f7f9dad5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420769168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3420769168
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2514442783
Short name T240
Test name
Test status
Simulation time 1122717679 ps
CPU time 2.2 seconds
Started Dec 24 01:09:11 PM PST 23
Finished Dec 24 01:09:15 PM PST 23
Peak memory 210868 kb
Host smart-0c49c983-c3bf-45ed-a0f8-7b5c96e7e402
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514442783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2514442783
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1282919628
Short name T281
Test name
Test status
Simulation time 299315274 ps
CPU time 2.59 seconds
Started Dec 24 01:09:21 PM PST 23
Finished Dec 24 01:09:30 PM PST 23
Peak memory 217836 kb
Host smart-e13cb700-d9e0-488f-8ac7-a3e1bba73de3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128291
9628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1282919628
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1832603813
Short name T244
Test name
Test status
Simulation time 239991199 ps
CPU time 1.98 seconds
Started Dec 24 01:09:17 PM PST 23
Finished Dec 24 01:09:24 PM PST 23
Peak memory 209508 kb
Host smart-d4e472bf-6933-4081-970a-258b2425028e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832603813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1832603813
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2027023552
Short name T229
Test name
Test status
Simulation time 19935896 ps
CPU time 1.45 seconds
Started Dec 24 01:09:09 PM PST 23
Finished Dec 24 01:09:14 PM PST 23
Peak memory 211528 kb
Host smart-50024999-0642-4bb5-84e0-1c0647897334
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027023552 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.2027023552
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.367582769
Short name T164
Test name
Test status
Simulation time 51028450 ps
CPU time 1.16 seconds
Started Dec 24 01:09:17 PM PST 23
Finished Dec 24 01:09:23 PM PST 23
Peak memory 209000 kb
Host smart-212b1f9e-2221-447b-9725-833259e6bd55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367582769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
same_csr_outstanding.367582769
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3942724961
Short name T267
Test name
Test status
Simulation time 131585204 ps
CPU time 2.24 seconds
Started Dec 24 01:09:15 PM PST 23
Finished Dec 24 01:09:21 PM PST 23
Peak memory 217680 kb
Host smart-4e6dacf5-ea7a-488c-967b-4d804ac74e1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942724961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.3942724961
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1959469898
Short name T134
Test name
Test status
Simulation time 67793283 ps
CPU time 2.07 seconds
Started Dec 24 01:09:19 PM PST 23
Finished Dec 24 01:09:28 PM PST 23
Peak memory 221460 kb
Host smart-c3f66efa-8610-4359-ba1f-df8660437323
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959469898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.1959469898
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2836556019
Short name T216
Test name
Test status
Simulation time 19464487 ps
CPU time 1.08 seconds
Started Dec 24 01:09:18 PM PST 23
Finished Dec 24 01:09:25 PM PST 23
Peak memory 218012 kb
Host smart-41a524a7-ef85-4243-a7dc-8f5a8f3d04b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836556019 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.2836556019
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2251455128
Short name T162
Test name
Test status
Simulation time 18129173 ps
CPU time 0.95 seconds
Started Dec 24 01:09:32 PM PST 23
Finished Dec 24 01:09:39 PM PST 23
Peak memory 209516 kb
Host smart-8d7a6843-1bca-40bc-9732-cca0ae8ce477
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251455128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.2251455128
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3025460837
Short name T168
Test name
Test status
Simulation time 153142206 ps
CPU time 1.13 seconds
Started Dec 24 01:09:28 PM PST 23
Finished Dec 24 01:09:32 PM PST 23
Peak memory 209376 kb
Host smart-27fe96b8-cb32-4d91-9464-852db8695601
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025460837 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.3025460837
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1359375252
Short name T95
Test name
Test status
Simulation time 1507183119 ps
CPU time 5.09 seconds
Started Dec 24 01:09:20 PM PST 23
Finished Dec 24 01:09:32 PM PST 23
Peak memory 209408 kb
Host smart-e760bb28-c91f-44d4-8108-2054dd6b43e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359375252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.1359375252
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.982287272
Short name T230
Test name
Test status
Simulation time 3477059699 ps
CPU time 20.5 seconds
Started Dec 24 01:09:20 PM PST 23
Finished Dec 24 01:09:47 PM PST 23
Peak memory 208460 kb
Host smart-f9d5decb-ea16-4f93-80dc-76b0fe612905
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982287272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.982287272
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2644325940
Short name T288
Test name
Test status
Simulation time 216462206 ps
CPU time 1.8 seconds
Started Dec 24 01:09:27 PM PST 23
Finished Dec 24 01:09:33 PM PST 23
Peak memory 210632 kb
Host smart-8ac7287f-b10b-498d-902f-7bc5b29310bf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644325940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.2644325940
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1183766048
Short name T277
Test name
Test status
Simulation time 33257938 ps
CPU time 1.08 seconds
Started Dec 24 01:09:17 PM PST 23
Finished Dec 24 01:09:24 PM PST 23
Peak memory 209604 kb
Host smart-73d0be8a-6e5f-483d-8db0-eeb53d377e49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118376
6048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1183766048
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2650940465
Short name T282
Test name
Test status
Simulation time 114362284 ps
CPU time 1.16 seconds
Started Dec 24 01:09:15 PM PST 23
Finished Dec 24 01:09:21 PM PST 23
Peak memory 209400 kb
Host smart-36be97b4-62f3-40ff-a34d-11b02a8755d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650940465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.2650940465
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3951703693
Short name T256
Test name
Test status
Simulation time 20867549 ps
CPU time 1.2 seconds
Started Dec 24 01:09:21 PM PST 23
Finished Dec 24 01:09:28 PM PST 23
Peak memory 209164 kb
Host smart-00b3c675-73f7-4a3c-8171-82f9b41e9ac7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951703693 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3951703693
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2160353559
Short name T92
Test name
Test status
Simulation time 38365765 ps
CPU time 1.21 seconds
Started Dec 24 01:09:16 PM PST 23
Finished Dec 24 01:09:23 PM PST 23
Peak memory 209468 kb
Host smart-c122c205-76b3-4e48-b05f-f0f2d43492c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160353559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.2160353559
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.731566738
Short name T271
Test name
Test status
Simulation time 148261292 ps
CPU time 2.5 seconds
Started Dec 24 01:09:19 PM PST 23
Finished Dec 24 01:09:28 PM PST 23
Peak memory 219772 kb
Host smart-fc10a620-81a5-4928-883b-3d0cad1ed0ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731566738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.731566738
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.570709967
Short name T133
Test name
Test status
Simulation time 118896475 ps
CPU time 3 seconds
Started Dec 24 01:09:17 PM PST 23
Finished Dec 24 01:09:26 PM PST 23
Peak memory 222012 kb
Host smart-597e801f-a017-49d4-a7cf-16d6381292a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570709967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_e
rr.570709967
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3463989001
Short name T146
Test name
Test status
Simulation time 193263601 ps
CPU time 1.16 seconds
Started Dec 24 01:09:18 PM PST 23
Finished Dec 24 01:09:26 PM PST 23
Peak memory 218304 kb
Host smart-b05aa577-ff01-48c3-8369-5a4d6944299a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463989001 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.3463989001
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1323901584
Short name T218
Test name
Test status
Simulation time 49029588 ps
CPU time 0.93 seconds
Started Dec 24 01:09:30 PM PST 23
Finished Dec 24 01:09:36 PM PST 23
Peak memory 209076 kb
Host smart-f78c8f0b-34f4-4fbe-afc1-94717ad87cc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323901584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1323901584
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.860020230
Short name T236
Test name
Test status
Simulation time 37122529 ps
CPU time 1.51 seconds
Started Dec 24 01:09:27 PM PST 23
Finished Dec 24 01:09:32 PM PST 23
Peak memory 209416 kb
Host smart-6865fed0-44b3-4261-9cc7-5889183e1640
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860020230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.lc_ctrl_jtag_alert_test.860020230
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.4192695129
Short name T197
Test name
Test status
Simulation time 1360348558 ps
CPU time 4.18 seconds
Started Dec 24 01:09:29 PM PST 23
Finished Dec 24 01:09:36 PM PST 23
Peak memory 209408 kb
Host smart-76c18223-f14e-4215-b751-af5bc774d189
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192695129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.4192695129
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1172661329
Short name T290
Test name
Test status
Simulation time 475193710 ps
CPU time 5.61 seconds
Started Dec 24 01:09:16 PM PST 23
Finished Dec 24 01:09:27 PM PST 23
Peak memory 208484 kb
Host smart-37a7f7a7-70c1-4ffc-aa1e-32f493b080b8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172661329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1172661329
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.4233225125
Short name T252
Test name
Test status
Simulation time 206308689 ps
CPU time 4.41 seconds
Started Dec 24 01:09:32 PM PST 23
Finished Dec 24 01:09:42 PM PST 23
Peak memory 210912 kb
Host smart-bf0d6873-702b-4f82-a0b9-37cbe4d54465
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233225125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.4233225125
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1581150286
Short name T293
Test name
Test status
Simulation time 67473613 ps
CPU time 1.35 seconds
Started Dec 24 01:09:31 PM PST 23
Finished Dec 24 01:09:37 PM PST 23
Peak memory 209608 kb
Host smart-145083e7-21cb-493a-be3a-688fbd5fe1d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158115
0286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1581150286
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3361425633
Short name T228
Test name
Test status
Simulation time 138664577 ps
CPU time 2.03 seconds
Started Dec 24 01:09:15 PM PST 23
Finished Dec 24 01:09:22 PM PST 23
Peak memory 209408 kb
Host smart-0bf46478-79ea-4923-be24-37d7f3d9178d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361425633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.3361425633
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2641528723
Short name T272
Test name
Test status
Simulation time 82201382 ps
CPU time 1.26 seconds
Started Dec 24 01:09:19 PM PST 23
Finished Dec 24 01:09:27 PM PST 23
Peak memory 209528 kb
Host smart-ef88376f-af10-4647-a84d-03b90f206649
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641528723 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.2641528723
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2417315788
Short name T217
Test name
Test status
Simulation time 125489550 ps
CPU time 1.23 seconds
Started Dec 24 01:09:29 PM PST 23
Finished Dec 24 01:09:33 PM PST 23
Peak memory 211304 kb
Host smart-a403b2cb-a156-4602-8c7b-35658cea3808
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417315788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.2417315788
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2775937223
Short name T135
Test name
Test status
Simulation time 113373309 ps
CPU time 2.75 seconds
Started Dec 24 01:09:18 PM PST 23
Finished Dec 24 01:09:26 PM PST 23
Peak memory 221748 kb
Host smart-f015a05d-3557-4646-afa0-677535f1c6f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775937223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.2775937223
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.992824835
Short name T222
Test name
Test status
Simulation time 19296440 ps
CPU time 1.07 seconds
Started Dec 24 01:09:33 PM PST 23
Finished Dec 24 01:09:41 PM PST 23
Peak memory 219196 kb
Host smart-3027ff86-98bb-47a3-95ea-fff6be7abb38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992824835 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.992824835
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1304881729
Short name T251
Test name
Test status
Simulation time 238673782 ps
CPU time 0.98 seconds
Started Dec 24 01:09:29 PM PST 23
Finished Dec 24 01:09:32 PM PST 23
Peak memory 209448 kb
Host smart-0a0b4be8-47d2-46d6-9fb5-c744e6326ebc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304881729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.1304881729
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3145390489
Short name T242
Test name
Test status
Simulation time 274854288 ps
CPU time 1.29 seconds
Started Dec 24 01:09:20 PM PST 23
Finished Dec 24 01:09:28 PM PST 23
Peak memory 207776 kb
Host smart-492930a9-3060-4393-a27c-e3a009c1a177
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145390489 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.3145390489
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3233097314
Short name T225
Test name
Test status
Simulation time 2665849911 ps
CPU time 5.68 seconds
Started Dec 24 01:09:31 PM PST 23
Finished Dec 24 01:09:42 PM PST 23
Peak memory 208520 kb
Host smart-8f92ab03-9ad6-48e2-898c-ab3ab24ed1f7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233097314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.3233097314
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1812256710
Short name T167
Test name
Test status
Simulation time 1488831747 ps
CPU time 10.83 seconds
Started Dec 24 01:09:28 PM PST 23
Finished Dec 24 01:09:42 PM PST 23
Peak memory 209476 kb
Host smart-ced9a53d-62f0-429d-a38d-839b9f04ef99
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812256710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.1812256710
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3168873530
Short name T210
Test name
Test status
Simulation time 130768497 ps
CPU time 1.69 seconds
Started Dec 24 01:09:17 PM PST 23
Finished Dec 24 01:09:25 PM PST 23
Peak memory 210584 kb
Host smart-b1f98d3a-b087-48cf-a53c-2700ade1c9c0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168873530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.3168873530
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2347814557
Short name T211
Test name
Test status
Simulation time 345993208 ps
CPU time 2.17 seconds
Started Dec 24 01:09:51 PM PST 23
Finished Dec 24 01:09:59 PM PST 23
Peak memory 224376 kb
Host smart-c15050d4-9a48-449d-8ce0-6a1456c771c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234781
4557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2347814557
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.4189997414
Short name T227
Test name
Test status
Simulation time 62114736 ps
CPU time 1.42 seconds
Started Dec 24 01:09:32 PM PST 23
Finished Dec 24 01:09:40 PM PST 23
Peak memory 209364 kb
Host smart-4418f518-031a-47b1-855d-d035202bb8fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189997414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.4189997414
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3179112077
Short name T264
Test name
Test status
Simulation time 32443618 ps
CPU time 0.98 seconds
Started Dec 24 01:09:27 PM PST 23
Finished Dec 24 01:09:31 PM PST 23
Peak memory 209180 kb
Host smart-f6115dec-55c3-4244-9944-1806edca8f70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179112077 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.3179112077
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.4190704831
Short name T257
Test name
Test status
Simulation time 15700774 ps
CPU time 1.15 seconds
Started Dec 24 01:09:28 PM PST 23
Finished Dec 24 01:09:32 PM PST 23
Peak memory 209488 kb
Host smart-33397665-35db-42d5-8252-1773e05c2f04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190704831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.4190704831
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.433132820
Short name T125
Test name
Test status
Simulation time 76822040 ps
CPU time 2.74 seconds
Started Dec 24 01:09:30 PM PST 23
Finished Dec 24 01:09:37 PM PST 23
Peak memory 217744 kb
Host smart-6fe0a6ab-ca6a-4c91-8f76-6ba44c3edb08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433132820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.433132820
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3464947311
Short name T238
Test name
Test status
Simulation time 18958479 ps
CPU time 1.48 seconds
Started Dec 24 01:09:35 PM PST 23
Finished Dec 24 01:09:43 PM PST 23
Peak memory 219244 kb
Host smart-8c8754f5-63b0-498a-ba70-d7d6840b9de3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464947311 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.3464947311
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2675791982
Short name T94
Test name
Test status
Simulation time 12467945 ps
CPU time 1.03 seconds
Started Dec 24 01:09:32 PM PST 23
Finished Dec 24 01:09:38 PM PST 23
Peak memory 209496 kb
Host smart-05ee32c6-66d5-4261-b878-f03bf98631cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675791982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2675791982
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2146266622
Short name T140
Test name
Test status
Simulation time 42040891 ps
CPU time 1.16 seconds
Started Dec 24 01:09:40 PM PST 23
Finished Dec 24 01:09:48 PM PST 23
Peak memory 209320 kb
Host smart-474c8994-fa86-4554-ba47-2d9da7a04f94
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146266622 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.2146266622
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2227928474
Short name T261
Test name
Test status
Simulation time 692680315 ps
CPU time 3.85 seconds
Started Dec 24 01:09:16 PM PST 23
Finished Dec 24 01:09:25 PM PST 23
Peak memory 208460 kb
Host smart-9788a826-4df5-489d-9a77-a22ced4e8667
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227928474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.2227928474
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3119801898
Short name T266
Test name
Test status
Simulation time 541267667 ps
CPU time 11.89 seconds
Started Dec 24 01:09:19 PM PST 23
Finished Dec 24 01:09:38 PM PST 23
Peak memory 209436 kb
Host smart-be5ee924-3a88-4729-b683-7915e3eb764d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119801898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3119801898
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1869998904
Short name T195
Test name
Test status
Simulation time 1556828959 ps
CPU time 1.83 seconds
Started Dec 24 01:09:18 PM PST 23
Finished Dec 24 01:09:26 PM PST 23
Peak memory 210892 kb
Host smart-62753ffa-15a7-4f34-b3a0-e77ec7fb350f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869998904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.1869998904
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2710928831
Short name T265
Test name
Test status
Simulation time 143197108 ps
CPU time 1.82 seconds
Started Dec 24 01:09:19 PM PST 23
Finished Dec 24 01:09:28 PM PST 23
Peak memory 217736 kb
Host smart-fa60a51b-1e9c-49b7-856e-7cb7224cc180
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271092
8831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2710928831
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2800602607
Short name T145
Test name
Test status
Simulation time 160384206 ps
CPU time 2.01 seconds
Started Dec 24 01:09:31 PM PST 23
Finished Dec 24 01:09:39 PM PST 23
Peak memory 209428 kb
Host smart-bffda951-e5d4-44bc-b63f-d361c0db9daa
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800602607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.2800602607
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2442928884
Short name T221
Test name
Test status
Simulation time 37957204 ps
CPU time 1.18 seconds
Started Dec 24 01:09:32 PM PST 23
Finished Dec 24 01:09:39 PM PST 23
Peak memory 209540 kb
Host smart-c4e0f79d-a16c-4c3a-850e-4d9c054c00e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442928884 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.2442928884
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3717070506
Short name T284
Test name
Test status
Simulation time 122905956 ps
CPU time 1.08 seconds
Started Dec 24 01:09:34 PM PST 23
Finished Dec 24 01:09:42 PM PST 23
Peak memory 209488 kb
Host smart-7662fd37-e3ae-42ce-82c3-49464637750f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717070506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.3717070506
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.649842308
Short name T124
Test name
Test status
Simulation time 527016103 ps
CPU time 4.22 seconds
Started Dec 24 01:09:32 PM PST 23
Finished Dec 24 01:09:43 PM PST 23
Peak memory 217768 kb
Host smart-d9a15216-ffc4-4ecf-831c-baade7d3b4bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649842308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.649842308
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1106533260
Short name T298
Test name
Test status
Simulation time 25484256 ps
CPU time 1.24 seconds
Started Dec 24 01:09:31 PM PST 23
Finished Dec 24 01:09:37 PM PST 23
Peak memory 218980 kb
Host smart-8957fbb1-feb6-4d38-b21a-7fb4fd4a38de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106533260 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.1106533260
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.525355395
Short name T166
Test name
Test status
Simulation time 45416278 ps
CPU time 0.81 seconds
Started Dec 24 01:09:33 PM PST 23
Finished Dec 24 01:09:40 PM PST 23
Peak memory 209292 kb
Host smart-f6051442-db7f-4098-967a-f9fc6c417299
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525355395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.525355395
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2654098175
Short name T199
Test name
Test status
Simulation time 296212857 ps
CPU time 1.1 seconds
Started Dec 24 01:09:34 PM PST 23
Finished Dec 24 01:09:42 PM PST 23
Peak memory 209340 kb
Host smart-a41e3691-73a6-4759-b11b-2b6136a4ecfa
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654098175 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2654098175
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2285688317
Short name T223
Test name
Test status
Simulation time 2514751444 ps
CPU time 13.45 seconds
Started Dec 24 01:09:39 PM PST 23
Finished Dec 24 01:10:00 PM PST 23
Peak memory 209568 kb
Host smart-46c3dbf7-7528-4a05-ae60-34c2ca09ba1f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285688317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2285688317
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1483438946
Short name T141
Test name
Test status
Simulation time 810001342 ps
CPU time 17.72 seconds
Started Dec 24 01:09:43 PM PST 23
Finished Dec 24 01:10:07 PM PST 23
Peak memory 208488 kb
Host smart-f4f31463-747b-4f56-88ba-37bbd017deaa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483438946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.1483438946
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.960421641
Short name T204
Test name
Test status
Simulation time 137545842 ps
CPU time 1.51 seconds
Started Dec 24 01:09:39 PM PST 23
Finished Dec 24 01:09:48 PM PST 23
Peak memory 210624 kb
Host smart-424a7a3a-07bf-44b3-a338-e98142e80497
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960421641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.960421641
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3670786445
Short name T189
Test name
Test status
Simulation time 75205553 ps
CPU time 1.37 seconds
Started Dec 24 01:09:34 PM PST 23
Finished Dec 24 01:09:42 PM PST 23
Peak memory 219400 kb
Host smart-8227af3f-a106-49e3-a14a-5ef29009e2e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367078
6445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3670786445
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1097547834
Short name T201
Test name
Test status
Simulation time 626147124 ps
CPU time 1.41 seconds
Started Dec 24 01:09:38 PM PST 23
Finished Dec 24 01:09:46 PM PST 23
Peak memory 209356 kb
Host smart-3d833480-d1c1-4911-8761-e859d81ecd80
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097547834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.1097547834
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1654396307
Short name T248
Test name
Test status
Simulation time 19358383 ps
CPU time 1.03 seconds
Started Dec 24 01:09:34 PM PST 23
Finished Dec 24 01:09:42 PM PST 23
Peak memory 208772 kb
Host smart-f4b56030-7776-4d3e-8bfb-791726fdef4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654396307 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.1654396307
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2580769983
Short name T151
Test name
Test status
Simulation time 71947835 ps
CPU time 1.35 seconds
Started Dec 24 01:09:36 PM PST 23
Finished Dec 24 01:09:45 PM PST 23
Peak memory 211308 kb
Host smart-dc3bdad6-417e-496b-9a08-a3fb2601d052
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580769983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.2580769983
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.307581839
Short name T209
Test name
Test status
Simulation time 141861035 ps
CPU time 3.2 seconds
Started Dec 24 01:09:32 PM PST 23
Finished Dec 24 01:09:41 PM PST 23
Peak memory 217652 kb
Host smart-029c6fcd-1f00-4129-914d-d57f716db954
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307581839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.307581839
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.1911596103
Short name T458
Test name
Test status
Simulation time 19237384 ps
CPU time 0.88 seconds
Started Dec 24 01:05:45 PM PST 23
Finished Dec 24 01:05:54 PM PST 23
Peak memory 209696 kb
Host smart-e2d340ed-259a-4d7e-a9d9-136f9d66e6ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911596103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.1911596103
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.3974330605
Short name T26
Test name
Test status
Simulation time 498788478 ps
CPU time 12.18 seconds
Started Dec 24 01:05:46 PM PST 23
Finished Dec 24 01:06:08 PM PST 23
Peak memory 209700 kb
Host smart-f7163003-18a9-4cba-8ca8-9a2ac0975486
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974330605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_ac
cess.3974330605
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.357906932
Short name T909
Test name
Test status
Simulation time 1705881992 ps
CPU time 30.3 seconds
Started Dec 24 01:05:49 PM PST 23
Finished Dec 24 01:06:29 PM PST 23
Peak memory 218140 kb
Host smart-08333aab-b1c4-4cef-8122-47efa64d808a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357906932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_err
ors.357906932
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.2697632297
Short name T861
Test name
Test status
Simulation time 498396617 ps
CPU time 6.26 seconds
Started Dec 24 01:05:51 PM PST 23
Finished Dec 24 01:06:05 PM PST 23
Peak memory 217952 kb
Host smart-9a5bab84-c205-43b1-988d-d11b5681d8a5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697632297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
priority.2697632297
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.2604934499
Short name T341
Test name
Test status
Simulation time 2385899968 ps
CPU time 17.68 seconds
Started Dec 24 01:05:59 PM PST 23
Finished Dec 24 01:06:20 PM PST 23
Peak memory 218172 kb
Host smart-de0a8fa8-b4ba-455f-87cb-b5ef24e8c793
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604934499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.2604934499
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.151156014
Short name T640
Test name
Test status
Simulation time 2455599924 ps
CPU time 19.08 seconds
Started Dec 24 01:05:48 PM PST 23
Finished Dec 24 01:06:16 PM PST 23
Peak memory 213228 kb
Host smart-d0d7c833-35af-42dc-9044-a4e066bc8743
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151156014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_regwen_during_op.151156014
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.2305513592
Short name T977
Test name
Test status
Simulation time 1544593891 ps
CPU time 3.66 seconds
Started Dec 24 01:05:56 PM PST 23
Finished Dec 24 01:06:06 PM PST 23
Peak memory 213104 kb
Host smart-6be2dd3a-2ad1-45f3-a755-b9291b628993
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305513592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
2305513592
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.4167549105
Short name T518
Test name
Test status
Simulation time 27611904385 ps
CPU time 61.63 seconds
Started Dec 24 01:05:41 PM PST 23
Finished Dec 24 01:06:52 PM PST 23
Peak memory 275628 kb
Host smart-d831db26-15ae-4bbd-9223-fc60c23a7b07
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167549105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.4167549105
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.2716633496
Short name T687
Test name
Test status
Simulation time 268764895 ps
CPU time 13.46 seconds
Started Dec 24 01:05:51 PM PST 23
Finished Dec 24 01:06:13 PM PST 23
Peak memory 246412 kb
Host smart-c7512919-6d5a-4a81-992d-da4df28cec41
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716633496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.2716633496
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.574768591
Short name T711
Test name
Test status
Simulation time 76041234 ps
CPU time 1.43 seconds
Started Dec 24 01:05:55 PM PST 23
Finished Dec 24 01:06:03 PM PST 23
Peak memory 218132 kb
Host smart-c62c8775-0d74-47fc-94f9-6ec2d81c976b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574768591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.574768591
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.3938467580
Short name T455
Test name
Test status
Simulation time 1018347433 ps
CPU time 21.13 seconds
Started Dec 24 01:05:47 PM PST 23
Finished Dec 24 01:06:17 PM PST 23
Peak memory 214244 kb
Host smart-a4de48e4-c578-441c-9be9-1fff06c28e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938467580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.3938467580
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.4019124424
Short name T96
Test name
Test status
Simulation time 532720913 ps
CPU time 24.03 seconds
Started Dec 24 01:05:47 PM PST 23
Finished Dec 24 01:06:20 PM PST 23
Peak memory 282164 kb
Host smart-4f8e04fb-089a-4da5-82de-8237490cf912
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019124424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.4019124424
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.2236501067
Short name T809
Test name
Test status
Simulation time 2822706555 ps
CPU time 14.78 seconds
Started Dec 24 01:05:52 PM PST 23
Finished Dec 24 01:06:15 PM PST 23
Peak memory 219192 kb
Host smart-3f6fee75-12f9-4493-98ff-79c42e4da6d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236501067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.2236501067
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.1689299776
Short name T954
Test name
Test status
Simulation time 795475576 ps
CPU time 15.9 seconds
Started Dec 24 01:05:49 PM PST 23
Finished Dec 24 01:06:13 PM PST 23
Peak memory 218092 kb
Host smart-3b3e5e48-4b8b-49fe-b3b7-a3b0ed808e39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689299776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.1689299776
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.1587884438
Short name T368
Test name
Test status
Simulation time 288756364 ps
CPU time 12.48 seconds
Started Dec 24 01:05:57 PM PST 23
Finished Dec 24 01:06:15 PM PST 23
Peak memory 218108 kb
Host smart-5c7279c1-5626-41df-8b2e-6582f94d56d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587884438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.1
587884438
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.458241378
Short name T54
Test name
Test status
Simulation time 865006533 ps
CPU time 7.72 seconds
Started Dec 24 01:05:45 PM PST 23
Finished Dec 24 01:06:01 PM PST 23
Peak memory 218164 kb
Host smart-20b1c0cf-79c8-4040-b393-65b9f0249e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458241378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.458241378
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.2196059824
Short name T552
Test name
Test status
Simulation time 124431616 ps
CPU time 1.85 seconds
Started Dec 24 01:05:47 PM PST 23
Finished Dec 24 01:05:58 PM PST 23
Peak memory 213596 kb
Host smart-3a587587-633a-42cf-9acc-92a8e36e2c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196059824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.2196059824
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.2808349083
Short name T522
Test name
Test status
Simulation time 210503434 ps
CPU time 25.86 seconds
Started Dec 24 01:05:47 PM PST 23
Finished Dec 24 01:06:22 PM PST 23
Peak memory 251188 kb
Host smart-8c971af6-5eef-4f89-a398-f70be84d95bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808349083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.2808349083
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.4015193110
Short name T736
Test name
Test status
Simulation time 343038535 ps
CPU time 4.31 seconds
Started Dec 24 01:05:53 PM PST 23
Finished Dec 24 01:06:05 PM PST 23
Peak memory 222268 kb
Host smart-e38957f8-c6ca-4663-9a33-b77bd536f717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015193110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.4015193110
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.623030641
Short name T462
Test name
Test status
Simulation time 3400070644 ps
CPU time 89.74 seconds
Started Dec 24 01:05:55 PM PST 23
Finished Dec 24 01:07:31 PM PST 23
Peak memory 226868 kb
Host smart-9a8c1d06-cacb-4a5b-b6c2-be5603ac5040
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623030641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.623030641
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2026581253
Short name T765
Test name
Test status
Simulation time 16080924 ps
CPU time 1.03 seconds
Started Dec 24 01:05:47 PM PST 23
Finished Dec 24 01:05:57 PM PST 23
Peak memory 211464 kb
Host smart-35754b53-dc7e-41ef-90f0-7dce1139e62f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026581253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.2026581253
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.3723810969
Short name T890
Test name
Test status
Simulation time 21825733 ps
CPU time 0.99 seconds
Started Dec 24 01:05:44 PM PST 23
Finished Dec 24 01:05:54 PM PST 23
Peak memory 209796 kb
Host smart-5e3490ab-4b96-41fa-8930-5dfebc519f26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723810969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.3723810969
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.789884923
Short name T591
Test name
Test status
Simulation time 10852775 ps
CPU time 0.79 seconds
Started Dec 24 01:05:55 PM PST 23
Finished Dec 24 01:06:02 PM PST 23
Peak memory 209444 kb
Host smart-4aac6714-62c0-4bfb-bab7-5798b033b93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789884923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.789884923
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.3820576813
Short name T626
Test name
Test status
Simulation time 907349264 ps
CPU time 23.23 seconds
Started Dec 24 01:05:45 PM PST 23
Finished Dec 24 01:06:17 PM PST 23
Peak memory 218204 kb
Host smart-d681bfe8-a156-4da8-9273-1c46c59eed00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820576813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.3820576813
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.860369911
Short name T574
Test name
Test status
Simulation time 469581472 ps
CPU time 7.92 seconds
Started Dec 24 01:05:51 PM PST 23
Finished Dec 24 01:06:07 PM PST 23
Peak memory 209700 kb
Host smart-00c037d2-1452-4776-b679-603ab2d0cb0d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860369911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_acc
ess.860369911
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.3353284811
Short name T435
Test name
Test status
Simulation time 8259074129 ps
CPU time 60.82 seconds
Started Dec 24 01:05:56 PM PST 23
Finished Dec 24 01:07:02 PM PST 23
Peak memory 218332 kb
Host smart-7720aa20-24bb-40f4-aae7-53810facde82
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353284811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.3353284811
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.589532790
Short name T527
Test name
Test status
Simulation time 729750812 ps
CPU time 9.23 seconds
Started Dec 24 01:05:49 PM PST 23
Finished Dec 24 01:06:08 PM PST 23
Peak memory 217848 kb
Host smart-41e91a30-d47f-4332-bec5-51f651808024
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589532790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_p
riority.589532790
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.2956590117
Short name T302
Test name
Test status
Simulation time 518446860 ps
CPU time 14.33 seconds
Started Dec 24 01:05:54 PM PST 23
Finished Dec 24 01:06:15 PM PST 23
Peak memory 218156 kb
Host smart-ab244904-e0fe-42bc-9150-e86fcfec182a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956590117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.2956590117
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.4136695262
Short name T773
Test name
Test status
Simulation time 1893773109 ps
CPU time 14.34 seconds
Started Dec 24 01:05:49 PM PST 23
Finished Dec 24 01:06:13 PM PST 23
Peak memory 213048 kb
Host smart-392b94dc-0546-4cb0-8625-39250618b54e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136695262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.4136695262
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.572945628
Short name T15
Test name
Test status
Simulation time 381682493 ps
CPU time 6.31 seconds
Started Dec 24 01:05:53 PM PST 23
Finished Dec 24 01:06:07 PM PST 23
Peak memory 212908 kb
Host smart-2b43b8a3-1392-48f6-9555-0391084467f2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572945628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.572945628
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3301693526
Short name T401
Test name
Test status
Simulation time 5625226785 ps
CPU time 34.11 seconds
Started Dec 24 01:05:51 PM PST 23
Finished Dec 24 01:06:33 PM PST 23
Peak memory 251176 kb
Host smart-a5a0e57f-af65-421c-b856-fa9172f31e09
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301693526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.3301693526
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1385730024
Short name T725
Test name
Test status
Simulation time 1520906568 ps
CPU time 9.97 seconds
Started Dec 24 01:05:45 PM PST 23
Finished Dec 24 01:06:04 PM PST 23
Peak memory 250188 kb
Host smart-24faab64-7abc-4ce6-8502-3a089fe8d844
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385730024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1385730024
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.2043341041
Short name T374
Test name
Test status
Simulation time 117178070 ps
CPU time 2.18 seconds
Started Dec 24 01:05:56 PM PST 23
Finished Dec 24 01:06:04 PM PST 23
Peak memory 217944 kb
Host smart-6dddffba-ddad-40af-ac18-60a40a2e9825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043341041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.2043341041
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.377314872
Short name T960
Test name
Test status
Simulation time 1198835613 ps
CPU time 17.21 seconds
Started Dec 24 01:05:55 PM PST 23
Finished Dec 24 01:06:19 PM PST 23
Peak memory 214124 kb
Host smart-338f82bb-caaf-4059-8a81-9aa9655c485d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377314872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.377314872
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.4043995898
Short name T97
Test name
Test status
Simulation time 710847024 ps
CPU time 22.24 seconds
Started Dec 24 01:05:54 PM PST 23
Finished Dec 24 01:06:23 PM PST 23
Peak memory 281052 kb
Host smart-f0edb192-6116-44d9-9d2b-598701d9176b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043995898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.4043995898
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.3743707571
Short name T538
Test name
Test status
Simulation time 211601147 ps
CPU time 11.44 seconds
Started Dec 24 01:05:49 PM PST 23
Finished Dec 24 01:06:10 PM PST 23
Peak memory 218212 kb
Host smart-3f27cd61-4ba4-477d-afef-0b7fb2df31d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743707571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.3743707571
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.4114944104
Short name T304
Test name
Test status
Simulation time 828363912 ps
CPU time 11.19 seconds
Started Dec 24 01:05:47 PM PST 23
Finished Dec 24 01:06:08 PM PST 23
Peak memory 218076 kb
Host smart-b2f7900d-eafb-4c69-aca9-3d875e1a43f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114944104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.4114944104
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.4224394923
Short name T758
Test name
Test status
Simulation time 963312475 ps
CPU time 10.29 seconds
Started Dec 24 01:05:56 PM PST 23
Finished Dec 24 01:06:12 PM PST 23
Peak memory 218148 kb
Host smart-95158020-0c2b-4ac9-b65a-b4a280e7dc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224394923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.4224394923
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.3838939247
Short name T105
Test name
Test status
Simulation time 844969193 ps
CPU time 7.11 seconds
Started Dec 24 01:05:51 PM PST 23
Finished Dec 24 01:06:07 PM PST 23
Peak memory 213936 kb
Host smart-079b0f87-3dbf-4722-be62-c115b8b86116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838939247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.3838939247
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.1570697246
Short name T824
Test name
Test status
Simulation time 156164228 ps
CPU time 23.78 seconds
Started Dec 24 01:05:46 PM PST 23
Finished Dec 24 01:06:19 PM PST 23
Peak memory 251088 kb
Host smart-2c967dfc-b8f5-4fa4-9306-1ec02b9bed93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570697246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.1570697246
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.3868350970
Short name T333
Test name
Test status
Simulation time 241974197 ps
CPU time 2.64 seconds
Started Dec 24 01:05:57 PM PST 23
Finished Dec 24 01:06:05 PM PST 23
Peak memory 218216 kb
Host smart-b0f9ffe1-f4b6-4099-9062-c016611794e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868350970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.3868350970
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.3306108637
Short name T497
Test name
Test status
Simulation time 9196779447 ps
CPU time 320.28 seconds
Started Dec 24 01:05:57 PM PST 23
Finished Dec 24 01:11:22 PM PST 23
Peak memory 276360 kb
Host smart-c02fedbd-9cbd-4ab7-a576-9935d016f127
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306108637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.3306108637
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.2924835324
Short name T603
Test name
Test status
Simulation time 15502258 ps
CPU time 0.88 seconds
Started Dec 24 01:07:16 PM PST 23
Finished Dec 24 01:07:22 PM PST 23
Peak memory 209660 kb
Host smart-50200632-cfeb-46be-830f-39837cb351e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924835324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.2924835324
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.953176824
Short name T408
Test name
Test status
Simulation time 319438485 ps
CPU time 11.34 seconds
Started Dec 24 01:07:24 PM PST 23
Finished Dec 24 01:07:39 PM PST 23
Peak memory 218212 kb
Host smart-1037e8ab-1473-4a57-b476-ca18ed3b9bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953176824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.953176824
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.1099712055
Short name T571
Test name
Test status
Simulation time 2555979894 ps
CPU time 4.85 seconds
Started Dec 24 01:07:25 PM PST 23
Finished Dec 24 01:07:33 PM PST 23
Peak memory 209684 kb
Host smart-cec0fdfe-7dfe-4769-baeb-82d41b6829cd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099712055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_a
ccess.1099712055
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.354055138
Short name T644
Test name
Test status
Simulation time 4924847390 ps
CPU time 130.79 seconds
Started Dec 24 01:07:22 PM PST 23
Finished Dec 24 01:09:37 PM PST 23
Peak memory 220452 kb
Host smart-2c7133e0-0e7a-4d12-8194-09d3709f39fe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354055138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_er
rors.354055138
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.837073282
Short name T937
Test name
Test status
Simulation time 514855102 ps
CPU time 13.89 seconds
Started Dec 24 01:07:22 PM PST 23
Finished Dec 24 01:07:40 PM PST 23
Peak memory 218036 kb
Host smart-56f1b270-218b-4b7d-bfbd-4d992d4fa6c4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837073282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag
_prog_failure.837073282
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.3124406482
Short name T80
Test name
Test status
Simulation time 211349859 ps
CPU time 3.48 seconds
Started Dec 24 01:07:21 PM PST 23
Finished Dec 24 01:07:28 PM PST 23
Peak memory 213124 kb
Host smart-786a3ce5-e1d0-4ab7-bda3-885f78e2aa20
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124406482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.3124406482
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.1046531439
Short name T506
Test name
Test status
Simulation time 1675160615 ps
CPU time 66.48 seconds
Started Dec 24 01:07:20 PM PST 23
Finished Dec 24 01:08:31 PM PST 23
Peak memory 251340 kb
Host smart-1267554e-938c-4b7b-8bda-22a9b6512142
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046531439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.1046531439
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.1557657249
Short name T614
Test name
Test status
Simulation time 2578217044 ps
CPU time 24.91 seconds
Started Dec 24 01:07:10 PM PST 23
Finished Dec 24 01:07:42 PM PST 23
Peak memory 251216 kb
Host smart-875c6e48-f993-467f-9471-88b68d14fff6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557657249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.1557657249
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.1252522610
Short name T480
Test name
Test status
Simulation time 234664144 ps
CPU time 3.48 seconds
Started Dec 24 01:07:22 PM PST 23
Finished Dec 24 01:07:29 PM PST 23
Peak memory 218208 kb
Host smart-52ac4970-e163-4565-b608-3e2cb02fdcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252522610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.1252522610
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.3848860629
Short name T849
Test name
Test status
Simulation time 6693489070 ps
CPU time 15.69 seconds
Started Dec 24 01:07:06 PM PST 23
Finished Dec 24 01:07:25 PM PST 23
Peak memory 220360 kb
Host smart-f9f8a289-bc52-4ddb-96de-72c3776f7447
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848860629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.3848860629
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.2961712189
Short name T863
Test name
Test status
Simulation time 1024960390 ps
CPU time 10.86 seconds
Started Dec 24 01:07:23 PM PST 23
Finished Dec 24 01:07:38 PM PST 23
Peak memory 218040 kb
Host smart-3ad44982-a754-456f-87ab-44526c289d47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961712189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.2961712189
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1050091170
Short name T531
Test name
Test status
Simulation time 845629000 ps
CPU time 10.21 seconds
Started Dec 24 01:07:09 PM PST 23
Finished Dec 24 01:07:26 PM PST 23
Peak memory 218128 kb
Host smart-d4a7b939-c1a9-45c2-bdba-f53c45f07e3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050091170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
1050091170
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.1858868233
Short name T696
Test name
Test status
Simulation time 1046415381 ps
CPU time 8.31 seconds
Started Dec 24 01:07:20 PM PST 23
Finished Dec 24 01:07:32 PM PST 23
Peak memory 218200 kb
Host smart-f889940d-b2c5-4751-8c90-c46b0a95746a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858868233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1858868233
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3917492431
Short name T451
Test name
Test status
Simulation time 38209499 ps
CPU time 3.01 seconds
Started Dec 24 01:07:22 PM PST 23
Finished Dec 24 01:07:28 PM PST 23
Peak memory 214180 kb
Host smart-45d1a237-b2c8-40f6-9470-2c41719190b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917492431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3917492431
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.4130523144
Short name T907
Test name
Test status
Simulation time 1758119471 ps
CPU time 35.26 seconds
Started Dec 24 01:07:15 PM PST 23
Finished Dec 24 01:07:56 PM PST 23
Peak memory 251076 kb
Host smart-00985605-1ac1-411d-901f-8541b5d9d6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130523144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.4130523144
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.1180485749
Short name T870
Test name
Test status
Simulation time 435272590 ps
CPU time 7.53 seconds
Started Dec 24 01:07:26 PM PST 23
Finished Dec 24 01:07:37 PM PST 23
Peak memory 251208 kb
Host smart-c3373510-5b10-4651-9bab-6d095297fb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180485749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.1180485749
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.3122298881
Short name T18
Test name
Test status
Simulation time 24819486250 ps
CPU time 63.88 seconds
Started Dec 24 01:07:09 PM PST 23
Finished Dec 24 01:08:20 PM PST 23
Peak memory 227544 kb
Host smart-d65c8433-d257-43ec-baea-33a4b81d91eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122298881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.3122298881
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.1441792614
Short name T378
Test name
Test status
Simulation time 12704926 ps
CPU time 0.78 seconds
Started Dec 24 01:07:24 PM PST 23
Finished Dec 24 01:07:28 PM PST 23
Peak memory 208108 kb
Host smart-5739f7d0-3471-41c2-99c5-9950da2dba26
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441792614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.1441792614
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.2589105010
Short name T445
Test name
Test status
Simulation time 33145815 ps
CPU time 1.03 seconds
Started Dec 24 01:07:04 PM PST 23
Finished Dec 24 01:07:09 PM PST 23
Peak memory 209708 kb
Host smart-5ac94c7c-f726-4ba7-a97c-59266347b8c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589105010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.2589105010
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.74223584
Short name T844
Test name
Test status
Simulation time 225958981 ps
CPU time 11.57 seconds
Started Dec 24 01:06:50 PM PST 23
Finished Dec 24 01:07:06 PM PST 23
Peak memory 218192 kb
Host smart-61b2f156-0ab8-4640-96c7-99458358a8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74223584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.74223584
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.4293810424
Short name T490
Test name
Test status
Simulation time 354955224 ps
CPU time 4.61 seconds
Started Dec 24 01:07:09 PM PST 23
Finished Dec 24 01:07:20 PM PST 23
Peak memory 209568 kb
Host smart-29b26d8e-6978-427b-94a4-4304d67057c8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293810424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_a
ccess.4293810424
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2432572535
Short name T430
Test name
Test status
Simulation time 5468433251 ps
CPU time 143.09 seconds
Started Dec 24 01:07:06 PM PST 23
Finished Dec 24 01:09:33 PM PST 23
Peak memory 220252 kb
Host smart-26ee16ea-e891-48d7-ab20-0b047b329f21
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432572535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2432572535
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.2797063545
Short name T925
Test name
Test status
Simulation time 302303384 ps
CPU time 9.74 seconds
Started Dec 24 01:06:51 PM PST 23
Finished Dec 24 01:07:06 PM PST 23
Peak memory 217072 kb
Host smart-39244fef-463a-4e27-bae5-2d24a4ff03dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797063545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.2797063545
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.666690608
Short name T81
Test name
Test status
Simulation time 449831374 ps
CPU time 7.05 seconds
Started Dec 24 01:07:08 PM PST 23
Finished Dec 24 01:07:20 PM PST 23
Peak memory 213636 kb
Host smart-c5982610-c8cc-464c-9c5d-219a8430a710
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666690608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke.
666690608
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.427506115
Short name T384
Test name
Test status
Simulation time 1763470582 ps
CPU time 37.89 seconds
Started Dec 24 01:07:05 PM PST 23
Finished Dec 24 01:07:46 PM PST 23
Peak memory 250996 kb
Host smart-b301da9b-83e4-499f-a49e-91e579a29525
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427506115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_state_failure.427506115
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.882269542
Short name T884
Test name
Test status
Simulation time 1005766312 ps
CPU time 14.95 seconds
Started Dec 24 01:07:05 PM PST 23
Finished Dec 24 01:07:23 PM PST 23
Peak memory 223780 kb
Host smart-b92fae30-6bf2-4151-bf26-2bf932f631c6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882269542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_
jtag_state_post_trans.882269542
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.280356125
Short name T734
Test name
Test status
Simulation time 96718800 ps
CPU time 2.3 seconds
Started Dec 24 01:06:51 PM PST 23
Finished Dec 24 01:06:59 PM PST 23
Peak memory 218200 kb
Host smart-89166ac7-237e-48fc-86fa-fd0b157b4d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280356125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.280356125
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.109212453
Short name T511
Test name
Test status
Simulation time 427137114 ps
CPU time 11.93 seconds
Started Dec 24 01:07:06 PM PST 23
Finished Dec 24 01:07:21 PM PST 23
Peak memory 218208 kb
Host smart-2ed8364c-05d7-4123-9e44-120e8a771afb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109212453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.109212453
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.850182382
Short name T556
Test name
Test status
Simulation time 568354563 ps
CPU time 20.54 seconds
Started Dec 24 01:06:51 PM PST 23
Finished Dec 24 01:07:16 PM PST 23
Peak memory 217044 kb
Host smart-6b95fa6c-2bec-4d5a-9cb2-6c2e160302fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850182382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_di
gest.850182382
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.2971565830
Short name T424
Test name
Test status
Simulation time 1747178703 ps
CPU time 16.02 seconds
Started Dec 24 01:06:57 PM PST 23
Finished Dec 24 01:07:17 PM PST 23
Peak memory 218160 kb
Host smart-5c0ef85e-1f39-48f0-b481-71de3fcbc460
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971565830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
2971565830
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.2730114014
Short name T752
Test name
Test status
Simulation time 170132580 ps
CPU time 7.43 seconds
Started Dec 24 01:07:03 PM PST 23
Finished Dec 24 01:07:13 PM PST 23
Peak memory 218120 kb
Host smart-79cdd333-d3b9-4568-9ff8-34e2aebd71bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730114014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.2730114014
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.2944830290
Short name T494
Test name
Test status
Simulation time 517613708 ps
CPU time 2.27 seconds
Started Dec 24 01:07:23 PM PST 23
Finished Dec 24 01:07:29 PM PST 23
Peak memory 213960 kb
Host smart-5a439a0c-7030-49ce-b112-0d8cbb790ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944830290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.2944830290
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.4028074772
Short name T9
Test name
Test status
Simulation time 216770298 ps
CPU time 20.97 seconds
Started Dec 24 01:06:33 PM PST 23
Finished Dec 24 01:06:55 PM PST 23
Peak memory 250376 kb
Host smart-9149ff08-1b2a-450d-b188-ed69df6e62fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028074772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.4028074772
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.3073965160
Short name T846
Test name
Test status
Simulation time 91269764 ps
CPU time 9.13 seconds
Started Dec 24 01:06:56 PM PST 23
Finished Dec 24 01:07:10 PM PST 23
Peak memory 251148 kb
Host smart-859c7084-44bd-4769-89a2-861aac2aa20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073965160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.3073965160
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.1273103821
Short name T335
Test name
Test status
Simulation time 10576005045 ps
CPU time 131.99 seconds
Started Dec 24 01:07:09 PM PST 23
Finished Dec 24 01:09:28 PM PST 23
Peak memory 251948 kb
Host smart-f6b122fe-8afd-4278-a47c-e120a9e80018
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273103821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.1273103821
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.4195406789
Short name T420
Test name
Test status
Simulation time 44688284 ps
CPU time 0.81 seconds
Started Dec 24 01:07:09 PM PST 23
Finished Dec 24 01:07:17 PM PST 23
Peak memory 208304 kb
Host smart-cf04d1cb-4e87-40b2-a6aa-a937723a534a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195406789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.4195406789
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.1573204365
Short name T492
Test name
Test status
Simulation time 29010086 ps
CPU time 1.4 seconds
Started Dec 24 01:06:51 PM PST 23
Finished Dec 24 01:06:57 PM PST 23
Peak memory 209784 kb
Host smart-3310f9c3-ae15-4857-b490-6d155603e2bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573204365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.1573204365
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.3806864475
Short name T456
Test name
Test status
Simulation time 264734907 ps
CPU time 12.51 seconds
Started Dec 24 01:06:48 PM PST 23
Finished Dec 24 01:07:04 PM PST 23
Peak memory 218244 kb
Host smart-040023ed-bfc4-4308-a31c-7e0a66329966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806864475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.3806864475
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.1361274109
Short name T635
Test name
Test status
Simulation time 179563207 ps
CPU time 2.59 seconds
Started Dec 24 01:06:48 PM PST 23
Finished Dec 24 01:06:54 PM PST 23
Peak memory 209704 kb
Host smart-c2698ee9-ea86-483e-a542-6614518e9928
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361274109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_a
ccess.1361274109
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.1564720306
Short name T782
Test name
Test status
Simulation time 6378923347 ps
CPU time 45.75 seconds
Started Dec 24 01:06:46 PM PST 23
Finished Dec 24 01:07:34 PM PST 23
Peak memory 218692 kb
Host smart-d217b8d9-0f97-4548-9b32-f81d76da42e8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564720306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.1564720306
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.858814478
Short name T831
Test name
Test status
Simulation time 983750890 ps
CPU time 8.61 seconds
Started Dec 24 01:07:05 PM PST 23
Finished Dec 24 01:07:17 PM PST 23
Peak memory 218348 kb
Host smart-cad44eb8-bb9a-4cf8-8bb0-856044fb6323
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858814478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag
_prog_failure.858814478
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2412672438
Short name T943
Test name
Test status
Simulation time 1566280093 ps
CPU time 8.3 seconds
Started Dec 24 01:07:04 PM PST 23
Finished Dec 24 01:07:15 PM PST 23
Peak memory 213432 kb
Host smart-fba5dfc4-eb8e-4a96-96b5-54a08d2a5dc7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412672438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.2412672438
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.2694139118
Short name T426
Test name
Test status
Simulation time 1964272115 ps
CPU time 40.04 seconds
Started Dec 24 01:06:51 PM PST 23
Finished Dec 24 01:07:40 PM PST 23
Peak memory 251136 kb
Host smart-8d7db951-3645-4b4c-890a-1f462ff5949f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694139118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.2694139118
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.1271006128
Short name T713
Test name
Test status
Simulation time 362570343 ps
CPU time 12.04 seconds
Started Dec 24 01:07:04 PM PST 23
Finished Dec 24 01:07:19 PM PST 23
Peak memory 223680 kb
Host smart-a21ba985-72b0-4d8e-bece-30fe7ae0e63d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271006128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.1271006128
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.1184553731
Short name T751
Test name
Test status
Simulation time 145884916 ps
CPU time 3.26 seconds
Started Dec 24 01:06:52 PM PST 23
Finished Dec 24 01:07:00 PM PST 23
Peak memory 218208 kb
Host smart-490e4619-83b5-4216-be9d-66fb77703c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184553731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.1184553731
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.2888852168
Short name T406
Test name
Test status
Simulation time 332916903 ps
CPU time 13.16 seconds
Started Dec 24 01:06:49 PM PST 23
Finished Dec 24 01:07:06 PM PST 23
Peak memory 218252 kb
Host smart-bb83a3ea-8fd3-41e0-8db5-eb4dc0a07ce3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888852168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.2888852168
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.1440876083
Short name T520
Test name
Test status
Simulation time 1342459904 ps
CPU time 14.16 seconds
Started Dec 24 01:06:51 PM PST 23
Finished Dec 24 01:07:09 PM PST 23
Peak memory 218096 kb
Host smart-1eb24e30-6db3-4027-aa36-bc42d39bace5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440876083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.1440876083
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.561085185
Short name T308
Test name
Test status
Simulation time 1102150392 ps
CPU time 8.35 seconds
Started Dec 24 01:07:04 PM PST 23
Finished Dec 24 01:07:15 PM PST 23
Peak memory 218112 kb
Host smart-d3f6f6a9-1684-4908-b09d-8bee554def81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561085185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.561085185
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.463761529
Short name T336
Test name
Test status
Simulation time 29573062 ps
CPU time 1.3 seconds
Started Dec 24 01:06:52 PM PST 23
Finished Dec 24 01:06:58 PM PST 23
Peak memory 213036 kb
Host smart-8b54d09b-8e8a-4acd-aa5f-e7f6c6cb8641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463761529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.463761529
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.470024969
Short name T312
Test name
Test status
Simulation time 213244645 ps
CPU time 24.58 seconds
Started Dec 24 01:07:09 PM PST 23
Finished Dec 24 01:07:40 PM PST 23
Peak memory 251004 kb
Host smart-47ab0091-0063-4e95-8e78-d620c4c493a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470024969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.470024969
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.2481215816
Short name T383
Test name
Test status
Simulation time 183293921 ps
CPU time 6.08 seconds
Started Dec 24 01:06:49 PM PST 23
Finished Dec 24 01:06:59 PM PST 23
Peak memory 246824 kb
Host smart-c2d64f91-d253-4c12-b40f-3ed0da2302a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481215816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.2481215816
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.613595723
Short name T324
Test name
Test status
Simulation time 2871911148 ps
CPU time 20.38 seconds
Started Dec 24 01:07:07 PM PST 23
Finished Dec 24 01:07:32 PM PST 23
Peak memory 250844 kb
Host smart-e5f6245e-11b0-4adf-915a-c91807619ce0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613595723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.613595723
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.2983283514
Short name T957
Test name
Test status
Simulation time 12540093 ps
CPU time 0.93 seconds
Started Dec 24 01:07:09 PM PST 23
Finished Dec 24 01:07:17 PM PST 23
Peak memory 207696 kb
Host smart-6eb960d1-b4a0-4da5-973c-2f13544be4a7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983283514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.2983283514
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.1620955218
Short name T694
Test name
Test status
Simulation time 1104362600 ps
CPU time 10.82 seconds
Started Dec 24 01:07:06 PM PST 23
Finished Dec 24 01:07:21 PM PST 23
Peak memory 218156 kb
Host smart-b1780a7d-0c90-4bcb-b2c8-22bf2fc96715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620955218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1620955218
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.3069792824
Short name T23
Test name
Test status
Simulation time 476623523 ps
CPU time 11.89 seconds
Started Dec 24 01:07:15 PM PST 23
Finished Dec 24 01:07:33 PM PST 23
Peak memory 209608 kb
Host smart-a0895b50-cf82-4286-8538-56a9ac24ac74
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069792824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_a
ccess.3069792824
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.1414888889
Short name T832
Test name
Test status
Simulation time 5779294910 ps
CPU time 38.82 seconds
Started Dec 24 01:07:17 PM PST 23
Finished Dec 24 01:08:00 PM PST 23
Peak memory 218464 kb
Host smart-d934b71e-6002-4950-a4fa-d5f205c5df2e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414888889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.1414888889
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2488907904
Short name T536
Test name
Test status
Simulation time 2717531640 ps
CPU time 8.63 seconds
Started Dec 24 01:07:10 PM PST 23
Finished Dec 24 01:07:26 PM PST 23
Peak memory 218184 kb
Host smart-6e27849c-5aee-4c1b-923a-2c1a9304a5a4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488907904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2488907904
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.80093290
Short name T562
Test name
Test status
Simulation time 558890435 ps
CPU time 2.65 seconds
Started Dec 24 01:07:26 PM PST 23
Finished Dec 24 01:07:32 PM PST 23
Peak memory 212904 kb
Host smart-c5761bbb-3034-45b1-a04b-4d92c3abd9c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80093290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke.80093290
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.1439580764
Short name T87
Test name
Test status
Simulation time 1673541134 ps
CPU time 57.25 seconds
Started Dec 24 01:07:11 PM PST 23
Finished Dec 24 01:08:15 PM PST 23
Peak memory 267488 kb
Host smart-2f9078ec-8123-4ec1-ac68-c30eebaaaec9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439580764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.1439580764
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.1227184835
Short name T913
Test name
Test status
Simulation time 381784142 ps
CPU time 15.22 seconds
Started Dec 24 01:07:15 PM PST 23
Finished Dec 24 01:07:36 PM PST 23
Peak memory 246116 kb
Host smart-740844c1-45af-46cd-8712-17f1a0eb4914
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227184835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.1227184835
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.1444043218
Short name T889
Test name
Test status
Simulation time 31031040 ps
CPU time 1.68 seconds
Started Dec 24 01:07:19 PM PST 23
Finished Dec 24 01:07:25 PM PST 23
Peak memory 218160 kb
Host smart-b5b2bbea-00b2-40d5-945b-14aee38a286c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444043218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.1444043218
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.2552520348
Short name T921
Test name
Test status
Simulation time 1339668705 ps
CPU time 13.15 seconds
Started Dec 24 01:07:10 PM PST 23
Finished Dec 24 01:07:30 PM PST 23
Peak memory 218240 kb
Host smart-3271e080-7066-404b-a201-8202941e13b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552520348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.2552520348
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.2279246052
Short name T344
Test name
Test status
Simulation time 2489735089 ps
CPU time 10.07 seconds
Started Dec 24 01:07:09 PM PST 23
Finished Dec 24 01:07:26 PM PST 23
Peak memory 218220 kb
Host smart-e80af334-42e1-4bbc-a7b0-956fe726200d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279246052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.2279246052
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1326919918
Short name T616
Test name
Test status
Simulation time 294228031 ps
CPU time 10.45 seconds
Started Dec 24 01:07:10 PM PST 23
Finished Dec 24 01:07:27 PM PST 23
Peak memory 218132 kb
Host smart-5a4a6413-5fc7-4b5a-a142-41ccb5c2b034
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326919918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
1326919918
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2671550409
Short name T563
Test name
Test status
Simulation time 551213274 ps
CPU time 10.2 seconds
Started Dec 24 01:07:06 PM PST 23
Finished Dec 24 01:07:20 PM PST 23
Peak memory 218224 kb
Host smart-55f08240-0c06-4a55-80ac-abdbbe1bb430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671550409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2671550409
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.1574756075
Short name T598
Test name
Test status
Simulation time 200602600 ps
CPU time 6.02 seconds
Started Dec 24 01:06:55 PM PST 23
Finished Dec 24 01:07:05 PM PST 23
Peak memory 214504 kb
Host smart-387ac48e-460b-4144-9a96-fb40876a4307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574756075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.1574756075
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.531770993
Short name T85
Test name
Test status
Simulation time 679138762 ps
CPU time 28.45 seconds
Started Dec 24 01:06:52 PM PST 23
Finished Dec 24 01:07:26 PM PST 23
Peak memory 251156 kb
Host smart-7935e9c8-827a-4bdc-ad86-17a18113ca5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531770993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.531770993
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.1366685485
Short name T935
Test name
Test status
Simulation time 65676504 ps
CPU time 8.07 seconds
Started Dec 24 01:07:06 PM PST 23
Finished Dec 24 01:07:19 PM PST 23
Peak memory 251220 kb
Host smart-6ac93527-ca7a-4be1-af1f-0784f4ef96d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366685485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1366685485
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.659895736
Short name T619
Test name
Test status
Simulation time 5944767313 ps
CPU time 66.74 seconds
Started Dec 24 01:07:25 PM PST 23
Finished Dec 24 01:08:35 PM PST 23
Peak memory 247300 kb
Host smart-413aa70d-48b9-434a-8293-2b96dd5a6d0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659895736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.659895736
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.497657447
Short name T760
Test name
Test status
Simulation time 14157774 ps
CPU time 1.12 seconds
Started Dec 24 01:06:55 PM PST 23
Finished Dec 24 01:07:00 PM PST 23
Peak memory 211444 kb
Host smart-db6e1679-90d3-4580-b742-a796ea335515
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497657447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct
rl_volatile_unlock_smoke.497657447
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.1859942487
Short name T898
Test name
Test status
Simulation time 69673022 ps
CPU time 0.93 seconds
Started Dec 24 01:07:14 PM PST 23
Finished Dec 24 01:07:21 PM PST 23
Peak memory 209700 kb
Host smart-d6c1c7d1-9554-4369-a392-ed3300351318
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859942487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.1859942487
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.2184175904
Short name T486
Test name
Test status
Simulation time 1727819846 ps
CPU time 14.22 seconds
Started Dec 24 01:07:24 PM PST 23
Finished Dec 24 01:07:42 PM PST 23
Peak memory 218188 kb
Host smart-ca9b517e-0f74-432f-ac56-cda49c5fe0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184175904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.2184175904
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.3577928087
Short name T714
Test name
Test status
Simulation time 679786713 ps
CPU time 4.98 seconds
Started Dec 24 01:07:07 PM PST 23
Finished Dec 24 01:07:16 PM PST 23
Peak memory 209716 kb
Host smart-142d0a0e-190d-4783-bd0c-66198bbaa7cd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577928087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_a
ccess.3577928087
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.1644243743
Short name T482
Test name
Test status
Simulation time 5195426924 ps
CPU time 40.05 seconds
Started Dec 24 01:07:06 PM PST 23
Finished Dec 24 01:07:50 PM PST 23
Peak memory 218148 kb
Host smart-b497432f-f7e4-4ef9-91be-f42780b2a57c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644243743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.1644243743
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.1069318823
Short name T984
Test name
Test status
Simulation time 358372622 ps
CPU time 7.11 seconds
Started Dec 24 01:07:15 PM PST 23
Finished Dec 24 01:07:27 PM PST 23
Peak memory 218084 kb
Host smart-16b51f02-d226-46e6-846b-04f6a1d282e8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069318823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.1069318823
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1338580276
Short name T390
Test name
Test status
Simulation time 1463615846 ps
CPU time 5.88 seconds
Started Dec 24 01:07:34 PM PST 23
Finished Dec 24 01:07:41 PM PST 23
Peak memory 213492 kb
Host smart-da9be37a-4416-4fd8-bd33-334835c9ff2e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338580276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1338580276
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.2887318440
Short name T102
Test name
Test status
Simulation time 16273579330 ps
CPU time 88.08 seconds
Started Dec 24 01:07:23 PM PST 23
Finished Dec 24 01:08:55 PM PST 23
Peak memory 270152 kb
Host smart-ea8ac22c-7f24-40b4-8e80-e0e6ec179e8f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887318440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.2887318440
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.984140363
Short name T415
Test name
Test status
Simulation time 3028920601 ps
CPU time 8.03 seconds
Started Dec 24 01:07:11 PM PST 23
Finished Dec 24 01:07:25 PM PST 23
Peak memory 222096 kb
Host smart-546bb4e9-df40-410f-96a0-fec428c15dc0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984140363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_
jtag_state_post_trans.984140363
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.3168116086
Short name T577
Test name
Test status
Simulation time 250986061 ps
CPU time 3.44 seconds
Started Dec 24 01:07:23 PM PST 23
Finished Dec 24 01:07:31 PM PST 23
Peak memory 218208 kb
Host smart-0f8a0ba0-76f7-4aeb-9ada-bffb6cae6e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168116086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.3168116086
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.1875835234
Short name T662
Test name
Test status
Simulation time 894320881 ps
CPU time 11.88 seconds
Started Dec 24 01:07:03 PM PST 23
Finished Dec 24 01:07:17 PM PST 23
Peak memory 218312 kb
Host smart-433162bf-7ab6-4348-a564-af2c232fdc1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875835234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.1875835234
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.458706322
Short name T463
Test name
Test status
Simulation time 1244360636 ps
CPU time 17.33 seconds
Started Dec 24 01:07:08 PM PST 23
Finished Dec 24 01:07:30 PM PST 23
Peak memory 218108 kb
Host smart-08261eb7-539d-46bc-a5a1-99461712d4d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458706322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_di
gest.458706322
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.3154438755
Short name T364
Test name
Test status
Simulation time 1228442841 ps
CPU time 9.12 seconds
Started Dec 24 01:07:07 PM PST 23
Finished Dec 24 01:07:21 PM PST 23
Peak memory 218076 kb
Host smart-dbdb22e4-7d59-48fc-8261-d74baa19fefb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154438755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
3154438755
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.106085473
Short name T554
Test name
Test status
Simulation time 2020818613 ps
CPU time 7.87 seconds
Started Dec 24 01:07:25 PM PST 23
Finished Dec 24 01:07:36 PM PST 23
Peak memory 218228 kb
Host smart-771fc98b-92e9-4bb4-8047-d75c41c7c063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106085473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.106085473
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.4248472746
Short name T79
Test name
Test status
Simulation time 75795272 ps
CPU time 3.81 seconds
Started Dec 24 01:07:19 PM PST 23
Finished Dec 24 01:07:27 PM PST 23
Peak memory 213880 kb
Host smart-438a1c34-726c-4184-a192-f85c5dc91cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248472746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.4248472746
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.1614382949
Short name T906
Test name
Test status
Simulation time 854440944 ps
CPU time 35.62 seconds
Started Dec 24 01:07:20 PM PST 23
Finished Dec 24 01:08:00 PM PST 23
Peak memory 251032 kb
Host smart-e51cabc7-5511-48ee-b85e-38b1b6f428d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614382949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.1614382949
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.3705457553
Short name T11
Test name
Test status
Simulation time 78994675 ps
CPU time 3.2 seconds
Started Dec 24 01:07:09 PM PST 23
Finished Dec 24 01:07:18 PM PST 23
Peak memory 222176 kb
Host smart-f9886363-dcff-4ed1-84b0-c3e33df61f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705457553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.3705457553
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.4143573664
Short name T505
Test name
Test status
Simulation time 31528312551 ps
CPU time 242.5 seconds
Started Dec 24 01:07:10 PM PST 23
Finished Dec 24 01:11:19 PM PST 23
Peak memory 251324 kb
Host smart-28e80adb-b708-4d61-8458-3fbbec5bacd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143573664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.4143573664
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1717677890
Short name T926
Test name
Test status
Simulation time 28820507 ps
CPU time 0.73 seconds
Started Dec 24 01:07:04 PM PST 23
Finished Dec 24 01:07:07 PM PST 23
Peak memory 207972 kb
Host smart-c124e257-52d4-4173-8496-f07425a0bbd4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717677890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.1717677890
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.436063175
Short name T419
Test name
Test status
Simulation time 67094376 ps
CPU time 1.19 seconds
Started Dec 24 01:07:26 PM PST 23
Finished Dec 24 01:07:30 PM PST 23
Peak memory 209748 kb
Host smart-97f8bf9f-65a2-4be9-81e5-6cb78c86d32b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436063175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.436063175
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.2390733898
Short name T709
Test name
Test status
Simulation time 696099869 ps
CPU time 18.85 seconds
Started Dec 24 01:07:00 PM PST 23
Finished Dec 24 01:07:23 PM PST 23
Peak memory 218228 kb
Host smart-219b1752-5b7f-4813-bad0-36223a628849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390733898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2390733898
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.2834557103
Short name T634
Test name
Test status
Simulation time 73429816 ps
CPU time 1.17 seconds
Started Dec 24 01:07:16 PM PST 23
Finished Dec 24 01:07:22 PM PST 23
Peak memory 209704 kb
Host smart-ecc4b508-3b22-43f6-b653-de03649eb2ae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834557103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_a
ccess.2834557103
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.3952897119
Short name T421
Test name
Test status
Simulation time 4012868428 ps
CPU time 50.67 seconds
Started Dec 24 01:06:56 PM PST 23
Finished Dec 24 01:07:51 PM PST 23
Peak memory 220316 kb
Host smart-a4d9d2f2-e263-4707-8b18-3ca4a1ceb5a3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952897119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.3952897119
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.3481773223
Short name T400
Test name
Test status
Simulation time 572293593 ps
CPU time 3.85 seconds
Started Dec 24 01:07:07 PM PST 23
Finished Dec 24 01:07:16 PM PST 23
Peak memory 218136 kb
Host smart-b1144b58-c819-47fb-8cad-972459f2bd7f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481773223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.3481773223
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1626917774
Short name T309
Test name
Test status
Simulation time 1510159322 ps
CPU time 9.89 seconds
Started Dec 24 01:07:03 PM PST 23
Finished Dec 24 01:07:15 PM PST 23
Peak memory 213500 kb
Host smart-925f34e6-1d5d-4c74-9e19-a72dbe2c78ee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626917774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.1626917774
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3917750754
Short name T905
Test name
Test status
Simulation time 3506080249 ps
CPU time 119.75 seconds
Started Dec 24 01:07:08 PM PST 23
Finished Dec 24 01:09:12 PM PST 23
Peak memory 283572 kb
Host smart-b20fec65-d774-47c4-b8bf-583de6cf4ef5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917750754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.3917750754
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.2470717576
Short name T985
Test name
Test status
Simulation time 790851026 ps
CPU time 11.95 seconds
Started Dec 24 01:07:11 PM PST 23
Finished Dec 24 01:07:30 PM PST 23
Peak memory 221624 kb
Host smart-d26cbf8d-3d79-4118-8d2b-3fecdc01e53f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470717576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.2470717576
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.785996609
Short name T649
Test name
Test status
Simulation time 17833780 ps
CPU time 1.43 seconds
Started Dec 24 01:07:13 PM PST 23
Finished Dec 24 01:07:20 PM PST 23
Peak memory 218244 kb
Host smart-ef7ae2af-90d9-4d9c-ba17-f6f20abc2a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785996609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.785996609
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.3947224867
Short name T186
Test name
Test status
Simulation time 2242697596 ps
CPU time 13.29 seconds
Started Dec 24 01:06:58 PM PST 23
Finished Dec 24 01:07:15 PM PST 23
Peak memory 218416 kb
Host smart-8ba34352-2ac9-4a11-a8b0-d29de60bd1db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947224867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.3947224867
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.3718520452
Short name T537
Test name
Test status
Simulation time 264207847 ps
CPU time 10.11 seconds
Started Dec 24 01:07:11 PM PST 23
Finished Dec 24 01:07:28 PM PST 23
Peak memory 218064 kb
Host smart-74e1179c-c2d6-484e-83f3-ce8d63b2a054
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718520452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.3718520452
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1531685951
Short name T901
Test name
Test status
Simulation time 958267738 ps
CPU time 7.04 seconds
Started Dec 24 01:07:06 PM PST 23
Finished Dec 24 01:07:18 PM PST 23
Peak memory 218148 kb
Host smart-eec87735-1577-44b2-a24a-36172294778c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531685951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
1531685951
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.167959006
Short name T838
Test name
Test status
Simulation time 88431404 ps
CPU time 2.43 seconds
Started Dec 24 01:07:15 PM PST 23
Finished Dec 24 01:07:23 PM PST 23
Peak memory 214136 kb
Host smart-1428f326-5bc0-491e-8157-4ce2db09e470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167959006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.167959006
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.227848600
Short name T448
Test name
Test status
Simulation time 534355410 ps
CPU time 29.42 seconds
Started Dec 24 01:07:11 PM PST 23
Finished Dec 24 01:07:48 PM PST 23
Peak memory 251096 kb
Host smart-204f8328-2d5b-4982-b7de-ffd54a02b15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227848600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.227848600
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.2503504257
Short name T583
Test name
Test status
Simulation time 76583888 ps
CPU time 3.22 seconds
Started Dec 24 01:07:16 PM PST 23
Finished Dec 24 01:07:25 PM PST 23
Peak memory 226540 kb
Host smart-6ce72a61-eb08-4a67-9a16-cb7d2ede56d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503504257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.2503504257
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.3117152307
Short name T101
Test name
Test status
Simulation time 5036269589 ps
CPU time 136.58 seconds
Started Dec 24 01:06:58 PM PST 23
Finished Dec 24 01:09:19 PM PST 23
Peak memory 251072 kb
Host smart-7d83acbb-99d2-474c-80dd-961c82737249
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117152307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.3117152307
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.144797838
Short name T743
Test name
Test status
Simulation time 40701609 ps
CPU time 0.86 seconds
Started Dec 24 01:07:00 PM PST 23
Finished Dec 24 01:07:05 PM PST 23
Peak memory 208352 kb
Host smart-c86578f3-eb74-4bda-b787-fb57111a48d3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144797838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ct
rl_volatile_unlock_smoke.144797838
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.64309257
Short name T755
Test name
Test status
Simulation time 24221615 ps
CPU time 1.29 seconds
Started Dec 24 01:06:59 PM PST 23
Finished Dec 24 01:07:05 PM PST 23
Peak memory 208568 kb
Host smart-39e3e9b1-7158-488b-8f0a-14aca6dc0ed3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64309257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.64309257
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.3585234793
Short name T303
Test name
Test status
Simulation time 682990915 ps
CPU time 11.34 seconds
Started Dec 24 01:07:07 PM PST 23
Finished Dec 24 01:07:23 PM PST 23
Peak memory 218216 kb
Host smart-d7435381-d939-4f70-848b-b3fa1fba792d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585234793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.3585234793
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.1208486158
Short name T498
Test name
Test status
Simulation time 1454453532 ps
CPU time 8.42 seconds
Started Dec 24 01:07:09 PM PST 23
Finished Dec 24 01:07:23 PM PST 23
Peak memory 209656 kb
Host smart-97f74bb4-274c-4c71-b86c-21526179c2aa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208486158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_a
ccess.1208486158
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.4258909407
Short name T475
Test name
Test status
Simulation time 1737095882 ps
CPU time 48.74 seconds
Started Dec 24 01:07:02 PM PST 23
Finished Dec 24 01:07:54 PM PST 23
Peak memory 218112 kb
Host smart-c6318b53-659d-4bea-8174-4cf8d616d0eb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258909407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.4258909407
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.4276447812
Short name T330
Test name
Test status
Simulation time 419982239 ps
CPU time 6.37 seconds
Started Dec 24 01:07:08 PM PST 23
Finished Dec 24 01:07:20 PM PST 23
Peak memory 218216 kb
Host smart-f2603a61-1c3d-43c7-8ecd-92ef9ae119e6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276447812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.4276447812
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.4184197667
Short name T73
Test name
Test status
Simulation time 731787084 ps
CPU time 2.89 seconds
Started Dec 24 01:07:02 PM PST 23
Finished Dec 24 01:07:08 PM PST 23
Peak memory 212836 kb
Host smart-a4131917-8143-4d10-a481-408e43c2af86
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184197667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.4184197667
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.875734264
Short name T513
Test name
Test status
Simulation time 5379458539 ps
CPU time 48.97 seconds
Started Dec 24 01:07:18 PM PST 23
Finished Dec 24 01:08:11 PM PST 23
Peak memory 251168 kb
Host smart-39104728-3008-4da0-80e5-83f507bee58c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875734264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_state_failure.875734264
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.285237996
Short name T369
Test name
Test status
Simulation time 2244851876 ps
CPU time 18.25 seconds
Started Dec 24 01:06:58 PM PST 23
Finished Dec 24 01:07:20 PM PST 23
Peak memory 245056 kb
Host smart-cdd6b823-4dff-4e5a-af2b-55014100564c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285237996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_
jtag_state_post_trans.285237996
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.2150999892
Short name T797
Test name
Test status
Simulation time 27870243 ps
CPU time 2.05 seconds
Started Dec 24 01:06:56 PM PST 23
Finished Dec 24 01:07:02 PM PST 23
Peak memory 218224 kb
Host smart-afe549cc-9a95-4a6a-8fce-d6b4ac5f1047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150999892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2150999892
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.1743700580
Short name T978
Test name
Test status
Simulation time 247340134 ps
CPU time 12.39 seconds
Started Dec 24 01:07:08 PM PST 23
Finished Dec 24 01:07:25 PM PST 23
Peak memory 219240 kb
Host smart-b1e30f10-b9a1-42a3-80b2-19de1eedbabf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743700580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1743700580
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.4149208628
Short name T570
Test name
Test status
Simulation time 2616519488 ps
CPU time 14.7 seconds
Started Dec 24 01:07:17 PM PST 23
Finished Dec 24 01:07:36 PM PST 23
Peak memory 218148 kb
Host smart-aba5077d-73fb-45b1-b1ba-88655dfc9509
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149208628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.4149208628
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2202373569
Short name T951
Test name
Test status
Simulation time 659881371 ps
CPU time 11.36 seconds
Started Dec 24 01:07:14 PM PST 23
Finished Dec 24 01:07:31 PM PST 23
Peak memory 218140 kb
Host smart-40015fec-3203-4f08-be51-f9175a0875d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202373569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
2202373569
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.1160583148
Short name T799
Test name
Test status
Simulation time 278626059 ps
CPU time 11.66 seconds
Started Dec 24 01:07:09 PM PST 23
Finished Dec 24 01:07:26 PM PST 23
Peak memory 218196 kb
Host smart-3a78017f-646e-420a-8bfc-a0a1c47ee0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160583148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.1160583148
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.3274155851
Short name T902
Test name
Test status
Simulation time 779046555 ps
CPU time 8.43 seconds
Started Dec 24 01:07:07 PM PST 23
Finished Dec 24 01:07:20 PM PST 23
Peak memory 214232 kb
Host smart-ad23867b-14af-4e0a-914e-abeffb3fcfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274155851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.3274155851
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.2364293178
Short name T781
Test name
Test status
Simulation time 1283202394 ps
CPU time 23.29 seconds
Started Dec 24 01:07:07 PM PST 23
Finished Dec 24 01:07:35 PM PST 23
Peak memory 250880 kb
Host smart-ccdc975b-faa2-49d8-9978-dfb24d52e0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364293178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.2364293178
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.3698403331
Short name T534
Test name
Test status
Simulation time 439395051 ps
CPU time 8.17 seconds
Started Dec 24 01:07:07 PM PST 23
Finished Dec 24 01:07:20 PM PST 23
Peak memory 251144 kb
Host smart-78491e1d-e79c-4809-b170-bb62b90d91a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698403331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.3698403331
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.2664033640
Short name T731
Test name
Test status
Simulation time 4011079902 ps
CPU time 118.58 seconds
Started Dec 24 01:06:57 PM PST 23
Finished Dec 24 01:09:00 PM PST 23
Peak memory 247484 kb
Host smart-533b81fb-939d-4d9b-a9a3-270cb66c06f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664033640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.2664033640
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1992392
Short name T883
Test name
Test status
Simulation time 23771611 ps
CPU time 0.9 seconds
Started Dec 24 01:07:06 PM PST 23
Finished Dec 24 01:07:12 PM PST 23
Peak memory 208212 kb
Host smart-1b1afa4d-5686-42e8-a803-32b4777efebb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vola
tile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_volatile_unlock_smoke.1992392
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.550733158
Short name T750
Test name
Test status
Simulation time 62180481 ps
CPU time 0.86 seconds
Started Dec 24 01:07:45 PM PST 23
Finished Dec 24 01:07:55 PM PST 23
Peak memory 209632 kb
Host smart-ae53bd9b-6ac7-41b7-941b-efb5cec7f70f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550733158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.550733158
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.469309967
Short name T42
Test name
Test status
Simulation time 582086892 ps
CPU time 13.41 seconds
Started Dec 24 01:07:10 PM PST 23
Finished Dec 24 01:07:31 PM PST 23
Peak memory 218120 kb
Host smart-b3410e74-2fc0-4bbd-83e7-7d27fdc8f625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469309967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.469309967
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.1692626801
Short name T588
Test name
Test status
Simulation time 706077974 ps
CPU time 4.73 seconds
Started Dec 24 01:07:52 PM PST 23
Finished Dec 24 01:08:06 PM PST 23
Peak memory 209652 kb
Host smart-5b3cc547-2981-4aed-98f8-c11b143959d9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692626801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_a
ccess.1692626801
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.412913369
Short name T886
Test name
Test status
Simulation time 19031138658 ps
CPU time 112.58 seconds
Started Dec 24 01:07:59 PM PST 23
Finished Dec 24 01:10:00 PM PST 23
Peak memory 218540 kb
Host smart-30b2f330-b5b6-42f4-a4cd-4b0b72cfc6dc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412913369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_er
rors.412913369
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.2096831513
Short name T299
Test name
Test status
Simulation time 120686791 ps
CPU time 3.18 seconds
Started Dec 24 01:06:58 PM PST 23
Finished Dec 24 01:07:05 PM PST 23
Peak memory 218156 kb
Host smart-62c19fd7-b418-4cdc-93e1-93c0bef07587
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096831513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.2096831513
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.4093143700
Short name T559
Test name
Test status
Simulation time 1270737544 ps
CPU time 4.5 seconds
Started Dec 24 01:07:15 PM PST 23
Finished Dec 24 01:07:25 PM PST 23
Peak memory 212788 kb
Host smart-81bcb2a1-3e1a-4cdc-a5ab-362073cf71d2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093143700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.4093143700
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.3767654059
Short name T342
Test name
Test status
Simulation time 4318453885 ps
CPU time 43.54 seconds
Started Dec 24 01:07:05 PM PST 23
Finished Dec 24 01:07:52 PM PST 23
Peak memory 268912 kb
Host smart-b800d4ee-6913-45be-b4d9-d4ad86df65c9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767654059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.3767654059
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.1339353266
Short name T485
Test name
Test status
Simulation time 944897851 ps
CPU time 30.76 seconds
Started Dec 24 01:07:11 PM PST 23
Finished Dec 24 01:07:49 PM PST 23
Peak memory 251112 kb
Host smart-8754d71a-e31e-47fe-b153-959a01cb7632
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339353266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.1339353266
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.1240924262
Short name T578
Test name
Test status
Simulation time 399181228 ps
CPU time 2.8 seconds
Started Dec 24 01:07:08 PM PST 23
Finished Dec 24 01:07:17 PM PST 23
Peak memory 218256 kb
Host smart-c37dbbfd-c190-4cef-93da-3d84e1cac259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240924262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1240924262
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.2088915035
Short name T507
Test name
Test status
Simulation time 454482095 ps
CPU time 14.03 seconds
Started Dec 24 01:07:48 PM PST 23
Finished Dec 24 01:08:11 PM PST 23
Peak memory 218772 kb
Host smart-6671874b-c9cd-4172-b920-af510742d590
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088915035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.2088915035
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.4120906325
Short name T817
Test name
Test status
Simulation time 192997961 ps
CPU time 7.18 seconds
Started Dec 24 01:07:47 PM PST 23
Finished Dec 24 01:08:04 PM PST 23
Peak memory 218144 kb
Host smart-058ff463-d582-407e-a41b-fe5f35d7fb3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120906325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.4120906325
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.3079969948
Short name T965
Test name
Test status
Simulation time 3113661809 ps
CPU time 12.21 seconds
Started Dec 24 01:07:39 PM PST 23
Finished Dec 24 01:08:01 PM PST 23
Peak memory 218136 kb
Host smart-27c65662-01a6-4ab8-9b50-f1c39ce22b4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079969948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
3079969948
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.4195052809
Short name T934
Test name
Test status
Simulation time 1091012174 ps
CPU time 8.55 seconds
Started Dec 24 01:07:03 PM PST 23
Finished Dec 24 01:07:14 PM PST 23
Peak memory 218156 kb
Host smart-6d460a55-302e-4c23-b22e-b8ec2d2da9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195052809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.4195052809
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.1817597612
Short name T548
Test name
Test status
Simulation time 258735607 ps
CPU time 3.58 seconds
Started Dec 24 01:07:08 PM PST 23
Finished Dec 24 01:07:17 PM PST 23
Peak memory 214524 kb
Host smart-fe6deb14-539c-4cc6-ada2-45d12872c9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817597612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.1817597612
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.106727358
Short name T625
Test name
Test status
Simulation time 312509853 ps
CPU time 29.92 seconds
Started Dec 24 01:07:06 PM PST 23
Finished Dec 24 01:07:39 PM PST 23
Peak memory 251168 kb
Host smart-ef823d32-acf7-4afe-afb2-115f9ab7a60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106727358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.106727358
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.3642517546
Short name T904
Test name
Test status
Simulation time 262476819 ps
CPU time 8.31 seconds
Started Dec 24 01:07:00 PM PST 23
Finished Dec 24 01:07:12 PM PST 23
Peak memory 251200 kb
Host smart-8b94c7cc-29f4-4e4a-9360-dfd1e1182c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642517546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3642517546
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.1063320783
Short name T74
Test name
Test status
Simulation time 2240718044 ps
CPU time 62.1 seconds
Started Dec 24 01:08:05 PM PST 23
Finished Dec 24 01:09:22 PM PST 23
Peak memory 251804 kb
Host smart-1e2b83ba-239e-4c9a-8fd6-7faae59d5a71
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063320783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.1063320783
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.686045480
Short name T388
Test name
Test status
Simulation time 29497109 ps
CPU time 0.77 seconds
Started Dec 24 01:07:15 PM PST 23
Finished Dec 24 01:07:21 PM PST 23
Peak memory 208040 kb
Host smart-87e909ed-f547-4d3f-88e0-580967149a67
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686045480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ct
rl_volatile_unlock_smoke.686045480
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.2319060726
Short name T509
Test name
Test status
Simulation time 40561160 ps
CPU time 0.88 seconds
Started Dec 24 01:08:05 PM PST 23
Finished Dec 24 01:08:22 PM PST 23
Peak memory 209560 kb
Host smart-bd5dd7ac-8d5f-4734-b427-d026b33bb69d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319060726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.2319060726
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.2842057590
Short name T892
Test name
Test status
Simulation time 1439958350 ps
CPU time 13.75 seconds
Started Dec 24 01:08:05 PM PST 23
Finished Dec 24 01:08:35 PM PST 23
Peak memory 218144 kb
Host smart-7c78930e-5d93-4c27-b132-b44963c2cea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842057590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.2842057590
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.3108975286
Short name T968
Test name
Test status
Simulation time 2360870410 ps
CPU time 14.44 seconds
Started Dec 24 01:08:06 PM PST 23
Finished Dec 24 01:08:38 PM PST 23
Peak memory 209724 kb
Host smart-ae46fde9-279b-4466-b7b9-e540f7014037
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108975286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_a
ccess.3108975286
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.2805626857
Short name T301
Test name
Test status
Simulation time 7164453376 ps
CPU time 31.03 seconds
Started Dec 24 01:08:03 PM PST 23
Finished Dec 24 01:08:47 PM PST 23
Peak memory 218448 kb
Host smart-0d16fa58-8616-4bb2-9a0b-a460d1f6674d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805626857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.2805626857
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.1069714506
Short name T382
Test name
Test status
Simulation time 3080906432 ps
CPU time 10.5 seconds
Started Dec 24 01:08:02 PM PST 23
Finished Dec 24 01:08:25 PM PST 23
Peak memory 218180 kb
Host smart-895195ef-a849-4ffc-b188-b29122fab471
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069714506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.1069714506
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2153709677
Short name T397
Test name
Test status
Simulation time 428883940 ps
CPU time 6.72 seconds
Started Dec 24 01:07:45 PM PST 23
Finished Dec 24 01:08:01 PM PST 23
Peak memory 213176 kb
Host smart-3c7bcacc-8270-4200-9f1b-337884a9f879
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153709677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.2153709677
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.2574845398
Short name T86
Test name
Test status
Simulation time 2998530381 ps
CPU time 101.44 seconds
Started Dec 24 01:08:04 PM PST 23
Finished Dec 24 01:09:57 PM PST 23
Peak memory 283924 kb
Host smart-5fefd685-1fe4-4b70-a8bf-176dc1fc7269
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574845398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.2574845398
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.2226250373
Short name T555
Test name
Test status
Simulation time 385558763 ps
CPU time 12.58 seconds
Started Dec 24 01:08:10 PM PST 23
Finished Dec 24 01:08:41 PM PST 23
Peak memory 251124 kb
Host smart-afe435e6-74c2-4ce4-bf62-c94e849b6d35
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226250373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.2226250373
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.2085891135
Short name T524
Test name
Test status
Simulation time 71336684 ps
CPU time 1.71 seconds
Started Dec 24 01:07:58 PM PST 23
Finished Dec 24 01:08:08 PM PST 23
Peak memory 218204 kb
Host smart-ec6b48e5-3d7e-49d3-9037-eeb9e9889d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085891135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.2085891135
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.1841087141
Short name T447
Test name
Test status
Simulation time 451935461 ps
CPU time 21.03 seconds
Started Dec 24 01:08:05 PM PST 23
Finished Dec 24 01:08:41 PM PST 23
Peak memory 219276 kb
Host smart-7737a3f2-b82c-44cb-ae76-709489ea11cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841087141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.1841087141
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.95800716
Short name T702
Test name
Test status
Simulation time 1796982523 ps
CPU time 14.41 seconds
Started Dec 24 01:08:00 PM PST 23
Finished Dec 24 01:08:27 PM PST 23
Peak memory 218056 kb
Host smart-9059ab16-e501-4f34-a0f3-153e72ff0d6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95800716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_dig
est.95800716
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.717775552
Short name T502
Test name
Test status
Simulation time 545478843 ps
CPU time 8.11 seconds
Started Dec 24 01:08:02 PM PST 23
Finished Dec 24 01:08:22 PM PST 23
Peak memory 218116 kb
Host smart-fb83bd97-6ca4-4d95-95b0-30329ae09975
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717775552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.717775552
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.2636131066
Short name T924
Test name
Test status
Simulation time 308316309 ps
CPU time 8.76 seconds
Started Dec 24 01:08:01 PM PST 23
Finished Dec 24 01:08:23 PM PST 23
Peak memory 218220 kb
Host smart-cad153bd-2d94-466b-b776-e69991c440a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636131066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2636131066
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.1376216753
Short name T515
Test name
Test status
Simulation time 299577367 ps
CPU time 2.7 seconds
Started Dec 24 01:07:52 PM PST 23
Finished Dec 24 01:08:06 PM PST 23
Peak memory 214200 kb
Host smart-6e313439-1cd0-42cb-955c-e24b8d0921ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376216753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.1376216753
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.642065449
Short name T928
Test name
Test status
Simulation time 1858294892 ps
CPU time 21.62 seconds
Started Dec 24 01:07:56 PM PST 23
Finished Dec 24 01:08:27 PM PST 23
Peak memory 251060 kb
Host smart-9df0fdb1-3270-4d47-adb9-35c81171cc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642065449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.642065449
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.1959784857
Short name T585
Test name
Test status
Simulation time 424524934 ps
CPU time 3.79 seconds
Started Dec 24 01:07:51 PM PST 23
Finished Dec 24 01:08:05 PM PST 23
Peak memory 222312 kb
Host smart-dc6c2e4f-d2ea-40d2-a4ae-4706063035b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959784857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.1959784857
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.838248577
Short name T587
Test name
Test status
Simulation time 4909658618 ps
CPU time 27.9 seconds
Started Dec 24 01:08:03 PM PST 23
Finished Dec 24 01:08:43 PM PST 23
Peak memory 251216 kb
Host smart-3c6264b3-9edf-4e6c-bf5d-8903c06a86f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838248577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.838248577
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2904517326
Short name T39
Test name
Test status
Simulation time 30463825 ps
CPU time 0.75 seconds
Started Dec 24 01:07:52 PM PST 23
Finished Dec 24 01:08:02 PM PST 23
Peak memory 208236 kb
Host smart-0d6c9a00-511a-4477-beb8-0aa059db5522
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904517326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.2904517326
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.2158327716
Short name T779
Test name
Test status
Simulation time 14669958 ps
CPU time 0.86 seconds
Started Dec 24 01:08:03 PM PST 23
Finished Dec 24 01:08:16 PM PST 23
Peak memory 209680 kb
Host smart-9da41ab1-3732-48c5-96eb-0c782f73fc1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158327716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.2158327716
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.1944962155
Short name T816
Test name
Test status
Simulation time 1113709305 ps
CPU time 11.24 seconds
Started Dec 24 01:08:08 PM PST 23
Finished Dec 24 01:08:40 PM PST 23
Peak memory 218224 kb
Host smart-2e3cac88-4555-4baa-ac2c-c4cbd1f357d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944962155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.1944962155
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.514991673
Short name T508
Test name
Test status
Simulation time 754815031 ps
CPU time 5.23 seconds
Started Dec 24 01:08:08 PM PST 23
Finished Dec 24 01:08:34 PM PST 23
Peak memory 209556 kb
Host smart-f342d0aa-5acc-4a04-8e06-94a17a599711
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514991673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_ac
cess.514991673
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.2650715846
Short name T582
Test name
Test status
Simulation time 3856439549 ps
CPU time 50.71 seconds
Started Dec 24 01:08:04 PM PST 23
Finished Dec 24 01:09:07 PM PST 23
Peak memory 219228 kb
Host smart-4ec1b4a9-215a-43f0-adba-60a2c80fee71
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650715846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.2650715846
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.2392891043
Short name T859
Test name
Test status
Simulation time 1477068542 ps
CPU time 20.3 seconds
Started Dec 24 01:08:06 PM PST 23
Finished Dec 24 01:08:44 PM PST 23
Peak memory 218140 kb
Host smart-db5d5273-2599-4636-ac95-cb40357fdca4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392891043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.2392891043
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.615328089
Short name T601
Test name
Test status
Simulation time 299665118 ps
CPU time 9.1 seconds
Started Dec 24 01:08:09 PM PST 23
Finished Dec 24 01:08:38 PM PST 23
Peak memory 213564 kb
Host smart-45f4164d-fcc8-4940-adc4-1c6a89300999
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615328089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke.
615328089
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3267669641
Short name T777
Test name
Test status
Simulation time 5719904772 ps
CPU time 61.55 seconds
Started Dec 24 01:08:13 PM PST 23
Finished Dec 24 01:09:36 PM PST 23
Peak memory 283476 kb
Host smart-f5e7382d-553d-4c06-aa06-36868d175817
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267669641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.3267669641
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.4062638930
Short name T643
Test name
Test status
Simulation time 898976588 ps
CPU time 8.02 seconds
Started Dec 24 01:08:06 PM PST 23
Finished Dec 24 01:08:30 PM PST 23
Peak memory 223424 kb
Host smart-3d3e17e4-b691-44ad-b594-29bb9ea7a3f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062638930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.4062638930
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.1871284299
Short name T528
Test name
Test status
Simulation time 300279744 ps
CPU time 2.7 seconds
Started Dec 24 01:08:10 PM PST 23
Finished Dec 24 01:08:32 PM PST 23
Peak memory 218104 kb
Host smart-ab98ac60-35c1-47e3-af6b-cdd523ecef65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871284299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.1871284299
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.2881806362
Short name T896
Test name
Test status
Simulation time 273478688 ps
CPU time 13.88 seconds
Started Dec 24 01:08:05 PM PST 23
Finished Dec 24 01:08:36 PM PST 23
Peak memory 219172 kb
Host smart-6480b93f-e450-45ac-a159-09baddfbb582
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881806362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.2881806362
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.473047384
Short name T772
Test name
Test status
Simulation time 1222621823 ps
CPU time 13.83 seconds
Started Dec 24 01:08:08 PM PST 23
Finished Dec 24 01:08:43 PM PST 23
Peak memory 218344 kb
Host smart-242459cd-51a7-4cb9-834d-4baba24b0b2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473047384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_di
gest.473047384
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.512228581
Short name T339
Test name
Test status
Simulation time 2183972281 ps
CPU time 14.88 seconds
Started Dec 24 01:08:07 PM PST 23
Finished Dec 24 01:08:42 PM PST 23
Peak memory 218220 kb
Host smart-9b55fbfd-974a-48e7-ab9c-d6ab9081d0f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512228581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.512228581
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.3665660801
Short name T908
Test name
Test status
Simulation time 1061611379 ps
CPU time 6.75 seconds
Started Dec 24 01:08:08 PM PST 23
Finished Dec 24 01:08:36 PM PST 23
Peak memory 217196 kb
Host smart-6f3afeae-97a2-42c2-ba33-ccf71526bb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665660801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.3665660801
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.2406021531
Short name T441
Test name
Test status
Simulation time 22251404 ps
CPU time 0.97 seconds
Started Dec 24 01:08:08 PM PST 23
Finished Dec 24 01:08:30 PM PST 23
Peak memory 208700 kb
Host smart-6e9a92f4-e082-4c55-bf44-b2f5200c7b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406021531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.2406021531
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.2424504866
Short name T958
Test name
Test status
Simulation time 714855549 ps
CPU time 22.91 seconds
Started Dec 24 01:08:20 PM PST 23
Finished Dec 24 01:09:04 PM PST 23
Peak memory 251124 kb
Host smart-3c22ef9c-7885-4d70-91af-45630cde5c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424504866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.2424504866
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.3924081219
Short name T688
Test name
Test status
Simulation time 217340386 ps
CPU time 6.13 seconds
Started Dec 24 01:08:00 PM PST 23
Finished Dec 24 01:08:18 PM PST 23
Peak memory 246424 kb
Host smart-3ff3ea5f-1bd9-40f5-b9d0-107966b5f773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924081219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.3924081219
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.3846022442
Short name T606
Test name
Test status
Simulation time 20235747244 ps
CPU time 64.93 seconds
Started Dec 24 01:08:10 PM PST 23
Finished Dec 24 01:09:34 PM PST 23
Peak memory 246828 kb
Host smart-68d1548d-cabf-4f7e-9842-73f5cb6912ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846022442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.3846022442
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.786631102
Short name T828
Test name
Test status
Simulation time 46095527 ps
CPU time 0.76 seconds
Started Dec 24 01:08:25 PM PST 23
Finished Dec 24 01:08:44 PM PST 23
Peak memory 208200 kb
Host smart-2827cad2-94fd-4aab-90ea-c246369c04a8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786631102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ct
rl_volatile_unlock_smoke.786631102
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.3790434365
Short name T84
Test name
Test status
Simulation time 149646442 ps
CPU time 1.07 seconds
Started Dec 24 01:06:29 PM PST 23
Finished Dec 24 01:06:31 PM PST 23
Peak memory 209648 kb
Host smart-a37d3846-bf31-484f-9d9a-5755289d2b9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790434365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.3790434365
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.3781436714
Short name T659
Test name
Test status
Simulation time 1853251958 ps
CPU time 17.61 seconds
Started Dec 24 01:06:25 PM PST 23
Finished Dec 24 01:06:44 PM PST 23
Peak memory 218192 kb
Host smart-7372520b-433d-42df-bb9c-07c2506c13f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781436714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.3781436714
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.630824118
Short name T8
Test name
Test status
Simulation time 6849070145 ps
CPU time 9.94 seconds
Started Dec 24 01:06:22 PM PST 23
Finished Dec 24 01:06:33 PM PST 23
Peak memory 209780 kb
Host smart-9232635f-2876-4056-87f7-c47913f5be62
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630824118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_acc
ess.630824118
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.4204292764
Short name T791
Test name
Test status
Simulation time 2721503265 ps
CPU time 38.51 seconds
Started Dec 24 01:06:28 PM PST 23
Finished Dec 24 01:07:07 PM PST 23
Peak memory 218292 kb
Host smart-eafffb5e-b9e3-4486-acc2-8b28b2ca9387
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204292764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.4204292764
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.562612218
Short name T68
Test name
Test status
Simulation time 1033710543 ps
CPU time 3.42 seconds
Started Dec 24 01:06:37 PM PST 23
Finished Dec 24 01:06:42 PM PST 23
Peak memory 209720 kb
Host smart-b8f2017c-9721-4079-8b55-8d315898a70c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562612218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_p
riority.562612218
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.755225972
Short name T510
Test name
Test status
Simulation time 1123393595 ps
CPU time 8.47 seconds
Started Dec 24 01:06:32 PM PST 23
Finished Dec 24 01:06:42 PM PST 23
Peak memory 218156 kb
Host smart-3a63d638-6549-43e1-85ba-1cb58b7463e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755225972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_
prog_failure.755225972
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3359620432
Short name T981
Test name
Test status
Simulation time 1108494081 ps
CPU time 14.04 seconds
Started Dec 24 01:06:23 PM PST 23
Finished Dec 24 01:06:38 PM PST 23
Peak memory 213032 kb
Host smart-10c17b32-1ce5-48f5-aaf3-c95c35d83580
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359620432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.3359620432
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.18008622
Short name T798
Test name
Test status
Simulation time 358310670 ps
CPU time 5.34 seconds
Started Dec 24 01:06:11 PM PST 23
Finished Dec 24 01:06:18 PM PST 23
Peak memory 213044 kb
Host smart-77fbb27b-b7c7-44c8-986a-fc858b65681f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18008622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.18008622
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.1118967258
Short name T646
Test name
Test status
Simulation time 6280813670 ps
CPU time 63.06 seconds
Started Dec 24 01:06:22 PM PST 23
Finished Dec 24 01:07:26 PM PST 23
Peak memory 276368 kb
Host smart-6fac8918-ed67-4f85-8e47-8418102cad24
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118967258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.1118967258
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.244309666
Short name T468
Test name
Test status
Simulation time 1340543613 ps
CPU time 11.57 seconds
Started Dec 24 01:06:22 PM PST 23
Finished Dec 24 01:06:34 PM PST 23
Peak memory 251148 kb
Host smart-e2942244-6ed5-421c-9ccf-172f3a4d7c3c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244309666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_state_post_trans.244309666
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.2974382792
Short name T467
Test name
Test status
Simulation time 69138144 ps
CPU time 2.27 seconds
Started Dec 24 01:06:23 PM PST 23
Finished Dec 24 01:06:26 PM PST 23
Peak memory 218148 kb
Host smart-1171206c-09ec-4420-9887-b5efad75a303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974382792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.2974382792
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2494845745
Short name T69
Test name
Test status
Simulation time 356741788 ps
CPU time 8.43 seconds
Started Dec 24 01:06:40 PM PST 23
Finished Dec 24 01:06:50 PM PST 23
Peak memory 214184 kb
Host smart-ec97ab23-fbc5-4689-9813-131a8b1f8084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494845745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2494845745
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.2872198069
Short name T394
Test name
Test status
Simulation time 4906072939 ps
CPU time 15.29 seconds
Started Dec 24 01:06:11 PM PST 23
Finished Dec 24 01:06:27 PM PST 23
Peak memory 219168 kb
Host smart-1849dd71-5e30-4d23-a9c2-53ba157a1b81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872198069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.2872198069
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.1691057129
Short name T735
Test name
Test status
Simulation time 1405227471 ps
CPU time 10.2 seconds
Started Dec 24 01:06:47 PM PST 23
Finished Dec 24 01:07:00 PM PST 23
Peak memory 217988 kb
Host smart-6e9692ca-b1d6-4fb4-b423-73e786cd9d24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691057129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.1691057129
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.547764396
Short name T923
Test name
Test status
Simulation time 508386989 ps
CPU time 15.32 seconds
Started Dec 24 01:06:31 PM PST 23
Finished Dec 24 01:06:48 PM PST 23
Peak memory 218352 kb
Host smart-11e855f0-3e82-4f3b-b22d-83cd4c32b786
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547764396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.547764396
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.1560342600
Short name T959
Test name
Test status
Simulation time 448661641 ps
CPU time 12.19 seconds
Started Dec 24 01:06:10 PM PST 23
Finished Dec 24 01:06:23 PM PST 23
Peak memory 218112 kb
Host smart-0fd39e65-e092-444e-b963-796d2f9c246e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560342600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.1560342600
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.3278063815
Short name T10
Test name
Test status
Simulation time 1354523680 ps
CPU time 3.8 seconds
Started Dec 24 01:05:47 PM PST 23
Finished Dec 24 01:06:00 PM PST 23
Peak memory 214240 kb
Host smart-9ca2c243-6efb-470f-bb69-4462202a2683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278063815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.3278063815
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.1869486355
Short name T697
Test name
Test status
Simulation time 214507294 ps
CPU time 25.55 seconds
Started Dec 24 01:05:58 PM PST 23
Finished Dec 24 01:06:28 PM PST 23
Peak memory 251128 kb
Host smart-5b71c806-8168-4a71-bb5b-258be2308221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869486355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.1869486355
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.2183563324
Short name T815
Test name
Test status
Simulation time 195821026 ps
CPU time 3.14 seconds
Started Dec 24 01:05:47 PM PST 23
Finished Dec 24 01:05:59 PM PST 23
Peak memory 221956 kb
Host smart-8b75b414-72e3-49e9-b519-19307b1b22c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183563324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.2183563324
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2478164771
Short name T753
Test name
Test status
Simulation time 21771495 ps
CPU time 0.77 seconds
Started Dec 24 01:05:58 PM PST 23
Finished Dec 24 01:06:03 PM PST 23
Peak memory 208348 kb
Host smart-1250f1d6-2dab-48ea-9903-25ccd84e2f25
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478164771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.2478164771
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.1482859822
Short name T357
Test name
Test status
Simulation time 44709703 ps
CPU time 1.66 seconds
Started Dec 24 01:08:05 PM PST 23
Finished Dec 24 01:08:27 PM PST 23
Peak memory 208564 kb
Host smart-7167ffc0-e9c1-471a-8230-f7088326824c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482859822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.1482859822
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.1342139506
Short name T444
Test name
Test status
Simulation time 342693219 ps
CPU time 13.35 seconds
Started Dec 24 01:08:09 PM PST 23
Finished Dec 24 01:08:42 PM PST 23
Peak memory 218208 kb
Host smart-57a80d67-663e-4d4f-a333-e2122e4624f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342139506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.1342139506
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.3581663736
Short name T784
Test name
Test status
Simulation time 6529648322 ps
CPU time 6.76 seconds
Started Dec 24 01:07:45 PM PST 23
Finished Dec 24 01:08:01 PM PST 23
Peak memory 209648 kb
Host smart-aa3c6e9f-6b87-40eb-abd7-1d35b8dbb0c0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581663736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_a
ccess.3581663736
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2936750823
Short name T403
Test name
Test status
Simulation time 110168155 ps
CPU time 2.39 seconds
Started Dec 24 01:08:19 PM PST 23
Finished Dec 24 01:08:43 PM PST 23
Peak memory 218240 kb
Host smart-f48debd7-b330-467a-bdce-06eb710f30e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936750823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2936750823
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.4280178266
Short name T349
Test name
Test status
Simulation time 364485980 ps
CPU time 16.2 seconds
Started Dec 24 01:08:01 PM PST 23
Finished Dec 24 01:08:30 PM PST 23
Peak memory 218696 kb
Host smart-6a7256a7-c18e-41bc-8e95-cd9b86bd7d3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280178266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.4280178266
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.3980079037
Short name T392
Test name
Test status
Simulation time 755366335 ps
CPU time 12.06 seconds
Started Dec 24 01:07:52 PM PST 23
Finished Dec 24 01:08:15 PM PST 23
Peak memory 218152 kb
Host smart-075f4dd4-c166-498a-90fd-081cf505388a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980079037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.3980079037
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.1113860574
Short name T551
Test name
Test status
Simulation time 1073438495 ps
CPU time 8.67 seconds
Started Dec 24 01:07:57 PM PST 23
Finished Dec 24 01:08:15 PM PST 23
Peak memory 218148 kb
Host smart-ca2f9196-0549-4590-883c-a8cbe1e9157b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113860574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
1113860574
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.792032883
Short name T525
Test name
Test status
Simulation time 1169571218 ps
CPU time 8.58 seconds
Started Dec 24 01:07:57 PM PST 23
Finished Dec 24 01:08:15 PM PST 23
Peak memory 218184 kb
Host smart-3da98a12-4cce-4991-b0a5-3fc0cf9f4fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792032883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.792032883
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.2759130426
Short name T638
Test name
Test status
Simulation time 90988686 ps
CPU time 1.28 seconds
Started Dec 24 01:08:15 PM PST 23
Finished Dec 24 01:08:38 PM PST 23
Peak memory 213268 kb
Host smart-11635463-39aa-4ae8-bcf2-ae085b10c92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759130426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.2759130426
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.2661534451
Short name T533
Test name
Test status
Simulation time 600427334 ps
CPU time 23.13 seconds
Started Dec 24 01:08:04 PM PST 23
Finished Dec 24 01:08:39 PM PST 23
Peak memory 250996 kb
Host smart-53ad3d4d-254b-41e5-9da9-2101bcf5b41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661534451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.2661534451
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.1989857660
Short name T432
Test name
Test status
Simulation time 87845302 ps
CPU time 6 seconds
Started Dec 24 01:08:09 PM PST 23
Finished Dec 24 01:08:35 PM PST 23
Peak memory 244124 kb
Host smart-0ff02cde-eff4-4e50-840e-62f08b41a746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989857660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.1989857660
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.2838172439
Short name T749
Test name
Test status
Simulation time 5716087798 ps
CPU time 102.77 seconds
Started Dec 24 01:08:01 PM PST 23
Finished Dec 24 01:09:57 PM PST 23
Peak memory 276176 kb
Host smart-b7dccb25-b823-4613-9177-30d2a75c79bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838172439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.2838172439
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1586519426
Short name T405
Test name
Test status
Simulation time 15970679 ps
CPU time 0.99 seconds
Started Dec 24 01:08:06 PM PST 23
Finished Dec 24 01:08:24 PM PST 23
Peak memory 212700 kb
Host smart-86723b2e-6f92-42db-b5f4-6c53851f421b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586519426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.1586519426
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.1844018965
Short name T712
Test name
Test status
Simulation time 63525060 ps
CPU time 1.11 seconds
Started Dec 24 01:08:04 PM PST 23
Finished Dec 24 01:08:18 PM PST 23
Peak memory 208380 kb
Host smart-5d60be34-6423-4a7a-a62b-d5607fcbc035
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844018965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.1844018965
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.1399523789
Short name T613
Test name
Test status
Simulation time 1221623698 ps
CPU time 15.57 seconds
Started Dec 24 01:08:00 PM PST 23
Finished Dec 24 01:08:27 PM PST 23
Peak memory 218072 kb
Host smart-4444f4fd-7106-4ea2-b473-ba13af493701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399523789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.1399523789
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.2637077801
Short name T899
Test name
Test status
Simulation time 301692149 ps
CPU time 3.16 seconds
Started Dec 24 01:08:03 PM PST 23
Finished Dec 24 01:08:19 PM PST 23
Peak memory 209604 kb
Host smart-d3f3c06a-3cf4-4ac2-a486-ff46574aafa1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637077801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_a
ccess.2637077801
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.368953810
Short name T367
Test name
Test status
Simulation time 16406482 ps
CPU time 1.63 seconds
Started Dec 24 01:07:50 PM PST 23
Finished Dec 24 01:08:00 PM PST 23
Peak memory 218232 kb
Host smart-d24be946-b366-47bf-a0d8-e0f0d4077e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368953810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.368953810
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.3883326567
Short name T488
Test name
Test status
Simulation time 2955047062 ps
CPU time 13.45 seconds
Started Dec 24 01:08:06 PM PST 23
Finished Dec 24 01:08:35 PM PST 23
Peak memory 219248 kb
Host smart-495ad9ec-d5b8-4253-99f2-535530231230
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883326567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.3883326567
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.4012918771
Short name T366
Test name
Test status
Simulation time 806753235 ps
CPU time 15.56 seconds
Started Dec 24 01:08:04 PM PST 23
Finished Dec 24 01:08:31 PM PST 23
Peak memory 218112 kb
Host smart-40ff27e6-c348-4183-914b-d0ee8d0f8d81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012918771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.4012918771
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.924512131
Short name T496
Test name
Test status
Simulation time 337695079 ps
CPU time 10.8 seconds
Started Dec 24 01:08:07 PM PST 23
Finished Dec 24 01:08:40 PM PST 23
Peak memory 218128 kb
Host smart-7ffa627b-a015-40a8-a465-47b53b5704e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924512131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.924512131
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.2631273460
Short name T572
Test name
Test status
Simulation time 570361888 ps
CPU time 11.06 seconds
Started Dec 24 01:08:06 PM PST 23
Finished Dec 24 01:08:34 PM PST 23
Peak memory 218192 kb
Host smart-bd7d023f-a740-43e1-9686-b186c4c6ea87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631273460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.2631273460
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.3320658236
Short name T77
Test name
Test status
Simulation time 84565223 ps
CPU time 1.29 seconds
Started Dec 24 01:08:00 PM PST 23
Finished Dec 24 01:08:13 PM PST 23
Peak memory 213208 kb
Host smart-abd2adc3-722b-4755-85ca-8699ae188f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320658236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.3320658236
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.2973908141
Short name T437
Test name
Test status
Simulation time 230563944 ps
CPU time 25.13 seconds
Started Dec 24 01:08:00 PM PST 23
Finished Dec 24 01:08:38 PM PST 23
Peak memory 251156 kb
Host smart-ebd2162f-de91-426c-bc07-5cd40f6fff16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973908141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.2973908141
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.1710971675
Short name T545
Test name
Test status
Simulation time 58725461 ps
CPU time 6.67 seconds
Started Dec 24 01:08:03 PM PST 23
Finished Dec 24 01:08:22 PM PST 23
Peak memory 250344 kb
Host smart-5cf9def2-87bc-43a8-8d83-854c8992b5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710971675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.1710971675
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.3648232762
Short name T982
Test name
Test status
Simulation time 16244978757 ps
CPU time 88.32 seconds
Started Dec 24 01:07:59 PM PST 23
Finished Dec 24 01:09:36 PM PST 23
Peak memory 221312 kb
Host smart-5a8eb5f3-4bb0-4983-86db-9e9a43fc3a11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648232762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.3648232762
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1990956261
Short name T446
Test name
Test status
Simulation time 32816721 ps
CPU time 0.86 seconds
Started Dec 24 01:07:50 PM PST 23
Finished Dec 24 01:08:00 PM PST 23
Peak memory 208184 kb
Host smart-aa2b314f-c6ba-4ae8-9b1b-29fc02fc429e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990956261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.1990956261
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.1036312236
Short name T624
Test name
Test status
Simulation time 109415790 ps
CPU time 1.38 seconds
Started Dec 24 01:08:08 PM PST 23
Finished Dec 24 01:08:30 PM PST 23
Peak memory 209928 kb
Host smart-f073830d-96fd-42c2-85fe-3995646def49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036312236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.1036312236
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.1318553496
Short name T739
Test name
Test status
Simulation time 548280123 ps
CPU time 12.21 seconds
Started Dec 24 01:08:09 PM PST 23
Finished Dec 24 01:08:41 PM PST 23
Peak memory 218204 kb
Host smart-b072885a-677b-48b3-b2e0-7b1660b0b6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318553496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.1318553496
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.1501804771
Short name T929
Test name
Test status
Simulation time 1004184260 ps
CPU time 6.44 seconds
Started Dec 24 01:08:10 PM PST 23
Finished Dec 24 01:08:35 PM PST 23
Peak memory 209704 kb
Host smart-883b27a8-fe5b-48f4-aabe-3e27734c2dc1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501804771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_a
ccess.1501804771
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.597628132
Short name T431
Test name
Test status
Simulation time 34576070 ps
CPU time 2.21 seconds
Started Dec 24 01:08:08 PM PST 23
Finished Dec 24 01:08:31 PM PST 23
Peak memory 217436 kb
Host smart-ba8da364-f223-47e2-9466-a1a6491d8a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597628132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.597628132
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.1048611249
Short name T829
Test name
Test status
Simulation time 2324547419 ps
CPU time 17.09 seconds
Started Dec 24 01:08:04 PM PST 23
Finished Dec 24 01:08:34 PM PST 23
Peak memory 218276 kb
Host smart-2862689f-c34b-4259-b570-43500c6ea8e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048611249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.1048611249
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.343337767
Short name T858
Test name
Test status
Simulation time 546166811 ps
CPU time 13.68 seconds
Started Dec 24 01:08:07 PM PST 23
Finished Dec 24 01:08:38 PM PST 23
Peak memory 218144 kb
Host smart-e56d6bdc-82e4-4132-b470-15c797885718
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343337767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_di
gest.343337767
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.4231966377
Short name T728
Test name
Test status
Simulation time 654085834 ps
CPU time 9.82 seconds
Started Dec 24 01:08:05 PM PST 23
Finished Dec 24 01:08:29 PM PST 23
Peak memory 218144 kb
Host smart-87476107-3296-4fff-ac54-fc42786127ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231966377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
4231966377
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.3734747400
Short name T621
Test name
Test status
Simulation time 272620671 ps
CPU time 10.94 seconds
Started Dec 24 01:08:03 PM PST 23
Finished Dec 24 01:08:26 PM PST 23
Peak memory 218208 kb
Host smart-7357972e-3901-49b3-b12a-f44f9940e90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734747400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.3734747400
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.758075549
Short name T919
Test name
Test status
Simulation time 186279105 ps
CPU time 2.26 seconds
Started Dec 24 01:08:06 PM PST 23
Finished Dec 24 01:08:25 PM PST 23
Peak memory 213988 kb
Host smart-976b8969-2b8f-4194-b799-009b8d268602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758075549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.758075549
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.1687715795
Short name T425
Test name
Test status
Simulation time 1069025667 ps
CPU time 25.24 seconds
Started Dec 24 01:08:05 PM PST 23
Finished Dec 24 01:08:46 PM PST 23
Peak memory 251156 kb
Host smart-34bf5a28-b38b-412f-8e66-97e452c1866f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687715795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.1687715795
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.2851715904
Short name T678
Test name
Test status
Simulation time 887211572 ps
CPU time 2.89 seconds
Started Dec 24 01:08:08 PM PST 23
Finished Dec 24 01:08:32 PM PST 23
Peak memory 221856 kb
Host smart-05b24535-0eb8-4e11-924b-b47eff5d3c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851715904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.2851715904
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.3246586190
Short name T500
Test name
Test status
Simulation time 514397155 ps
CPU time 15.19 seconds
Started Dec 24 01:08:05 PM PST 23
Finished Dec 24 01:08:36 PM PST 23
Peak memory 219144 kb
Host smart-af8b1729-26fc-4a87-8d78-7028fe0ff1dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246586190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.3246586190
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.206050100
Short name T607
Test name
Test status
Simulation time 61618342 ps
CPU time 0.88 seconds
Started Dec 24 01:08:10 PM PST 23
Finished Dec 24 01:08:30 PM PST 23
Peak memory 208016 kb
Host smart-eb0646c5-a626-4a20-8927-d8f8a3e28a84
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206050100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ct
rl_volatile_unlock_smoke.206050100
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.7065566
Short name T776
Test name
Test status
Simulation time 40775919 ps
CPU time 0.92 seconds
Started Dec 24 01:08:08 PM PST 23
Finished Dec 24 01:08:30 PM PST 23
Peak memory 209712 kb
Host smart-1f72a820-cf65-46ee-8f91-aabcbf9621ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7065566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.7065566
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.3389607933
Short name T699
Test name
Test status
Simulation time 808121132 ps
CPU time 14.03 seconds
Started Dec 24 01:08:07 PM PST 23
Finished Dec 24 01:08:39 PM PST 23
Peak memory 218232 kb
Host smart-665ab29f-8f21-4a55-9b49-b2203948c60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389607933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3389607933
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.2269748325
Short name T847
Test name
Test status
Simulation time 496505350 ps
CPU time 6.19 seconds
Started Dec 24 01:08:06 PM PST 23
Finished Dec 24 01:08:28 PM PST 23
Peak memory 209460 kb
Host smart-bbf28df7-cabc-49e7-9966-4e205d0fb9e0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269748325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_a
ccess.2269748325
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.2641065906
Short name T648
Test name
Test status
Simulation time 67008246 ps
CPU time 2.65 seconds
Started Dec 24 01:08:07 PM PST 23
Finished Dec 24 01:08:34 PM PST 23
Peak memory 217992 kb
Host smart-bccd2fec-e134-4d1e-a55a-2830893c57cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641065906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.2641065906
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.3975139090
Short name T841
Test name
Test status
Simulation time 223482131 ps
CPU time 9.5 seconds
Started Dec 24 01:08:09 PM PST 23
Finished Dec 24 01:08:38 PM PST 23
Peak memory 218240 kb
Host smart-61473c38-2eb6-47cc-9f21-6bdca9f34cfb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975139090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.3975139090
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.2335631289
Short name T769
Test name
Test status
Simulation time 1585607379 ps
CPU time 10.01 seconds
Started Dec 24 01:08:04 PM PST 23
Finished Dec 24 01:08:27 PM PST 23
Peak memory 218204 kb
Host smart-2ec897cc-d3bb-4f83-9f7f-075ca8cd683c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335631289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.2335631289
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.263998340
Short name T740
Test name
Test status
Simulation time 1583563514 ps
CPU time 7.99 seconds
Started Dec 24 01:08:08 PM PST 23
Finished Dec 24 01:08:37 PM PST 23
Peak memory 218184 kb
Host smart-94b01101-99ce-4a50-b209-5513f90d6bc7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263998340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.263998340
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.2146344707
Short name T866
Test name
Test status
Simulation time 251480041 ps
CPU time 9.75 seconds
Started Dec 24 01:08:09 PM PST 23
Finished Dec 24 01:08:39 PM PST 23
Peak memory 218216 kb
Host smart-031c3263-c573-45de-a1df-6fb6304717d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146344707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.2146344707
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.1194562340
Short name T622
Test name
Test status
Simulation time 61318265 ps
CPU time 1.04 seconds
Started Dec 24 01:08:05 PM PST 23
Finished Dec 24 01:08:22 PM PST 23
Peak memory 212868 kb
Host smart-eb7b746d-b8b8-47f5-874b-7067f659a173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194562340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.1194562340
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.2248648004
Short name T512
Test name
Test status
Simulation time 1356673160 ps
CPU time 29.78 seconds
Started Dec 24 01:08:07 PM PST 23
Finished Dec 24 01:08:57 PM PST 23
Peak memory 250988 kb
Host smart-e764d211-8d52-4091-ac17-8856b9d81216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248648004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.2248648004
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.319168831
Short name T483
Test name
Test status
Simulation time 63902229 ps
CPU time 3.57 seconds
Started Dec 24 01:08:07 PM PST 23
Finished Dec 24 01:08:32 PM PST 23
Peak memory 226592 kb
Host smart-fc68bd87-3842-4fe3-93ee-8f404c89a1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319168831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.319168831
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3359837680
Short name T836
Test name
Test status
Simulation time 31093191320 ps
CPU time 81.85 seconds
Started Dec 24 01:08:09 PM PST 23
Finished Dec 24 01:09:51 PM PST 23
Peak memory 251208 kb
Host smart-62ec7c4e-e8e1-4dee-abd9-0c30f735cc2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359837680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3359837680
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.2942891084
Short name T973
Test name
Test status
Simulation time 27870858 ps
CPU time 0.8 seconds
Started Dec 24 01:08:24 PM PST 23
Finished Dec 24 01:08:43 PM PST 23
Peak memory 208248 kb
Host smart-4c09f1b9-02d0-406c-88bf-07829f412011
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942891084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.2942891084
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.3825146984
Short name T543
Test name
Test status
Simulation time 51375346 ps
CPU time 1.04 seconds
Started Dec 24 01:08:10 PM PST 23
Finished Dec 24 01:08:30 PM PST 23
Peak memory 209696 kb
Host smart-e2de0159-148c-4b21-b746-14c0b731891b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825146984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.3825146984
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.3638325699
Short name T474
Test name
Test status
Simulation time 930726263 ps
CPU time 8.5 seconds
Started Dec 24 01:08:11 PM PST 23
Finished Dec 24 01:08:37 PM PST 23
Peak memory 218112 kb
Host smart-21cac137-67b8-4f9d-a34c-c83956248967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638325699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.3638325699
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.1543316521
Short name T27
Test name
Test status
Simulation time 88881145 ps
CPU time 1.67 seconds
Started Dec 24 01:08:12 PM PST 23
Finished Dec 24 01:08:34 PM PST 23
Peak memory 209676 kb
Host smart-a1b56e3e-034c-42ca-85f7-5c6623df90e3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543316521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_a
ccess.1543316521
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.3818366377
Short name T790
Test name
Test status
Simulation time 74662699 ps
CPU time 3.53 seconds
Started Dec 24 01:08:07 PM PST 23
Finished Dec 24 01:08:29 PM PST 23
Peak memory 218132 kb
Host smart-9e36f7b6-4c68-49d1-95a0-92505a00732d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818366377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.3818366377
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.1740134731
Short name T473
Test name
Test status
Simulation time 1130254696 ps
CPU time 10.51 seconds
Started Dec 24 01:08:02 PM PST 23
Finished Dec 24 01:08:25 PM PST 23
Peak memory 218468 kb
Host smart-55ace818-5194-4c6c-b0c2-9477d5de6bd6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740134731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.1740134731
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.1343421966
Short name T466
Test name
Test status
Simulation time 389442535 ps
CPU time 14.92 seconds
Started Dec 24 01:07:59 PM PST 23
Finished Dec 24 01:08:22 PM PST 23
Peak memory 218164 kb
Host smart-4f2500a7-394a-4239-b96f-fd0e00ce3125
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343421966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.1343421966
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.3073250404
Short name T416
Test name
Test status
Simulation time 2292151977 ps
CPU time 8.69 seconds
Started Dec 24 01:08:00 PM PST 23
Finished Dec 24 01:08:21 PM PST 23
Peak memory 218200 kb
Host smart-ee5b2be3-e9bc-4721-bad0-9b1a65d2c109
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073250404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
3073250404
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.1055206078
Short name T745
Test name
Test status
Simulation time 498173842 ps
CPU time 9.62 seconds
Started Dec 24 01:08:15 PM PST 23
Finished Dec 24 01:08:46 PM PST 23
Peak memory 218212 kb
Host smart-b81cca18-80e0-4ad6-b117-8464024900ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055206078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.1055206078
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.126953378
Short name T875
Test name
Test status
Simulation time 132911346 ps
CPU time 2.4 seconds
Started Dec 24 01:08:11 PM PST 23
Finished Dec 24 01:08:33 PM PST 23
Peak memory 214000 kb
Host smart-103e6def-e05b-4692-9854-c3f1a27c833d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126953378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.126953378
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.837750235
Short name T789
Test name
Test status
Simulation time 1344265995 ps
CPU time 36.4 seconds
Started Dec 24 01:08:10 PM PST 23
Finished Dec 24 01:09:08 PM PST 23
Peak memory 251140 kb
Host smart-1352d236-a9df-4adc-a15b-176a51fbdb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837750235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.837750235
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.2981970643
Short name T854
Test name
Test status
Simulation time 318727479 ps
CPU time 7.84 seconds
Started Dec 24 01:08:10 PM PST 23
Finished Dec 24 01:08:37 PM PST 23
Peak memory 250724 kb
Host smart-97f12939-a57c-4c31-8c9f-c50532d6d35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981970643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.2981970643
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.2756337430
Short name T955
Test name
Test status
Simulation time 11115885972 ps
CPU time 176.95 seconds
Started Dec 24 01:08:05 PM PST 23
Finished Dec 24 01:11:18 PM PST 23
Peak memory 251300 kb
Host smart-62c0a00a-b3df-42bb-ac64-a01868e87a56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756337430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.2756337430
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3430376511
Short name T766
Test name
Test status
Simulation time 24170370 ps
CPU time 0.92 seconds
Started Dec 24 01:08:09 PM PST 23
Finished Dec 24 01:08:30 PM PST 23
Peak memory 208184 kb
Host smart-69c492cf-75d5-4f25-b87e-78bc84579c40
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430376511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.3430376511
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.2355797268
Short name T380
Test name
Test status
Simulation time 31408542 ps
CPU time 1.07 seconds
Started Dec 24 01:08:02 PM PST 23
Finished Dec 24 01:08:15 PM PST 23
Peak memory 209808 kb
Host smart-b875e0d9-51d4-4836-8f16-8d3b322a9f13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355797268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.2355797268
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.3180230792
Short name T971
Test name
Test status
Simulation time 938386842 ps
CPU time 11.54 seconds
Started Dec 24 01:08:06 PM PST 23
Finished Dec 24 01:08:33 PM PST 23
Peak memory 218140 kb
Host smart-04698ea5-d522-43d1-abab-eb213f214148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180230792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.3180230792
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.953116817
Short name T848
Test name
Test status
Simulation time 844452493 ps
CPU time 3.12 seconds
Started Dec 24 01:08:08 PM PST 23
Finished Dec 24 01:08:32 PM PST 23
Peak memory 209552 kb
Host smart-f1019ec2-a52e-4040-8eec-98dbc021093b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953116817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_ac
cess.953116817
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.1523573028
Short name T361
Test name
Test status
Simulation time 290394551 ps
CPU time 3.17 seconds
Started Dec 24 01:08:01 PM PST 23
Finished Dec 24 01:08:17 PM PST 23
Peak memory 218152 kb
Host smart-60a5b278-8b03-45c3-9331-ea7057c3fd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523573028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.1523573028
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.2555491436
Short name T788
Test name
Test status
Simulation time 322770248 ps
CPU time 12.85 seconds
Started Dec 24 01:08:06 PM PST 23
Finished Dec 24 01:08:36 PM PST 23
Peak memory 218132 kb
Host smart-c9102187-1b15-4ac9-ae64-17208c5fe66a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555491436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.2555491436
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.166113665
Short name T306
Test name
Test status
Simulation time 584214693 ps
CPU time 16.82 seconds
Started Dec 24 01:08:00 PM PST 23
Finished Dec 24 01:08:29 PM PST 23
Peak memory 218148 kb
Host smart-feed7f62-ea7c-4b6c-956c-e1f06ae59350
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166113665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.166113665
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.2206994486
Short name T933
Test name
Test status
Simulation time 969284406 ps
CPU time 9.59 seconds
Started Dec 24 01:08:05 PM PST 23
Finished Dec 24 01:08:29 PM PST 23
Peak memory 218188 kb
Host smart-d6a6fe60-1dd5-4147-82f0-2ebf4a94d957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206994486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.2206994486
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3778116628
Short name T107
Test name
Test status
Simulation time 351679282 ps
CPU time 2.26 seconds
Started Dec 24 01:07:59 PM PST 23
Finished Dec 24 01:08:14 PM PST 23
Peak memory 214160 kb
Host smart-5990962b-369f-47ec-a9b1-d04f7d83a2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778116628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3778116628
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.3417681803
Short name T353
Test name
Test status
Simulation time 365401662 ps
CPU time 38.38 seconds
Started Dec 24 01:08:05 PM PST 23
Finished Dec 24 01:08:59 PM PST 23
Peak memory 251124 kb
Host smart-73e3e890-a066-44d5-8190-aeb5864ea036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417681803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3417681803
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.3748555950
Short name T185
Test name
Test status
Simulation time 91849720 ps
CPU time 8.5 seconds
Started Dec 24 01:08:05 PM PST 23
Finished Dec 24 01:08:30 PM PST 23
Peak memory 251124 kb
Host smart-522bf3ad-0322-4334-9171-4bafa13df477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748555950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.3748555950
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.3928984435
Short name T595
Test name
Test status
Simulation time 15947594054 ps
CPU time 76.22 seconds
Started Dec 24 01:08:03 PM PST 23
Finished Dec 24 01:09:31 PM PST 23
Peak memory 277348 kb
Host smart-981fc457-206e-438b-9628-57f590d717e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928984435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.3928984435
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.4166357038
Short name T580
Test name
Test status
Simulation time 16858298874 ps
CPU time 512.99 seconds
Started Dec 24 01:08:03 PM PST 23
Finished Dec 24 01:16:49 PM PST 23
Peak memory 284080 kb
Host smart-f3a4cee9-289f-4615-8c5d-7518b5afe6ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4166357038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.4166357038
Directory /workspace/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.942127172
Short name T434
Test name
Test status
Simulation time 27222652 ps
CPU time 0.92 seconds
Started Dec 24 01:08:03 PM PST 23
Finished Dec 24 01:08:16 PM PST 23
Peak memory 211416 kb
Host smart-05558f98-325f-4426-a81e-e8d78bd3b741
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942127172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ct
rl_volatile_unlock_smoke.942127172
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.183347117
Short name T407
Test name
Test status
Simulation time 33308713 ps
CPU time 0.93 seconds
Started Dec 24 01:08:09 PM PST 23
Finished Dec 24 01:08:30 PM PST 23
Peak memory 209732 kb
Host smart-bf907c7f-083d-4d92-89e3-6f845f6caeec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183347117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.183347117
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.1501002838
Short name T917
Test name
Test status
Simulation time 1324606697 ps
CPU time 14.91 seconds
Started Dec 24 01:08:05 PM PST 23
Finished Dec 24 01:08:35 PM PST 23
Peak memory 218184 kb
Host smart-26b87002-d078-456e-88b4-2fc579575f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501002838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.1501002838
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1715039064
Short name T952
Test name
Test status
Simulation time 3559891480 ps
CPU time 7.85 seconds
Started Dec 24 01:08:02 PM PST 23
Finished Dec 24 01:08:22 PM PST 23
Peak memory 209764 kb
Host smart-19e9cee2-2e1e-43e6-ab9b-098f62b20844
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715039064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_a
ccess.1715039064
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.1015625746
Short name T842
Test name
Test status
Simulation time 161583876 ps
CPU time 3.08 seconds
Started Dec 24 01:08:06 PM PST 23
Finished Dec 24 01:08:26 PM PST 23
Peak memory 218132 kb
Host smart-3e87bfc0-d181-4232-a0a9-7ee0189c6b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015625746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.1015625746
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.1696023879
Short name T814
Test name
Test status
Simulation time 419244493 ps
CPU time 13.19 seconds
Started Dec 24 01:08:06 PM PST 23
Finished Dec 24 01:08:35 PM PST 23
Peak memory 219316 kb
Host smart-9e9c466f-1bdb-477a-8d92-dcdfbaa0393b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696023879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.1696023879
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.3280901026
Short name T768
Test name
Test status
Simulation time 534840910 ps
CPU time 10.94 seconds
Started Dec 24 01:08:03 PM PST 23
Finished Dec 24 01:08:27 PM PST 23
Peak memory 218080 kb
Host smart-da54bcc8-86e9-4f71-85c5-02e6dea94254
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280901026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.3280901026
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.2618510811
Short name T523
Test name
Test status
Simulation time 374848171 ps
CPU time 8.82 seconds
Started Dec 24 01:08:03 PM PST 23
Finished Dec 24 01:08:24 PM PST 23
Peak memory 218080 kb
Host smart-1543845d-31f2-4604-af45-cfdca9639504
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618510811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
2618510811
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.2214310900
Short name T690
Test name
Test status
Simulation time 510293118 ps
CPU time 9.75 seconds
Started Dec 24 01:08:04 PM PST 23
Finished Dec 24 01:08:26 PM PST 23
Peak memory 218188 kb
Host smart-e0e8026b-a950-49d3-9ea1-5be8e7f16b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214310900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.2214310900
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.1802733914
Short name T72
Test name
Test status
Simulation time 204184529 ps
CPU time 3.68 seconds
Started Dec 24 01:08:06 PM PST 23
Finished Dec 24 01:08:26 PM PST 23
Peak memory 214660 kb
Host smart-13e1738e-05eb-4a28-82b6-6fcebca9a3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802733914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.1802733914
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.3021732590
Short name T804
Test name
Test status
Simulation time 496960780 ps
CPU time 20.89 seconds
Started Dec 24 01:07:59 PM PST 23
Finished Dec 24 01:08:28 PM PST 23
Peak memory 251108 kb
Host smart-4eeccb54-a219-43c8-84b9-ed1d58c1d7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021732590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.3021732590
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.2187684354
Short name T594
Test name
Test status
Simulation time 311242626 ps
CPU time 7.33 seconds
Started Dec 24 01:08:05 PM PST 23
Finished Dec 24 01:08:28 PM PST 23
Peak memory 250676 kb
Host smart-4f1e594f-9244-4ca4-89f0-fc06dc29662f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187684354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.2187684354
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.891814323
Short name T110
Test name
Test status
Simulation time 10523555393 ps
CPU time 112.31 seconds
Started Dec 24 01:08:04 PM PST 23
Finished Dec 24 01:10:10 PM PST 23
Peak memory 275852 kb
Host smart-397b51bf-f60a-4f2f-8cae-5e9dc64e7483
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891814323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.891814323
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1088171647
Short name T910
Test name
Test status
Simulation time 25937657 ps
CPU time 0.85 seconds
Started Dec 24 01:08:07 PM PST 23
Finished Dec 24 01:08:27 PM PST 23
Peak memory 208288 kb
Host smart-bef8f90f-6c28-4f17-acfd-03527e05ebef
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088171647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1088171647
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.416309472
Short name T371
Test name
Test status
Simulation time 56886833 ps
CPU time 0.84 seconds
Started Dec 24 01:08:08 PM PST 23
Finished Dec 24 01:08:30 PM PST 23
Peak memory 209540 kb
Host smart-ba385342-09e1-42f8-a7a0-edde1b4a6312
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416309472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.416309472
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.3740717774
Short name T695
Test name
Test status
Simulation time 1160061191 ps
CPU time 11.48 seconds
Started Dec 24 01:08:06 PM PST 23
Finished Dec 24 01:08:33 PM PST 23
Peak memory 218232 kb
Host smart-97c9d131-82f0-4546-b5a0-8de8c08d7103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740717774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.3740717774
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.739984130
Short name T827
Test name
Test status
Simulation time 906358714 ps
CPU time 3.11 seconds
Started Dec 24 01:08:00 PM PST 23
Finished Dec 24 01:08:15 PM PST 23
Peak memory 209732 kb
Host smart-f6db5da0-737d-4d9b-b897-178627591219
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739984130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_ac
cess.739984130
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3688581079
Short name T936
Test name
Test status
Simulation time 69528588 ps
CPU time 2.96 seconds
Started Dec 24 01:08:03 PM PST 23
Finished Dec 24 01:08:19 PM PST 23
Peak memory 218112 kb
Host smart-28b157ab-2f7a-4786-be3f-fead49dde809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688581079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3688581079
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.438875878
Short name T355
Test name
Test status
Simulation time 456904838 ps
CPU time 14.82 seconds
Started Dec 24 01:08:07 PM PST 23
Finished Dec 24 01:08:42 PM PST 23
Peak memory 219328 kb
Host smart-1ea22de3-a46e-4dc2-83f4-b6f7006237ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438875878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.438875878
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2682239452
Short name T414
Test name
Test status
Simulation time 1213149511 ps
CPU time 10.32 seconds
Started Dec 24 01:08:06 PM PST 23
Finished Dec 24 01:08:32 PM PST 23
Peak memory 218144 kb
Host smart-683f2ec4-a283-4fda-9dec-1aeb0cad0cc5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682239452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.2682239452
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.1310204468
Short name T338
Test name
Test status
Simulation time 4048530549 ps
CPU time 8.12 seconds
Started Dec 24 01:08:07 PM PST 23
Finished Dec 24 01:08:36 PM PST 23
Peak memory 218292 kb
Host smart-387038ca-12d0-4321-bb65-560225808bb3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310204468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
1310204468
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.1280228154
Short name T811
Test name
Test status
Simulation time 2600778801 ps
CPU time 9.11 seconds
Started Dec 24 01:08:01 PM PST 23
Finished Dec 24 01:08:23 PM PST 23
Peak memory 218368 kb
Host smart-57d5d8b3-e97c-4e34-959c-893c8afac50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280228154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.1280228154
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.2161131329
Short name T76
Test name
Test status
Simulation time 113297353 ps
CPU time 1.91 seconds
Started Dec 24 01:08:01 PM PST 23
Finished Dec 24 01:08:16 PM PST 23
Peak memory 213552 kb
Host smart-db5b60a6-4b9d-42dd-a32f-231bd2a72cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161131329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.2161131329
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.2083930565
Short name T106
Test name
Test status
Simulation time 1365425004 ps
CPU time 26.19 seconds
Started Dec 24 01:08:05 PM PST 23
Finished Dec 24 01:08:47 PM PST 23
Peak memory 251116 kb
Host smart-21e745ca-3838-4645-8479-1aeda4358be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083930565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.2083930565
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.715518506
Short name T741
Test name
Test status
Simulation time 323882784 ps
CPU time 3.33 seconds
Started Dec 24 01:08:04 PM PST 23
Finished Dec 24 01:08:19 PM PST 23
Peak memory 226560 kb
Host smart-2e353abb-aad0-4683-8100-02c1970a737a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715518506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.715518506
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.701899202
Short name T862
Test name
Test status
Simulation time 6386088625 ps
CPU time 193.48 seconds
Started Dec 24 01:08:07 PM PST 23
Finished Dec 24 01:11:42 PM PST 23
Peak memory 251156 kb
Host smart-5224611b-d902-47f9-a704-802cbc8c66e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701899202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.701899202
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2661215400
Short name T38
Test name
Test status
Simulation time 18422516 ps
CPU time 0.86 seconds
Started Dec 24 01:08:06 PM PST 23
Finished Dec 24 01:08:25 PM PST 23
Peak memory 208096 kb
Host smart-9ef9f660-5384-4584-a7e1-38f11651d006
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661215400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.2661215400
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.4236514351
Short name T947
Test name
Test status
Simulation time 16742345 ps
CPU time 0.87 seconds
Started Dec 24 01:08:07 PM PST 23
Finished Dec 24 01:08:25 PM PST 23
Peak memory 209496 kb
Host smart-e3cd378d-bd9c-4a0d-8c13-15156aeae309
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236514351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.4236514351
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3039762447
Short name T679
Test name
Test status
Simulation time 2108772510 ps
CPU time 13.36 seconds
Started Dec 24 01:08:09 PM PST 23
Finished Dec 24 01:08:42 PM PST 23
Peak memory 218184 kb
Host smart-d3eaa047-d751-479c-a579-5da1439d68ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039762447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3039762447
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.3054403209
Short name T454
Test name
Test status
Simulation time 401225063 ps
CPU time 10.44 seconds
Started Dec 24 01:08:14 PM PST 23
Finished Dec 24 01:08:45 PM PST 23
Peak memory 209688 kb
Host smart-6868a447-999e-48ab-ae32-42f691492046
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054403209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_a
ccess.3054403209
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.607190980
Short name T519
Test name
Test status
Simulation time 26931316 ps
CPU time 2.01 seconds
Started Dec 24 01:08:06 PM PST 23
Finished Dec 24 01:08:26 PM PST 23
Peak memory 218204 kb
Host smart-b736d8c4-15dd-4c6c-8f56-d95c6ce8d9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607190980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.607190980
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.4227998847
Short name T722
Test name
Test status
Simulation time 1389853358 ps
CPU time 10.33 seconds
Started Dec 24 01:08:05 PM PST 23
Finished Dec 24 01:08:29 PM PST 23
Peak memory 218216 kb
Host smart-2007e2a1-51b8-4e27-97a8-504c5279d869
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227998847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.4227998847
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.3652904484
Short name T930
Test name
Test status
Simulation time 346237716 ps
CPU time 10.42 seconds
Started Dec 24 01:08:19 PM PST 23
Finished Dec 24 01:08:50 PM PST 23
Peak memory 218152 kb
Host smart-3f7eac5e-1c56-4567-889c-7688c7180110
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652904484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.3652904484
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.4183184573
Short name T517
Test name
Test status
Simulation time 2169809166 ps
CPU time 12.82 seconds
Started Dec 24 01:08:07 PM PST 23
Finished Dec 24 01:08:40 PM PST 23
Peak memory 218224 kb
Host smart-74411616-9884-49ed-a9d7-a35537ec6d6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183184573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
4183184573
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.858397082
Short name T667
Test name
Test status
Simulation time 603354714 ps
CPU time 9.54 seconds
Started Dec 24 01:08:06 PM PST 23
Finished Dec 24 01:08:33 PM PST 23
Peak memory 218132 kb
Host smart-9013c064-75d5-469e-9d03-372c76807ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858397082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.858397082
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.635670506
Short name T62
Test name
Test status
Simulation time 143393518 ps
CPU time 2.77 seconds
Started Dec 24 01:08:17 PM PST 23
Finished Dec 24 01:08:41 PM PST 23
Peak memory 214036 kb
Host smart-75f96294-d11d-44d7-8901-cd71a4f8e314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635670506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.635670506
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.3593406333
Short name T729
Test name
Test status
Simulation time 368339505 ps
CPU time 20.79 seconds
Started Dec 24 01:08:08 PM PST 23
Finished Dec 24 01:08:50 PM PST 23
Peak memory 251056 kb
Host smart-17dc155a-9b1b-457c-ad38-e5f0bd3d20e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593406333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.3593406333
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.3323921825
Short name T514
Test name
Test status
Simulation time 94737385 ps
CPU time 3.72 seconds
Started Dec 24 01:08:16 PM PST 23
Finished Dec 24 01:08:41 PM PST 23
Peak memory 222392 kb
Host smart-b7dac176-ba51-4675-8634-f2f0a319249d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323921825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.3323921825
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.1704756437
Short name T666
Test name
Test status
Simulation time 22645441026 ps
CPU time 421.65 seconds
Started Dec 24 01:08:09 PM PST 23
Finished Dec 24 01:15:33 PM PST 23
Peak memory 251280 kb
Host smart-7fc4864f-6816-41cb-aa0e-1072ed8b2b2e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704756437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.1704756437
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.4458964
Short name T564
Test name
Test status
Simulation time 20043193 ps
CPU time 0.91 seconds
Started Dec 24 01:08:04 PM PST 23
Finished Dec 24 01:08:18 PM PST 23
Peak memory 208152 kb
Host smart-a4bd2683-940d-4890-afbc-fbcea637d981
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4458964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vola
tile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl
_volatile_unlock_smoke.4458964
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.1507482872
Short name T681
Test name
Test status
Simulation time 56889043 ps
CPU time 0.96 seconds
Started Dec 24 01:08:11 PM PST 23
Finished Dec 24 01:08:30 PM PST 23
Peak memory 208256 kb
Host smart-488c2eca-dfa1-4c5f-9bf0-7dc221ab0e5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507482872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.1507482872
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.2568215066
Short name T1
Test name
Test status
Simulation time 343103477 ps
CPU time 15.59 seconds
Started Dec 24 01:08:08 PM PST 23
Finished Dec 24 01:08:44 PM PST 23
Peak memory 218208 kb
Host smart-edb8be38-c02a-4df8-8c2d-10e7a13c5b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568215066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.2568215066
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.3181876205
Short name T12
Test name
Test status
Simulation time 82384224 ps
CPU time 1.73 seconds
Started Dec 24 01:08:04 PM PST 23
Finished Dec 24 01:08:19 PM PST 23
Peak memory 209692 kb
Host smart-0f32c6dd-5e66-405c-aed5-a88d871cf5f7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181876205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_a
ccess.3181876205
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.1732905090
Short name T395
Test name
Test status
Simulation time 23832567 ps
CPU time 1.68 seconds
Started Dec 24 01:08:08 PM PST 23
Finished Dec 24 01:08:31 PM PST 23
Peak memory 218028 kb
Host smart-8fb0dbb3-2898-4774-b953-e716c4addb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732905090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.1732905090
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.303404489
Short name T812
Test name
Test status
Simulation time 1663746365 ps
CPU time 14.58 seconds
Started Dec 24 01:08:08 PM PST 23
Finished Dec 24 01:08:43 PM PST 23
Peak memory 219232 kb
Host smart-804eb01f-5821-4421-8abc-5a826e12c265
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303404489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.303404489
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.1858151500
Short name T942
Test name
Test status
Simulation time 202697887 ps
CPU time 9.28 seconds
Started Dec 24 01:08:10 PM PST 23
Finished Dec 24 01:08:38 PM PST 23
Peak memory 218160 kb
Host smart-cca0678a-3e9c-4fb0-bcab-2472e19b89e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858151500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.1858151500
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.1461543014
Short name T354
Test name
Test status
Simulation time 954235357 ps
CPU time 9.49 seconds
Started Dec 24 01:08:10 PM PST 23
Finished Dec 24 01:08:38 PM PST 23
Peak memory 218124 kb
Host smart-d008ce11-9fd2-4d1c-bc5c-c30ebd0515ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461543014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
1461543014
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.1618642922
Short name T41
Test name
Test status
Simulation time 635471338 ps
CPU time 7.29 seconds
Started Dec 24 01:08:08 PM PST 23
Finished Dec 24 01:08:36 PM PST 23
Peak memory 218036 kb
Host smart-e37f9cca-4e6d-4e1f-9c06-e490e142ed78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618642922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.1618642922
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.33174624
Short name T409
Test name
Test status
Simulation time 40296380 ps
CPU time 1.6 seconds
Started Dec 24 01:08:09 PM PST 23
Finished Dec 24 01:08:30 PM PST 23
Peak memory 213316 kb
Host smart-c34d6228-2c1a-4dbe-a4a2-e4b07ef36b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33174624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.33174624
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.1166607757
Short name T553
Test name
Test status
Simulation time 312480231 ps
CPU time 34.88 seconds
Started Dec 24 01:08:09 PM PST 23
Finished Dec 24 01:09:06 PM PST 23
Peak memory 250940 kb
Host smart-2a002064-4266-4229-8c30-67d29411f222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166607757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.1166607757
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.970502485
Short name T689
Test name
Test status
Simulation time 67812732 ps
CPU time 3.24 seconds
Started Dec 24 01:08:05 PM PST 23
Finished Dec 24 01:08:25 PM PST 23
Peak memory 218228 kb
Host smart-71048083-b939-4226-bea6-defe8062926a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970502485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.970502485
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.1795248890
Short name T975
Test name
Test status
Simulation time 985718137 ps
CPU time 32.33 seconds
Started Dec 24 01:08:11 PM PST 23
Finished Dec 24 01:09:01 PM PST 23
Peak memory 251224 kb
Host smart-dc29dee5-556c-42f5-bec8-f5197411668a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795248890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.1795248890
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.500123424
Short name T723
Test name
Test status
Simulation time 21082349 ps
CPU time 0.94 seconds
Started Dec 24 01:08:08 PM PST 23
Finished Dec 24 01:08:30 PM PST 23
Peak memory 208168 kb
Host smart-05f5e22e-e50c-468f-b872-24ecfa2316fd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500123424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ct
rl_volatile_unlock_smoke.500123424
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.1698422254
Short name T778
Test name
Test status
Simulation time 34212220 ps
CPU time 0.89 seconds
Started Dec 24 01:06:22 PM PST 23
Finished Dec 24 01:06:24 PM PST 23
Peak memory 209608 kb
Host smart-729b4e37-2886-4a70-83bf-e7bbcc085d45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698422254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.1698422254
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.340685017
Short name T823
Test name
Test status
Simulation time 524207924 ps
CPU time 12.04 seconds
Started Dec 24 01:06:47 PM PST 23
Finished Dec 24 01:07:01 PM PST 23
Peak memory 218208 kb
Host smart-fd5d441f-ae1c-4d7a-8989-a3a62bcccc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340685017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.340685017
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.1505896216
Short name T25
Test name
Test status
Simulation time 534406768 ps
CPU time 6.91 seconds
Started Dec 24 01:06:41 PM PST 23
Finished Dec 24 01:06:48 PM PST 23
Peak memory 209664 kb
Host smart-68901b30-cd43-4efc-86e0-d4d86b837270
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505896216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_ac
cess.1505896216
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.1945353780
Short name T389
Test name
Test status
Simulation time 2018559593 ps
CPU time 28.71 seconds
Started Dec 24 01:06:22 PM PST 23
Finished Dec 24 01:06:51 PM PST 23
Peak memory 218144 kb
Host smart-36dbd91e-465b-4188-8411-169d92d3b56d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945353780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.1945353780
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.282411887
Short name T653
Test name
Test status
Simulation time 5648101158 ps
CPU time 6.74 seconds
Started Dec 24 01:06:51 PM PST 23
Finished Dec 24 01:07:03 PM PST 23
Peak memory 209740 kb
Host smart-df1f164c-e78a-4a76-8465-c065122f2474
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282411887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_p
riority.282411887
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.909292870
Short name T464
Test name
Test status
Simulation time 2524749728 ps
CPU time 17.69 seconds
Started Dec 24 01:06:44 PM PST 23
Finished Dec 24 01:07:04 PM PST 23
Peak memory 218136 kb
Host smart-7b7e3ca7-c365-40d0-8eeb-e6c14accb0cc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909292870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_
prog_failure.909292870
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.230175726
Short name T387
Test name
Test status
Simulation time 4446200543 ps
CPU time 32.41 seconds
Started Dec 24 01:06:45 PM PST 23
Finished Dec 24 01:07:20 PM PST 23
Peak memory 213760 kb
Host smart-fb56e8a6-329b-4f0a-aad6-bc60948b7742
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230175726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_regwen_during_op.230175726
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.2904944442
Short name T82
Test name
Test status
Simulation time 379767260 ps
CPU time 2.49 seconds
Started Dec 24 01:06:44 PM PST 23
Finished Dec 24 01:06:49 PM PST 23
Peak memory 213048 kb
Host smart-96fa6c54-139d-4d48-bfc8-5dd561f8c3d3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904944442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
2904944442
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2156125011
Short name T775
Test name
Test status
Simulation time 3912009183 ps
CPU time 43.65 seconds
Started Dec 24 01:06:50 PM PST 23
Finished Dec 24 01:07:38 PM PST 23
Peak memory 251160 kb
Host smart-241118a7-4e58-4b27-b724-da62721a59ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156125011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.2156125011
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.75500883
Short name T412
Test name
Test status
Simulation time 642804566 ps
CPU time 16.21 seconds
Started Dec 24 01:06:31 PM PST 23
Finished Dec 24 01:06:49 PM PST 23
Peak memory 249172 kb
Host smart-6e09c0ef-74e8-4d79-af32-e2e1ea9c5d54
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75500883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jt
ag_state_post_trans.75500883
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.2200523943
Short name T402
Test name
Test status
Simulation time 18575323 ps
CPU time 1.45 seconds
Started Dec 24 01:06:44 PM PST 23
Finished Dec 24 01:06:48 PM PST 23
Peak memory 218176 kb
Host smart-0f8b02cf-110f-4765-a291-8e24ebfe0a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200523943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.2200523943
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.3231828694
Short name T78
Test name
Test status
Simulation time 328547459 ps
CPU time 16.41 seconds
Started Dec 24 01:06:23 PM PST 23
Finished Dec 24 01:06:40 PM PST 23
Peak memory 218000 kb
Host smart-ab303e36-9a17-4d96-85ef-cd21d1238108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231828694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.3231828694
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.3243991886
Short name T56
Test name
Test status
Simulation time 952725777 ps
CPU time 21.59 seconds
Started Dec 24 01:06:12 PM PST 23
Finished Dec 24 01:06:35 PM PST 23
Peak memory 272276 kb
Host smart-447d4027-c838-4956-bd29-d1c4a1fbf6b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243991886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.3243991886
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.1251658317
Short name T786
Test name
Test status
Simulation time 1672901393 ps
CPU time 13.79 seconds
Started Dec 24 01:06:19 PM PST 23
Finished Dec 24 01:06:34 PM PST 23
Peak memory 219180 kb
Host smart-366e93fb-c451-4010-bfe4-7c0c70979d8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251658317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.1251658317
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.1965487999
Short name T3
Test name
Test status
Simulation time 235156930 ps
CPU time 11.49 seconds
Started Dec 24 01:06:21 PM PST 23
Finished Dec 24 01:06:34 PM PST 23
Peak memory 218120 kb
Host smart-c327bd62-cb27-48e9-9dd4-2f8d05db790d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965487999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.1965487999
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1187939802
Short name T307
Test name
Test status
Simulation time 290225882 ps
CPU time 8.1 seconds
Started Dec 24 01:06:11 PM PST 23
Finished Dec 24 01:06:20 PM PST 23
Peak memory 218084 kb
Host smart-5d7f2f5d-f326-4a42-ae5c-cea71ed330df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187939802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.1
187939802
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.631087222
Short name T575
Test name
Test status
Simulation time 301930646 ps
CPU time 8.82 seconds
Started Dec 24 01:06:22 PM PST 23
Finished Dec 24 01:06:32 PM PST 23
Peak memory 218200 kb
Host smart-335c4218-c2b4-44bc-a232-127086b5f3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631087222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.631087222
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.1516100270
Short name T579
Test name
Test status
Simulation time 170224067 ps
CPU time 3.21 seconds
Started Dec 24 01:06:46 PM PST 23
Finished Dec 24 01:06:51 PM PST 23
Peak memory 214532 kb
Host smart-4ed2ff76-c001-4bf5-b996-8332142ae7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516100270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.1516100270
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.665452145
Short name T343
Test name
Test status
Simulation time 1659066118 ps
CPU time 33.65 seconds
Started Dec 24 01:06:12 PM PST 23
Finished Dec 24 01:06:46 PM PST 23
Peak memory 250188 kb
Host smart-bceb48b5-c46b-49c4-a1b8-3d4dd0570eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665452145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.665452145
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.4160021359
Short name T418
Test name
Test status
Simulation time 205785262 ps
CPU time 3.55 seconds
Started Dec 24 01:06:23 PM PST 23
Finished Dec 24 01:06:28 PM PST 23
Peak memory 218220 kb
Host smart-c7530c64-a1d2-4666-b9af-4dc7dc560254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160021359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.4160021359
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.2010605660
Short name T675
Test name
Test status
Simulation time 6722449802 ps
CPU time 150.54 seconds
Started Dec 24 01:06:23 PM PST 23
Finished Dec 24 01:08:54 PM PST 23
Peak memory 267796 kb
Host smart-8847c6a0-2e50-4330-bb2d-8c0490b6b974
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010605660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.2010605660
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.3087520841
Short name T49
Test name
Test status
Simulation time 11341559892 ps
CPU time 466.3 seconds
Started Dec 24 01:06:17 PM PST 23
Finished Dec 24 01:14:04 PM PST 23
Peak memory 497136 kb
Host smart-d016190d-0d5d-48e0-9a27-11948c6b9397
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3087520841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.3087520841
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.4012668070
Short name T363
Test name
Test status
Simulation time 19411023 ps
CPU time 1.11 seconds
Started Dec 24 01:08:10 PM PST 23
Finished Dec 24 01:08:30 PM PST 23
Peak memory 209760 kb
Host smart-f1b082f6-f509-4b91-9562-fdaae85bc663
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012668070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.4012668070
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.3911221469
Short name T48
Test name
Test status
Simulation time 1312097710 ps
CPU time 13.98 seconds
Started Dec 24 01:08:06 PM PST 23
Finished Dec 24 01:08:43 PM PST 23
Peak memory 218156 kb
Host smart-657fd7d7-a633-4d34-8efd-f0edad17ff3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911221469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.3911221469
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.1183228364
Short name T669
Test name
Test status
Simulation time 946681968 ps
CPU time 2.33 seconds
Started Dec 24 01:08:30 PM PST 23
Finished Dec 24 01:08:47 PM PST 23
Peak memory 209688 kb
Host smart-9840000b-9158-4ade-9268-30972e9380e2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183228364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_a
ccess.1183228364
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.375380414
Short name T710
Test name
Test status
Simulation time 18028926 ps
CPU time 1.66 seconds
Started Dec 24 01:08:09 PM PST 23
Finished Dec 24 01:08:31 PM PST 23
Peak memory 218192 kb
Host smart-ca796d91-a382-40bf-b881-a13af865dca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375380414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.375380414
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.4098399312
Short name T967
Test name
Test status
Simulation time 214985097 ps
CPU time 9.15 seconds
Started Dec 24 01:08:36 PM PST 23
Finished Dec 24 01:08:55 PM PST 23
Peak memory 218240 kb
Host smart-8c4435e0-5305-4db8-940c-c2d7b2a11cd8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098399312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.4098399312
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.2437343564
Short name T796
Test name
Test status
Simulation time 5027316963 ps
CPU time 9.16 seconds
Started Dec 24 01:08:11 PM PST 23
Finished Dec 24 01:08:38 PM PST 23
Peak memory 218292 kb
Host smart-d2a3ed4c-af7a-4773-895e-a5be3401cbe0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437343564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.2437343564
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.3983188201
Short name T558
Test name
Test status
Simulation time 566438874 ps
CPU time 8.91 seconds
Started Dec 24 01:08:12 PM PST 23
Finished Dec 24 01:08:41 PM PST 23
Peak memory 218104 kb
Host smart-664495ef-0e0b-4f41-b3d2-14904bae0382
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983188201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
3983188201
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.1009526725
Short name T770
Test name
Test status
Simulation time 1227188360 ps
CPU time 11.07 seconds
Started Dec 24 01:08:11 PM PST 23
Finished Dec 24 01:08:42 PM PST 23
Peak memory 218140 kb
Host smart-4717fbec-4637-4342-be18-557d6c334ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009526725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.1009526725
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.653197330
Short name T726
Test name
Test status
Simulation time 76139308 ps
CPU time 1.66 seconds
Started Dec 24 01:08:09 PM PST 23
Finished Dec 24 01:08:31 PM PST 23
Peak memory 213372 kb
Host smart-ee866831-66d3-4c92-abb6-dcd37d0ea7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653197330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.653197330
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.1526700603
Short name T637
Test name
Test status
Simulation time 1707542616 ps
CPU time 27.39 seconds
Started Dec 24 01:08:09 PM PST 23
Finished Dec 24 01:08:56 PM PST 23
Peak memory 251080 kb
Host smart-48affc94-125f-4257-99b7-bbfacad1011c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526700603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.1526700603
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.3112257464
Short name T316
Test name
Test status
Simulation time 52708694 ps
CPU time 5.92 seconds
Started Dec 24 01:08:04 PM PST 23
Finished Dec 24 01:08:22 PM PST 23
Peak memory 246124 kb
Host smart-28909069-7687-4122-8bda-e0bfb45843be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112257464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.3112257464
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.937271889
Short name T17
Test name
Test status
Simulation time 3605218157 ps
CPU time 33.63 seconds
Started Dec 24 01:08:23 PM PST 23
Finished Dec 24 01:09:16 PM PST 23
Peak memory 248884 kb
Host smart-38b6996d-2d58-4c2d-8239-88ef7badef1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937271889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.937271889
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.557621319
Short name T893
Test name
Test status
Simulation time 23640638 ps
CPU time 0.94 seconds
Started Dec 24 01:08:10 PM PST 23
Finished Dec 24 01:08:30 PM PST 23
Peak memory 208096 kb
Host smart-a1d8f26e-b6d7-4ddd-8132-db4deeb86ca0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557621319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ct
rl_volatile_unlock_smoke.557621319
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.2546913388
Short name T744
Test name
Test status
Simulation time 157625269 ps
CPU time 0.98 seconds
Started Dec 24 01:08:17 PM PST 23
Finished Dec 24 01:08:39 PM PST 23
Peak memory 209656 kb
Host smart-6f42f7cd-78c2-44f6-a6d0-123b6fed1261
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546913388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.2546913388
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.3171387492
Short name T931
Test name
Test status
Simulation time 1152045224 ps
CPU time 12.2 seconds
Started Dec 24 01:08:28 PM PST 23
Finished Dec 24 01:08:56 PM PST 23
Peak memory 218208 kb
Host smart-4bc55460-752f-4a55-9f03-013cc199c70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171387492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.3171387492
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.2609385570
Short name T915
Test name
Test status
Simulation time 341618648 ps
CPU time 5.7 seconds
Started Dec 24 01:08:26 PM PST 23
Finished Dec 24 01:08:49 PM PST 23
Peak memory 209692 kb
Host smart-b1ed2b7e-e173-4821-9e80-b893b6398ff3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609385570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_a
ccess.2609385570
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.4135049700
Short name T449
Test name
Test status
Simulation time 108663817 ps
CPU time 3.49 seconds
Started Dec 24 01:08:14 PM PST 23
Finished Dec 24 01:08:38 PM PST 23
Peak memory 218204 kb
Host smart-f4752934-0b9f-4b5c-a0e1-5beeca9eda45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135049700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.4135049700
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.2374299597
Short name T65
Test name
Test status
Simulation time 769539679 ps
CPU time 8.15 seconds
Started Dec 24 01:08:18 PM PST 23
Finished Dec 24 01:08:47 PM PST 23
Peak memory 218224 kb
Host smart-5600a0d5-fdd0-40da-b0fc-654d0c2a397f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374299597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2374299597
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.3282990128
Short name T360
Test name
Test status
Simulation time 1570667207 ps
CPU time 13.59 seconds
Started Dec 24 01:08:22 PM PST 23
Finished Dec 24 01:08:56 PM PST 23
Peak memory 218040 kb
Host smart-7a127f86-cf95-4ce4-8343-e020da4ab0df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282990128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.3282990128
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3530191702
Short name T642
Test name
Test status
Simulation time 1785040286 ps
CPU time 11.65 seconds
Started Dec 24 01:08:32 PM PST 23
Finished Dec 24 01:08:57 PM PST 23
Peak memory 218160 kb
Host smart-5dd3d82a-d594-4921-9f43-51be12a11722
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530191702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
3530191702
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.2898824586
Short name T785
Test name
Test status
Simulation time 55817262 ps
CPU time 2.17 seconds
Started Dec 24 01:08:36 PM PST 23
Finished Dec 24 01:08:48 PM PST 23
Peak memory 213556 kb
Host smart-188d7213-1a20-44e2-a936-d3877e03d156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898824586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.2898824586
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.3560141722
Short name T938
Test name
Test status
Simulation time 276525210 ps
CPU time 23.11 seconds
Started Dec 24 01:08:29 PM PST 23
Finished Dec 24 01:09:07 PM PST 23
Peak memory 251140 kb
Host smart-04637e87-c087-4ada-a28a-ba1621cf1aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560141722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.3560141722
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.836648974
Short name T568
Test name
Test status
Simulation time 47070066 ps
CPU time 7.58 seconds
Started Dec 24 01:08:10 PM PST 23
Finished Dec 24 01:08:36 PM PST 23
Peak memory 251300 kb
Host smart-00f8429d-1982-4177-89dc-06a0b915b937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836648974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.836648974
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.3231066815
Short name T657
Test name
Test status
Simulation time 10746312892 ps
CPU time 157.27 seconds
Started Dec 24 01:08:41 PM PST 23
Finished Dec 24 01:11:26 PM PST 23
Peak memory 227024 kb
Host smart-fba25758-8e12-4726-bd16-4ea083f9ef5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231066815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.3231066815
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2396931795
Short name T757
Test name
Test status
Simulation time 38121994 ps
CPU time 0.79 seconds
Started Dec 24 01:08:14 PM PST 23
Finished Dec 24 01:08:35 PM PST 23
Peak memory 208264 kb
Host smart-13a9dd16-8079-493c-805d-66b3c0acdc52
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396931795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.2396931795
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.1166734931
Short name T529
Test name
Test status
Simulation time 15748260 ps
CPU time 0.9 seconds
Started Dec 24 01:08:16 PM PST 23
Finished Dec 24 01:08:38 PM PST 23
Peak memory 209648 kb
Host smart-77292f83-8bb3-4cd1-b811-cdd6d4d54d69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166734931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.1166734931
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.791048705
Short name T818
Test name
Test status
Simulation time 376452928 ps
CPU time 16.17 seconds
Started Dec 24 01:08:29 PM PST 23
Finished Dec 24 01:09:00 PM PST 23
Peak memory 218224 kb
Host smart-5b07a430-ff46-4cbe-a773-3ee13eee47c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791048705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.791048705
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.822307140
Short name T721
Test name
Test status
Simulation time 1091991141 ps
CPU time 7.58 seconds
Started Dec 24 01:08:18 PM PST 23
Finished Dec 24 01:08:48 PM PST 23
Peak memory 209692 kb
Host smart-0e807776-fa94-4c47-85b9-3749ba316ff8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822307140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_ac
cess.822307140
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.2875204730
Short name T351
Test name
Test status
Simulation time 160954042 ps
CPU time 2.17 seconds
Started Dec 24 01:08:33 PM PST 23
Finished Dec 24 01:08:48 PM PST 23
Peak memory 218212 kb
Host smart-22e34dca-eb0b-4faf-934b-b7bd0bd407f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875204730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.2875204730
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.54818026
Short name T939
Test name
Test status
Simulation time 232850637 ps
CPU time 8.64 seconds
Started Dec 24 01:08:13 PM PST 23
Finished Dec 24 01:08:41 PM PST 23
Peak memory 218204 kb
Host smart-a2e38f85-6f73-44d3-b7a2-c968fc27f738
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54818026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.54818026
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.2479858626
Short name T703
Test name
Test status
Simulation time 528209634 ps
CPU time 14.27 seconds
Started Dec 24 01:08:19 PM PST 23
Finished Dec 24 01:08:55 PM PST 23
Peak memory 218060 kb
Host smart-5fbdb1e8-ffed-423a-a727-e40c5c90d1a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479858626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.2479858626
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.2114926641
Short name T561
Test name
Test status
Simulation time 1036994759 ps
CPU time 11.73 seconds
Started Dec 24 01:08:11 PM PST 23
Finished Dec 24 01:08:41 PM PST 23
Peak memory 218080 kb
Host smart-2d559ba9-3324-44ac-bf51-06bf6e327173
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114926641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
2114926641
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.3261506567
Short name T61
Test name
Test status
Simulation time 281022123 ps
CPU time 9.61 seconds
Started Dec 24 01:08:25 PM PST 23
Finished Dec 24 01:08:53 PM PST 23
Peak memory 218208 kb
Host smart-fdf25d2a-9583-460e-86fd-d9187cc8332b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261506567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3261506567
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.438526929
Short name T979
Test name
Test status
Simulation time 43792639 ps
CPU time 1.74 seconds
Started Dec 24 01:08:31 PM PST 23
Finished Dec 24 01:08:47 PM PST 23
Peak memory 213572 kb
Host smart-a12150d4-8777-41ea-b49f-034777b5c685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438526929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.438526929
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.3399841227
Short name T972
Test name
Test status
Simulation time 233462800 ps
CPU time 27.08 seconds
Started Dec 24 01:08:29 PM PST 23
Finished Dec 24 01:09:11 PM PST 23
Peak memory 251136 kb
Host smart-c9bb7092-0832-41b2-9b5a-0f7933c8fa87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399841227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.3399841227
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.3138502136
Short name T460
Test name
Test status
Simulation time 60063335 ps
CPU time 3.71 seconds
Started Dec 24 01:08:14 PM PST 23
Finished Dec 24 01:08:39 PM PST 23
Peak memory 226532 kb
Host smart-f238f7d4-59d9-4119-9e22-e089fd07e470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138502136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.3138502136
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.762706522
Short name T903
Test name
Test status
Simulation time 5039128134 ps
CPU time 101.05 seconds
Started Dec 24 01:08:13 PM PST 23
Finished Dec 24 01:10:13 PM PST 23
Peak memory 273040 kb
Host smart-d954a974-9558-480f-b635-195286f3e0a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762706522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.762706522
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.1659699599
Short name T479
Test name
Test status
Simulation time 19216543 ps
CPU time 0.85 seconds
Started Dec 24 01:08:12 PM PST 23
Finished Dec 24 01:08:34 PM PST 23
Peak memory 208192 kb
Host smart-d988d336-5cb0-406e-adb5-f2f2a1a51aac
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659699599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.1659699599
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.843039781
Short name T665
Test name
Test status
Simulation time 34842026 ps
CPU time 0.84 seconds
Started Dec 24 01:08:36 PM PST 23
Finished Dec 24 01:08:47 PM PST 23
Peak memory 208076 kb
Host smart-940305e0-f492-40a2-94b7-b6dfc65efdc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843039781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.843039781
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.3981522635
Short name T747
Test name
Test status
Simulation time 1131565390 ps
CPU time 13.88 seconds
Started Dec 24 01:08:41 PM PST 23
Finished Dec 24 01:09:02 PM PST 23
Peak memory 218148 kb
Host smart-b030796c-5b08-47e0-adbc-17f33ff8108d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981522635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3981522635
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.4167801062
Short name T808
Test name
Test status
Simulation time 558062110 ps
CPU time 3.98 seconds
Started Dec 24 01:08:35 PM PST 23
Finished Dec 24 01:08:50 PM PST 23
Peak memory 209616 kb
Host smart-a5e3ac45-5d16-4bfd-a554-9c17bfb8d479
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167801062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_a
ccess.4167801062
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.3720457363
Short name T337
Test name
Test status
Simulation time 37761867 ps
CPU time 1.6 seconds
Started Dec 24 01:08:42 PM PST 23
Finished Dec 24 01:08:51 PM PST 23
Peak memory 218188 kb
Host smart-b28052fa-a14b-444c-afc3-34c87a35ad65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720457363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.3720457363
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.3367588509
Short name T682
Test name
Test status
Simulation time 300234474 ps
CPU time 13.69 seconds
Started Dec 24 01:08:34 PM PST 23
Finished Dec 24 01:08:59 PM PST 23
Peak memory 219120 kb
Host smart-9aa0e3a9-c8e4-48d3-8a05-67a86d35c270
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367588509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.3367588509
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.618952897
Short name T969
Test name
Test status
Simulation time 4255797347 ps
CPU time 12.1 seconds
Started Dec 24 01:08:26 PM PST 23
Finished Dec 24 01:08:56 PM PST 23
Peak memory 218200 kb
Host smart-54b139d5-b95c-4776-8db9-27ce37f0ea1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618952897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_di
gest.618952897
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.2624723471
Short name T375
Test name
Test status
Simulation time 1078505232 ps
CPU time 9.83 seconds
Started Dec 24 01:08:34 PM PST 23
Finished Dec 24 01:08:55 PM PST 23
Peak memory 218036 kb
Host smart-f0215a27-68c1-450a-8130-8e77bf43399a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624723471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
2624723471
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.3025953481
Short name T632
Test name
Test status
Simulation time 261415184 ps
CPU time 10.41 seconds
Started Dec 24 01:08:21 PM PST 23
Finished Dec 24 01:08:51 PM PST 23
Peak memory 218196 kb
Host smart-ae62e1a5-2a55-4881-92d1-ac50140557a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025953481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.3025953481
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.2971402602
Short name T70
Test name
Test status
Simulation time 26805947 ps
CPU time 1.46 seconds
Started Dec 24 01:08:35 PM PST 23
Finished Dec 24 01:08:47 PM PST 23
Peak memory 213156 kb
Host smart-4ea3a943-e571-468e-972f-29294ecec825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971402602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.2971402602
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.238099030
Short name T391
Test name
Test status
Simulation time 260556651 ps
CPU time 31.77 seconds
Started Dec 24 01:08:46 PM PST 23
Finished Dec 24 01:09:24 PM PST 23
Peak memory 250700 kb
Host smart-5eb111ff-9873-470a-b591-711a6661f5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238099030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.238099030
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.2780155015
Short name T756
Test name
Test status
Simulation time 62911532 ps
CPU time 3.37 seconds
Started Dec 24 01:08:32 PM PST 23
Finished Dec 24 01:08:49 PM PST 23
Peak memory 222116 kb
Host smart-486f000d-8e5f-4539-8b77-1374984010e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780155015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.2780155015
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.1897405800
Short name T365
Test name
Test status
Simulation time 5059705605 ps
CPU time 28.37 seconds
Started Dec 24 01:08:32 PM PST 23
Finished Dec 24 01:09:14 PM PST 23
Peak memory 251212 kb
Host smart-0f156151-be5b-40da-8f87-d53f9bd53334
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897405800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.1897405800
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.493338961
Short name T850
Test name
Test status
Simulation time 29532218 ps
CPU time 0.84 seconds
Started Dec 24 01:08:16 PM PST 23
Finished Dec 24 01:08:39 PM PST 23
Peak memory 208064 kb
Host smart-7e202aff-0842-4c2c-a373-6122699d1a9d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493338961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ct
rl_volatile_unlock_smoke.493338961
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.3873341535
Short name T674
Test name
Test status
Simulation time 18155601 ps
CPU time 1.05 seconds
Started Dec 24 01:08:48 PM PST 23
Finished Dec 24 01:08:55 PM PST 23
Peak memory 209636 kb
Host smart-8d7a1414-eb3d-4bf0-a54d-279af6d8feee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873341535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.3873341535
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.4152351585
Short name T660
Test name
Test status
Simulation time 1458171994 ps
CPU time 12.83 seconds
Started Dec 24 01:08:34 PM PST 23
Finished Dec 24 01:08:59 PM PST 23
Peak memory 218156 kb
Host smart-607dce38-8f42-4c19-81ad-e500d421d60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152351585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.4152351585
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.141744819
Short name T795
Test name
Test status
Simulation time 1195219986 ps
CPU time 6.65 seconds
Started Dec 24 01:08:30 PM PST 23
Finished Dec 24 01:08:52 PM PST 23
Peak memory 209724 kb
Host smart-310349ef-e80d-4d50-b055-4ed16801f2ac
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141744819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_ac
cess.141744819
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.3954795858
Short name T611
Test name
Test status
Simulation time 95762819 ps
CPU time 2.52 seconds
Started Dec 24 01:08:32 PM PST 23
Finished Dec 24 01:08:48 PM PST 23
Peak memory 218108 kb
Host smart-c4957e3a-a885-4ded-b321-dfb5c1c0a930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954795858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.3954795858
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.1716256554
Short name T974
Test name
Test status
Simulation time 462442427 ps
CPU time 19.28 seconds
Started Dec 24 01:08:34 PM PST 23
Finished Dec 24 01:09:05 PM PST 23
Peak memory 218960 kb
Host smart-2222e973-7420-42cc-9bf9-1123836a8b44
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716256554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.1716256554
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.815488874
Short name T869
Test name
Test status
Simulation time 703853585 ps
CPU time 14.45 seconds
Started Dec 24 01:08:36 PM PST 23
Finished Dec 24 01:09:00 PM PST 23
Peak memory 218156 kb
Host smart-3fa5d0bb-cb0f-496a-8c9c-7c19d29cc7a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815488874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_di
gest.815488874
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.1800912069
Short name T319
Test name
Test status
Simulation time 522178268 ps
CPU time 6.62 seconds
Started Dec 24 01:08:33 PM PST 23
Finished Dec 24 01:08:52 PM PST 23
Peak memory 218140 kb
Host smart-51c4ad41-6c98-439b-a11b-8a5ffddc867b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800912069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
1800912069
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.3172400552
Short name T668
Test name
Test status
Simulation time 329430073 ps
CPU time 8.13 seconds
Started Dec 24 01:08:37 PM PST 23
Finished Dec 24 01:08:54 PM PST 23
Peak memory 218148 kb
Host smart-6d4b8304-4eba-4570-a99c-079f1c4cdc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172400552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.3172400552
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.3177741436
Short name T698
Test name
Test status
Simulation time 145741610 ps
CPU time 2.05 seconds
Started Dec 24 01:08:22 PM PST 23
Finished Dec 24 01:08:44 PM PST 23
Peak memory 213792 kb
Host smart-2778ab14-7416-4615-a0b8-ff18a7f55ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177741436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.3177741436
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1975032171
Short name T399
Test name
Test status
Simulation time 1266629013 ps
CPU time 27.94 seconds
Started Dec 24 01:08:13 PM PST 23
Finished Dec 24 01:09:01 PM PST 23
Peak memory 251124 kb
Host smart-1b250130-24be-4f96-a71f-12b561089b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975032171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1975032171
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.1524251300
Short name T705
Test name
Test status
Simulation time 166040655 ps
CPU time 8.8 seconds
Started Dec 24 01:08:23 PM PST 23
Finished Dec 24 01:08:51 PM PST 23
Peak memory 251148 kb
Host smart-0111d81e-69a6-4009-99a1-69f785a8a71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524251300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.1524251300
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.494544399
Short name T874
Test name
Test status
Simulation time 5448376984 ps
CPU time 115.51 seconds
Started Dec 24 01:08:30 PM PST 23
Finished Dec 24 01:10:41 PM PST 23
Peak memory 268108 kb
Host smart-48c7d6c7-f41e-47c8-a222-ead9e52c2dec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494544399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.494544399
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.5016685
Short name T35
Test name
Test status
Simulation time 14730398 ps
CPU time 0.79 seconds
Started Dec 24 01:08:18 PM PST 23
Finished Dec 24 01:08:41 PM PST 23
Peak memory 208252 kb
Host smart-c5dddbba-2395-40d5-a6cd-f17335ce4fa1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5016685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vola
tile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl
_volatile_unlock_smoke.5016685
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.4247219839
Short name T310
Test name
Test status
Simulation time 38328002 ps
CPU time 1.16 seconds
Started Dec 24 01:08:33 PM PST 23
Finished Dec 24 01:08:47 PM PST 23
Peak memory 209692 kb
Host smart-c4f77592-6ede-4047-b226-7a8a6003fdec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247219839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.4247219839
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.691616975
Short name T569
Test name
Test status
Simulation time 218624312 ps
CPU time 11.85 seconds
Started Dec 24 01:08:36 PM PST 23
Finished Dec 24 01:08:58 PM PST 23
Peak memory 218188 kb
Host smart-4cc729b7-d3a5-430b-9fcd-9653e67024e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691616975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.691616975
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.2335216406
Short name T21
Test name
Test status
Simulation time 1022552521 ps
CPU time 12.81 seconds
Started Dec 24 01:08:43 PM PST 23
Finished Dec 24 01:09:03 PM PST 23
Peak memory 209600 kb
Host smart-45f85f1c-1e22-453a-a80c-03f30a29a722
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335216406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_a
ccess.2335216406
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.118966390
Short name T617
Test name
Test status
Simulation time 46478521 ps
CPU time 1.74 seconds
Started Dec 24 01:08:33 PM PST 23
Finished Dec 24 01:08:47 PM PST 23
Peak memory 218204 kb
Host smart-ce72f340-205b-4714-92c4-2fbd9c2a3e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118966390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.118966390
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.475169446
Short name T856
Test name
Test status
Simulation time 3504047448 ps
CPU time 14.53 seconds
Started Dec 24 01:08:42 PM PST 23
Finished Dec 24 01:09:03 PM PST 23
Peak memory 220336 kb
Host smart-d2358c35-234f-4008-a2f5-0107c9e705eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475169446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.475169446
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.1434577402
Short name T60
Test name
Test status
Simulation time 845558887 ps
CPU time 11.31 seconds
Started Dec 24 01:08:35 PM PST 23
Finished Dec 24 01:08:57 PM PST 23
Peak memory 218120 kb
Host smart-b0453a9e-dbc9-46a0-af20-eeaa0d61a099
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434577402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.1434577402
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.2915925229
Short name T428
Test name
Test status
Simulation time 1177514613 ps
CPU time 9.78 seconds
Started Dec 24 01:08:39 PM PST 23
Finished Dec 24 01:08:57 PM PST 23
Peak memory 218124 kb
Host smart-471023a1-ab0e-4063-949d-a0319e4cf824
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915925229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
2915925229
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.1200595175
Short name T184
Test name
Test status
Simulation time 285681095 ps
CPU time 11.5 seconds
Started Dec 24 01:08:42 PM PST 23
Finished Dec 24 01:09:01 PM PST 23
Peak memory 218188 kb
Host smart-dee07d6c-4c3e-4716-8213-f8cf130bd7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200595175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.1200595175
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.3547766386
Short name T404
Test name
Test status
Simulation time 26834357 ps
CPU time 2.14 seconds
Started Dec 24 01:08:40 PM PST 23
Finished Dec 24 01:08:50 PM PST 23
Peak memory 213728 kb
Host smart-813693b3-b611-4a5a-ae5c-0233edcaf575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547766386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.3547766386
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.1460899295
Short name T840
Test name
Test status
Simulation time 282162982 ps
CPU time 25.56 seconds
Started Dec 24 01:08:34 PM PST 23
Finished Dec 24 01:09:11 PM PST 23
Peak memory 251064 kb
Host smart-f92cf95b-1a08-4cbd-8797-424ae1a833a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460899295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.1460899295
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.3522983372
Short name T691
Test name
Test status
Simulation time 219456389 ps
CPU time 3.72 seconds
Started Dec 24 01:08:31 PM PST 23
Finished Dec 24 01:08:49 PM PST 23
Peak memory 222216 kb
Host smart-4837533f-5cb2-4e83-8cf8-47fad2b90c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522983372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.3522983372
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.851786507
Short name T986
Test name
Test status
Simulation time 14619777468 ps
CPU time 65.93 seconds
Started Dec 24 01:08:45 PM PST 23
Finished Dec 24 01:09:57 PM PST 23
Peak memory 251232 kb
Host smart-62cb9a8f-7a4b-477e-85d8-b23811429246
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851786507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.851786507
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.955787800
Short name T837
Test name
Test status
Simulation time 24485205 ps
CPU time 0.72 seconds
Started Dec 24 01:08:34 PM PST 23
Finished Dec 24 01:08:46 PM PST 23
Peak memory 207880 kb
Host smart-5274da95-5c83-4f3d-8e33-4f57bbd8a90a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955787800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ct
rl_volatile_unlock_smoke.955787800
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.591714345
Short name T32
Test name
Test status
Simulation time 29549635 ps
CPU time 0.92 seconds
Started Dec 24 01:08:46 PM PST 23
Finished Dec 24 01:08:53 PM PST 23
Peak memory 209704 kb
Host smart-a9ebe0cc-4981-46b1-9792-59326d2e4a32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591714345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.591714345
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.524030026
Short name T469
Test name
Test status
Simulation time 2540637221 ps
CPU time 15.79 seconds
Started Dec 24 01:08:42 PM PST 23
Finished Dec 24 01:09:05 PM PST 23
Peak memory 218316 kb
Host smart-0fbc9166-27a6-465e-9605-1d2320c43fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524030026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.524030026
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.96141649
Short name T845
Test name
Test status
Simulation time 100836985 ps
CPU time 1.99 seconds
Started Dec 24 01:08:33 PM PST 23
Finished Dec 24 01:08:48 PM PST 23
Peak memory 218160 kb
Host smart-f7309e9a-dd86-4308-8e09-079f3a84cd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96141649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.96141649
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.3080134581
Short name T987
Test name
Test status
Simulation time 595924999 ps
CPU time 13.98 seconds
Started Dec 24 01:08:35 PM PST 23
Finished Dec 24 01:09:00 PM PST 23
Peak memory 219256 kb
Host smart-b8990102-9551-455e-976f-e6b091138491
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080134581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.3080134581
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.1724036653
Short name T949
Test name
Test status
Simulation time 281208310 ps
CPU time 10.55 seconds
Started Dec 24 01:08:30 PM PST 23
Finished Dec 24 01:08:55 PM PST 23
Peak memory 218156 kb
Host smart-dd99a17b-ff72-4e52-ba75-e03e73ce1e88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724036653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.1724036653
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.245620876
Short name T30
Test name
Test status
Simulation time 4175051034 ps
CPU time 8.65 seconds
Started Dec 24 01:08:29 PM PST 23
Finished Dec 24 01:08:53 PM PST 23
Peak memory 218272 kb
Host smart-94434c03-5375-4507-b21e-9910a8a2919e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245620876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.245620876
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.1501030163
Short name T51
Test name
Test status
Simulation time 796821089 ps
CPU time 9.21 seconds
Started Dec 24 01:08:37 PM PST 23
Finished Dec 24 01:08:55 PM PST 23
Peak memory 218180 kb
Host smart-8df2fae8-eb3b-4b8c-ae25-e30a96e7fa9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501030163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1501030163
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.3309747878
Short name T835
Test name
Test status
Simulation time 827460141 ps
CPU time 2.88 seconds
Started Dec 24 01:08:32 PM PST 23
Finished Dec 24 01:08:48 PM PST 23
Peak memory 213828 kb
Host smart-4f28b7bb-2d10-4b7f-88da-1e45d86cbc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309747878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.3309747878
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.951417236
Short name T100
Test name
Test status
Simulation time 1389976964 ps
CPU time 29.84 seconds
Started Dec 24 01:08:40 PM PST 23
Finished Dec 24 01:09:18 PM PST 23
Peak memory 251108 kb
Host smart-8c811d5c-ade5-43ad-81aa-1fa3eb44c318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951417236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.951417236
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.3889700809
Short name T717
Test name
Test status
Simulation time 364355128 ps
CPU time 6.88 seconds
Started Dec 24 01:08:35 PM PST 23
Finished Dec 24 01:08:53 PM PST 23
Peak memory 246232 kb
Host smart-caccbd79-117e-492e-a92f-89b9ac945f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889700809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.3889700809
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.1182476149
Short name T932
Test name
Test status
Simulation time 25414819792 ps
CPU time 232.12 seconds
Started Dec 24 01:08:23 PM PST 23
Finished Dec 24 01:12:34 PM PST 23
Peak memory 284128 kb
Host smart-b17083a1-aa2c-419e-94fd-563d7d6619be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182476149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.1182476149
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.16718714
Short name T803
Test name
Test status
Simulation time 10816765 ps
CPU time 0.89 seconds
Started Dec 24 01:08:53 PM PST 23
Finished Dec 24 01:09:00 PM PST 23
Peak memory 208188 kb
Host smart-d3a93963-df7d-4c56-9a82-c2ec0351d2e7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16718714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctr
l_volatile_unlock_smoke.16718714
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.3654934530
Short name T877
Test name
Test status
Simulation time 60027713 ps
CPU time 0.88 seconds
Started Dec 24 01:08:42 PM PST 23
Finished Dec 24 01:08:50 PM PST 23
Peak memory 208340 kb
Host smart-0ee490c4-964c-47e7-9f78-7b63ed670040
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654934530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.3654934530
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.344257639
Short name T720
Test name
Test status
Simulation time 266008399 ps
CPU time 10.89 seconds
Started Dec 24 01:08:32 PM PST 23
Finished Dec 24 01:08:56 PM PST 23
Peak memory 218152 kb
Host smart-981e38d8-b1d6-4ffa-920a-79b3654ede02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344257639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.344257639
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.3497320907
Short name T708
Test name
Test status
Simulation time 2205520830 ps
CPU time 5.16 seconds
Started Dec 24 01:08:34 PM PST 23
Finished Dec 24 01:08:51 PM PST 23
Peak memory 209740 kb
Host smart-f4e93c6a-2162-430c-b2d0-56a713925986
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497320907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_a
ccess.3497320907
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.1332117160
Short name T912
Test name
Test status
Simulation time 208843165 ps
CPU time 4.87 seconds
Started Dec 24 01:08:31 PM PST 23
Finished Dec 24 01:08:50 PM PST 23
Peak memory 218212 kb
Host smart-a5cd323b-bafd-4c37-8351-b15fa98ca189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332117160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.1332117160
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.860441403
Short name T673
Test name
Test status
Simulation time 1031486504 ps
CPU time 11.28 seconds
Started Dec 24 01:08:43 PM PST 23
Finished Dec 24 01:09:01 PM PST 23
Peak memory 219244 kb
Host smart-362a44d1-97a0-41fa-86db-37b1b4890beb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860441403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.860441403
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2405857791
Short name T608
Test name
Test status
Simulation time 1141254307 ps
CPU time 13.13 seconds
Started Dec 24 01:08:38 PM PST 23
Finished Dec 24 01:09:00 PM PST 23
Peak memory 218080 kb
Host smart-71c86eb2-4d7d-466e-9409-85605d489af0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405857791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.2405857791
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.2433155107
Short name T470
Test name
Test status
Simulation time 364755238 ps
CPU time 8.42 seconds
Started Dec 24 01:08:38 PM PST 23
Finished Dec 24 01:08:55 PM PST 23
Peak memory 218052 kb
Host smart-bd3faefd-9c61-404d-86a4-d9ca2b49f9d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433155107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
2433155107
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.3192696270
Short name T59
Test name
Test status
Simulation time 302965976 ps
CPU time 8.36 seconds
Started Dec 24 01:08:24 PM PST 23
Finished Dec 24 01:08:51 PM PST 23
Peak memory 218104 kb
Host smart-dd83c185-0625-43a7-9efe-73dc877782ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192696270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.3192696270
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.920570417
Short name T945
Test name
Test status
Simulation time 455129936 ps
CPU time 4.98 seconds
Started Dec 24 01:08:46 PM PST 23
Finished Dec 24 01:08:57 PM PST 23
Peak memory 213756 kb
Host smart-6e5090d2-12ac-442d-81f4-c65566fb0b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920570417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.920570417
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.3108322078
Short name T413
Test name
Test status
Simulation time 1048362945 ps
CPU time 21.23 seconds
Started Dec 24 01:08:13 PM PST 23
Finished Dec 24 01:08:55 PM PST 23
Peak memory 251132 kb
Host smart-aaa491c1-0c02-48b0-80b6-7e1b8103e92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108322078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3108322078
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.42224225
Short name T501
Test name
Test status
Simulation time 326724243 ps
CPU time 7.28 seconds
Started Dec 24 01:08:34 PM PST 23
Finished Dec 24 01:08:53 PM PST 23
Peak memory 246196 kb
Host smart-f7703c15-9b1f-4017-8266-8e4b58142045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42224225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.42224225
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.240708964
Short name T647
Test name
Test status
Simulation time 7791650393 ps
CPU time 44.37 seconds
Started Dec 24 01:08:29 PM PST 23
Finished Dec 24 01:09:29 PM PST 23
Peak memory 274584 kb
Host smart-227e98cf-cc00-42c6-80af-9989803cf9cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240708964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.240708964
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1562784759
Short name T34
Test name
Test status
Simulation time 55514549 ps
CPU time 1.08 seconds
Started Dec 24 01:08:17 PM PST 23
Finished Dec 24 01:08:39 PM PST 23
Peak memory 212876 kb
Host smart-681ffc65-4eea-4d96-a77a-b9c1e4f5eb29
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562784759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.1562784759
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.2376103237
Short name T322
Test name
Test status
Simulation time 64021585 ps
CPU time 1.06 seconds
Started Dec 24 01:08:39 PM PST 23
Finished Dec 24 01:08:48 PM PST 23
Peak memory 209740 kb
Host smart-d4e960ff-e2cc-4e53-92e8-5075cc5f5ca8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376103237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.2376103237
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.2027438204
Short name T372
Test name
Test status
Simulation time 497581377 ps
CPU time 18.34 seconds
Started Dec 24 01:08:36 PM PST 23
Finished Dec 24 01:09:04 PM PST 23
Peak memory 218124 kb
Host smart-6cd51341-aab0-467b-9ac8-d3f3cb058fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027438204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2027438204
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.1614768519
Short name T478
Test name
Test status
Simulation time 1408520367 ps
CPU time 4.74 seconds
Started Dec 24 01:08:31 PM PST 23
Finished Dec 24 01:08:50 PM PST 23
Peak memory 209604 kb
Host smart-83c9fb18-19fd-442f-90fe-1b625168d32c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614768519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_a
ccess.1614768519
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.300337683
Short name T373
Test name
Test status
Simulation time 91522913 ps
CPU time 3.11 seconds
Started Dec 24 01:08:37 PM PST 23
Finished Dec 24 01:08:49 PM PST 23
Peak memory 218220 kb
Host smart-6f465af4-9f5d-4e56-8bf9-aa349e87fddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300337683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.300337683
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.1775561582
Short name T897
Test name
Test status
Simulation time 436314740 ps
CPU time 15.17 seconds
Started Dec 24 01:08:53 PM PST 23
Finished Dec 24 01:09:14 PM PST 23
Peak memory 218180 kb
Host smart-870ca42d-9cee-413c-adeb-d5aae7482c9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775561582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.1775561582
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.1163363533
Short name T377
Test name
Test status
Simulation time 255630478 ps
CPU time 9.31 seconds
Started Dec 24 01:08:46 PM PST 23
Finished Dec 24 01:09:02 PM PST 23
Peak memory 218124 kb
Host smart-dc409978-e84b-40c3-93e6-498c7bc23a5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163363533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.1163363533
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3491324658
Short name T573
Test name
Test status
Simulation time 1317674866 ps
CPU time 9.94 seconds
Started Dec 24 01:08:38 PM PST 23
Finished Dec 24 01:08:57 PM PST 23
Peak memory 218128 kb
Host smart-c98202a9-e31c-403b-996b-4d66389bfe6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491324658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
3491324658
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.1859071481
Short name T53
Test name
Test status
Simulation time 1443436412 ps
CPU time 12.95 seconds
Started Dec 24 01:08:39 PM PST 23
Finished Dec 24 01:09:00 PM PST 23
Peak memory 218208 kb
Host smart-5809b7ae-186e-400f-9120-d8e08acad0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859071481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.1859071481
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.3272577719
Short name T983
Test name
Test status
Simulation time 106750213 ps
CPU time 6.34 seconds
Started Dec 24 01:08:39 PM PST 23
Finished Dec 24 01:08:54 PM PST 23
Peak memory 214564 kb
Host smart-c51fe8e7-2eac-4955-a7c7-c70c73c3b228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272577719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.3272577719
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.1279236838
Short name T944
Test name
Test status
Simulation time 426591001 ps
CPU time 27.67 seconds
Started Dec 24 01:08:44 PM PST 23
Finished Dec 24 01:09:19 PM PST 23
Peak memory 251072 kb
Host smart-c19c3304-db05-4585-a60e-8bc8c5641281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279236838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.1279236838
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.3181786897
Short name T477
Test name
Test status
Simulation time 85613882 ps
CPU time 3.06 seconds
Started Dec 24 01:08:40 PM PST 23
Finished Dec 24 01:08:50 PM PST 23
Peak memory 218240 kb
Host smart-cefb9972-18c2-4704-a755-3701caff5dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181786897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.3181786897
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.2373477967
Short name T953
Test name
Test status
Simulation time 19018502824 ps
CPU time 156.35 seconds
Started Dec 24 01:08:28 PM PST 23
Finished Dec 24 01:11:21 PM PST 23
Peak memory 284032 kb
Host smart-98eaf89b-346e-4758-a221-9a343e6e002a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373477967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.2373477967
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.2314736815
Short name T652
Test name
Test status
Simulation time 43121316777 ps
CPU time 633.12 seconds
Started Dec 24 01:08:43 PM PST 23
Finished Dec 24 01:19:23 PM PST 23
Peak memory 276152 kb
Host smart-93f6452f-984b-4f39-a032-ef964b90f3c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2314736815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.2314736815
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.1739497268
Short name T655
Test name
Test status
Simulation time 40525707 ps
CPU time 0.98 seconds
Started Dec 24 01:08:36 PM PST 23
Finished Dec 24 01:08:47 PM PST 23
Peak memory 211460 kb
Host smart-c274617f-4d5f-44d2-bc8e-1ca4dc30f3c8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739497268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.1739497268
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.688962528
Short name T334
Test name
Test status
Simulation time 73679125 ps
CPU time 1.17 seconds
Started Dec 24 01:08:53 PM PST 23
Finished Dec 24 01:09:00 PM PST 23
Peak memory 209624 kb
Host smart-0990c829-ab39-456f-b200-bea5903faa16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688962528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.688962528
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.1988023709
Short name T43
Test name
Test status
Simulation time 1663347395 ps
CPU time 15.09 seconds
Started Dec 24 01:08:42 PM PST 23
Finished Dec 24 01:09:04 PM PST 23
Peak memory 218212 kb
Host smart-86948e69-26b4-45ac-8839-395752459e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988023709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.1988023709
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.1089254156
Short name T471
Test name
Test status
Simulation time 529943259 ps
CPU time 7.06 seconds
Started Dec 24 01:08:44 PM PST 23
Finished Dec 24 01:08:58 PM PST 23
Peak memory 209600 kb
Host smart-a1a1bd42-c280-470e-b960-74907e0efe17
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089254156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_a
ccess.1089254156
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.161495348
Short name T671
Test name
Test status
Simulation time 181296141 ps
CPU time 4.38 seconds
Started Dec 24 01:08:39 PM PST 23
Finished Dec 24 01:08:51 PM PST 23
Peak memory 218228 kb
Host smart-292785db-6f05-450c-bedc-01eeaf93e5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161495348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.161495348
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.3957613690
Short name T707
Test name
Test status
Simulation time 2075521884 ps
CPU time 14.67 seconds
Started Dec 24 01:08:42 PM PST 23
Finished Dec 24 01:09:04 PM PST 23
Peak memory 219208 kb
Host smart-d031958e-0a57-49a6-be9e-fbecfc5311a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957613690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.3957613690
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.2307714334
Short name T313
Test name
Test status
Simulation time 746525442 ps
CPU time 14.77 seconds
Started Dec 24 01:08:44 PM PST 23
Finished Dec 24 01:09:05 PM PST 23
Peak memory 218040 kb
Host smart-30392dcb-0daf-4d4d-9ceb-40d6cb22dc8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307714334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.2307714334
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.1268256547
Short name T305
Test name
Test status
Simulation time 628423315 ps
CPU time 13.7 seconds
Started Dec 24 01:08:42 PM PST 23
Finished Dec 24 01:09:03 PM PST 23
Peak memory 218084 kb
Host smart-ca672e24-6757-4cb4-b7b1-43686cc41f3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268256547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
1268256547
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.4282125991
Short name T661
Test name
Test status
Simulation time 1493592155 ps
CPU time 10.06 seconds
Started Dec 24 01:08:46 PM PST 23
Finished Dec 24 01:09:02 PM PST 23
Peak memory 218228 kb
Host smart-a6b5af2a-2bb0-46ae-9282-f3c3651366d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282125991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.4282125991
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.2169236187
Short name T352
Test name
Test status
Simulation time 101101598 ps
CPU time 1.51 seconds
Started Dec 24 01:08:35 PM PST 23
Finished Dec 24 01:08:47 PM PST 23
Peak memory 213560 kb
Host smart-c17727ae-c3b4-4c36-a72f-2ce19cdc2fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169236187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.2169236187
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.308105781
Short name T540
Test name
Test status
Simulation time 3139751757 ps
CPU time 21.78 seconds
Started Dec 24 01:08:28 PM PST 23
Finished Dec 24 01:09:06 PM PST 23
Peak memory 251132 kb
Host smart-4a30bff1-30b5-4bc1-83ba-d02cbb79a421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308105781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.308105781
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.3397528670
Short name T567
Test name
Test status
Simulation time 367457150 ps
CPU time 3.9 seconds
Started Dec 24 01:08:51 PM PST 23
Finished Dec 24 01:09:01 PM PST 23
Peak memory 221980 kb
Host smart-a74919e9-c368-4f76-9d11-7f7529a78399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397528670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.3397528670
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.685029630
Short name T547
Test name
Test status
Simulation time 197724913738 ps
CPU time 287.48 seconds
Started Dec 24 01:08:40 PM PST 23
Finished Dec 24 01:13:35 PM PST 23
Peak memory 316744 kb
Host smart-14c8ca3e-bbfe-4d8d-bd85-191a69e383a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685029630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.685029630
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2246172369
Short name T40
Test name
Test status
Simulation time 13294649 ps
CPU time 0.79 seconds
Started Dec 24 01:08:32 PM PST 23
Finished Dec 24 01:08:46 PM PST 23
Peak memory 208544 kb
Host smart-bd44284f-6665-4c4c-aefc-d7b7f753b9de
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246172369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.2246172369
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.3577177799
Short name T436
Test name
Test status
Simulation time 67079165 ps
CPU time 1.14 seconds
Started Dec 24 01:06:59 PM PST 23
Finished Dec 24 01:07:04 PM PST 23
Peak memory 209716 kb
Host smart-99e765b0-d9da-442e-8b42-a53ab42bc879
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577177799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.3577177799
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.3002603272
Short name T605
Test name
Test status
Simulation time 336296050 ps
CPU time 9.7 seconds
Started Dec 24 01:06:41 PM PST 23
Finished Dec 24 01:06:51 PM PST 23
Peak memory 218292 kb
Host smart-3b0f65c7-050b-4cc2-aaca-29e69c8f69f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002603272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.3002603272
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.576960321
Short name T693
Test name
Test status
Simulation time 60193941 ps
CPU time 1.43 seconds
Started Dec 24 01:06:22 PM PST 23
Finished Dec 24 01:06:24 PM PST 23
Peak memory 209632 kb
Host smart-1fe2c990-b742-4bcd-a81a-8b9393b8f749
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576960321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_acc
ess.576960321
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.2913045280
Short name T868
Test name
Test status
Simulation time 1927446339 ps
CPU time 47.85 seconds
Started Dec 24 01:06:51 PM PST 23
Finished Dec 24 01:07:43 PM PST 23
Peak memory 218128 kb
Host smart-ad7585a8-e7cb-41cb-b37e-3463c3f74a97
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913045280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.2913045280
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.2361614554
Short name T801
Test name
Test status
Simulation time 3631596430 ps
CPU time 85.75 seconds
Started Dec 24 01:06:52 PM PST 23
Finished Dec 24 01:08:23 PM PST 23
Peak memory 217656 kb
Host smart-5df23d6f-e2d4-4ba3-a760-640f92672ac7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361614554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
priority.2361614554
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.3310765487
Short name T411
Test name
Test status
Simulation time 950068615 ps
CPU time 15.27 seconds
Started Dec 24 01:06:24 PM PST 23
Finished Dec 24 01:06:41 PM PST 23
Peak memory 218124 kb
Host smart-54faee22-6a9c-48a9-8705-15a647646aae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310765487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.3310765487
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.990842328
Short name T701
Test name
Test status
Simulation time 4017612392 ps
CPU time 27.74 seconds
Started Dec 24 01:06:29 PM PST 23
Finished Dec 24 01:06:58 PM PST 23
Peak memory 213852 kb
Host smart-4b3a2bd9-2436-4c50-a797-c29f37b49317
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990842328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_regwen_during_op.990842328
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.3945116820
Short name T746
Test name
Test status
Simulation time 180140784 ps
CPU time 4.62 seconds
Started Dec 24 01:06:45 PM PST 23
Finished Dec 24 01:06:52 PM PST 23
Peak memory 212916 kb
Host smart-391a795d-5797-4600-919b-73a3bf177014
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945116820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
3945116820
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.2189154783
Short name T16
Test name
Test status
Simulation time 7932825171 ps
CPU time 81.61 seconds
Started Dec 24 01:06:30 PM PST 23
Finished Dec 24 01:07:54 PM PST 23
Peak memory 275812 kb
Host smart-f3e192d0-7f9e-44f0-80af-e7b4da66ca79
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189154783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.2189154783
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.1151999110
Short name T964
Test name
Test status
Simulation time 4939735108 ps
CPU time 7.19 seconds
Started Dec 24 01:06:47 PM PST 23
Finished Dec 24 01:06:57 PM PST 23
Peak memory 218048 kb
Host smart-978897aa-963a-4af5-87ef-973097cdc438
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151999110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.1151999110
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.2759820727
Short name T962
Test name
Test status
Simulation time 58280483 ps
CPU time 1.62 seconds
Started Dec 24 01:06:47 PM PST 23
Finished Dec 24 01:06:52 PM PST 23
Peak memory 218196 kb
Host smart-a44778d0-734f-4219-9636-d1a0ac7bf348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759820727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.2759820727
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.551911479
Short name T876
Test name
Test status
Simulation time 360837352 ps
CPU time 24.69 seconds
Started Dec 24 01:06:22 PM PST 23
Finished Dec 24 01:06:47 PM PST 23
Peak memory 213888 kb
Host smart-27e08f68-23fc-439c-ac5d-4a824ca5d5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551911479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.551911479
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.1065375987
Short name T57
Test name
Test status
Simulation time 209886699 ps
CPU time 34.83 seconds
Started Dec 24 01:06:30 PM PST 23
Finished Dec 24 01:07:07 PM PST 23
Peak memory 281588 kb
Host smart-493ed1cc-dddd-4cad-9525-8c80fca3e7d3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065375987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.1065375987
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.2294354169
Short name T656
Test name
Test status
Simulation time 242681296 ps
CPU time 9.55 seconds
Started Dec 24 01:06:44 PM PST 23
Finished Dec 24 01:06:56 PM PST 23
Peak memory 218216 kb
Host smart-c9049492-989c-49ff-b229-0eeb75ac3432
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294354169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.2294354169
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1801820611
Short name T639
Test name
Test status
Simulation time 1109875878 ps
CPU time 11.6 seconds
Started Dec 24 01:06:51 PM PST 23
Finished Dec 24 01:07:07 PM PST 23
Peak memory 218160 kb
Host smart-5cd1f760-872d-4af8-a42d-fe2ed6282174
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801820611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.1801820611
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.3341566643
Short name T792
Test name
Test status
Simulation time 869370947 ps
CPU time 9.61 seconds
Started Dec 24 01:06:46 PM PST 23
Finished Dec 24 01:06:57 PM PST 23
Peak memory 218048 kb
Host smart-f8cce8eb-29ac-411d-94d4-7c7ab81a92c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341566643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.3
341566643
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.3572720808
Short name T651
Test name
Test status
Simulation time 950506042 ps
CPU time 18.11 seconds
Started Dec 24 01:06:26 PM PST 23
Finished Dec 24 01:06:45 PM PST 23
Peak memory 218192 kb
Host smart-373134b2-5240-48b0-9b89-f1b6e5fcb296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572720808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.3572720808
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3658633185
Short name T894
Test name
Test status
Simulation time 36191714 ps
CPU time 1.75 seconds
Started Dec 24 01:06:49 PM PST 23
Finished Dec 24 01:06:55 PM PST 23
Peak memory 213460 kb
Host smart-31fcf7cd-be56-4102-a16e-ca8adbd52221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658633185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3658633185
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.2169936714
Short name T641
Test name
Test status
Simulation time 224503708 ps
CPU time 28.36 seconds
Started Dec 24 01:06:46 PM PST 23
Finished Dec 24 01:07:16 PM PST 23
Peak memory 251048 kb
Host smart-d20d8100-2e62-481a-bf30-c5111b5cd1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169936714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.2169936714
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.3952752367
Short name T560
Test name
Test status
Simulation time 84708919 ps
CPU time 3.39 seconds
Started Dec 24 01:06:46 PM PST 23
Finished Dec 24 01:06:51 PM PST 23
Peak memory 222232 kb
Host smart-679f9a5f-a7d6-4c26-a644-4f5d74900330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952752367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.3952752367
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.3581148405
Short name T672
Test name
Test status
Simulation time 10026364733 ps
CPU time 91.94 seconds
Started Dec 24 01:06:28 PM PST 23
Finished Dec 24 01:08:01 PM PST 23
Peak memory 251224 kb
Host smart-320b4f45-341e-49d0-93c5-45f92695245d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581148405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.3581148405
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.322007384
Short name T46
Test name
Test status
Simulation time 193745170644 ps
CPU time 842.24 seconds
Started Dec 24 01:06:29 PM PST 23
Finished Dec 24 01:20:32 PM PST 23
Peak memory 259612 kb
Host smart-e3b3b47f-d383-4394-8c5b-9266ce5168d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=322007384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.322007384
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.3398178286
Short name T727
Test name
Test status
Simulation time 20074259 ps
CPU time 1.17 seconds
Started Dec 24 01:06:29 PM PST 23
Finished Dec 24 01:06:31 PM PST 23
Peak memory 212812 kb
Host smart-8d4e4079-ef1d-4d20-b543-4664c6b0b20d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398178286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.3398178286
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.1395065625
Short name T75
Test name
Test status
Simulation time 18091092 ps
CPU time 0.87 seconds
Started Dec 24 01:08:41 PM PST 23
Finished Dec 24 01:08:49 PM PST 23
Peak memory 208268 kb
Host smart-0f253ee4-8abd-477e-be2d-c456a366ebc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395065625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.1395065625
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.2689652303
Short name T535
Test name
Test status
Simulation time 929014881 ps
CPU time 10.18 seconds
Started Dec 24 01:08:34 PM PST 23
Finished Dec 24 01:08:56 PM PST 23
Peak memory 218084 kb
Host smart-3d6ebee7-38a4-4d34-ac71-4b4637ce92a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689652303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2689652303
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.1330594274
Short name T872
Test name
Test status
Simulation time 285108240 ps
CPU time 4.27 seconds
Started Dec 24 01:08:52 PM PST 23
Finished Dec 24 01:09:02 PM PST 23
Peak memory 209644 kb
Host smart-5ab80a7c-2f17-4c2a-b8ff-a293af201de9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330594274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_a
ccess.1330594274
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.3068702330
Short name T627
Test name
Test status
Simulation time 108449101 ps
CPU time 2.83 seconds
Started Dec 24 01:08:49 PM PST 23
Finished Dec 24 01:08:57 PM PST 23
Peak memory 218152 kb
Host smart-cc64cab7-f65e-4c1d-9f51-8940a960d36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068702330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.3068702330
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.772560621
Short name T822
Test name
Test status
Simulation time 226346652 ps
CPU time 10.56 seconds
Started Dec 24 01:08:57 PM PST 23
Finished Dec 24 01:09:14 PM PST 23
Peak memory 218156 kb
Host smart-c5e1e469-ab54-4948-af00-d5c8064ec59c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772560621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.772560621
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2326515895
Short name T920
Test name
Test status
Simulation time 333967953 ps
CPU time 9.4 seconds
Started Dec 24 01:08:34 PM PST 23
Finished Dec 24 01:08:55 PM PST 23
Peak memory 218120 kb
Host smart-a78a157f-3cfc-423d-a040-b3ecd074d815
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326515895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.2326515895
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.960838864
Short name T63
Test name
Test status
Simulation time 295209988 ps
CPU time 8.74 seconds
Started Dec 24 01:08:44 PM PST 23
Finished Dec 24 01:09:00 PM PST 23
Peak memory 218024 kb
Host smart-7f2a4292-5a13-41d8-88cd-287c63b47805
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960838864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.960838864
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.609988072
Short name T733
Test name
Test status
Simulation time 3286732513 ps
CPU time 10.09 seconds
Started Dec 24 01:08:50 PM PST 23
Finished Dec 24 01:09:06 PM PST 23
Peak memory 218212 kb
Host smart-d40ddfa6-7e86-40ff-b25d-03a76208c6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609988072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.609988072
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.685683085
Short name T546
Test name
Test status
Simulation time 37119888 ps
CPU time 1.09 seconds
Started Dec 24 01:08:55 PM PST 23
Finished Dec 24 01:09:04 PM PST 23
Peak memory 213044 kb
Host smart-08777e59-1eed-4520-b72c-86dd1776277e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685683085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.685683085
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.3647318402
Short name T592
Test name
Test status
Simulation time 323007817 ps
CPU time 23.48 seconds
Started Dec 24 01:08:39 PM PST 23
Finished Dec 24 01:09:11 PM PST 23
Peak memory 251156 kb
Host smart-9ce281d9-4c5b-4d73-abaf-7f3d8ed5710e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647318402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3647318402
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.2877654725
Short name T386
Test name
Test status
Simulation time 993282797 ps
CPU time 3.53 seconds
Started Dec 24 01:08:34 PM PST 23
Finished Dec 24 01:08:49 PM PST 23
Peak memory 218232 kb
Host smart-3c0cc3bc-42d5-4d28-ae44-c94f5d958814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877654725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2877654725
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.2740548844
Short name T843
Test name
Test status
Simulation time 91289321404 ps
CPU time 336.07 seconds
Started Dec 24 01:08:48 PM PST 23
Finished Dec 24 01:14:31 PM PST 23
Peak memory 251136 kb
Host smart-416fef14-eea6-4812-8511-963ef82adc3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740548844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.2740548844
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.836527124
Short name T645
Test name
Test status
Simulation time 47219054 ps
CPU time 0.75 seconds
Started Dec 24 01:08:43 PM PST 23
Finished Dec 24 01:08:51 PM PST 23
Peak memory 207896 kb
Host smart-193d8631-6b10-42a0-ae0a-efb48943e508
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836527124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ct
rl_volatile_unlock_smoke.836527124
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.1324477710
Short name T887
Test name
Test status
Simulation time 59757966 ps
CPU time 0.86 seconds
Started Dec 24 01:08:53 PM PST 23
Finished Dec 24 01:09:00 PM PST 23
Peak memory 209672 kb
Host smart-bfd263ab-7496-48d6-a06d-97d29e9fa97b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324477710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.1324477710
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.4064317810
Short name T878
Test name
Test status
Simulation time 764242792 ps
CPU time 10.05 seconds
Started Dec 24 01:08:41 PM PST 23
Finished Dec 24 01:08:59 PM PST 23
Peak memory 218240 kb
Host smart-1d02bce8-4a54-40e7-acb3-3f19b8ab4e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064317810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.4064317810
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.2992775562
Short name T24
Test name
Test status
Simulation time 664999786 ps
CPU time 4.72 seconds
Started Dec 24 01:08:51 PM PST 23
Finished Dec 24 01:09:02 PM PST 23
Peak memory 209368 kb
Host smart-c95ffc4b-dd65-423a-b526-fa76aba358bb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992775562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_a
ccess.2992775562
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.1175992850
Short name T780
Test name
Test status
Simulation time 128751281 ps
CPU time 2.04 seconds
Started Dec 24 01:08:55 PM PST 23
Finished Dec 24 01:09:04 PM PST 23
Peak memory 218140 kb
Host smart-c0c8756f-b569-42e7-8a62-d2a79fbb4622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175992850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.1175992850
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.3242869527
Short name T443
Test name
Test status
Simulation time 2291663203 ps
CPU time 14.28 seconds
Started Dec 24 01:08:39 PM PST 23
Finished Dec 24 01:09:01 PM PST 23
Peak memory 218300 kb
Host smart-9a873699-deb9-4c56-a3dc-c3587982d9b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242869527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.3242869527
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.2348918469
Short name T499
Test name
Test status
Simulation time 864392857 ps
CPU time 23.27 seconds
Started Dec 24 01:08:55 PM PST 23
Finished Dec 24 01:09:24 PM PST 23
Peak memory 218092 kb
Host smart-e710a75b-b3cc-403b-9047-57116cd24da7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348918469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.2348918469
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.2694701246
Short name T911
Test name
Test status
Simulation time 495913998 ps
CPU time 10.89 seconds
Started Dec 24 01:08:53 PM PST 23
Finished Dec 24 01:09:10 PM PST 23
Peak memory 218100 kb
Host smart-0e7fc06c-896c-443e-a061-1d7d6c399c4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694701246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
2694701246
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.3210715989
Short name T359
Test name
Test status
Simulation time 710362470 ps
CPU time 7.7 seconds
Started Dec 24 01:08:30 PM PST 23
Finished Dec 24 01:08:53 PM PST 23
Peak memory 218240 kb
Host smart-36c9ce9b-3b79-46e1-91d2-03be6ecc41ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210715989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.3210715989
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.2094193941
Short name T370
Test name
Test status
Simulation time 134979594 ps
CPU time 2.09 seconds
Started Dec 24 01:08:41 PM PST 23
Finished Dec 24 01:08:51 PM PST 23
Peak memory 213624 kb
Host smart-234b521d-da18-4a77-a0ba-aaaeb4790f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094193941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2094193941
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.64994048
Short name T450
Test name
Test status
Simulation time 341426068 ps
CPU time 28.21 seconds
Started Dec 24 01:08:50 PM PST 23
Finished Dec 24 01:09:25 PM PST 23
Peak memory 250952 kb
Host smart-74e4041a-f847-4693-bc34-16e5dfe90f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64994048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.64994048
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.3210330603
Short name T429
Test name
Test status
Simulation time 202732827 ps
CPU time 6.48 seconds
Started Dec 24 01:08:49 PM PST 23
Finished Dec 24 01:09:02 PM PST 23
Peak memory 246620 kb
Host smart-fe2905e6-c4ee-4869-8baf-a03904cbc4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210330603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.3210330603
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.44268236
Short name T5
Test name
Test status
Simulation time 36366010764 ps
CPU time 174.71 seconds
Started Dec 24 01:08:40 PM PST 23
Finished Dec 24 01:11:42 PM PST 23
Peak memory 283164 kb
Host smart-4f9b8b81-39f8-4b66-abe8-7986f7a38a90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44268236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.lc_ctrl_stress_all.44268236
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3040322309
Short name T806
Test name
Test status
Simulation time 40146331 ps
CPU time 0.88 seconds
Started Dec 24 01:08:40 PM PST 23
Finished Dec 24 01:08:49 PM PST 23
Peak memory 208408 kb
Host smart-9661e959-3d79-4fcb-ac18-14c6c4341b43
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040322309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.3040322309
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.18392331
Short name T318
Test name
Test status
Simulation time 63640266 ps
CPU time 0.87 seconds
Started Dec 24 01:08:46 PM PST 23
Finished Dec 24 01:08:53 PM PST 23
Peak memory 208408 kb
Host smart-2f03e60c-744c-434b-b91e-66043309a232
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18392331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.18392331
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.3075866679
Short name T684
Test name
Test status
Simulation time 1716394274 ps
CPU time 11.38 seconds
Started Dec 24 01:08:59 PM PST 23
Finished Dec 24 01:09:18 PM PST 23
Peak memory 218216 kb
Host smart-24b1fe1c-5999-46fa-9301-551f416c21d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075866679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.3075866679
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.3564319281
Short name T787
Test name
Test status
Simulation time 1622585958 ps
CPU time 9.45 seconds
Started Dec 24 01:08:47 PM PST 23
Finished Dec 24 01:09:02 PM PST 23
Peak memory 209676 kb
Host smart-93688559-6cf6-4760-a3a3-4aa4420e0eba
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564319281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_a
ccess.3564319281
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.1792557414
Short name T385
Test name
Test status
Simulation time 124513944 ps
CPU time 3.07 seconds
Started Dec 24 01:08:55 PM PST 23
Finished Dec 24 01:09:04 PM PST 23
Peak memory 218152 kb
Host smart-f8e9f7df-1df5-4e57-8995-53f9eef9e94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792557414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.1792557414
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.2661560575
Short name T966
Test name
Test status
Simulation time 703120553 ps
CPU time 13.16 seconds
Started Dec 24 01:08:53 PM PST 23
Finished Dec 24 01:09:12 PM PST 23
Peak memory 218176 kb
Host smart-bbe3dcb4-3bcb-49bb-8f1c-84910b6d0fa1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661560575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.2661560575
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.3387059118
Short name T491
Test name
Test status
Simulation time 574683164 ps
CPU time 13.73 seconds
Started Dec 24 01:08:44 PM PST 23
Finished Dec 24 01:09:05 PM PST 23
Peak memory 218076 kb
Host smart-59289651-cdb7-427c-8c42-2c05beb0a818
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387059118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.3387059118
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.625100518
Short name T29
Test name
Test status
Simulation time 813845157 ps
CPU time 12.64 seconds
Started Dec 24 01:08:54 PM PST 23
Finished Dec 24 01:09:13 PM PST 23
Peak memory 218056 kb
Host smart-9e8b7ca9-a918-483a-be8f-0aed899dab37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625100518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.625100518
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.1311700787
Short name T716
Test name
Test status
Simulation time 390366586 ps
CPU time 9.74 seconds
Started Dec 24 01:08:57 PM PST 23
Finished Dec 24 01:09:14 PM PST 23
Peak memory 218108 kb
Host smart-eadf2e92-f58e-4f9f-ad57-9d3b53fa217b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311700787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.1311700787
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.3551188003
Short name T604
Test name
Test status
Simulation time 105342444 ps
CPU time 2.87 seconds
Started Dec 24 01:08:43 PM PST 23
Finished Dec 24 01:08:53 PM PST 23
Peak memory 214100 kb
Host smart-c415a108-16d9-4542-8478-bf3c17a78607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551188003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.3551188003
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.547859316
Short name T465
Test name
Test status
Simulation time 1422254970 ps
CPU time 28.56 seconds
Started Dec 24 01:08:53 PM PST 23
Finished Dec 24 01:09:28 PM PST 23
Peak memory 251048 kb
Host smart-010acedd-fb7c-423f-b3a8-3e0905082334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547859316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.547859316
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.1736126799
Short name T636
Test name
Test status
Simulation time 163318368 ps
CPU time 9.24 seconds
Started Dec 24 01:08:53 PM PST 23
Finished Dec 24 01:09:08 PM PST 23
Peak memory 251112 kb
Host smart-dfe26ee6-629a-4a0f-aeee-59c343de7d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736126799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.1736126799
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.1447833785
Short name T916
Test name
Test status
Simulation time 5467479463 ps
CPU time 181.1 seconds
Started Dec 24 01:08:54 PM PST 23
Finished Dec 24 01:12:01 PM PST 23
Peak memory 283556 kb
Host smart-2fd8b903-b059-4fdb-9306-3122e13b8027
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447833785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.1447833785
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2331103318
Short name T948
Test name
Test status
Simulation time 22994980 ps
CPU time 0.76 seconds
Started Dec 24 01:08:40 PM PST 23
Finished Dec 24 01:08:48 PM PST 23
Peak memory 208144 kb
Host smart-056fff60-0eb1-4597-8ec9-d659a8fc16b9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331103318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.2331103318
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.753422844
Short name T71
Test name
Test status
Simulation time 136332385 ps
CPU time 0.82 seconds
Started Dec 24 01:08:44 PM PST 23
Finished Dec 24 01:08:51 PM PST 23
Peak memory 209632 kb
Host smart-c3dfb5ce-e15d-45f5-bc3c-e7745032e91a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753422844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.753422844
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.957545655
Short name T623
Test name
Test status
Simulation time 406047781 ps
CPU time 16.06 seconds
Started Dec 24 01:08:55 PM PST 23
Finished Dec 24 01:09:18 PM PST 23
Peak memory 218196 kb
Host smart-1b85dd6b-1211-4e41-8c44-03efff0e99bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957545655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.957545655
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.3767597469
Short name T732
Test name
Test status
Simulation time 2400274186 ps
CPU time 8.65 seconds
Started Dec 24 01:08:44 PM PST 23
Finished Dec 24 01:09:00 PM PST 23
Peak memory 209768 kb
Host smart-578b809d-8655-43de-97ae-c29b69446d5a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767597469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_a
ccess.3767597469
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.2596476638
Short name T566
Test name
Test status
Simulation time 72010725 ps
CPU time 2.76 seconds
Started Dec 24 01:08:41 PM PST 23
Finished Dec 24 01:08:51 PM PST 23
Peak memory 218208 kb
Host smart-9eee3953-4435-4d65-8a21-9826b003f149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596476638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.2596476638
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.3663566644
Short name T670
Test name
Test status
Simulation time 313783488 ps
CPU time 13.58 seconds
Started Dec 24 01:08:54 PM PST 23
Finished Dec 24 01:09:13 PM PST 23
Peak memory 218128 kb
Host smart-c326c090-e53b-4b1c-a8de-aa79e0b56320
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663566644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.3663566644
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.4086460172
Short name T900
Test name
Test status
Simulation time 565642871 ps
CPU time 8.99 seconds
Started Dec 24 01:08:46 PM PST 23
Finished Dec 24 01:09:01 PM PST 23
Peak memory 218120 kb
Host smart-a3033140-b18f-4d23-b287-ef036859ae77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086460172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.4086460172
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.1961284093
Short name T550
Test name
Test status
Simulation time 374404780 ps
CPU time 10.09 seconds
Started Dec 24 01:09:00 PM PST 23
Finished Dec 24 01:09:17 PM PST 23
Peak memory 218148 kb
Host smart-613400d7-7cec-4a75-a320-63b5b90fc90b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961284093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
1961284093
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.2855177152
Short name T663
Test name
Test status
Simulation time 870486871 ps
CPU time 10.49 seconds
Started Dec 24 01:08:53 PM PST 23
Finished Dec 24 01:09:10 PM PST 23
Peak memory 218204 kb
Host smart-e9a1b8cf-625d-4773-be95-dfeb88d6de27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855177152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2855177152
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.737100627
Short name T472
Test name
Test status
Simulation time 283730891 ps
CPU time 2.86 seconds
Started Dec 24 01:08:51 PM PST 23
Finished Dec 24 01:09:01 PM PST 23
Peak memory 213928 kb
Host smart-5be6e3fa-d8e0-4a71-a971-c8f55d618d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737100627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.737100627
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.2629764304
Short name T346
Test name
Test status
Simulation time 462163708 ps
CPU time 33.39 seconds
Started Dec 24 01:08:53 PM PST 23
Finished Dec 24 01:09:33 PM PST 23
Peak memory 251172 kb
Host smart-22a971f4-4c52-41d0-bdc7-b5d527a35334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629764304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.2629764304
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.1729270605
Short name T549
Test name
Test status
Simulation time 158967569 ps
CPU time 7.33 seconds
Started Dec 24 01:08:42 PM PST 23
Finished Dec 24 01:08:57 PM PST 23
Peak memory 245996 kb
Host smart-479ddec8-0a0f-45b4-888d-d1b448d46237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729270605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.1729270605
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3289482924
Short name T620
Test name
Test status
Simulation time 16057328 ps
CPU time 0.84 seconds
Started Dec 24 01:08:41 PM PST 23
Finished Dec 24 01:08:50 PM PST 23
Peak memory 208508 kb
Host smart-21d411c7-95e2-4637-8386-7a84ded38860
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289482924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.3289482924
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.102931154
Short name T730
Test name
Test status
Simulation time 131285362 ps
CPU time 0.97 seconds
Started Dec 24 01:08:53 PM PST 23
Finished Dec 24 01:09:00 PM PST 23
Peak memory 209700 kb
Host smart-28d41d1d-0dc8-4814-890e-fdcd3fb0fd40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102931154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.102931154
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.845932288
Short name T914
Test name
Test status
Simulation time 233180806 ps
CPU time 11.99 seconds
Started Dec 24 01:08:50 PM PST 23
Finished Dec 24 01:09:09 PM PST 23
Peak memory 218044 kb
Host smart-f78d26ea-7b89-43e3-81c5-956e993d84ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845932288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.845932288
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.3099581947
Short name T7
Test name
Test status
Simulation time 557920255 ps
CPU time 6.23 seconds
Started Dec 24 01:08:41 PM PST 23
Finished Dec 24 01:08:55 PM PST 23
Peak memory 209700 kb
Host smart-fd5e6806-de9e-44a3-bf5d-c40301853930
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099581947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_a
ccess.3099581947
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.524659699
Short name T793
Test name
Test status
Simulation time 185852815 ps
CPU time 2.7 seconds
Started Dec 24 01:08:50 PM PST 23
Finished Dec 24 01:08:59 PM PST 23
Peak memory 218048 kb
Host smart-9d809ee7-be85-41d8-8c16-dbe892bd6ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524659699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.524659699
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.2044244041
Short name T807
Test name
Test status
Simulation time 846571555 ps
CPU time 10.83 seconds
Started Dec 24 01:08:49 PM PST 23
Finished Dec 24 01:09:06 PM PST 23
Peak memory 218480 kb
Host smart-d2195ce6-8427-4e81-aa79-38044aae30fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044244041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.2044244041
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.743923563
Short name T800
Test name
Test status
Simulation time 246357210 ps
CPU time 11.16 seconds
Started Dec 24 01:08:51 PM PST 23
Finished Dec 24 01:09:08 PM PST 23
Peak memory 217992 kb
Host smart-1511cffe-112d-40cb-b010-8bffd9119ad6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743923563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_di
gest.743923563
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.322594079
Short name T706
Test name
Test status
Simulation time 1932537703 ps
CPU time 12.28 seconds
Started Dec 24 01:08:47 PM PST 23
Finished Dec 24 01:09:06 PM PST 23
Peak memory 218152 kb
Host smart-4ddc04ba-a304-428c-938d-347297748721
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322594079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.322594079
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.664828281
Short name T783
Test name
Test status
Simulation time 1016975289 ps
CPU time 12.05 seconds
Started Dec 24 01:08:37 PM PST 23
Finished Dec 24 01:08:58 PM PST 23
Peak memory 218224 kb
Host smart-9b4231be-ee74-4d50-938f-054a69b3e45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664828281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.664828281
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.501518350
Short name T970
Test name
Test status
Simulation time 75098259 ps
CPU time 2.08 seconds
Started Dec 24 01:08:50 PM PST 23
Finished Dec 24 01:08:59 PM PST 23
Peak memory 213920 kb
Host smart-24bee3e1-9dbd-4504-ab53-c1c272bd2458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501518350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.501518350
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.2065035104
Short name T956
Test name
Test status
Simulation time 190885410 ps
CPU time 14.5 seconds
Started Dec 24 01:08:35 PM PST 23
Finished Dec 24 01:09:00 PM PST 23
Peak memory 251000 kb
Host smart-cf52d3dc-8aae-4dc8-a936-985276d5db44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065035104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.2065035104
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.413267032
Short name T927
Test name
Test status
Simulation time 297628875 ps
CPU time 9.08 seconds
Started Dec 24 01:08:44 PM PST 23
Finished Dec 24 01:09:00 PM PST 23
Peak memory 251224 kb
Host smart-9e75fa18-7356-469c-9af6-1e37b280953b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413267032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.413267032
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.1321929160
Short name T326
Test name
Test status
Simulation time 28947899291 ps
CPU time 235.45 seconds
Started Dec 24 01:08:55 PM PST 23
Finished Dec 24 01:12:57 PM PST 23
Peak memory 251088 kb
Host smart-a79b36e4-4a13-44ce-b6f5-892333108c1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321929160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.1321929160
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2649853138
Short name T762
Test name
Test status
Simulation time 15474282 ps
CPU time 0.79 seconds
Started Dec 24 01:08:41 PM PST 23
Finished Dec 24 01:08:49 PM PST 23
Peak memory 208376 kb
Host smart-f28a8f92-1677-4919-9ac7-c0707c13e998
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649853138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.2649853138
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.1343131046
Short name T589
Test name
Test status
Simulation time 17828731 ps
CPU time 0.88 seconds
Started Dec 24 01:08:44 PM PST 23
Finished Dec 24 01:08:52 PM PST 23
Peak memory 209644 kb
Host smart-624df751-e23d-4b91-9dce-6672e692b9ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343131046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.1343131046
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.784902216
Short name T873
Test name
Test status
Simulation time 243121150 ps
CPU time 10.03 seconds
Started Dec 24 01:08:50 PM PST 23
Finished Dec 24 01:09:06 PM PST 23
Peak memory 218204 kb
Host smart-804698fe-ae0e-49ff-a187-92437f44ca2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784902216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.784902216
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.4013735801
Short name T66
Test name
Test status
Simulation time 348586518 ps
CPU time 1.89 seconds
Started Dec 24 01:08:52 PM PST 23
Finished Dec 24 01:09:00 PM PST 23
Peak memory 209704 kb
Host smart-8bd6d2ee-1f52-45ae-9157-68aa56990b21
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013735801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_a
ccess.4013735801
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.1061923349
Short name T767
Test name
Test status
Simulation time 149069617 ps
CPU time 3.25 seconds
Started Dec 24 01:08:53 PM PST 23
Finished Dec 24 01:09:03 PM PST 23
Peak memory 218168 kb
Host smart-d9402d47-4e60-4bd3-b582-bae7c34b9734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061923349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.1061923349
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.1980765483
Short name T853
Test name
Test status
Simulation time 835834666 ps
CPU time 14.12 seconds
Started Dec 24 01:08:51 PM PST 23
Finished Dec 24 01:09:11 PM PST 23
Peak memory 219188 kb
Host smart-913c6d16-43cb-4d66-af9c-8483924abe6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980765483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.1980765483
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.3046048397
Short name T452
Test name
Test status
Simulation time 876591991 ps
CPU time 10.55 seconds
Started Dec 24 01:08:49 PM PST 23
Finished Dec 24 01:09:05 PM PST 23
Peak memory 218132 kb
Host smart-26fd49d8-add1-4091-a935-478a1d367e69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046048397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.3046048397
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.3103422238
Short name T356
Test name
Test status
Simulation time 2848069116 ps
CPU time 16.28 seconds
Started Dec 24 01:08:44 PM PST 23
Finished Dec 24 01:09:07 PM PST 23
Peak memory 218184 kb
Host smart-37023f47-4f30-4e7a-92aa-24eec1fb185a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103422238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
3103422238
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.1711388137
Short name T819
Test name
Test status
Simulation time 2161009724 ps
CPU time 11.41 seconds
Started Dec 24 01:08:53 PM PST 23
Finished Dec 24 01:09:11 PM PST 23
Peak memory 218292 kb
Host smart-4bddf469-b1f1-4cc0-a9a9-28cdce574003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711388137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1711388137
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.2870094164
Short name T67
Test name
Test status
Simulation time 19720735 ps
CPU time 1.66 seconds
Started Dec 24 01:08:55 PM PST 23
Finished Dec 24 01:09:03 PM PST 23
Peak memory 213412 kb
Host smart-49c30a20-18b3-40e6-badc-f427f3b0d48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870094164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.2870094164
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.353862325
Short name T503
Test name
Test status
Simulation time 285197219 ps
CPU time 34.63 seconds
Started Dec 24 01:08:49 PM PST 23
Finished Dec 24 01:09:30 PM PST 23
Peak memory 251220 kb
Host smart-183ecb4b-af8e-4b2d-83d0-ad810da02ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353862325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.353862325
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.3028993603
Short name T311
Test name
Test status
Simulation time 186060367 ps
CPU time 8.9 seconds
Started Dec 24 01:08:52 PM PST 23
Finished Dec 24 01:09:08 PM PST 23
Peak memory 251184 kb
Host smart-1838124f-4560-4a67-9098-57869675d404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028993603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.3028993603
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.1110160561
Short name T881
Test name
Test status
Simulation time 51428152325 ps
CPU time 176.85 seconds
Started Dec 24 01:08:46 PM PST 23
Finished Dec 24 01:11:50 PM PST 23
Peak memory 284024 kb
Host smart-5ed875a5-f3d2-43f4-9941-1cf96c17cf9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110160561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.1110160561
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.4198100331
Short name T393
Test name
Test status
Simulation time 19683363 ps
CPU time 0.9 seconds
Started Dec 24 01:08:54 PM PST 23
Finished Dec 24 01:09:02 PM PST 23
Peak memory 208176 kb
Host smart-3a3ab8bd-3b61-4ba5-97e5-8950f8c2aa57
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198100331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.4198100331
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.2384535886
Short name T345
Test name
Test status
Simulation time 23138487 ps
CPU time 0.87 seconds
Started Dec 24 01:08:50 PM PST 23
Finished Dec 24 01:08:57 PM PST 23
Peak memory 209660 kb
Host smart-1c51296e-096e-4f4e-95e7-1c1a71349a8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384535886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.2384535886
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.3151629947
Short name T738
Test name
Test status
Simulation time 1145368040 ps
CPU time 14.09 seconds
Started Dec 24 01:09:04 PM PST 23
Finished Dec 24 01:09:22 PM PST 23
Peak memory 218208 kb
Host smart-be4bb8d1-fbc4-4f52-bac1-3e2f315b3f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151629947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.3151629947
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.768415495
Short name T963
Test name
Test status
Simulation time 4591488241 ps
CPU time 11.19 seconds
Started Dec 24 01:08:54 PM PST 23
Finished Dec 24 01:09:11 PM PST 23
Peak memory 209704 kb
Host smart-d9f6dfb6-cf64-4ce3-a870-a3fd7c5228da
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768415495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_ac
cess.768415495
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.4197661928
Short name T839
Test name
Test status
Simulation time 29227196 ps
CPU time 1.8 seconds
Started Dec 24 01:08:49 PM PST 23
Finished Dec 24 01:08:57 PM PST 23
Peak memory 218216 kb
Host smart-f20bbbd8-52c6-426a-8d4b-8d67abd807cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197661928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.4197661928
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.3588037085
Short name T590
Test name
Test status
Simulation time 2381842910 ps
CPU time 17.53 seconds
Started Dec 24 01:08:52 PM PST 23
Finished Dec 24 01:09:16 PM PST 23
Peak memory 219208 kb
Host smart-a354bc9c-0ba3-4270-8eed-9f29b2ca2b71
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588037085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3588037085
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.4126086587
Short name T882
Test name
Test status
Simulation time 288596227 ps
CPU time 12.25 seconds
Started Dec 24 01:08:52 PM PST 23
Finished Dec 24 01:09:11 PM PST 23
Peak memory 218168 kb
Host smart-8c886664-b2f9-44ee-b8b8-1640c05fb2bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126086587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.4126086587
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.4233259260
Short name T323
Test name
Test status
Simulation time 602717755 ps
CPU time 5.19 seconds
Started Dec 24 01:08:51 PM PST 23
Finished Dec 24 01:09:02 PM PST 23
Peak memory 218144 kb
Host smart-8bcbe421-1ced-405c-83b4-62a0ad68a85c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233259260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
4233259260
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.2191246494
Short name T557
Test name
Test status
Simulation time 3630647204 ps
CPU time 15.62 seconds
Started Dec 24 01:08:47 PM PST 23
Finished Dec 24 01:09:09 PM PST 23
Peak memory 218212 kb
Host smart-6c479451-6075-4dda-ba4e-b4987af71bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191246494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.2191246494
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.2105403927
Short name T980
Test name
Test status
Simulation time 144305784 ps
CPU time 4.5 seconds
Started Dec 24 01:08:52 PM PST 23
Finished Dec 24 01:09:03 PM PST 23
Peak memory 214500 kb
Host smart-8719446d-8838-409e-a1dc-d77732cc242c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105403927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.2105403927
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.865645516
Short name T602
Test name
Test status
Simulation time 488452664 ps
CPU time 28.11 seconds
Started Dec 24 01:08:51 PM PST 23
Finished Dec 24 01:09:25 PM PST 23
Peak memory 251128 kb
Host smart-bfbbb6d6-49d8-4a05-964a-a0602e62a913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865645516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.865645516
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.3420066372
Short name T332
Test name
Test status
Simulation time 217166750 ps
CPU time 3.73 seconds
Started Dec 24 01:08:55 PM PST 23
Finished Dec 24 01:09:05 PM PST 23
Peak memory 218240 kb
Host smart-ee0d01c4-2f1b-498c-b215-f92a7d0831bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420066372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.3420066372
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.1254745317
Short name T610
Test name
Test status
Simulation time 7587588304 ps
CPU time 202.36 seconds
Started Dec 24 01:09:02 PM PST 23
Finished Dec 24 01:12:30 PM PST 23
Peak memory 267644 kb
Host smart-253e4957-b47b-490c-bc29-8da5084e1a85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254745317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.1254745317
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.163412197
Short name T880
Test name
Test status
Simulation time 15798160 ps
CPU time 0.84 seconds
Started Dec 24 01:08:55 PM PST 23
Finished Dec 24 01:09:03 PM PST 23
Peak memory 208336 kb
Host smart-262262c7-e02b-4548-9f91-bf9aeb94e70d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163412197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ct
rl_volatile_unlock_smoke.163412197
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.3395430346
Short name T584
Test name
Test status
Simulation time 25148806 ps
CPU time 1.36 seconds
Started Dec 24 01:08:57 PM PST 23
Finished Dec 24 01:09:05 PM PST 23
Peak memory 209668 kb
Host smart-33035c10-1720-45f6-85a5-c70656edd8bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395430346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.3395430346
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.734358261
Short name T541
Test name
Test status
Simulation time 344872316 ps
CPU time 12.75 seconds
Started Dec 24 01:08:48 PM PST 23
Finished Dec 24 01:09:07 PM PST 23
Peak memory 218120 kb
Host smart-cbab0602-c8d1-40be-8a64-5a4d01018b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734358261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.734358261
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.1357396894
Short name T895
Test name
Test status
Simulation time 786443818 ps
CPU time 3.67 seconds
Started Dec 24 01:08:52 PM PST 23
Finished Dec 24 01:09:02 PM PST 23
Peak memory 209664 kb
Host smart-a341206f-1568-46da-a387-5c1217bd3269
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357396894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_a
ccess.1357396894
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.1665023118
Short name T771
Test name
Test status
Simulation time 90447372 ps
CPU time 1.68 seconds
Started Dec 24 01:08:44 PM PST 23
Finished Dec 24 01:08:53 PM PST 23
Peak memory 218172 kb
Host smart-eb09646e-43c5-46ed-8584-b467cd8996bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665023118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.1665023118
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.1409203007
Short name T516
Test name
Test status
Simulation time 295125553 ps
CPU time 11.92 seconds
Started Dec 24 01:08:53 PM PST 23
Finished Dec 24 01:09:11 PM PST 23
Peak memory 218244 kb
Host smart-c68cf4c1-803d-4569-842e-1ce0ced26285
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409203007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.1409203007
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.3765034237
Short name T327
Test name
Test status
Simulation time 1133784027 ps
CPU time 21.92 seconds
Started Dec 24 01:08:47 PM PST 23
Finished Dec 24 01:09:15 PM PST 23
Peak memory 218124 kb
Host smart-44e3a1fd-ac32-4be5-858c-b069b334ad8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765034237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.3765034237
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.1998184476
Short name T680
Test name
Test status
Simulation time 160339038 ps
CPU time 6.01 seconds
Started Dec 24 01:08:48 PM PST 23
Finished Dec 24 01:09:00 PM PST 23
Peak memory 218160 kb
Host smart-71938e7d-e836-49ec-a6a4-30655595415d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998184476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
1998184476
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.283446865
Short name T183
Test name
Test status
Simulation time 703265459 ps
CPU time 10.92 seconds
Started Dec 24 01:08:59 PM PST 23
Finished Dec 24 01:09:17 PM PST 23
Peak memory 218236 kb
Host smart-21ca4637-c108-45d4-9e71-9113de30f56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283446865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.283446865
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.4235971080
Short name T83
Test name
Test status
Simulation time 309295726 ps
CPU time 3.39 seconds
Started Dec 24 01:08:46 PM PST 23
Finished Dec 24 01:08:55 PM PST 23
Peak memory 213812 kb
Host smart-68ea6b51-b425-452d-a141-d5c4587e1cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235971080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.4235971080
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.3211754120
Short name T461
Test name
Test status
Simulation time 252857526 ps
CPU time 23.43 seconds
Started Dec 24 01:08:47 PM PST 23
Finished Dec 24 01:09:17 PM PST 23
Peak memory 251124 kb
Host smart-4639e33d-b0b5-4ac3-8fd8-e188108ec3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211754120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3211754120
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.3340297527
Short name T376
Test name
Test status
Simulation time 258338697 ps
CPU time 8.26 seconds
Started Dec 24 01:08:56 PM PST 23
Finished Dec 24 01:09:11 PM PST 23
Peak memory 251224 kb
Host smart-c30f6836-0379-4723-8f6c-6dcde28f7d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340297527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.3340297527
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.1002230122
Short name T457
Test name
Test status
Simulation time 8515067575 ps
CPU time 114.3 seconds
Started Dec 24 01:08:52 PM PST 23
Finished Dec 24 01:10:53 PM PST 23
Peak memory 404596 kb
Host smart-4404d7b2-0eb1-4e3d-a566-a9a77c577f6f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002230122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.1002230122
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.972720641
Short name T633
Test name
Test status
Simulation time 40583053 ps
CPU time 0.85 seconds
Started Dec 24 01:08:58 PM PST 23
Finished Dec 24 01:09:06 PM PST 23
Peak memory 208336 kb
Host smart-3b9d90bd-f0b6-428a-9038-fb2ceafbaa97
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972720641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ct
rl_volatile_unlock_smoke.972720641
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.4047445997
Short name T19
Test name
Test status
Simulation time 16952024 ps
CPU time 0.89 seconds
Started Dec 24 01:09:20 PM PST 23
Finished Dec 24 01:09:28 PM PST 23
Peak memory 209656 kb
Host smart-063b3fb4-4588-45be-b5e7-d94b5a427cb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047445997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.4047445997
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.2517019316
Short name T328
Test name
Test status
Simulation time 540762107 ps
CPU time 14.29 seconds
Started Dec 24 01:08:52 PM PST 23
Finished Dec 24 01:09:13 PM PST 23
Peak memory 218184 kb
Host smart-82be701a-6005-40d6-bd72-3d2694a015fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517019316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.2517019316
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.1393227649
Short name T22
Test name
Test status
Simulation time 506392340 ps
CPU time 3.45 seconds
Started Dec 24 01:08:52 PM PST 23
Finished Dec 24 01:09:02 PM PST 23
Peak memory 209640 kb
Host smart-8f5bd3b6-1dc1-4ce4-ac35-06443179822e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393227649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_a
ccess.1393227649
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.1220640985
Short name T593
Test name
Test status
Simulation time 178202892 ps
CPU time 2.25 seconds
Started Dec 24 01:08:58 PM PST 23
Finished Dec 24 01:09:07 PM PST 23
Peak memory 218228 kb
Host smart-968fcec6-b498-427c-a80b-e026137bbe33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220640985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.1220640985
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.2991157639
Short name T442
Test name
Test status
Simulation time 1728722607 ps
CPU time 10.92 seconds
Started Dec 24 01:08:57 PM PST 23
Finished Dec 24 01:09:15 PM PST 23
Peak memory 218624 kb
Host smart-edf51266-96d8-49fa-8e53-7e5ea999f41b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991157639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.2991157639
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.3208885610
Short name T348
Test name
Test status
Simulation time 946942458 ps
CPU time 12.53 seconds
Started Dec 24 01:08:54 PM PST 23
Finished Dec 24 01:09:12 PM PST 23
Peak memory 218116 kb
Host smart-5a16cc29-4be5-4500-a32c-0f414b6b9258
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208885610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.3208885610
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.3429637867
Short name T764
Test name
Test status
Simulation time 361196589 ps
CPU time 13.12 seconds
Started Dec 24 01:08:55 PM PST 23
Finished Dec 24 01:09:15 PM PST 23
Peak memory 218116 kb
Host smart-ac30f249-245b-4179-97a5-34aaabb97ae7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429637867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
3429637867
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.2858512138
Short name T52
Test name
Test status
Simulation time 312798188 ps
CPU time 7.37 seconds
Started Dec 24 01:08:56 PM PST 23
Finished Dec 24 01:09:10 PM PST 23
Peak memory 218228 kb
Host smart-2e28b6b0-621e-4a13-a218-dff338c63eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858512138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.2858512138
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.2545255461
Short name T438
Test name
Test status
Simulation time 102502329 ps
CPU time 1.92 seconds
Started Dec 24 01:08:48 PM PST 23
Finished Dec 24 01:08:56 PM PST 23
Peak memory 213948 kb
Host smart-c9653832-9a24-4c34-85e8-a0852cb84d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545255461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.2545255461
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.604084580
Short name T481
Test name
Test status
Simulation time 499443209 ps
CPU time 26.4 seconds
Started Dec 24 01:08:52 PM PST 23
Finished Dec 24 01:09:25 PM PST 23
Peak memory 251036 kb
Host smart-f1117801-0b7f-4310-9981-a14aee00fe9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604084580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.604084580
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.3365306674
Short name T761
Test name
Test status
Simulation time 228412744 ps
CPU time 3.89 seconds
Started Dec 24 01:09:01 PM PST 23
Finished Dec 24 01:09:12 PM PST 23
Peak memory 222336 kb
Host smart-e43dc1e1-3677-4132-81e8-d8f53ea88db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365306674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.3365306674
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.3241733089
Short name T347
Test name
Test status
Simulation time 49513610722 ps
CPU time 200.72 seconds
Started Dec 24 01:09:11 PM PST 23
Finished Dec 24 01:12:34 PM PST 23
Peak memory 284056 kb
Host smart-0f6db783-e202-4fd1-95c2-31b315292323
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241733089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.3241733089
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3741085065
Short name T612
Test name
Test status
Simulation time 158312905 ps
CPU time 0.91 seconds
Started Dec 24 01:08:55 PM PST 23
Finished Dec 24 01:09:03 PM PST 23
Peak memory 211396 kb
Host smart-e32379c8-4434-443f-9d56-5af875d0accd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741085065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3741085065
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.3683230552
Short name T300
Test name
Test status
Simulation time 55128424 ps
CPU time 1.33 seconds
Started Dec 24 01:09:19 PM PST 23
Finished Dec 24 01:09:28 PM PST 23
Peak memory 209632 kb
Host smart-56a3c6fa-7d7c-4e9f-ad34-b7c4b34c7b69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683230552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.3683230552
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.3858034758
Short name T439
Test name
Test status
Simulation time 400031420 ps
CPU time 17.09 seconds
Started Dec 24 01:09:15 PM PST 23
Finished Dec 24 01:09:36 PM PST 23
Peak memory 218200 kb
Host smart-4ce6fe8c-e957-4258-88ea-ba135be3f722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858034758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3858034758
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.1696051390
Short name T879
Test name
Test status
Simulation time 199111917 ps
CPU time 2.41 seconds
Started Dec 24 01:09:11 PM PST 23
Finished Dec 24 01:09:16 PM PST 23
Peak memory 209700 kb
Host smart-9e8e7347-0c08-4926-874d-459150138d0e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696051390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_a
ccess.1696051390
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.2969130260
Short name T526
Test name
Test status
Simulation time 369269127 ps
CPU time 2.93 seconds
Started Dec 24 01:09:15 PM PST 23
Finished Dec 24 01:09:22 PM PST 23
Peak memory 218264 kb
Host smart-7623994a-c822-4ef0-bc30-0cccd688c702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969130260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.2969130260
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.681817798
Short name T45
Test name
Test status
Simulation time 525459221 ps
CPU time 12.5 seconds
Started Dec 24 01:09:14 PM PST 23
Finished Dec 24 01:09:28 PM PST 23
Peak memory 219220 kb
Host smart-795044e4-8ff3-4bd7-b28c-aed6fc7e057d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681817798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.681817798
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1690775000
Short name T325
Test name
Test status
Simulation time 1343927722 ps
CPU time 10.63 seconds
Started Dec 24 01:09:15 PM PST 23
Finished Dec 24 01:09:31 PM PST 23
Peak memory 217976 kb
Host smart-6c6e12ed-e3a9-4342-b6be-a49dbe98eac0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690775000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1690775000
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.2136213285
Short name T331
Test name
Test status
Simulation time 1008338504 ps
CPU time 9.49 seconds
Started Dec 24 01:09:12 PM PST 23
Finished Dec 24 01:09:24 PM PST 23
Peak memory 218160 kb
Host smart-82af33c9-79d2-4782-86bb-241b38df0753
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136213285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
2136213285
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.3219364376
Short name T813
Test name
Test status
Simulation time 295279143 ps
CPU time 7.24 seconds
Started Dec 24 01:08:56 PM PST 23
Finished Dec 24 01:09:10 PM PST 23
Peak memory 218176 kb
Host smart-72a77d3b-43e7-4541-8f21-024db9977d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219364376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3219364376
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.1305090817
Short name T918
Test name
Test status
Simulation time 23814061 ps
CPU time 1.52 seconds
Started Dec 24 01:09:12 PM PST 23
Finished Dec 24 01:09:15 PM PST 23
Peak memory 213296 kb
Host smart-60175aad-315a-43f8-bec2-2b73e92ce16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305090817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.1305090817
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.3868164217
Short name T719
Test name
Test status
Simulation time 6191455151 ps
CPU time 28.79 seconds
Started Dec 24 01:08:58 PM PST 23
Finished Dec 24 01:09:34 PM PST 23
Peak memory 251084 kb
Host smart-36562581-c674-4d4c-873a-0e443880ec45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868164217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.3868164217
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.2018378122
Short name T493
Test name
Test status
Simulation time 54330668 ps
CPU time 7.36 seconds
Started Dec 24 01:09:12 PM PST 23
Finished Dec 24 01:09:21 PM PST 23
Peak memory 251184 kb
Host smart-437e351e-743e-4e04-ae35-9b51a60b0639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018378122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.2018378122
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.12627862
Short name T108
Test name
Test status
Simulation time 1866063520 ps
CPU time 50.96 seconds
Started Dec 24 01:09:07 PM PST 23
Finished Dec 24 01:10:00 PM PST 23
Peak memory 250700 kb
Host smart-33a3a8a2-dfa3-446f-b30b-eb0b30deba45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12627862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.lc_ctrl_stress_all.12627862
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.3782729473
Short name T37
Test name
Test status
Simulation time 14163192 ps
CPU time 0.95 seconds
Started Dec 24 01:09:05 PM PST 23
Finished Dec 24 01:09:09 PM PST 23
Peak memory 208224 kb
Host smart-49389abd-cd78-40b6-8e89-bc3c2b7c9c48
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782729473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.3782729473
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.4273854941
Short name T654
Test name
Test status
Simulation time 51643886 ps
CPU time 0.93 seconds
Started Dec 24 01:07:02 PM PST 23
Finished Dec 24 01:07:06 PM PST 23
Peak memory 208488 kb
Host smart-5532825c-1488-4a85-bf2c-76490a1bb220
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273854941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.4273854941
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2438718399
Short name T329
Test name
Test status
Simulation time 37070237 ps
CPU time 0.8 seconds
Started Dec 24 01:06:26 PM PST 23
Finished Dec 24 01:06:28 PM PST 23
Peak memory 209340 kb
Host smart-0213cd86-b38a-44af-8575-b637eecf15b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438718399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2438718399
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.1299098980
Short name T532
Test name
Test status
Simulation time 1368821612 ps
CPU time 9.04 seconds
Started Dec 24 01:07:04 PM PST 23
Finished Dec 24 01:07:16 PM PST 23
Peak memory 218120 kb
Host smart-6f4fdde1-abf5-4b6c-ab74-b416d766b299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299098980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.1299098980
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.3810492510
Short name T618
Test name
Test status
Simulation time 302329481 ps
CPU time 4.61 seconds
Started Dec 24 01:07:00 PM PST 23
Finished Dec 24 01:07:08 PM PST 23
Peak memory 209652 kb
Host smart-b4de9d9a-2d0b-441f-974b-8cfeb06a0ef8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810492510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_ac
cess.3810492510
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.2075149686
Short name T950
Test name
Test status
Simulation time 3088158041 ps
CPU time 44.18 seconds
Started Dec 24 01:06:28 PM PST 23
Finished Dec 24 01:07:12 PM PST 23
Peak memory 218216 kb
Host smart-ed3e862c-1b7b-4a08-9ef0-93e4be75f5e7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075149686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.2075149686
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.3936387633
Short name T417
Test name
Test status
Simulation time 909122131 ps
CPU time 6.46 seconds
Started Dec 24 01:07:05 PM PST 23
Finished Dec 24 01:07:14 PM PST 23
Peak memory 217032 kb
Host smart-2c4fc3e1-72ee-42d2-8624-c6e225c04cdb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936387633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_
priority.3936387633
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3013102891
Short name T650
Test name
Test status
Simulation time 3235689435 ps
CPU time 7.39 seconds
Started Dec 24 01:06:29 PM PST 23
Finished Dec 24 01:06:37 PM PST 23
Peak memory 217628 kb
Host smart-604dfad7-dfc0-4c3e-8663-3e2d351c3051
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013102891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.3013102891
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2110410000
Short name T774
Test name
Test status
Simulation time 2567767743 ps
CPU time 9.98 seconds
Started Dec 24 01:07:04 PM PST 23
Finished Dec 24 01:07:17 PM PST 23
Peak memory 212952 kb
Host smart-257efa30-444d-47ec-9e5d-50f0d74dafa5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110410000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.2110410000
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.3878701520
Short name T440
Test name
Test status
Simulation time 462319853 ps
CPU time 5.97 seconds
Started Dec 24 01:07:03 PM PST 23
Finished Dec 24 01:07:12 PM PST 23
Peak memory 213188 kb
Host smart-e4f8d7be-af88-485d-adbf-bf29ce544413
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878701520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
3878701520
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.2952439080
Short name T941
Test name
Test status
Simulation time 17579791091 ps
CPU time 36.47 seconds
Started Dec 24 01:06:33 PM PST 23
Finished Dec 24 01:07:11 PM PST 23
Peak memory 267560 kb
Host smart-bb023609-8cb6-4348-b206-d0a31fc79ae3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952439080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.2952439080
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2503728456
Short name T381
Test name
Test status
Simulation time 413084336 ps
CPU time 13.59 seconds
Started Dec 24 01:07:05 PM PST 23
Finished Dec 24 01:07:22 PM PST 23
Peak memory 220900 kb
Host smart-7417b6c6-f7e1-440f-8cbb-54506f7aef76
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503728456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.2503728456
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.1150971493
Short name T922
Test name
Test status
Simulation time 732619879 ps
CPU time 2.56 seconds
Started Dec 24 01:06:26 PM PST 23
Finished Dec 24 01:06:29 PM PST 23
Peak memory 218216 kb
Host smart-65d50c27-bc14-4808-95fd-b806895e65bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150971493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.1150971493
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.562596974
Short name T599
Test name
Test status
Simulation time 163953334 ps
CPU time 9.65 seconds
Started Dec 24 01:06:47 PM PST 23
Finished Dec 24 01:06:59 PM PST 23
Peak memory 214016 kb
Host smart-78825f50-aec3-41c9-9124-71bf34bb5f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562596974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.562596974
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.2869860128
Short name T484
Test name
Test status
Simulation time 1431295987 ps
CPU time 15.78 seconds
Started Dec 24 01:06:34 PM PST 23
Finished Dec 24 01:06:52 PM PST 23
Peak memory 219368 kb
Host smart-cbf3f228-15d9-4d00-b915-519c3ef96686
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869860128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.2869860128
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.3546818189
Short name T28
Test name
Test status
Simulation time 939379212 ps
CPU time 13.31 seconds
Started Dec 24 01:06:36 PM PST 23
Finished Dec 24 01:06:50 PM PST 23
Peak memory 218080 kb
Host smart-8b60224e-4d17-404c-ac3b-ffd11a4297aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546818189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.3546818189
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3986858196
Short name T565
Test name
Test status
Simulation time 1650662301 ps
CPU time 9.92 seconds
Started Dec 24 01:06:29 PM PST 23
Finished Dec 24 01:06:40 PM PST 23
Peak memory 218156 kb
Host smart-94b5b3cb-2bf4-44b6-966b-06a0c76addc5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986858196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.3
986858196
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.1208767189
Short name T181
Test name
Test status
Simulation time 1805569479 ps
CPU time 9.53 seconds
Started Dec 24 01:06:52 PM PST 23
Finished Dec 24 01:07:06 PM PST 23
Peak memory 217760 kb
Host smart-73446f75-140b-49b9-a5bd-9bfdde94f704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208767189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1208767189
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.1439549228
Short name T476
Test name
Test status
Simulation time 25306885 ps
CPU time 1.66 seconds
Started Dec 24 01:06:28 PM PST 23
Finished Dec 24 01:06:31 PM PST 23
Peak memory 213060 kb
Host smart-916d4ccc-9ebc-45e4-9836-e5a8ae5aa617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439549228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.1439549228
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.592693530
Short name T609
Test name
Test status
Simulation time 224643983 ps
CPU time 18.13 seconds
Started Dec 24 01:06:31 PM PST 23
Finished Dec 24 01:06:51 PM PST 23
Peak memory 251108 kb
Host smart-df4a8ca2-7fbb-4733-8858-efa45b0d413c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592693530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.592693530
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.3778588167
Short name T597
Test name
Test status
Simulation time 98024407 ps
CPU time 7.74 seconds
Started Dec 24 01:06:30 PM PST 23
Finished Dec 24 01:06:40 PM PST 23
Peak memory 251220 kb
Host smart-d50aebef-e5aa-44aa-bebc-766b4dfd448a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778588167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.3778588167
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.1019490998
Short name T715
Test name
Test status
Simulation time 117387895469 ps
CPU time 923.86 seconds
Started Dec 24 01:06:47 PM PST 23
Finished Dec 24 01:22:12 PM PST 23
Peak memory 251108 kb
Host smart-c862c30e-d237-4ed0-b50a-ef69939ec113
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019490998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.1019490998
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.3844719560
Short name T852
Test name
Test status
Simulation time 28576395 ps
CPU time 0.72 seconds
Started Dec 24 01:06:47 PM PST 23
Finished Dec 24 01:06:52 PM PST 23
Peak memory 208168 kb
Host smart-4be3bbe6-e611-4f61-b269-0c595b1d2c47
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844719560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.3844719560
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.1743444168
Short name T495
Test name
Test status
Simulation time 44872038 ps
CPU time 0.93 seconds
Started Dec 24 01:06:35 PM PST 23
Finished Dec 24 01:06:38 PM PST 23
Peak memory 208504 kb
Host smart-3b9afec1-7575-49e3-b91f-546f3464b7c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743444168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.1743444168
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3945294835
Short name T175
Test name
Test status
Simulation time 13089613 ps
CPU time 0.81 seconds
Started Dec 24 01:06:33 PM PST 23
Finished Dec 24 01:06:35 PM PST 23
Peak memory 209328 kb
Host smart-98f5862c-0ab6-442f-abe6-be0d73bc3d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945294835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3945294835
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.1305492110
Short name T724
Test name
Test status
Simulation time 475206804 ps
CPU time 15.36 seconds
Started Dec 24 01:06:49 PM PST 23
Finished Dec 24 01:07:08 PM PST 23
Peak memory 218224 kb
Host smart-f75c0f9b-3957-46ed-881b-0c4471414854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305492110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.1305492110
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.172494639
Short name T759
Test name
Test status
Simulation time 2052110546 ps
CPU time 12.32 seconds
Started Dec 24 01:06:35 PM PST 23
Finished Dec 24 01:06:49 PM PST 23
Peak memory 209740 kb
Host smart-7f7f4a9e-ee28-4a5d-a1a5-45223ecc5fa6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172494639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_acc
ess.172494639
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.1595135294
Short name T683
Test name
Test status
Simulation time 1061121141 ps
CPU time 19.34 seconds
Started Dec 24 01:06:29 PM PST 23
Finished Dec 24 01:06:49 PM PST 23
Peak memory 218076 kb
Host smart-7d325490-7676-4739-8cd9-ef62e57538b6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595135294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.1595135294
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.3605987731
Short name T754
Test name
Test status
Simulation time 539018003 ps
CPU time 6.62 seconds
Started Dec 24 01:06:28 PM PST 23
Finished Dec 24 01:06:36 PM PST 23
Peak memory 209764 kb
Host smart-86c37c07-4723-424d-91fa-12ea58f86ad3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605987731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
priority.3605987731
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.917885936
Short name T794
Test name
Test status
Simulation time 274308116 ps
CPU time 5.37 seconds
Started Dec 24 01:06:45 PM PST 23
Finished Dec 24 01:06:52 PM PST 23
Peak memory 218048 kb
Host smart-b369dec9-7287-41cd-9dc2-507506679c6c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917885936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
prog_failure.917885936
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.657392139
Short name T542
Test name
Test status
Simulation time 3707036207 ps
CPU time 11.59 seconds
Started Dec 24 01:06:32 PM PST 23
Finished Dec 24 01:06:45 PM PST 23
Peak memory 213612 kb
Host smart-8801058a-b903-42c0-bb20-54bd9a2ed665
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657392139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_regwen_during_op.657392139
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.2610669733
Short name T487
Test name
Test status
Simulation time 1036570346 ps
CPU time 6.21 seconds
Started Dec 24 01:06:50 PM PST 23
Finished Dec 24 01:07:00 PM PST 23
Peak memory 213228 kb
Host smart-383ae1b1-7123-4185-9b0b-e1f99d704c4d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610669733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
2610669733
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.226967734
Short name T810
Test name
Test status
Simulation time 2684172145 ps
CPU time 54.4 seconds
Started Dec 24 01:06:35 PM PST 23
Finished Dec 24 01:07:31 PM PST 23
Peak memory 280904 kb
Host smart-ff068106-c685-4c4a-abad-4d5476d1b892
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226967734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_state_failure.226967734
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.4173704759
Short name T581
Test name
Test status
Simulation time 492565393 ps
CPU time 7.11 seconds
Started Dec 24 01:06:51 PM PST 23
Finished Dec 24 01:07:02 PM PST 23
Peak memory 218116 kb
Host smart-3ccd3bf7-21b5-43ca-ac65-1fcafc64927f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173704759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.4173704759
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.115732513
Short name T940
Test name
Test status
Simulation time 82868979 ps
CPU time 4.19 seconds
Started Dec 24 01:06:49 PM PST 23
Finished Dec 24 01:06:57 PM PST 23
Peak memory 218220 kb
Host smart-123a109b-7d62-4440-a701-534854d6b93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115732513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.115732513
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.727538059
Short name T410
Test name
Test status
Simulation time 1876763243 ps
CPU time 6.07 seconds
Started Dec 24 01:06:32 PM PST 23
Finished Dec 24 01:06:40 PM PST 23
Peak memory 218232 kb
Host smart-72a880ef-5cc2-4e81-acac-c812c5f844a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727538059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.727538059
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.3347286685
Short name T631
Test name
Test status
Simulation time 3090771071 ps
CPU time 19.86 seconds
Started Dec 24 01:06:51 PM PST 23
Finished Dec 24 01:07:15 PM PST 23
Peak memory 219760 kb
Host smart-c2d14bae-4d31-4bf2-b104-1b3ad186ae46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347286685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.3347286685
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.1418122591
Short name T628
Test name
Test status
Simulation time 651791054 ps
CPU time 10.23 seconds
Started Dec 24 01:06:35 PM PST 23
Finished Dec 24 01:06:47 PM PST 23
Peak memory 218204 kb
Host smart-937e2c9f-6fd4-449f-8fe0-cfe39e9d1311
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418122591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.1418122591
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.2211833478
Short name T396
Test name
Test status
Simulation time 2071713333 ps
CPU time 11.16 seconds
Started Dec 24 01:06:47 PM PST 23
Finished Dec 24 01:07:02 PM PST 23
Peak memory 218344 kb
Host smart-a7e9229a-c094-4d04-bc90-bcf43bc65ae1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211833478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.2
211833478
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.3441329275
Short name T676
Test name
Test status
Simulation time 307489874 ps
CPU time 7.77 seconds
Started Dec 24 01:06:30 PM PST 23
Finished Dec 24 01:06:40 PM PST 23
Peak memory 218208 kb
Host smart-1ee1b821-9c83-40b0-a96c-87c04e0239d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441329275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.3441329275
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.1130329824
Short name T315
Test name
Test status
Simulation time 991181124 ps
CPU time 6.1 seconds
Started Dec 24 01:07:00 PM PST 23
Finished Dec 24 01:07:10 PM PST 23
Peak memory 214404 kb
Host smart-3ad540d5-70ba-4415-b988-a4ff502638cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130329824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.1130329824
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.1733174606
Short name T820
Test name
Test status
Simulation time 728534873 ps
CPU time 16.55 seconds
Started Dec 24 01:06:32 PM PST 23
Finished Dec 24 01:06:51 PM PST 23
Peak memory 250872 kb
Host smart-ec25f7cf-6bd7-4abe-b6f9-c72f22d57653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733174606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.1733174606
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.940981982
Short name T103
Test name
Test status
Simulation time 223098879 ps
CPU time 7.36 seconds
Started Dec 24 01:06:25 PM PST 23
Finished Dec 24 01:06:33 PM PST 23
Peak memory 251144 kb
Host smart-3e138cc7-dc1a-4bf7-86e1-c843a3fe4cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940981982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.940981982
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.288048981
Short name T961
Test name
Test status
Simulation time 1593325028 ps
CPU time 62.64 seconds
Started Dec 24 01:06:56 PM PST 23
Finished Dec 24 01:08:03 PM PST 23
Peak memory 251196 kb
Host smart-223e24da-624e-40ef-ac32-00c0fbac3f36
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288048981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.288048981
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.3613451695
Short name T704
Test name
Test status
Simulation time 74376722 ps
CPU time 0.76 seconds
Started Dec 24 01:06:34 PM PST 23
Finished Dec 24 01:06:37 PM PST 23
Peak memory 208308 kb
Host smart-7812346d-60a4-4542-8c50-ab2ff0865805
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613451695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.3613451695
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.3451823707
Short name T314
Test name
Test status
Simulation time 11934471 ps
CPU time 0.87 seconds
Started Dec 24 01:07:22 PM PST 23
Finished Dec 24 01:07:26 PM PST 23
Peak memory 208060 kb
Host smart-cb7923ec-0d76-4acf-b702-03c4286f7bb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451823707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.3451823707
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.2207941770
Short name T692
Test name
Test status
Simulation time 343366670 ps
CPU time 11.96 seconds
Started Dec 24 01:07:05 PM PST 23
Finished Dec 24 01:07:20 PM PST 23
Peak memory 218212 kb
Host smart-ea02cf3a-7415-4fe2-9fa3-b8e05e8200a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207941770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.2207941770
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.1838234426
Short name T946
Test name
Test status
Simulation time 1244506533 ps
CPU time 27.87 seconds
Started Dec 24 01:07:06 PM PST 23
Finished Dec 24 01:07:37 PM PST 23
Peak memory 209620 kb
Host smart-80724f68-e355-4b32-828a-5aaceddb788f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838234426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_ac
cess.1838234426
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.1075121429
Short name T422
Test name
Test status
Simulation time 4964808106 ps
CPU time 35.14 seconds
Started Dec 24 01:07:09 PM PST 23
Finished Dec 24 01:07:51 PM PST 23
Peak memory 218144 kb
Host smart-d26eeaae-f14c-490d-87b3-330f9631c6b8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075121429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.1075121429
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.3913381391
Short name T860
Test name
Test status
Simulation time 396374049 ps
CPU time 2.01 seconds
Started Dec 24 01:06:57 PM PST 23
Finished Dec 24 01:07:03 PM PST 23
Peak memory 209680 kb
Host smart-ae5ac041-1b39-4b61-b8cc-3ec7c8cf96e6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913381391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
priority.3913381391
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.3370697412
Short name T350
Test name
Test status
Simulation time 2270599365 ps
CPU time 20.59 seconds
Started Dec 24 01:07:07 PM PST 23
Finished Dec 24 01:07:32 PM PST 23
Peak memory 218208 kb
Host smart-a60c335d-7b7a-4cd0-96d9-9a4fb79c2267
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370697412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.3370697412
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2897128099
Short name T718
Test name
Test status
Simulation time 2392776560 ps
CPU time 13.97 seconds
Started Dec 24 01:07:15 PM PST 23
Finished Dec 24 01:07:34 PM PST 23
Peak memory 213100 kb
Host smart-a8e14516-7250-49bd-81eb-d1baa1a3b05d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897128099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.2897128099
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1963050966
Short name T4
Test name
Test status
Simulation time 225314149 ps
CPU time 6.75 seconds
Started Dec 24 01:06:50 PM PST 23
Finished Dec 24 01:07:01 PM PST 23
Peak memory 213248 kb
Host smart-ee9fa395-ad3b-4221-baa4-803084f0386f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963050966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
1963050966
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.544205557
Short name T31
Test name
Test status
Simulation time 5754705741 ps
CPU time 32.32 seconds
Started Dec 24 01:07:09 PM PST 23
Finished Dec 24 01:07:48 PM PST 23
Peak memory 275740 kb
Host smart-eb6391ec-a325-43ff-8f37-d0c5fcaab42b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544205557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_state_failure.544205557
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.659145859
Short name T830
Test name
Test status
Simulation time 4544663917 ps
CPU time 14.44 seconds
Started Dec 24 01:06:55 PM PST 23
Finished Dec 24 01:07:14 PM PST 23
Peak memory 249720 kb
Host smart-8552ebb3-d148-49aa-8890-b97788cd4d8a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659145859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_state_post_trans.659145859
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.3744730019
Short name T976
Test name
Test status
Simulation time 510781089 ps
CPU time 3.83 seconds
Started Dec 24 01:06:56 PM PST 23
Finished Dec 24 01:07:05 PM PST 23
Peak memory 218132 kb
Host smart-0939c7d2-702e-4b3a-befa-3d2597523ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744730019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.3744730019
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.388182182
Short name T489
Test name
Test status
Simulation time 964216740 ps
CPU time 15.28 seconds
Started Dec 24 01:06:50 PM PST 23
Finished Dec 24 01:07:10 PM PST 23
Peak memory 213492 kb
Host smart-c515c702-19cc-4630-9f52-6601dedb82cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388182182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.388182182
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.1545411555
Short name T851
Test name
Test status
Simulation time 238742398 ps
CPU time 12.91 seconds
Started Dec 24 01:07:08 PM PST 23
Finished Dec 24 01:07:27 PM PST 23
Peak memory 219188 kb
Host smart-a1080d35-a087-4bbe-8469-e1058fae2cbb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545411555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.1545411555
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.211063717
Short name T686
Test name
Test status
Simulation time 404670161 ps
CPU time 16.07 seconds
Started Dec 24 01:07:07 PM PST 23
Finished Dec 24 01:07:28 PM PST 23
Peak memory 218132 kb
Host smart-9ec9e9a0-c6d2-4def-9993-7b5d7007f3a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211063717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_dig
est.211063717
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1012424280
Short name T865
Test name
Test status
Simulation time 340288443 ps
CPU time 9.57 seconds
Started Dec 24 01:07:29 PM PST 23
Finished Dec 24 01:07:40 PM PST 23
Peak memory 218080 kb
Host smart-48d0316f-d26c-486a-b6c2-c7d7f23f87c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012424280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
012424280
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.3342441866
Short name T182
Test name
Test status
Simulation time 449023482 ps
CPU time 6.39 seconds
Started Dec 24 01:06:48 PM PST 23
Finished Dec 24 01:06:58 PM PST 23
Peak memory 218168 kb
Host smart-5292b1a7-d8db-47c0-abc7-ddc1f0c4cb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342441866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.3342441866
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.725808540
Short name T677
Test name
Test status
Simulation time 39473220 ps
CPU time 3.09 seconds
Started Dec 24 01:06:50 PM PST 23
Finished Dec 24 01:06:57 PM PST 23
Peak memory 214576 kb
Host smart-1db7bc91-d33a-48af-a23b-b776ad4f4745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725808540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.725808540
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.2774951952
Short name T459
Test name
Test status
Simulation time 352435184 ps
CPU time 25.9 seconds
Started Dec 24 01:06:35 PM PST 23
Finished Dec 24 01:07:03 PM PST 23
Peak memory 251088 kb
Host smart-2c1148a1-f81f-4e91-8359-a7b2254238f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774951952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.2774951952
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.1639848348
Short name T763
Test name
Test status
Simulation time 88637529 ps
CPU time 7.37 seconds
Started Dec 24 01:06:50 PM PST 23
Finished Dec 24 01:07:02 PM PST 23
Peak memory 251192 kb
Host smart-ccfbcc78-dad5-4326-aca7-5447de12fda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639848348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1639848348
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.3279310780
Short name T855
Test name
Test status
Simulation time 15467886536 ps
CPU time 138.33 seconds
Started Dec 24 01:07:09 PM PST 23
Finished Dec 24 01:09:35 PM PST 23
Peak memory 274620 kb
Host smart-28a067fc-5a3b-4667-89e1-7f6407c6f621
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279310780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.3279310780
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3898255805
Short name T825
Test name
Test status
Simulation time 13607973 ps
CPU time 0.74 seconds
Started Dec 24 01:06:51 PM PST 23
Finished Dec 24 01:06:57 PM PST 23
Peak memory 207620 kb
Host smart-d85ed420-b2eb-4571-8af3-13811f15127f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898255805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.3898255805
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.2370215504
Short name T685
Test name
Test status
Simulation time 56669717 ps
CPU time 0.86 seconds
Started Dec 24 01:07:02 PM PST 23
Finished Dec 24 01:07:06 PM PST 23
Peak memory 209404 kb
Host smart-4c985a67-c911-46c9-be4e-4a65514242ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370215504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.2370215504
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.402873592
Short name T358
Test name
Test status
Simulation time 17279264 ps
CPU time 0.93 seconds
Started Dec 24 01:07:37 PM PST 23
Finished Dec 24 01:07:41 PM PST 23
Peak memory 209548 kb
Host smart-d9a7b29f-9901-48b1-984d-60ca4a017e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402873592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.402873592
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.3313928664
Short name T805
Test name
Test status
Simulation time 433573270 ps
CPU time 9.3 seconds
Started Dec 24 01:07:09 PM PST 23
Finished Dec 24 01:07:25 PM PST 23
Peak memory 218224 kb
Host smart-bf56e0f7-c992-4682-aa20-4e4f81ce798f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313928664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.3313928664
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.1510731928
Short name T427
Test name
Test status
Simulation time 338325110 ps
CPU time 9.44 seconds
Started Dec 24 01:06:45 PM PST 23
Finished Dec 24 01:06:56 PM PST 23
Peak memory 209760 kb
Host smart-b16cf2e6-4ff1-4abb-89c7-cde1802cf655
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510731928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_ac
cess.1510731928
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.2689865714
Short name T586
Test name
Test status
Simulation time 9186421804 ps
CPU time 30.13 seconds
Started Dec 24 01:06:47 PM PST 23
Finished Dec 24 01:07:21 PM PST 23
Peak memory 218764 kb
Host smart-afc5d24e-af04-4d66-8f23-9d3e79df4db3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689865714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.2689865714
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.4053619609
Short name T379
Test name
Test status
Simulation time 1249192047 ps
CPU time 8.44 seconds
Started Dec 24 01:06:56 PM PST 23
Finished Dec 24 01:07:09 PM PST 23
Peak memory 217908 kb
Host smart-e1391c13-e849-4253-ab17-9993a449be02
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053619609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
priority.4053619609
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.2119678039
Short name T317
Test name
Test status
Simulation time 714070143 ps
CPU time 8.3 seconds
Started Dec 24 01:06:31 PM PST 23
Finished Dec 24 01:06:41 PM PST 23
Peak memory 218096 kb
Host smart-2f73bfb2-7037-4222-8d7d-99cc63d88378
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119678039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.2119678039
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3824857909
Short name T530
Test name
Test status
Simulation time 1227178382 ps
CPU time 17.85 seconds
Started Dec 24 01:06:44 PM PST 23
Finished Dec 24 01:07:04 PM PST 23
Peak memory 213124 kb
Host smart-9add7daa-5347-4818-9aa1-e3214c16d2c4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824857909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.3824857909
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.4210536411
Short name T398
Test name
Test status
Simulation time 1330766292 ps
CPU time 5.4 seconds
Started Dec 24 01:06:59 PM PST 23
Finished Dec 24 01:07:09 PM PST 23
Peak memory 213580 kb
Host smart-dcfd2670-3e07-4b09-afe0-5018c3c54bd9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210536411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
4210536411
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.818806667
Short name T340
Test name
Test status
Simulation time 2835708651 ps
CPU time 64.39 seconds
Started Dec 24 01:06:47 PM PST 23
Finished Dec 24 01:07:53 PM PST 23
Peak memory 283816 kb
Host smart-83a0e1dc-9864-470d-bdd8-5d05ca564e7c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818806667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_state_failure.818806667
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.3113345481
Short name T742
Test name
Test status
Simulation time 5089691683 ps
CPU time 33.83 seconds
Started Dec 24 01:06:32 PM PST 23
Finished Dec 24 01:07:08 PM PST 23
Peak memory 251144 kb
Host smart-b04fb581-9401-49d1-9705-ea87538ff973
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113345481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.3113345481
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.3754785306
Short name T629
Test name
Test status
Simulation time 234380735 ps
CPU time 1.97 seconds
Started Dec 24 01:07:22 PM PST 23
Finished Dec 24 01:07:27 PM PST 23
Peak memory 218212 kb
Host smart-7e9b4794-d237-4242-bb7f-3ee50c42d1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754785306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.3754785306
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.3509570232
Short name T864
Test name
Test status
Simulation time 245975739 ps
CPU time 13.36 seconds
Started Dec 24 01:07:23 PM PST 23
Finished Dec 24 01:07:40 PM PST 23
Peak memory 214168 kb
Host smart-f1771248-b343-4051-9f34-2062df961807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509570232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.3509570232
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.198771529
Short name T423
Test name
Test status
Simulation time 575159261 ps
CPU time 10.94 seconds
Started Dec 24 01:06:33 PM PST 23
Finished Dec 24 01:06:45 PM PST 23
Peak memory 218304 kb
Host smart-c99bc86f-f16b-4669-8006-92944efcbacd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198771529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.198771529
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.527208785
Short name T737
Test name
Test status
Simulation time 666260559 ps
CPU time 11.61 seconds
Started Dec 24 01:06:34 PM PST 23
Finished Dec 24 01:06:47 PM PST 23
Peak memory 218060 kb
Host smart-980e002d-eb30-4fbd-8d3c-89c7bda369e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527208785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_dig
est.527208785
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.2272702995
Short name T664
Test name
Test status
Simulation time 2229208293 ps
CPU time 10.88 seconds
Started Dec 24 01:06:33 PM PST 23
Finished Dec 24 01:06:45 PM PST 23
Peak memory 218216 kb
Host smart-76830771-a4d6-49c1-882d-887829b0f535
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272702995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.2
272702995
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.3738185551
Short name T867
Test name
Test status
Simulation time 323453820 ps
CPU time 9.25 seconds
Started Dec 24 01:07:28 PM PST 23
Finished Dec 24 01:07:39 PM PST 23
Peak memory 218144 kb
Host smart-9ac6b071-b64d-4157-b3e5-5764e06e089e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738185551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.3738185551
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.3197060366
Short name T362
Test name
Test status
Simulation time 49998404 ps
CPU time 1.26 seconds
Started Dec 24 01:06:59 PM PST 23
Finished Dec 24 01:07:05 PM PST 23
Peak memory 213116 kb
Host smart-546628c9-df79-4a54-bedb-8540818210ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197060366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.3197060366
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.2984029085
Short name T33
Test name
Test status
Simulation time 1163294385 ps
CPU time 27.86 seconds
Started Dec 24 01:07:11 PM PST 23
Finished Dec 24 01:07:46 PM PST 23
Peak memory 251120 kb
Host smart-7227ec98-6f91-48e9-aa60-1e96acb4ea25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984029085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.2984029085
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.2921406997
Short name T833
Test name
Test status
Simulation time 60165538 ps
CPU time 9.22 seconds
Started Dec 24 01:07:09 PM PST 23
Finished Dec 24 01:07:25 PM PST 23
Peak memory 251100 kb
Host smart-b23d3bf4-a5f1-47eb-8ce0-2fa1f9e50699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921406997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.2921406997
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.3080641570
Short name T544
Test name
Test status
Simulation time 14597041568 ps
CPU time 141.19 seconds
Started Dec 24 01:07:05 PM PST 23
Finished Dec 24 01:09:29 PM PST 23
Peak memory 252464 kb
Host smart-62b9b1f0-8b8f-474f-8a17-2b6ba226b86f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080641570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.3080641570
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3828613606
Short name T834
Test name
Test status
Simulation time 45813186 ps
CPU time 0.91 seconds
Started Dec 24 01:07:24 PM PST 23
Finished Dec 24 01:07:29 PM PST 23
Peak memory 211436 kb
Host smart-3dee1970-b503-4bb1-bfd0-65e7ced9d96b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828613606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.3828613606
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.3409391884
Short name T320
Test name
Test status
Simulation time 35239018 ps
CPU time 1.13 seconds
Started Dec 24 01:07:17 PM PST 23
Finished Dec 24 01:07:23 PM PST 23
Peak memory 208472 kb
Host smart-4d1bbe7d-cb14-4634-a0b1-71e29a866f98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409391884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3409391884
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.930816633
Short name T658
Test name
Test status
Simulation time 437853394 ps
CPU time 12.46 seconds
Started Dec 24 01:06:48 PM PST 23
Finished Dec 24 01:07:04 PM PST 23
Peak memory 218164 kb
Host smart-871bdebd-39e9-4275-980a-6390697c2a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930816633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.930816633
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.3674860054
Short name T615
Test name
Test status
Simulation time 1173240470 ps
CPU time 6.18 seconds
Started Dec 24 01:06:45 PM PST 23
Finished Dec 24 01:06:53 PM PST 23
Peak memory 209676 kb
Host smart-5ba2f107-cbe3-48f6-a98d-4c337cd716d7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674860054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_ac
cess.3674860054
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.494621613
Short name T885
Test name
Test status
Simulation time 7121308188 ps
CPU time 52.66 seconds
Started Dec 24 01:06:48 PM PST 23
Finished Dec 24 01:07:44 PM PST 23
Peak memory 219260 kb
Host smart-ca3d1c47-c20b-49aa-8447-53c80efbaead
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494621613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_err
ors.494621613
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.2383189215
Short name T748
Test name
Test status
Simulation time 230430888 ps
CPU time 3.5 seconds
Started Dec 24 01:07:05 PM PST 23
Finished Dec 24 01:07:12 PM PST 23
Peak memory 209656 kb
Host smart-a6e413c1-590f-4bcf-9f93-3d0fd63400e3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383189215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_
priority.2383189215
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.3165591064
Short name T521
Test name
Test status
Simulation time 119731707 ps
CPU time 4.4 seconds
Started Dec 24 01:07:04 PM PST 23
Finished Dec 24 01:07:11 PM PST 23
Peak memory 218056 kb
Host smart-bca8084f-a22d-41a3-9000-c377f8f11234
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165591064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.3165591064
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2405015782
Short name T321
Test name
Test status
Simulation time 1443428928 ps
CPU time 19.63 seconds
Started Dec 24 01:07:01 PM PST 23
Finished Dec 24 01:07:24 PM PST 23
Peak memory 212940 kb
Host smart-048beab6-2251-4150-b8dd-6805a9892884
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405015782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.2405015782
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.926036509
Short name T600
Test name
Test status
Simulation time 1993889686 ps
CPU time 12.85 seconds
Started Dec 24 01:06:44 PM PST 23
Finished Dec 24 01:06:59 PM PST 23
Peak memory 213468 kb
Host smart-8a410b15-e318-408d-b5c3-d69b4873f499
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926036509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.926036509
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1141364748
Short name T891
Test name
Test status
Simulation time 7856663287 ps
CPU time 114.84 seconds
Started Dec 24 01:07:05 PM PST 23
Finished Dec 24 01:09:03 PM PST 23
Peak memory 278144 kb
Host smart-c6cb78b8-3b6b-431b-81be-43936e7189dc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141364748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.1141364748
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.121126050
Short name T888
Test name
Test status
Simulation time 479816296 ps
CPU time 14.13 seconds
Started Dec 24 01:06:41 PM PST 23
Finished Dec 24 01:06:56 PM PST 23
Peak memory 222904 kb
Host smart-1c7a8563-c6e7-45cf-a295-6ea364a16819
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121126050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_state_post_trans.121126050
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.2978303297
Short name T453
Test name
Test status
Simulation time 370734442 ps
CPU time 3.55 seconds
Started Dec 24 01:06:51 PM PST 23
Finished Dec 24 01:06:59 PM PST 23
Peak memory 218204 kb
Host smart-ac8879fd-4c0b-4f08-b74c-ed4fbf6eb03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978303297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.2978303297
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.2281115840
Short name T104
Test name
Test status
Simulation time 1332654538 ps
CPU time 7.35 seconds
Started Dec 24 01:07:04 PM PST 23
Finished Dec 24 01:07:14 PM PST 23
Peak memory 213552 kb
Host smart-25032bff-ab62-4501-913a-c07b12e9c3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281115840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.2281115840
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.1724062834
Short name T596
Test name
Test status
Simulation time 351745661 ps
CPU time 15.61 seconds
Started Dec 24 01:07:06 PM PST 23
Finished Dec 24 01:07:26 PM PST 23
Peak memory 219228 kb
Host smart-fb609e9c-fa57-41cd-820b-d2f74fd48190
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724062834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1724062834
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.204032431
Short name T433
Test name
Test status
Simulation time 229857242 ps
CPU time 10.64 seconds
Started Dec 24 01:07:09 PM PST 23
Finished Dec 24 01:07:26 PM PST 23
Peak memory 218080 kb
Host smart-0f7d3333-a49b-46eb-b255-43e079786760
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204032431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_dig
est.204032431
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.3579877582
Short name T871
Test name
Test status
Simulation time 378959323 ps
CPU time 13.93 seconds
Started Dec 24 01:07:05 PM PST 23
Finished Dec 24 01:07:23 PM PST 23
Peak memory 218128 kb
Host smart-cabeb2de-7a88-41c9-af26-d71f8b14f0a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579877582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.3
579877582
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.711267766
Short name T826
Test name
Test status
Simulation time 571686849 ps
CPU time 12.23 seconds
Started Dec 24 01:06:41 PM PST 23
Finished Dec 24 01:06:54 PM PST 23
Peak memory 218232 kb
Host smart-4df7beaa-0490-4b87-9e59-c3f0dd3833f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711267766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.711267766
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.3387019312
Short name T802
Test name
Test status
Simulation time 38682548 ps
CPU time 1.23 seconds
Started Dec 24 01:06:41 PM PST 23
Finished Dec 24 01:06:43 PM PST 23
Peak memory 213172 kb
Host smart-ca9f4498-3c16-44ff-9713-602b5f83fe12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387019312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.3387019312
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.453774934
Short name T504
Test name
Test status
Simulation time 2130196277 ps
CPU time 22.35 seconds
Started Dec 24 01:06:44 PM PST 23
Finished Dec 24 01:07:09 PM PST 23
Peak memory 251144 kb
Host smart-8a526929-9a0e-4928-8748-2b2af9b9f08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453774934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.453774934
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.935993333
Short name T821
Test name
Test status
Simulation time 227925572 ps
CPU time 3.72 seconds
Started Dec 24 01:06:34 PM PST 23
Finished Dec 24 01:06:39 PM PST 23
Peak memory 222304 kb
Host smart-58f8bec4-5845-4bb1-b627-a24ee8c22df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935993333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.935993333
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.3806072779
Short name T857
Test name
Test status
Simulation time 2590826914 ps
CPU time 58.41 seconds
Started Dec 24 01:07:17 PM PST 23
Finished Dec 24 01:08:20 PM PST 23
Peak memory 283824 kb
Host smart-643aa599-9cf8-469c-90b9-eb00fba9fc75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806072779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.3806072779
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3627141412
Short name T630
Test name
Test status
Simulation time 20676502 ps
CPU time 0.73 seconds
Started Dec 24 01:06:41 PM PST 23
Finished Dec 24 01:06:43 PM PST 23
Peak memory 206636 kb
Host smart-51531ced-417e-4565-80b5-9dc32a3a1888
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627141412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.3627141412
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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