LC_CTRL Simulation Results

Sunday December 24 2023 20:02:26 UTC

GitHub Revision: 671f2b57e2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 96716765175854174075659971574604807242747408006700796360560480210023744343645

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.430s	779.047us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.230s	75.426us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.180s	32.074us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.900s	185.240us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.360s	46.310us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.060s	87.828us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.180s	32.074us	20	20	100.00
		lc_ctrl_csr_aliasing	1.360s	46.310us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.240s	163.318us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	24.690s	360.837us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.970s	11.807us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.870s	208.843us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	38.380s	365.402us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	23.230s	907.349us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	38.380s	365.402us	50	50	100.00
		lc_ctrl_prog_failure	4.870s	208.843us	50	50	100.00
		lc_ctrl_errors	23.230s	907.349us	50	50	100.00
		lc_ctrl_security_escalation	18.110s	950.506us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.996m	3.506ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.590s	2.271ms	20	20	100.00
		lc_ctrl_jtag_errors	2.385m	5.468ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	12.850s	1.994ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	33.830s	5.090ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.590s	2.271ms	20	20	100.00
		lc_ctrl_jtag_errors	2.385m	5.468ms	20	20	100.00
		lc_ctrl_jtag_access	27.870s	1.245ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	32.410s	4.446ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.410s	206.309us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.740s	271.747us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	20.500s	3.477ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	13.750s	7.956ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.010s	46.791us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	2.590s	299.315us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.860s	92.648us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	1.429m	3.632ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.170s	20.074us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	15.398m	117.388ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.660s	44.710us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.220s	527.016us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.220s	527.016us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.230s	75.426us	5	5	100.00
		lc_ctrl_csr_rw	1.180s	32.074us	20	20	100.00
		lc_ctrl_csr_aliasing	1.360s	46.310us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.920s	79.470us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.230s	75.426us	5	5	100.00
		lc_ctrl_csr_rw	1.180s	32.074us	20	20	100.00
		lc_ctrl_csr_aliasing	1.360s	46.310us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.920s	79.470us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	34.830s	209.887us	5	5	100.00
		lc_ctrl_tl_intg_err	4.300s	111.129us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.300s	111.129us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	24.690s	360.837us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	38.380s	365.402us	50	50	100.00
		lc_ctrl_sec_cm	34.830s	209.887us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	38.380s	365.402us	50	50	100.00
		lc_ctrl_sec_cm	34.830s	209.887us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	38.380s	365.402us	50	50	100.00
		lc_ctrl_sec_cm	34.830s	209.887us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	38.380s	365.402us	50	50	100.00
		lc_ctrl_sec_cm	34.830s	209.887us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	38.380s	365.402us	50	50	100.00
		lc_ctrl_sec_cm	34.830s	209.887us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	38.380s	365.402us	50	50	100.00
		lc_ctrl_sec_cm	34.830s	209.887us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	38.380s	365.402us	50	50	100.00
		lc_ctrl_sec_cm	34.830s	209.887us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	38.380s	365.402us	50	50	100.00
		lc_ctrl_sec_cm	34.830s	209.887us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	18.110s	950.506us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.240s	163.318us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	33.830s	5.090ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	21.030s	451.935us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	21.030s	451.935us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	23.270s	864.393us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.820s	584.215us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.820s	584.215us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	14.037m	193.745ms	7	50	14.00
V3		TOTAL			7	50	14.00
		TOTAL			987	1030	95.83

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	97.29	95.79	91.98	97.67	95.93	98.48	95.36

Failure Buckets

• Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 28 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 28 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.1346937534953795940313445893519130870248379932266617469462688700163718984006
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:80ddb0fa-ea17-405c-854b-403542d6b15c
      

    • 1.lc_ctrl_stress_all_with_rand_reset.70819197207867827229067816860739720748816038427095143468383575033073531469955
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:16caddc0-9cc1-4ed2-85cc-41dcfefdc8d6
      

    • ... and 26 more failures.

• Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 10 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 10 failures.

    • 9.lc_ctrl_stress_all_with_rand_reset.51015475351800369847884833324662630810617637818941654782879571498952936594258
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:80136de6-f7e2-4208-b8fd-44ae8ded9a07
      

    • 10.lc_ctrl_stress_all_with_rand_reset.13073125303444458071650245554140848865597202007692378074239517731688221128551
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:78dfc526-5e07-485a-978a-06eed6ed73a5
      

    • ... and 8 more failures.

• UVM_ERROR (jtag_riscv_monitor.sv:80) monitor [monitor] Bad status - DmiReserved(*) has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.107392498905972882806274978022245345575927880654554509209364647665062385983944
      Line 8064, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 29924866090 ps: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
        UVM_INFO @ 29924866090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 33.lc_ctrl_stress_all_with_rand_reset.37068831556056909678658135778144237618590484974437930066880578982065461863404
      Line 9077, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/33.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2316902255 ps: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
        UVM_INFO @ 2316902255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (lc_ctrl_scoreboard.sv:265) scoreboard [scoreboard] Access unexpected addr * has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 7.lc_ctrl_stress_all_with_rand_reset.49538301894508355772780857661262489879265796749532079786447056407165723892600
      Line 27091, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 165597618817 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0xeeab3730
        UVM_INFO @ 165597618817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:743) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 8.lc_ctrl_stress_all_with_rand_reset.54578952534816099015970734749587400877694789028987098573944394534928780432905
      Line 13119, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10186019624 ps: (lc_ctrl_errors_vseq.sv:743) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 10186019624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:519) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 34.lc_ctrl_stress_all_with_rand_reset.639149540432075799999714044785853448343072346085337925895481153924146467813
      Line 13330, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 18995879163 ps: (cip_base_vseq.sv:519) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 18995879163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2023.12.21_00.15.46
• 2023.11.23_02.09.59
• 2023.11.02_03.38.10
• 2023.10.30_18.19.21
• 2023.10.26_03.01.18
• 2023.10.23_18.19.18