Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

69459285

1

T53

1853

T89

2641

T90

6007

auto[1]

1199710

1

T7

198

T8

396

T10

297

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

69460403

1

T53

1853

T89

2641

T90

6007

auto[1]

1198592

1

T8

396

T10

396

T12

4317

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5518433	1			T53	120		T89	186		T90	65
auto[IdleSt]	16379611	1			T53	1733		T89	2455		T90	5942
auto[ClkMuxSt]	29418	1			T1	9		T2	12		T3	6
auto[CntIncrSt]	29272	1			T1	9		T2	12		T3	6
auto[CntProgSt]	1478406	1			T1	3110		T2	24		T3	83
auto[TransCheckSt]	23080	1			T1	9		T2	12		T3	6
auto[TokenHashSt]	24365596	1			T1	102580		T2	263		T3	274
auto[FlashRmaSt]	22838	1			T1	28		T2	12		T3	23
auto[TokenCheck0St]	9920	1			T1	9		T2	12		T3	6
auto[TokenCheck1St]	7036	1			T1	9		T2	12		T3	6
auto[TransProgSt]	319749	1			T1	3100		T2	24		T3	118
auto[PostTransSt]	9540989	1			T1	3073		T2	6753		T3	1110
auto[ScrapSt]	119170	1			T91	3356		T116	1240		T117	2905
auto[EscalateSt]	5111486	1			T7	272		T8	2269		T10	1087
auto[InvalidSt]	7702636	1			T8	1244		T10	522		T12	142286

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1355	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	7702636	1			T8	1244		T10	522		T12	142286
EscalateSt	5111486	1			T7	272		T8	2269		T10	1087
ScrapSt	119170	1			T91	3356		T116	1240		T117	2905
PostTransSt	9540989	1			T1	3073		T2	6753		T3	1110
TransProgSt	319749	1			T1	3100		T2	24		T3	118
TokenCheck1St	7036	1			T1	9		T2	12		T3	6
TokenCheck0St	9920	1			T1	9		T2	12		T3	6
FlashRmaSt	22838	1			T1	28		T2	12		T3	23
TokenHashSt	24365596	1			T1	102580		T2	263		T3	274
TransCheckSt	23080	1			T1	9		T2	12		T3	6
CntProgSt	1478406	1			T1	3110		T2	24		T3	83
CntIncrSt	29272	1			T1	9		T2	12		T3	6
ClkMuxSt	29418	1			T1	9		T2	12		T3	6
IdleSt	16379611	1			T53	1733		T89	2455		T90	5942
ResetSt	5518433	1			T53	120		T89	186		T90	65
arcs[ResetSt=>IdleSt]	42792	1			T53	1		T89	3		T90	1
arcs[IdleSt=>ScrapSt]	212	1			T91	2		T116	2		T117	1
arcs[IdleSt=>ClkMuxSt]	29323	1			T1	9		T2	12		T3	6
arcs[ClkMuxSt=>CntIncrSt]	29272	1			T1	9		T2	12		T3	6
arcs[CntIncrSt=>PostTransSt]	1463	1			T33	15		T34	5		T35	7
arcs[CntIncrSt=>CntProgSt]	27735	1			T1	9		T2	12		T3	6
arcs[CntProgSt=>PostTransSt]	3610	1			T7	2		T12	12		T42	22
arcs[CntProgSt=>TransCheckSt]	23080	1			T1	9		T2	12		T3	6
arcs[TransCheckSt=>PostTransSt]	3249	1			T11	25		T13	25		T24	35
arcs[TransCheckSt=>TokenHashSt]	19694	1			T1	9		T2	12		T3	6
arcs[TokenHashSt=>PostTransSt]	8974	1			T9	53		T11	7		T13	12
arcs[TokenHashSt=>FlashRmaSt]	10028	1			T1	9		T2	12		T3	6
arcs[FlashRmaSt=>TokenCheck0St]	9920	1			T1	9		T2	12		T3	6
arcs[TokenCheck0St=>PostTransSt]	2855	1			T11	14		T13	17		T24	10
arcs[TokenCheck0St=>TokenCheck1St]	7036	1			T1	9		T2	12		T3	6
arcs[TokenCheck1St=>PostTransSt]	647	1			T11	10		T13	10		T24	9
arcs[TransProgSt=>PostTransSt]	5491	1			T1	9		T2	12		T3	6
arcs[IdleSt=>EscalateSt]	209	1			T83	3		T85	3		T183	5
arcs[ClkMuxSt=>EscalateSt]	51	1			T81	3		T82	1		T83	2
arcs[CntIncrSt=>EscalateSt]	74	1			T82	1		T83	2		T85	4
arcs[CntProgSt=>EscalateSt]	1045	1			T81	4		T82	27		T83	9
arcs[TransCheckSt=>EscalateSt]	137	1			T81	9		T82	2		T83	9
arcs[TokenHashSt=>EscalateSt]	682	1			T81	28		T82	16		T83	21
arcs[FlashRmaSt=>EscalateSt]	108	1			T81	3		T82	2		T83	3
arcs[TokenCheck0St=>EscalateSt]	29	1			T82	1		T85	1		T184	1
arcs[TokenCheck1St=>EscalateSt]	133	1			T81	2		T82	2		T83	1
arcs[TransProgSt=>EscalateSt]	765	1			T81	11		T82	15		T83	14
arcs[PostTransSt=>EscalateSt]	3863	1			T7	2		T12	12		T42	22
arcs[InvalidSt=>EscalateSt]	11074	1			T8	8		T10	7		T12	75

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5518243	1			T53	120		T89	186		T90	65
auto[0]	auto[IdleSt]	16379465	1			T53	1733		T89	2455		T90	5942
auto[0]	auto[ClkMuxSt]	29387	1			T1	9		T2	12		T3	6
auto[0]	auto[CntIncrSt]	29227	1			T1	9		T2	12		T3	6
auto[0]	auto[CntProgSt]	1477728	1			T1	3110		T2	24		T3	83
auto[0]	auto[TransCheckSt]	22983	1			T1	9		T2	12		T3	6
auto[0]	auto[TokenHashSt]	24365144	1			T1	102580		T2	263		T3	274
auto[0]	auto[FlashRmaSt]	22774	1			T1	28		T2	12		T3	23
auto[0]	auto[TokenCheck0St]	9904	1			T1	9		T2	12		T3	6
auto[0]	auto[TokenCheck1St]	6945	1			T1	9		T2	12		T3	6
auto[0]	auto[TransProgSt]	319247	1			T1	3100		T2	24		T3	118
auto[0]	auto[PostTransSt]	9539056	1			T1	3073		T2	6753		T3	1110
auto[0]	auto[ScrapSt]	119131	1			T91	3356		T116	1240		T117	2905
auto[0]	auto[EscalateSt]	3921620	1			T7	76		T8	1877		T10	793
auto[0]	auto[InvalidSt]	7697076	1			T8	1240		T10	519		T12	142250
auto[1]	auto[ResetSt]	190	1			T81	6		T82	4		T83	4
auto[1]	auto[IdleSt]	146	1			T83	3		T85	1		T183	4
auto[1]	auto[ClkMuxSt]	31	1			T81	2		T85	2		T184	1
auto[1]	auto[CntIncrSt]	45	1			T82	1		T85	3		T183	1
auto[1]	auto[CntProgSt]	678	1			T81	2		T82	20		T83	7
auto[1]	auto[TransCheckSt]	97	1			T81	5		T82	1		T83	7
auto[1]	auto[TokenHashSt]	452	1			T81	16		T82	11		T83	12
auto[1]	auto[FlashRmaSt]	64	1			T82	2		T83	3		T85	4
auto[1]	auto[TokenCheck0St]	16	1			T85	1		T184	1		T185	1
auto[1]	auto[TokenCheck1St]	91	1			T81	1		T82	1		T83	1
auto[1]	auto[TransProgSt]	502	1			T81	6		T82	13		T83	9
auto[1]	auto[PostTransSt]	1933	1			T7	2		T12	7		T42	13
auto[1]	auto[ScrapSt]	39	1			T81	1		T82	1		T85	3
auto[1]	auto[EscalateSt]	1189866	1			T7	196		T8	392		T10	294
auto[1]	auto[InvalidSt]	5560	1			T8	4		T10	3		T12	36

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5518266	1			T53	120		T89	186		T90	65
auto[0]	auto[IdleSt]	16379478	1			T53	1733		T89	2455		T90	5942
auto[0]	auto[ClkMuxSt]	29382	1			T1	9		T2	12		T3	6
auto[0]	auto[CntIncrSt]	29225	1			T1	9		T2	12		T3	6
auto[0]	auto[CntProgSt]	1477707	1			T1	3110		T2	24		T3	83
auto[0]	auto[TransCheckSt]	22993	1			T1	9		T2	12		T3	6
auto[0]	auto[TokenHashSt]	24365141	1			T1	102580		T2	263		T3	274
auto[0]	auto[FlashRmaSt]	22771	1			T1	28		T2	12		T3	23
auto[0]	auto[TokenCheck0St]	9895	1			T1	9		T2	12		T3	6
auto[0]	auto[TokenCheck1St]	6940	1			T1	9		T2	12		T3	6
auto[0]	auto[TransProgSt]	319239	1			T1	3100		T2	24		T3	118
auto[0]	auto[PostTransSt]	9538984	1			T1	3073		T2	6753		T3	1110
auto[0]	auto[ScrapSt]	119130	1			T91	3356		T116	1240		T117	2905
auto[0]	auto[EscalateSt]	3922775	1			T7	272		T8	1877		T10	695
auto[0]	auto[InvalidSt]	7697122	1			T8	1240		T10	518		T12	142247
auto[1]	auto[ResetSt]	167	1			T81	6		T82	2		T83	2
auto[1]	auto[IdleSt]	133	1			T83	2		T85	2		T183	4
auto[1]	auto[ClkMuxSt]	36	1			T81	2		T82	1		T83	2
auto[1]	auto[CntIncrSt]	47	1			T83	2		T85	2		T183	1
auto[1]	auto[CntProgSt]	699	1			T81	3		T82	15		T83	3
auto[1]	auto[TransCheckSt]	87	1			T81	6		T82	2		T83	5
auto[1]	auto[TokenHashSt]	455	1			T81	18		T82	10		T83	16
auto[1]	auto[FlashRmaSt]	67	1			T81	3		T85	2		T184	2
auto[1]	auto[TokenCheck0St]	25	1			T82	1		T85	1		T184	1
auto[1]	auto[TokenCheck1St]	96	1			T81	2		T82	2		T83	1
auto[1]	auto[TransProgSt]	510	1			T81	7		T82	6		T83	8
auto[1]	auto[PostTransSt]	2005	1			T12	5		T42	9		T33	6
auto[1]	auto[ScrapSt]	40	1			T81	2		T82	1		T83	1
auto[1]	auto[EscalateSt]	1188711	1			T8	392		T10	392		T12	4273
auto[1]	auto[InvalidSt]	5514	1			T8	4		T10	4		T12	39