Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	969086	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1160900

1

T89

608

T91

89

T92

209

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1834737	1			T89	160		T91	22		T92	29
values[0x0]	147001	1			T89	229		T91	33		T92	90
values[0x1]	148248	1			T89	262		T91	34		T92	90

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	767927	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1362059

1

T89

619

T91

89

T92

209

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7027	1			T89	2		T126	1		T158	5
valid_sources[0x01]	24970	1			T89	1		T92	3		T95	4
valid_sources[0x02]	6048	1			T95	1		T111	1		T126	3
valid_sources[0x03]	5713	1			T89	7		T126	2		T118	3
valid_sources[0x04]	10067	1			T89	6		T92	9		T96	4
valid_sources[0x05]	6961	1			T95	1		T126	4		T118	1
valid_sources[0x06]	5934	1			T89	2		T95	2		T96	10
valid_sources[0x07]	5866	1			T93	2		T118	1		T158	3
valid_sources[0x08]	5621	1			T92	1		T96	1		T126	7
valid_sources[0x09]	5901	1			T89	6		T95	2		T96	8
valid_sources[0x0a]	5736	1			T95	7		T96	3		T158	4
valid_sources[0x0b]	6258	1			T89	6		T92	3		T126	1
valid_sources[0x0c]	5767	1			T89	9		T92	6		T95	1
valid_sources[0x0d]	5948	1			T89	3		T93	2		T158	4
valid_sources[0x0e]	5639	1			T89	2		T92	6		T95	1
valid_sources[0x0f]	6392	1			T89	1		T93	11		T96	7
valid_sources[0x10]	6383	1			T89	1		T92	6		T96	16
valid_sources[0x11]	5742	1			T126	3		T118	1		T158	4
valid_sources[0x12]	5876	1			T95	1		T118	5		T158	3
valid_sources[0x13]	5630	1			T89	2		T118	3		T158	3
valid_sources[0x14]	5779	1			T89	3		T95	2		T118	1
valid_sources[0x15]	5825	1			T95	2		T118	3		T158	1
valid_sources[0x16]	7787	1			T89	4		T126	2		T118	3
valid_sources[0x17]	8364	1			T89	4		T95	1		T158	4
valid_sources[0x18]	5733	1			T89	1		T95	3		T111	2
valid_sources[0x19]	7194	1			T89	1		T92	11		T95	2
valid_sources[0x1a]	5979	1			T89	1		T95	5		T104	34
valid_sources[0x1b]	6038	1			T89	5		T93	4		T95	1
valid_sources[0x1c]	5864	1			T96	1		T158	5		T131	1
valid_sources[0x1d]	5926	1			T126	2		T118	2		T158	5
valid_sources[0x1e]	5947	1			T89	2		T95	1		T111	1
valid_sources[0x1f]	6707	1			T89	6		T95	1		T126	1
valid_sources[0x20]	5618	1			T93	1		T126	3		T118	1
valid_sources[0x21]	5750	1			T89	6		T93	16		T97	7
valid_sources[0x22]	5567	1			T89	3		T92	2		T93	2
valid_sources[0x23]	6126	1			T89	3		T93	1		T95	2
valid_sources[0x24]	5507	1			T93	1		T95	1		T126	2
valid_sources[0x25]	5637	1			T89	2		T93	9		T95	2
valid_sources[0x26]	5938	1			T89	14		T93	3		T95	1
valid_sources[0x27]	6313	1			T89	11		T93	11		T95	3
valid_sources[0x28]	7510	1			T97	8		T118	1		T156	2
valid_sources[0x29]	7527	1			T89	10		T92	5		T111	1
valid_sources[0x2a]	7407	1			T89	3		T92	13		T104	9
valid_sources[0x2b]	5525	1			T89	1		T92	1		T93	7
valid_sources[0x2c]	7335	1			T93	3		T95	4		T111	1
valid_sources[0x2d]	5851	1			T89	1		T95	3		T96	3
valid_sources[0x2e]	5930	1			T89	1		T92	6		T93	1
valid_sources[0x2f]	6247	1			T89	5		T96	5		T118	2
valid_sources[0x30]	8411	1			T89	4		T92	1		T126	4
valid_sources[0x31]	5678	1			T89	1		T118	3		T158	1
valid_sources[0x32]	11485	1			T89	2		T93	7		T95	1
valid_sources[0x33]	5792	1			T89	1		T92	8		T111	3
valid_sources[0x34]	7447	1			T89	7		T158	3		T106	4
valid_sources[0x35]	6077	1			T104	12		T115	7		T156	4
valid_sources[0x36]	5632	1			T89	1		T126	1		T158	1
valid_sources[0x37]	5604	1			T89	4		T118	1		T158	2
valid_sources[0x38]	5989	1			T89	11		T118	2		T158	4
valid_sources[0x39]	7118	1			T89	1		T95	1		T111	1
valid_sources[0x3a]	6535	1			T95	2		T158	2		T135	1
valid_sources[0x3b]	12482	1			T89	5		T111	1		T126	1
valid_sources[0x3c]	6690	1			T92	1		T93	2		T158	4
valid_sources[0x3d]	5777	1			T89	3		T118	1		T158	1
valid_sources[0x3e]	9797	1			T89	6		T118	4		T158	5
valid_sources[0x3f]	5796	1			T95	2		T96	6		T158	4
valid_sources[0x40]	6979	1			T89	5		T93	4		T95	1
valid_sources[0x41]	5871	1			T89	1		T115	17		T118	5
valid_sources[0x42]	6789	1			T118	1		T158	3		T106	2
valid_sources[0x43]	5791	1			T118	2		T158	3		T131	4
valid_sources[0x44]	5726	1			T89	4		T95	3		T126	1
valid_sources[0x45]	107897	1			T89	1		T95	4		T159	10
valid_sources[0x46]	5927	1			T95	1		T126	3		T158	7
valid_sources[0x47]	7672	1			T89	2		T97	3		T126	1
valid_sources[0x48]	5671	1			T89	2		T118	8		T158	2
valid_sources[0x49]	5856	1			T93	2		T95	3		T96	3
valid_sources[0x4a]	22994	1			T93	19		T95	2		T96	11
valid_sources[0x4b]	6150	1			T89	1		T93	1		T96	2
valid_sources[0x4c]	10974	1			T96	4		T104	1		T158	4
valid_sources[0x4d]	88210	1			T96	2		T126	4		T118	3
valid_sources[0x4e]	5966	1			T89	2		T95	4		T96	8
valid_sources[0x4f]	5829	1			T89	4		T93	11		T95	2
valid_sources[0x50]	5659	1			T89	2		T126	6		T118	1
valid_sources[0x51]	7219	1			T89	1		T118	1		T158	2
valid_sources[0x52]	6433	1			T126	1		T118	3		T158	3
valid_sources[0x53]	5811	1			T89	5		T93	12		T95	3
valid_sources[0x54]	7267	1			T89	6		T126	2		T158	4
valid_sources[0x55]	7427	1			T89	2		T92	4		T126	1
valid_sources[0x56]	7093	1			T97	4		T104	6		T118	1
valid_sources[0x57]	5960	1			T89	1		T92	4		T111	1
valid_sources[0x58]	6938	1			T158	1		T106	1		T131	3
valid_sources[0x59]	6019	1			T89	8		T111	1		T118	2
valid_sources[0x5a]	5744	1			T89	7		T93	2		T95	1
valid_sources[0x5b]	6894	1			T89	5		T126	1		T158	2
valid_sources[0x5c]	6113	1			T89	11		T91	44		T96	2
valid_sources[0x5d]	9154	1			T95	10		T96	15		T104	4
valid_sources[0x5e]	5808	1			T95	1		T126	1		T104	32
valid_sources[0x5f]	7936	1			T95	2		T97	3		T118	2
valid_sources[0x60]	5827	1			T89	8		T95	4		T118	1
valid_sources[0x61]	6979	1			T89	2		T118	3		T158	1
valid_sources[0x62]	5986	1			T95	3		T158	3		T106	2
valid_sources[0x63]	5902	1			T89	2		T92	2		T93	11
valid_sources[0x64]	5987	1			T89	2		T93	4		T95	1
valid_sources[0x65]	7827	1			T89	2		T93	6		T118	1
valid_sources[0x66]	5970	1			T89	1		T93	3		T96	4
valid_sources[0x67]	6050	1			T89	1		T126	10		T118	2
valid_sources[0x68]	5647	1			T89	5		T95	2		T118	2
valid_sources[0x69]	5750	1			T89	2		T93	20		T118	4
valid_sources[0x6a]	11328	1			T89	6		T93	4		T97	1
valid_sources[0x6b]	7055	1			T111	4		T126	5		T118	4
valid_sources[0x6c]	6137	1			T95	1		T96	4		T118	4
valid_sources[0x6d]	6150	1			T89	1		T93	22		T95	1
valid_sources[0x6e]	5549	1			T89	3		T95	1		T96	7
valid_sources[0x6f]	5897	1			T89	4		T93	11		T118	6
valid_sources[0x70]	5724	1			T89	3		T93	6		T158	3
valid_sources[0x71]	5646	1			T89	6		T95	2		T96	3
valid_sources[0x72]	5860	1			T89	3		T111	1		T118	2
valid_sources[0x73]	5735	1			T95	2		T96	1		T126	4
valid_sources[0x74]	7666	1			T89	5		T96	4		T158	3
valid_sources[0x75]	5835	1			T89	1		T92	2		T93	3
valid_sources[0x76]	5908	1			T93	1		T96	1		T97	3
valid_sources[0x77]	7195	1			T89	1		T93	5		T97	7
valid_sources[0x78]	6205	1			T95	1		T104	3		T118	1
valid_sources[0x79]	5979	1			T89	2		T93	1		T95	2
valid_sources[0x7a]	5702	1			T89	12		T95	4		T97	5
valid_sources[0x7b]	6079	1			T96	1		T158	2		T157	128
valid_sources[0x7c]	5577	1			T92	2		T97	1		T104	1
valid_sources[0x7d]	6220	1			T89	6		T92	2		T96	9
valid_sources[0x7e]	6560	1			T89	3		T95	1		T96	1
valid_sources[0x7f]	5905	1			T89	1		T92	5		T104	4
valid_sources[0x80]	6081	1			T89	3		T158	1		T106	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

906371

1

T89

135

T91

22

T92

29

values[0x0]

all_enables

biggest_size

127596

1

T89

227

T91

33

T92

90

values[0x1]

all_enables

biggest_size

126933

1

T89

246

T91

34

T92

90