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 LINE       1285
 EXPRESSION (addr_hit[25] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T89,T92,T96
1	0	1	Covered	T89,T92,T93
1	1	0	Covered	T136
1	1	1	Covered	T3,T7,T8

 LINE       1286
 EXPRESSION (addr_hit[26] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T89,T92,T96
1	0	1	Covered	T89,T91,T92
1	1	0	Not Covered
1	1	1	Covered	T3,T7,T8

 LINE       1287
 EXPRESSION (addr_hit[27] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T89,T92,T96
1	0	1	Covered	T89,T91,T92
1	1	0	Covered	T138,T133,T146
1	1	1	Covered	T3,T7,T8

 LINE       1288
 EXPRESSION (addr_hit[28] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T89,T92,T96
1	0	1	Covered	T89,T91,T92
1	1	0	Covered	T145
1	1	1	Covered	T3,T7,T8

 LINE       1289
 EXPRESSION (addr_hit[29] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T89,T92,T96
1	0	1	Covered	T89,T91,T92
1	1	0	Not Covered
1	1	1	Covered	T3,T7,T8

 LINE       1290
 EXPRESSION (addr_hit[30] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T89,T92,T96
1	0	1	Covered	T89,T91,T92
1	1	0	Covered	T114
1	1	1	Covered	T3,T7,T8

 LINE       1291
 EXPRESSION (addr_hit[31] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T89,T92,T96
1	0	1	Covered	T89,T91,T92
1	1	0	Covered	T139
1	1	1	Covered	T3,T7,T8

 LINE       1292
 EXPRESSION (addr_hit[32] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T89,T92,T96
1	0	1	Covered	T89,T91,T92
1	1	0	Covered	T105
1	1	1	Covered	T3,T7,T8

 LINE       1293
 EXPRESSION (addr_hit[33] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T89,T92,T96
1	0	1	Covered	T89,T91,T92
1	1	0	Covered	T128,T139,T143
1	1	1	Covered	T3,T7,T8

 LINE       1294
 EXPRESSION (addr_hit[34] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T89,T92,T96
1	0	1	Covered	T89,T92,T93
1	1	0	Not Covered
1	1	1	Covered	T3,T7,T8