Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.13	100.00	83.10	98.16		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	70658754	14275	0	0
claim_transition_if_regwen_rd_A	70658754	1858	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70658754	14275	0	0
T89	2641	265	0	0
T90	6006	0	0	0
T91	3539	44	0	0
T92	2592	0	0	0
T93	12937	852	0	0
T94	40365	0	0	0
T95	7839	404	0	0
T96	1750	0	0	0
T97	2124	0	0	0
T104	0	270	0	0
T106	0	9	0	0
T107	0	25	0	0
T111	1199	0	0	0
T118	0	306	0	0
T126	0	483	0	0
T152	0	142	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70658754	1858	0	0
T92	2592	4	0	0
T93	12937	27	0	0
T94	40365	0	0	0
T95	7839	13	0	0
T96	1750	0	0	0
T97	2124	13	0	0
T104	2865	0	0	0
T108	0	33	0	0
T110	0	8	0	0
T111	1199	0	0	0
T115	816	0	0	0
T116	0	5	0	0
T118	0	16	0	0
T126	2752	0	0	0
T156	0	119	0	0
T157	0	455	0	0