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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.02 97.29 95.61 91.98 97.67 96.13 98.48 95.00


Total test records in report: 983
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T759 /workspace/coverage/default/37.lc_ctrl_sec_token_digest.1060048000 Dec 27 01:02:59 PM PST 23 Dec 27 01:03:21 PM PST 23 949357204 ps
T760 /workspace/coverage/default/22.lc_ctrl_sec_mubi.4089851427 Dec 27 01:02:18 PM PST 23 Dec 27 01:02:35 PM PST 23 1733558346 ps
T761 /workspace/coverage/default/19.lc_ctrl_jtag_access.174141109 Dec 27 01:02:16 PM PST 23 Dec 27 01:02:24 PM PST 23 2341441564 ps
T762 /workspace/coverage/default/21.lc_ctrl_errors.93691668 Dec 27 01:02:21 PM PST 23 Dec 27 01:02:34 PM PST 23 235601826 ps
T763 /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3367203770 Dec 27 01:00:54 PM PST 23 Dec 27 01:01:36 PM PST 23 7672599528 ps
T764 /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.637180692 Dec 27 01:01:59 PM PST 23 Dec 27 01:02:00 PM PST 23 153561324 ps
T765 /workspace/coverage/default/8.lc_ctrl_smoke.3047467296 Dec 27 01:01:21 PM PST 23 Dec 27 01:01:28 PM PST 23 30246355 ps
T766 /workspace/coverage/default/17.lc_ctrl_state_post_trans.2249406102 Dec 27 01:01:50 PM PST 23 Dec 27 01:01:54 PM PST 23 305014225 ps
T767 /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.510363520 Dec 27 01:01:26 PM PST 23 Dec 27 01:02:32 PM PST 23 1356342668 ps
T768 /workspace/coverage/default/19.lc_ctrl_sec_token_digest.1221524315 Dec 27 01:02:05 PM PST 23 Dec 27 01:02:24 PM PST 23 978761872 ps
T769 /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3226369095 Dec 27 01:02:37 PM PST 23 Dec 27 01:02:44 PM PST 23 45342637 ps
T770 /workspace/coverage/default/11.lc_ctrl_errors.2913874465 Dec 27 01:02:01 PM PST 23 Dec 27 01:02:14 PM PST 23 2660628087 ps
T771 /workspace/coverage/default/44.lc_ctrl_state_failure.1967425534 Dec 27 01:03:00 PM PST 23 Dec 27 01:03:40 PM PST 23 1075073064 ps
T772 /workspace/coverage/default/2.lc_ctrl_state_failure.445702447 Dec 27 01:01:07 PM PST 23 Dec 27 01:01:48 PM PST 23 1057246680 ps
T773 /workspace/coverage/default/6.lc_ctrl_security_escalation.1035508779 Dec 27 01:01:15 PM PST 23 Dec 27 01:01:29 PM PST 23 303287732 ps
T774 /workspace/coverage/default/17.lc_ctrl_sec_token_digest.3670940884 Dec 27 01:01:51 PM PST 23 Dec 27 01:02:07 PM PST 23 2073461499 ps
T775 /workspace/coverage/default/14.lc_ctrl_security_escalation.3351168613 Dec 27 01:02:18 PM PST 23 Dec 27 01:02:29 PM PST 23 381074224 ps
T776 /workspace/coverage/default/41.lc_ctrl_prog_failure.2111901772 Dec 27 01:02:56 PM PST 23 Dec 27 01:03:11 PM PST 23 66863580 ps
T777 /workspace/coverage/default/38.lc_ctrl_stress_all.3575798386 Dec 27 01:02:37 PM PST 23 Dec 27 01:06:43 PM PST 23 10696372143 ps
T778 /workspace/coverage/default/8.lc_ctrl_prog_failure.1622750025 Dec 27 01:01:18 PM PST 23 Dec 27 01:01:27 PM PST 23 60152296 ps
T779 /workspace/coverage/default/2.lc_ctrl_prog_failure.3695679760 Dec 27 01:01:02 PM PST 23 Dec 27 01:01:07 PM PST 23 25407683 ps
T780 /workspace/coverage/default/4.lc_ctrl_stress_all.107071275 Dec 27 01:01:15 PM PST 23 Dec 27 01:03:16 PM PST 23 65321172233 ps
T781 /workspace/coverage/default/4.lc_ctrl_prog_failure.2604513135 Dec 27 01:01:18 PM PST 23 Dec 27 01:01:25 PM PST 23 492858729 ps
T782 /workspace/coverage/default/19.lc_ctrl_security_escalation.230887343 Dec 27 01:02:03 PM PST 23 Dec 27 01:02:15 PM PST 23 514282876 ps
T783 /workspace/coverage/default/3.lc_ctrl_jtag_smoke.663654227 Dec 27 01:01:07 PM PST 23 Dec 27 01:01:25 PM PST 23 2554297066 ps
T784 /workspace/coverage/default/4.lc_ctrl_jtag_errors.1844667416 Dec 27 01:01:06 PM PST 23 Dec 27 01:01:42 PM PST 23 2061247511 ps
T785 /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2141443099 Dec 27 01:02:18 PM PST 23 Dec 27 01:02:30 PM PST 23 1190846562 ps
T786 /workspace/coverage/default/35.lc_ctrl_security_escalation.1052759852 Dec 27 01:02:31 PM PST 23 Dec 27 01:02:47 PM PST 23 235279528 ps
T787 /workspace/coverage/default/31.lc_ctrl_state_post_trans.2381324467 Dec 27 01:02:21 PM PST 23 Dec 27 01:02:34 PM PST 23 489499435 ps
T788 /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1049888838 Dec 27 01:01:49 PM PST 23 Dec 27 01:01:51 PM PST 23 35148153 ps
T789 /workspace/coverage/default/34.lc_ctrl_sec_mubi.1300688966 Dec 27 01:02:31 PM PST 23 Dec 27 01:02:50 PM PST 23 1446897315 ps
T790 /workspace/coverage/default/10.lc_ctrl_jtag_smoke.1260378096 Dec 27 01:01:26 PM PST 23 Dec 27 01:01:38 PM PST 23 145959854 ps
T791 /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1531913188 Dec 27 01:02:40 PM PST 23 Dec 27 01:03:02 PM PST 23 407858799 ps
T792 /workspace/coverage/default/42.lc_ctrl_state_failure.765214027 Dec 27 01:02:58 PM PST 23 Dec 27 01:03:38 PM PST 23 2456121580 ps
T793 /workspace/coverage/default/11.lc_ctrl_state_post_trans.90528146 Dec 27 01:02:04 PM PST 23 Dec 27 01:02:08 PM PST 23 189310665 ps
T794 /workspace/coverage/default/38.lc_ctrl_sec_token_mux.904713868 Dec 27 01:02:51 PM PST 23 Dec 27 01:03:05 PM PST 23 1226940287 ps
T795 /workspace/coverage/default/10.lc_ctrl_security_escalation.802856040 Dec 27 01:01:26 PM PST 23 Dec 27 01:01:43 PM PST 23 244244165 ps
T796 /workspace/coverage/default/23.lc_ctrl_errors.2231870723 Dec 27 01:02:16 PM PST 23 Dec 27 01:02:35 PM PST 23 2630028498 ps
T797 /workspace/coverage/default/45.lc_ctrl_jtag_access.375505764 Dec 27 01:02:58 PM PST 23 Dec 27 01:03:19 PM PST 23 1722620740 ps
T798 /workspace/coverage/default/5.lc_ctrl_sec_token_mux.2901258804 Dec 27 01:01:17 PM PST 23 Dec 27 01:01:33 PM PST 23 312902817 ps
T799 /workspace/coverage/default/28.lc_ctrl_sec_mubi.1587160958 Dec 27 01:02:29 PM PST 23 Dec 27 01:02:51 PM PST 23 2112934932 ps
T800 /workspace/coverage/default/15.lc_ctrl_jtag_errors.2446896730 Dec 27 01:01:49 PM PST 23 Dec 27 01:02:39 PM PST 23 16029682614 ps
T801 /workspace/coverage/default/5.lc_ctrl_stress_all.1671171747 Dec 27 01:01:16 PM PST 23 Dec 27 01:02:33 PM PST 23 11455722591 ps
T802 /workspace/coverage/default/40.lc_ctrl_alert_test.131913582 Dec 27 01:02:46 PM PST 23 Dec 27 01:02:53 PM PST 23 23743288 ps
T803 /workspace/coverage/default/30.lc_ctrl_stress_all.1815189374 Dec 27 01:02:19 PM PST 23 Dec 27 01:03:36 PM PST 23 27947158606 ps
T804 /workspace/coverage/default/49.lc_ctrl_jtag_access.663729089 Dec 27 01:03:03 PM PST 23 Dec 27 01:03:22 PM PST 23 269512265 ps
T805 /workspace/coverage/default/10.lc_ctrl_jtag_errors.4259451160 Dec 27 01:01:26 PM PST 23 Dec 27 01:02:25 PM PST 23 6357489978 ps
T806 /workspace/coverage/default/23.lc_ctrl_prog_failure.2116334800 Dec 27 01:02:18 PM PST 23 Dec 27 01:02:22 PM PST 23 56660585 ps
T807 /workspace/coverage/default/25.lc_ctrl_stress_all.2877588478 Dec 27 01:02:34 PM PST 23 Dec 27 01:03:11 PM PST 23 1175611242 ps
T808 /workspace/coverage/default/3.lc_ctrl_state_failure.3536365822 Dec 27 01:01:11 PM PST 23 Dec 27 01:01:42 PM PST 23 2068441263 ps
T809 /workspace/coverage/default/14.lc_ctrl_prog_failure.4072237315 Dec 27 01:02:03 PM PST 23 Dec 27 01:02:06 PM PST 23 111141126 ps
T810 /workspace/coverage/default/5.lc_ctrl_security_escalation.1714035755 Dec 27 01:01:08 PM PST 23 Dec 27 01:01:24 PM PST 23 337474164 ps
T811 /workspace/coverage/default/43.lc_ctrl_prog_failure.832065944 Dec 27 01:02:54 PM PST 23 Dec 27 01:03:10 PM PST 23 523182684 ps
T812 /workspace/coverage/default/18.lc_ctrl_jtag_smoke.4215033698 Dec 27 01:02:18 PM PST 23 Dec 27 01:02:27 PM PST 23 685960229 ps
T813 /workspace/coverage/default/24.lc_ctrl_sec_token_mux.2013221588 Dec 27 01:02:19 PM PST 23 Dec 27 01:02:29 PM PST 23 176617140 ps
T814 /workspace/coverage/default/29.lc_ctrl_alert_test.987193933 Dec 27 01:02:39 PM PST 23 Dec 27 01:02:46 PM PST 23 100714718 ps
T815 /workspace/coverage/default/30.lc_ctrl_sec_token_digest.138959490 Dec 27 01:02:20 PM PST 23 Dec 27 01:02:35 PM PST 23 1696714578 ps
T816 /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3306584192 Dec 27 01:01:14 PM PST 23 Dec 27 01:01:45 PM PST 23 3142259382 ps
T817 /workspace/coverage/default/37.lc_ctrl_state_post_trans.2700412316 Dec 27 01:02:39 PM PST 23 Dec 27 01:02:49 PM PST 23 945253542 ps
T818 /workspace/coverage/default/19.lc_ctrl_jtag_errors.1222423073 Dec 27 01:02:04 PM PST 23 Dec 27 01:02:33 PM PST 23 7204889199 ps
T819 /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.982912187 Dec 27 01:03:07 PM PST 23 Dec 27 01:03:20 PM PST 23 63736376 ps
T820 /workspace/coverage/default/17.lc_ctrl_sec_mubi.3789617065 Dec 27 01:02:02 PM PST 23 Dec 27 01:02:16 PM PST 23 1042284211 ps
T821 /workspace/coverage/default/16.lc_ctrl_state_post_trans.3105942551 Dec 27 01:02:02 PM PST 23 Dec 27 01:02:11 PM PST 23 150052338 ps
T822 /workspace/coverage/default/39.lc_ctrl_jtag_access.2223098886 Dec 27 01:02:42 PM PST 23 Dec 27 01:02:52 PM PST 23 196592282 ps
T823 /workspace/coverage/default/46.lc_ctrl_sec_token_digest.3631464896 Dec 27 01:02:49 PM PST 23 Dec 27 01:03:16 PM PST 23 1053451169 ps
T182 /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2410333471 Dec 27 01:01:07 PM PST 23 Dec 27 01:01:10 PM PST 23 37486436 ps
T824 /workspace/coverage/default/14.lc_ctrl_sec_token_digest.3120926466 Dec 27 01:02:16 PM PST 23 Dec 27 01:02:33 PM PST 23 3894160795 ps
T825 /workspace/coverage/default/3.lc_ctrl_sec_token_mux.56652211 Dec 27 01:01:12 PM PST 23 Dec 27 01:01:26 PM PST 23 1172791968 ps
T826 /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2406098860 Dec 27 01:02:51 PM PST 23 Dec 27 01:03:09 PM PST 23 427551991 ps
T827 /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.3454072392 Dec 27 01:01:48 PM PST 23 Dec 27 01:01:58 PM PST 23 1253962500 ps
T828 /workspace/coverage/default/25.lc_ctrl_jtag_access.812150849 Dec 27 01:02:19 PM PST 23 Dec 27 01:02:39 PM PST 23 3165320884 ps
T829 /workspace/coverage/default/13.lc_ctrl_errors.3403865686 Dec 27 01:01:41 PM PST 23 Dec 27 01:01:59 PM PST 23 877263630 ps
T830 /workspace/coverage/default/32.lc_ctrl_state_post_trans.1923309259 Dec 27 01:02:24 PM PST 23 Dec 27 01:02:37 PM PST 23 243760166 ps
T831 /workspace/coverage/default/9.lc_ctrl_sec_mubi.1742385975 Dec 27 01:01:26 PM PST 23 Dec 27 01:01:49 PM PST 23 1706556882 ps
T832 /workspace/coverage/default/13.lc_ctrl_prog_failure.370937608 Dec 27 01:01:47 PM PST 23 Dec 27 01:01:51 PM PST 23 63890637 ps
T833 /workspace/coverage/default/8.lc_ctrl_claim_transition_if.664513996 Dec 27 01:01:18 PM PST 23 Dec 27 01:01:24 PM PST 23 98021648 ps
T834 /workspace/coverage/default/5.lc_ctrl_state_post_trans.1578728076 Dec 27 01:01:10 PM PST 23 Dec 27 01:01:25 PM PST 23 1269425387 ps
T835 /workspace/coverage/default/17.lc_ctrl_state_failure.4041955817 Dec 27 01:01:59 PM PST 23 Dec 27 01:02:28 PM PST 23 242552254 ps
T836 /workspace/coverage/default/15.lc_ctrl_stress_all.366340530 Dec 27 01:02:01 PM PST 23 Dec 27 01:03:21 PM PST 23 9836793834 ps
T122 /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.3372032985 Dec 27 01:02:09 PM PST 23 Dec 27 02:47:15 PM PST 23 103442804736 ps
T837 /workspace/coverage/default/41.lc_ctrl_jtag_access.3761699715 Dec 27 01:02:37 PM PST 23 Dec 27 01:02:48 PM PST 23 1458506919 ps
T838 /workspace/coverage/default/2.lc_ctrl_jtag_access.775082417 Dec 27 01:01:07 PM PST 23 Dec 27 01:01:28 PM PST 23 805563048 ps
T839 /workspace/coverage/default/8.lc_ctrl_jtag_errors.3061605689 Dec 27 01:01:20 PM PST 23 Dec 27 01:01:58 PM PST 23 8407238211 ps
T840 /workspace/coverage/default/32.lc_ctrl_sec_mubi.202643582 Dec 27 01:02:32 PM PST 23 Dec 27 01:02:55 PM PST 23 673109455 ps
T841 /workspace/coverage/default/11.lc_ctrl_alert_test.429875575 Dec 27 01:01:47 PM PST 23 Dec 27 01:01:50 PM PST 23 45082508 ps
T842 /workspace/coverage/default/46.lc_ctrl_sec_token_mux.4229948284 Dec 27 01:02:57 PM PST 23 Dec 27 01:03:18 PM PST 23 216289313 ps
T843 /workspace/coverage/default/25.lc_ctrl_prog_failure.796123910 Dec 27 01:02:16 PM PST 23 Dec 27 01:02:23 PM PST 23 295144188 ps
T844 /workspace/coverage/default/26.lc_ctrl_prog_failure.2054784540 Dec 27 01:02:31 PM PST 23 Dec 27 01:02:40 PM PST 23 92063585 ps
T845 /workspace/coverage/default/32.lc_ctrl_smoke.2128881868 Dec 27 01:02:28 PM PST 23 Dec 27 01:02:36 PM PST 23 37873892 ps
T846 /workspace/coverage/default/0.lc_ctrl_smoke.3728269409 Dec 27 01:00:49 PM PST 23 Dec 27 01:01:09 PM PST 23 652461521 ps
T847 /workspace/coverage/default/5.lc_ctrl_regwen_during_op.2505173168 Dec 27 01:01:11 PM PST 23 Dec 27 01:01:24 PM PST 23 368611730 ps
T848 /workspace/coverage/default/26.lc_ctrl_smoke.1068486111 Dec 27 01:02:36 PM PST 23 Dec 27 01:02:45 PM PST 23 524767031 ps
T849 /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2806682400 Dec 27 01:01:22 PM PST 23 Dec 27 01:01:29 PM PST 23 39043340 ps
T850 /workspace/coverage/default/48.lc_ctrl_jtag_access.2457356173 Dec 27 01:02:54 PM PST 23 Dec 27 01:03:08 PM PST 23 51534914 ps
T851 /workspace/coverage/default/7.lc_ctrl_errors.705438399 Dec 27 01:01:20 PM PST 23 Dec 27 01:01:39 PM PST 23 3129978147 ps
T68 /workspace/coverage/default/1.lc_ctrl_claim_transition_if.2560912597 Dec 27 01:01:03 PM PST 23 Dec 27 01:01:08 PM PST 23 49905070 ps
T852 /workspace/coverage/default/4.lc_ctrl_state_failure.2824870905 Dec 27 01:01:11 PM PST 23 Dec 27 01:01:45 PM PST 23 233472128 ps
T853 /workspace/coverage/default/38.lc_ctrl_sec_mubi.2961432426 Dec 27 01:02:51 PM PST 23 Dec 27 01:03:17 PM PST 23 633351439 ps
T854 /workspace/coverage/default/20.lc_ctrl_sec_token_mux.598113964 Dec 27 01:02:17 PM PST 23 Dec 27 01:02:26 PM PST 23 196332433 ps
T855 /workspace/coverage/default/29.lc_ctrl_sec_token_digest.2296372115 Dec 27 01:02:45 PM PST 23 Dec 27 01:03:14 PM PST 23 852100018 ps
T856 /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3594076136 Dec 27 01:01:10 PM PST 23 Dec 27 01:02:04 PM PST 23 13056189934 ps
T857 /workspace/coverage/default/45.lc_ctrl_state_post_trans.3771757394 Dec 27 01:03:01 PM PST 23 Dec 27 01:03:22 PM PST 23 260621193 ps
T858 /workspace/coverage/default/12.lc_ctrl_prog_failure.1672631053 Dec 27 01:01:50 PM PST 23 Dec 27 01:01:53 PM PST 23 316475153 ps
T859 /workspace/coverage/default/0.lc_ctrl_prog_failure.874596342 Dec 27 01:00:59 PM PST 23 Dec 27 01:01:06 PM PST 23 262918985 ps
T860 /workspace/coverage/default/21.lc_ctrl_security_escalation.2384467666 Dec 27 01:02:21 PM PST 23 Dec 27 01:02:39 PM PST 23 1116830811 ps
T861 /workspace/coverage/default/29.lc_ctrl_stress_all.535558154 Dec 27 01:02:37 PM PST 23 Dec 27 01:03:48 PM PST 23 2094821720 ps
T862 /workspace/coverage/default/3.lc_ctrl_jtag_access.922105827 Dec 27 01:01:10 PM PST 23 Dec 27 01:01:18 PM PST 23 589407909 ps
T863 /workspace/coverage/default/36.lc_ctrl_sec_mubi.4075724278 Dec 27 01:02:43 PM PST 23 Dec 27 01:03:02 PM PST 23 748324507 ps
T864 /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.945736478 Dec 27 01:02:19 PM PST 23 Dec 27 01:02:30 PM PST 23 2595265902 ps
T865 /workspace/coverage/default/47.lc_ctrl_state_failure.3438171606 Dec 27 01:02:52 PM PST 23 Dec 27 01:03:34 PM PST 23 1027004614 ps
T866 /workspace/coverage/default/36.lc_ctrl_state_post_trans.1399264087 Dec 27 01:02:41 PM PST 23 Dec 27 01:02:53 PM PST 23 217291620 ps
T867 /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.2990050360 Dec 27 01:02:32 PM PST 23 Dec 27 01:14:46 PM PST 23 865372208738 ps
T868 /workspace/coverage/default/48.lc_ctrl_sec_mubi.3479134841 Dec 27 01:03:01 PM PST 23 Dec 27 01:03:28 PM PST 23 352626287 ps
T869 /workspace/coverage/default/12.lc_ctrl_stress_all.940379299 Dec 27 01:01:48 PM PST 23 Dec 27 01:02:31 PM PST 23 7674365310 ps
T870 /workspace/coverage/default/19.lc_ctrl_prog_failure.3305990595 Dec 27 01:02:18 PM PST 23 Dec 27 01:02:25 PM PST 23 70459006 ps
T871 /workspace/coverage/default/17.lc_ctrl_jtag_access.3181600864 Dec 27 01:01:47 PM PST 23 Dec 27 01:02:02 PM PST 23 592426795 ps
T872 /workspace/coverage/default/49.lc_ctrl_errors.541199245 Dec 27 01:02:59 PM PST 23 Dec 27 01:03:26 PM PST 23 1752910102 ps
T873 /workspace/coverage/default/42.lc_ctrl_errors.25928716 Dec 27 01:02:56 PM PST 23 Dec 27 01:03:20 PM PST 23 609697338 ps
T874 /workspace/coverage/default/36.lc_ctrl_errors.77506847 Dec 27 01:02:40 PM PST 23 Dec 27 01:03:02 PM PST 23 2554114444 ps
T875 /workspace/coverage/default/37.lc_ctrl_alert_test.3138781469 Dec 27 01:02:45 PM PST 23 Dec 27 01:02:52 PM PST 23 30449891 ps
T876 /workspace/coverage/default/21.lc_ctrl_sec_mubi.616531088 Dec 27 01:02:21 PM PST 23 Dec 27 01:02:41 PM PST 23 4209106767 ps
T877 /workspace/coverage/default/49.lc_ctrl_smoke.3041118017 Dec 27 01:03:04 PM PST 23 Dec 27 01:03:19 PM PST 23 69150796 ps
T878 /workspace/coverage/default/39.lc_ctrl_alert_test.1540277257 Dec 27 01:02:46 PM PST 23 Dec 27 01:02:53 PM PST 23 16872307 ps
T879 /workspace/coverage/default/11.lc_ctrl_jtag_smoke.51908827 Dec 27 01:01:47 PM PST 23 Dec 27 01:01:53 PM PST 23 1858737601 ps
T880 /workspace/coverage/default/42.lc_ctrl_stress_all.1514514415 Dec 27 01:02:49 PM PST 23 Dec 27 01:04:26 PM PST 23 4421781051 ps
T881 /workspace/coverage/default/6.lc_ctrl_jtag_priority.433911820 Dec 27 01:01:20 PM PST 23 Dec 27 01:01:31 PM PST 23 266674526 ps
T882 /workspace/coverage/default/18.lc_ctrl_smoke.3501892986 Dec 27 01:01:52 PM PST 23 Dec 27 01:01:57 PM PST 23 139523189 ps
T883 /workspace/coverage/default/36.lc_ctrl_sec_token_digest.588123894 Dec 27 01:02:44 PM PST 23 Dec 27 01:03:02 PM PST 23 511830083 ps
T884 /workspace/coverage/default/28.lc_ctrl_sec_token_digest.4207606152 Dec 27 01:02:30 PM PST 23 Dec 27 01:02:44 PM PST 23 2439155176 ps
T885 /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.1250446266 Dec 27 01:01:11 PM PST 23 Dec 27 01:01:38 PM PST 23 26366805288 ps
T886 /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.30386492 Dec 27 01:01:05 PM PST 23 Dec 27 01:01:44 PM PST 23 2613799276 ps
T887 /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1173018856 Dec 27 01:01:32 PM PST 23 Dec 27 01:01:48 PM PST 23 334589104 ps
T888 /workspace/coverage/default/0.lc_ctrl_jtag_priority.1984533426 Dec 27 01:01:07 PM PST 23 Dec 27 01:01:17 PM PST 23 244508849 ps
T889 /workspace/coverage/default/28.lc_ctrl_stress_all.2698200362 Dec 27 01:02:32 PM PST 23 Dec 27 01:04:05 PM PST 23 7354537475 ps
T77 /workspace/coverage/default/45.lc_ctrl_smoke.4276078628 Dec 27 01:02:58 PM PST 23 Dec 27 01:03:13 PM PST 23 474961328 ps
T890 /workspace/coverage/default/36.lc_ctrl_jtag_access.2059356394 Dec 27 01:02:39 PM PST 23 Dec 27 01:02:47 PM PST 23 162334645 ps
T891 /workspace/coverage/default/9.lc_ctrl_state_failure.3546119015 Dec 27 01:01:28 PM PST 23 Dec 27 01:02:00 PM PST 23 4908832999 ps
T892 /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.4082686266 Dec 27 01:02:36 PM PST 23 Dec 27 01:02:47 PM PST 23 37651078 ps
T893 /workspace/coverage/default/39.lc_ctrl_prog_failure.2393963406 Dec 27 01:02:45 PM PST 23 Dec 27 01:02:53 PM PST 23 136720127 ps
T894 /workspace/coverage/default/13.lc_ctrl_sec_mubi.1229630529 Dec 27 01:02:00 PM PST 23 Dec 27 01:02:17 PM PST 23 317109660 ps
T895 /workspace/coverage/default/38.lc_ctrl_alert_test.205783335 Dec 27 01:02:41 PM PST 23 Dec 27 01:02:47 PM PST 23 19185438 ps
T896 /workspace/coverage/default/27.lc_ctrl_prog_failure.2259075890 Dec 27 01:02:44 PM PST 23 Dec 27 01:02:53 PM PST 23 544514206 ps
T897 /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.384145009 Dec 27 01:02:17 PM PST 23 Dec 27 01:02:49 PM PST 23 1940480718 ps
T898 /workspace/coverage/default/13.lc_ctrl_jtag_smoke.526275828 Dec 27 01:01:48 PM PST 23 Dec 27 01:01:57 PM PST 23 274431744 ps
T899 /workspace/coverage/default/22.lc_ctrl_sec_token_digest.2017418096 Dec 27 01:02:06 PM PST 23 Dec 27 01:02:23 PM PST 23 381890890 ps
T900 /workspace/coverage/default/16.lc_ctrl_state_failure.3823609500 Dec 27 01:02:03 PM PST 23 Dec 27 01:02:36 PM PST 23 695975692 ps
T901 /workspace/coverage/default/24.lc_ctrl_smoke.547179705 Dec 27 01:02:20 PM PST 23 Dec 27 01:02:27 PM PST 23 212929591 ps
T902 /workspace/coverage/default/8.lc_ctrl_stress_all.3880008625 Dec 27 01:01:22 PM PST 23 Dec 27 01:02:16 PM PST 23 16272732511 ps
T903 /workspace/coverage/default/19.lc_ctrl_errors.1900769647 Dec 27 01:02:16 PM PST 23 Dec 27 01:02:29 PM PST 23 263049463 ps
T904 /workspace/coverage/default/3.lc_ctrl_sec_token_digest.1809306165 Dec 27 01:01:13 PM PST 23 Dec 27 01:01:28 PM PST 23 1036357727 ps
T905 /workspace/coverage/default/33.lc_ctrl_state_failure.3642465399 Dec 27 01:03:00 PM PST 23 Dec 27 01:03:36 PM PST 23 860870422 ps
T906 /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2724409094 Dec 27 01:01:51 PM PST 23 Dec 27 01:02:53 PM PST 23 9984340227 ps
T907 /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1817206383 Dec 27 01:03:06 PM PST 23 Dec 27 01:03:25 PM PST 23 187392151 ps
T908 /workspace/coverage/default/21.lc_ctrl_sec_token_digest.4069821594 Dec 27 01:02:21 PM PST 23 Dec 27 01:02:36 PM PST 23 916850868 ps
T909 /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1457194404 Dec 27 01:01:23 PM PST 23 Dec 27 01:01:41 PM PST 23 1607172459 ps
T910 /workspace/coverage/default/11.lc_ctrl_state_failure.508585899 Dec 27 01:01:28 PM PST 23 Dec 27 01:02:04 PM PST 23 1195899333 ps
T911 /workspace/coverage/default/16.lc_ctrl_security_escalation.1294019166 Dec 27 01:02:18 PM PST 23 Dec 27 01:02:31 PM PST 23 1590266074 ps
T912 /workspace/coverage/default/40.lc_ctrl_state_post_trans.3128244070 Dec 27 01:02:41 PM PST 23 Dec 27 01:02:52 PM PST 23 69564608 ps
T913 /workspace/coverage/default/5.lc_ctrl_sec_mubi.3365701325 Dec 27 01:01:14 PM PST 23 Dec 27 01:01:34 PM PST 23 453713716 ps
T914 /workspace/coverage/default/9.lc_ctrl_errors.1765189800 Dec 27 01:01:29 PM PST 23 Dec 27 01:01:47 PM PST 23 713985893 ps
T915 /workspace/coverage/default/6.lc_ctrl_prog_failure.3486931758 Dec 27 01:01:23 PM PST 23 Dec 27 01:01:34 PM PST 23 467568501 ps
T916 /workspace/coverage/default/47.lc_ctrl_prog_failure.2776311363 Dec 27 01:02:57 PM PST 23 Dec 27 01:03:12 PM PST 23 112877173 ps
T917 /workspace/coverage/default/29.lc_ctrl_state_post_trans.3212280107 Dec 27 01:02:23 PM PST 23 Dec 27 01:02:35 PM PST 23 56369148 ps
T918 /workspace/coverage/default/26.lc_ctrl_errors.3414437791 Dec 27 01:02:37 PM PST 23 Dec 27 01:02:57 PM PST 23 1606581245 ps
T919 /workspace/coverage/default/39.lc_ctrl_sec_token_mux.3209353897 Dec 27 01:02:55 PM PST 23 Dec 27 01:03:17 PM PST 23 3046455284 ps
T920 /workspace/coverage/default/34.lc_ctrl_prog_failure.1532488927 Dec 27 01:02:29 PM PST 23 Dec 27 01:02:37 PM PST 23 68601649 ps
T921 /workspace/coverage/default/30.lc_ctrl_jtag_access.2417754636 Dec 27 01:02:19 PM PST 23 Dec 27 01:02:36 PM PST 23 10200997640 ps
T922 /workspace/coverage/default/24.lc_ctrl_sec_token_digest.215403845 Dec 27 01:02:20 PM PST 23 Dec 27 01:02:34 PM PST 23 490358639 ps
T923 /workspace/coverage/default/28.lc_ctrl_prog_failure.2267318022 Dec 27 01:02:19 PM PST 23 Dec 27 01:02:25 PM PST 23 1198860895 ps
T924 /workspace/coverage/default/45.lc_ctrl_errors.1013260586 Dec 27 01:02:48 PM PST 23 Dec 27 01:03:08 PM PST 23 1027297700 ps
T925 /workspace/coverage/default/33.lc_ctrl_security_escalation.2126360855 Dec 27 01:02:33 PM PST 23 Dec 27 01:02:46 PM PST 23 868764146 ps
T926 /workspace/coverage/default/0.lc_ctrl_sec_mubi.151141161 Dec 27 01:01:03 PM PST 23 Dec 27 01:01:15 PM PST 23 807595901 ps
T927 /workspace/coverage/default/9.lc_ctrl_regwen_during_op.3276853699 Dec 27 01:01:22 PM PST 23 Dec 27 01:01:39 PM PST 23 693058588 ps
T928 /workspace/coverage/default/2.lc_ctrl_errors.3864855316 Dec 27 01:01:05 PM PST 23 Dec 27 01:01:19 PM PST 23 1479603942 ps
T929 /workspace/coverage/default/36.lc_ctrl_state_failure.437426035 Dec 27 01:02:34 PM PST 23 Dec 27 01:03:05 PM PST 23 2351056767 ps
T930 /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2540621896 Dec 27 01:01:26 PM PST 23 Dec 27 01:01:37 PM PST 23 1431701543 ps
T78 /workspace/coverage/default/12.lc_ctrl_jtag_smoke.1140515548 Dec 27 01:01:46 PM PST 23 Dec 27 01:01:55 PM PST 23 1219660580 ps
T931 /workspace/coverage/default/36.lc_ctrl_security_escalation.416775556 Dec 27 01:02:40 PM PST 23 Dec 27 01:02:55 PM PST 23 478887611 ps
T932 /workspace/coverage/default/44.lc_ctrl_security_escalation.1578652182 Dec 27 01:02:48 PM PST 23 Dec 27 01:03:10 PM PST 23 777117906 ps
T933 /workspace/coverage/default/24.lc_ctrl_sec_mubi.2145774961 Dec 27 01:02:20 PM PST 23 Dec 27 01:02:42 PM PST 23 398407847 ps
T934 /workspace/coverage/default/19.lc_ctrl_stress_all.2811416921 Dec 27 01:02:09 PM PST 23 Dec 27 01:03:27 PM PST 23 2461981651 ps
T935 /workspace/coverage/default/5.lc_ctrl_prog_failure.654435222 Dec 27 01:01:17 PM PST 23 Dec 27 01:01:25 PM PST 23 166232460 ps
T936 /workspace/coverage/default/26.lc_ctrl_sec_token_digest.4149346420 Dec 27 01:02:36 PM PST 23 Dec 27 01:02:52 PM PST 23 989854118 ps
T937 /workspace/coverage/default/4.lc_ctrl_jtag_priority.1520084686 Dec 27 01:01:13 PM PST 23 Dec 27 01:01:38 PM PST 23 4391249988 ps
T938 /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1183285706 Dec 27 01:01:11 PM PST 23 Dec 27 01:01:16 PM PST 23 12995343 ps
T939 /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.1388357609 Dec 27 01:02:18 PM PST 23 Dec 27 01:02:22 PM PST 23 17681129 ps
T940 /workspace/coverage/default/17.lc_ctrl_security_escalation.2701575959 Dec 27 01:01:47 PM PST 23 Dec 27 01:01:57 PM PST 23 297359328 ps
T941 /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.751090387 Dec 27 01:01:29 PM PST 23 Dec 27 01:01:35 PM PST 23 44794996 ps
T942 /workspace/coverage/default/45.lc_ctrl_sec_token_mux.282994899 Dec 27 01:02:48 PM PST 23 Dec 27 01:03:07 PM PST 23 533985713 ps
T943 /workspace/coverage/default/39.lc_ctrl_security_escalation.591995348 Dec 27 01:02:37 PM PST 23 Dec 27 01:02:53 PM PST 23 2877775444 ps
T944 /workspace/coverage/default/25.lc_ctrl_sec_token_mux.2507527923 Dec 27 01:02:23 PM PST 23 Dec 27 01:02:39 PM PST 23 452878726 ps
T945 /workspace/coverage/default/41.lc_ctrl_security_escalation.3107953905 Dec 27 01:02:45 PM PST 23 Dec 27 01:03:01 PM PST 23 485186035 ps
T946 /workspace/coverage/default/35.lc_ctrl_sec_mubi.679944478 Dec 27 01:02:39 PM PST 23 Dec 27 01:03:00 PM PST 23 1165412007 ps
T947 /workspace/coverage/default/37.lc_ctrl_stress_all.2693511348 Dec 27 01:02:58 PM PST 23 Dec 27 01:03:36 PM PST 23 491186110 ps
T948 /workspace/coverage/default/16.lc_ctrl_errors.4146663115 Dec 27 01:02:14 PM PST 23 Dec 27 01:02:31 PM PST 23 1172392538 ps
T949 /workspace/coverage/default/34.lc_ctrl_state_failure.1339035262 Dec 27 01:02:30 PM PST 23 Dec 27 01:03:10 PM PST 23 2560093943 ps
T950 /workspace/coverage/default/40.lc_ctrl_state_failure.2822567995 Dec 27 01:02:55 PM PST 23 Dec 27 01:03:25 PM PST 23 192447706 ps
T951 /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.4144765991 Dec 27 01:02:47 PM PST 23 Dec 27 01:02:54 PM PST 23 33411569 ps
T952 /workspace/coverage/default/20.lc_ctrl_smoke.1438985432 Dec 27 01:02:17 PM PST 23 Dec 27 01:02:22 PM PST 23 259935746 ps
T953 /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.3556201437 Dec 27 01:00:59 PM PST 23 Dec 27 01:01:04 PM PST 23 20083727 ps
T954 /workspace/coverage/default/6.lc_ctrl_jtag_errors.4276633115 Dec 27 01:01:11 PM PST 23 Dec 27 01:03:02 PM PST 23 8532151953 ps
T955 /workspace/coverage/default/42.lc_ctrl_sec_mubi.1276436819 Dec 27 01:02:54 PM PST 23 Dec 27 01:03:17 PM PST 23 387112252 ps
T956 /workspace/coverage/default/26.lc_ctrl_state_post_trans.725816552 Dec 27 01:02:31 PM PST 23 Dec 27 01:02:44 PM PST 23 65244839 ps
T957 /workspace/coverage/default/47.lc_ctrl_sec_mubi.4132613499 Dec 27 01:02:58 PM PST 23 Dec 27 01:03:23 PM PST 23 204254221 ps
T958 /workspace/coverage/default/34.lc_ctrl_sec_token_digest.3571614224 Dec 27 01:02:49 PM PST 23 Dec 27 01:03:05 PM PST 23 619316797 ps
T959 /workspace/coverage/default/38.lc_ctrl_errors.1595144665 Dec 27 01:02:42 PM PST 23 Dec 27 01:03:06 PM PST 23 2799294317 ps
T960 /workspace/coverage/default/27.lc_ctrl_sec_token_digest.3732185871 Dec 27 01:02:21 PM PST 23 Dec 27 01:02:36 PM PST 23 602158215 ps
T961 /workspace/coverage/default/33.lc_ctrl_sec_mubi.1797766894 Dec 27 01:02:36 PM PST 23 Dec 27 01:02:56 PM PST 23 2156981529 ps
T962 /workspace/coverage/default/19.lc_ctrl_sec_mubi.2441181143 Dec 27 01:02:06 PM PST 23 Dec 27 01:02:21 PM PST 23 278013153 ps
T963 /workspace/coverage/default/3.lc_ctrl_stress_all.35024711 Dec 27 01:01:14 PM PST 23 Dec 27 01:08:53 PM PST 23 15784584197 ps
T964 /workspace/coverage/default/49.lc_ctrl_sec_token_mux.580180005 Dec 27 01:03:04 PM PST 23 Dec 27 01:03:23 PM PST 23 1192939672 ps
T69 /workspace/coverage/default/4.lc_ctrl_alert_test.3299704039 Dec 27 01:01:18 PM PST 23 Dec 27 01:01:24 PM PST 23 20511660 ps
T965 /workspace/coverage/default/18.lc_ctrl_sec_mubi.1999515079 Dec 27 01:02:04 PM PST 23 Dec 27 01:02:16 PM PST 23 262711127 ps
T966 /workspace/coverage/default/49.lc_ctrl_state_post_trans.3827260234 Dec 27 01:03:11 PM PST 23 Dec 27 01:03:27 PM PST 23 215245705 ps
T967 /workspace/coverage/default/21.lc_ctrl_state_post_trans.1610684445 Dec 27 01:02:21 PM PST 23 Dec 27 01:02:30 PM PST 23 74792929 ps
T968 /workspace/coverage/default/29.lc_ctrl_errors.1620213807 Dec 27 01:02:52 PM PST 23 Dec 27 01:03:15 PM PST 23 1515945647 ps
T969 /workspace/coverage/default/49.lc_ctrl_alert_test.3223873735 Dec 27 01:03:01 PM PST 23 Dec 27 01:03:15 PM PST 23 41190945 ps
T970 /workspace/coverage/default/15.lc_ctrl_security_escalation.1519007252 Dec 27 01:01:49 PM PST 23 Dec 27 01:02:00 PM PST 23 245308502 ps
T971 /workspace/coverage/default/38.lc_ctrl_sec_token_digest.2257177760 Dec 27 01:02:49 PM PST 23 Dec 27 01:03:11 PM PST 23 779051871 ps
T972 /workspace/coverage/default/37.lc_ctrl_smoke.97885281 Dec 27 01:02:52 PM PST 23 Dec 27 01:03:05 PM PST 23 52076496 ps
T973 /workspace/coverage/default/13.lc_ctrl_alert_test.161116524 Dec 27 01:01:58 PM PST 23 Dec 27 01:02:00 PM PST 23 83005332 ps
T974 /workspace/coverage/default/18.lc_ctrl_alert_test.2859974583 Dec 27 01:02:10 PM PST 23 Dec 27 01:02:12 PM PST 23 12474703 ps
T975 /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1574807668 Dec 27 01:02:55 PM PST 23 Dec 27 01:03:08 PM PST 23 32725991 ps
T976 /workspace/coverage/default/21.lc_ctrl_sec_token_mux.1404941361 Dec 27 01:02:22 PM PST 23 Dec 27 01:02:40 PM PST 23 663351115 ps
T977 /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1089217733 Dec 27 01:01:23 PM PST 23 Dec 27 01:01:30 PM PST 23 29244342 ps
T978 /workspace/coverage/default/17.lc_ctrl_errors.71498474 Dec 27 01:01:47 PM PST 23 Dec 27 01:02:03 PM PST 23 1782554477 ps
T979 /workspace/coverage/default/0.lc_ctrl_sec_token_mux.1117335774 Dec 27 01:01:01 PM PST 23 Dec 27 01:01:14 PM PST 23 245156993 ps
T980 /workspace/coverage/default/3.lc_ctrl_sec_mubi.180956499 Dec 27 01:01:18 PM PST 23 Dec 27 01:01:34 PM PST 23 292625739 ps
T981 /workspace/coverage/default/33.lc_ctrl_sec_token_digest.3971422035 Dec 27 01:02:35 PM PST 23 Dec 27 01:02:54 PM PST 23 1025401584 ps
T79 /workspace/coverage/default/4.lc_ctrl_regwen_during_op.4138149460 Dec 27 01:01:15 PM PST 23 Dec 27 01:01:40 PM PST 23 1596719595 ps
T52 /workspace/coverage/default/35.lc_ctrl_errors.3993986536 Dec 27 01:02:35 PM PST 23 Dec 27 01:02:51 PM PST 23 250895387 ps
T982 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1332412773 Dec 27 12:30:22 PM PST 23 Dec 27 12:31:40 PM PST 23 991168629 ps
T983 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3415660453 Dec 27 12:32:02 PM PST 23 Dec 27 12:32:48 PM PST 23 14146026 ps

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3236545392
Short name T53
Test name
Test status
Simulation time 18554515 ps
CPU time 1.03 seconds
Started Dec 27 12:29:47 PM PST 23
Finished Dec 27 12:30:40 PM PST 23
Peak memory 207776 kb
Host smart-8ade5b1a-5056-41dc-8e76-ad6076b6829b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236545392 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.3236545392
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.4157012174
Short name T12
Test name
Test status
Simulation time 12983699299 ps
CPU time 127.42 seconds
Started Dec 27 01:02:35 PM PST 23
Finished Dec 27 01:04:48 PM PST 23
Peak memory 276480 kb
Host smart-09e430b9-837a-49c9-a12c-676fb7fbdac9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157012174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.4157012174
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.398715735
Short name T89
Test name
Test status
Simulation time 51832555 ps
CPU time 2.05 seconds
Started Dec 27 12:30:11 PM PST 23
Finished Dec 27 12:31:06 PM PST 23
Peak memory 219504 kb
Host smart-fe4fc513-e3a0-49d9-9715-784791b2d389
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398715735 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.398715735
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.545091889
Short name T106
Test name
Test status
Simulation time 228713228 ps
CPU time 5.76 seconds
Started Dec 27 12:30:25 PM PST 23
Finished Dec 27 12:31:27 PM PST 23
Peak memory 217608 kb
Host smart-491b82c5-4029-4b1b-b5e5-17e184d803f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545091889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_e
rr.545091889
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.4204258554
Short name T117
Test name
Test status
Simulation time 131348261 ps
CPU time 1.35 seconds
Started Dec 27 12:29:47 PM PST 23
Finished Dec 27 12:30:41 PM PST 23
Peak memory 210540 kb
Host smart-f666b127-5673-43cd-8264-f0aedde9f891
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204258554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.4204258554
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.2507392225
Short name T42
Test name
Test status
Simulation time 822616043 ps
CPU time 12.91 seconds
Started Dec 27 01:02:33 PM PST 23
Finished Dec 27 01:02:51 PM PST 23
Peak memory 218816 kb
Host smart-bc29ab36-c8ae-4f5b-8ac6-d2fe33f5083f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507392225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.2507392225
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.2464317447
Short name T37
Test name
Test status
Simulation time 35286723843 ps
CPU time 263.21 seconds
Started Dec 27 01:03:01 PM PST 23
Finished Dec 27 01:07:37 PM PST 23
Peak memory 282748 kb
Host smart-202f861e-3623-4e3b-88b5-831a8a5465f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464317447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.2464317447
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.3454970269
Short name T85
Test name
Test status
Simulation time 813392477 ps
CPU time 8.96 seconds
Started Dec 27 01:02:24 PM PST 23
Finished Dec 27 01:02:38 PM PST 23
Peak memory 218128 kb
Host smart-3c2d8b42-2de5-4235-aaa1-b176ef9534aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454970269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.3454970269
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.4099228350
Short name T27
Test name
Test status
Simulation time 12694687 ps
CPU time 0.77 seconds
Started Dec 27 01:01:09 PM PST 23
Finished Dec 27 01:01:14 PM PST 23
Peak memory 208512 kb
Host smart-aa5fb888-e2d9-4c58-8a73-8d9e09ce0a36
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099228350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.4099228350
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.1280122844
Short name T11
Test name
Test status
Simulation time 347837795 ps
CPU time 7.25 seconds
Started Dec 27 01:02:20 PM PST 23
Finished Dec 27 01:02:32 PM PST 23
Peak memory 218160 kb
Host smart-5c79f993-e994-4e2c-83a6-1833adc64a4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280122844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
1280122844
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3746298957
Short name T156
Test name
Test status
Simulation time 127956841 ps
CPU time 1.57 seconds
Started Dec 27 12:29:52 PM PST 23
Finished Dec 27 12:30:45 PM PST 23
Peak memory 208676 kb
Host smart-65186d1e-bd44-4165-812c-73990400f6d7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746298957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.3746298957
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.3703404017
Short name T187
Test name
Test status
Simulation time 61648027 ps
CPU time 6.18 seconds
Started Dec 27 01:01:20 PM PST 23
Finished Dec 27 01:01:33 PM PST 23
Peak memory 248068 kb
Host smart-159c9911-f740-493d-8d70-c8bb48a55ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703404017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.3703404017
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.3352496010
Short name T121
Test name
Test status
Simulation time 49197191514 ps
CPU time 867.19 seconds
Started Dec 27 01:01:10 PM PST 23
Finished Dec 27 01:15:41 PM PST 23
Peak memory 406044 kb
Host smart-8fd6c1d9-bdd2-4751-bc80-873416c820a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3352496010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.3352496010
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.2611256019
Short name T39
Test name
Test status
Simulation time 177815990 ps
CPU time 25.94 seconds
Started Dec 27 01:01:16 PM PST 23
Finished Dec 27 01:01:46 PM PST 23
Peak memory 284408 kb
Host smart-dde62b32-5b0e-4e0f-b119-ed490689a91f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611256019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.2611256019
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3187812271
Short name T118
Test name
Test status
Simulation time 326156496 ps
CPU time 2.93 seconds
Started Dec 27 12:30:22 PM PST 23
Finished Dec 27 12:31:21 PM PST 23
Peak memory 217588 kb
Host smart-075ffbea-de1e-4d9c-91ab-a850dec354cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187812271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.3187812271
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.2888002238
Short name T44
Test name
Test status
Simulation time 495802007 ps
CPU time 10.83 seconds
Started Dec 27 01:02:42 PM PST 23
Finished Dec 27 01:02:59 PM PST 23
Peak memory 218236 kb
Host smart-ce9c28cd-b270-4e33-8175-2fe4a34c3424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888002238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.2888002238
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.1181649694
Short name T4
Test name
Test status
Simulation time 1801966731 ps
CPU time 5.31 seconds
Started Dec 27 01:02:04 PM PST 23
Finished Dec 27 01:02:12 PM PST 23
Peak memory 209572 kb
Host smart-f9204060-f8d8-48f5-8b90-53c1a3b55a16
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181649694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_a
ccess.1181649694
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1785927885
Short name T114
Test name
Test status
Simulation time 146386755 ps
CPU time 2.01 seconds
Started Dec 27 12:30:06 PM PST 23
Finished Dec 27 12:31:00 PM PST 23
Peak memory 221632 kb
Host smart-ea36c154-17f3-410e-b4fc-f450dd728bf6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785927885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.1785927885
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.2355782384
Short name T347
Test name
Test status
Simulation time 73053369 ps
CPU time 0.97 seconds
Started Dec 27 01:02:20 PM PST 23
Finished Dec 27 01:02:26 PM PST 23
Peak memory 209824 kb
Host smart-4845bbcb-6bc2-453b-af2c-86173bc82abd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355782384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.2355782384
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.560939138
Short name T123
Test name
Test status
Simulation time 387008506 ps
CPU time 24.5 seconds
Started Dec 27 01:02:04 PM PST 23
Finished Dec 27 01:02:31 PM PST 23
Peak memory 251176 kb
Host smart-6b852c3b-5126-4a51-bc04-d0f25f389563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560939138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.560939138
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2305438009
Short name T139
Test name
Test status
Simulation time 424501471 ps
CPU time 3.14 seconds
Started Dec 27 12:30:11 PM PST 23
Finished Dec 27 12:31:07 PM PST 23
Peak memory 217616 kb
Host smart-a59c3c8c-6eb3-4b84-aab0-aa6a81ff3cc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305438009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.2305438009
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2220726562
Short name T91
Test name
Test status
Simulation time 36131768 ps
CPU time 1.72 seconds
Started Dec 27 12:30:30 PM PST 23
Finished Dec 27 12:31:28 PM PST 23
Peak memory 217776 kb
Host smart-bcb590ae-d7dd-4a12-a475-39c1c952417a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222072
6562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2220726562
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2351628039
Short name T160
Test name
Test status
Simulation time 70938371 ps
CPU time 1.48 seconds
Started Dec 27 12:31:35 PM PST 23
Finished Dec 27 12:32:28 PM PST 23
Peak memory 210572 kb
Host smart-43879a4e-d523-4274-8ec0-61f8e0d98c5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351628039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.2351628039
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.2943157329
Short name T50
Test name
Test status
Simulation time 83357522565 ps
CPU time 526.39 seconds
Started Dec 27 01:02:04 PM PST 23
Finished Dec 27 01:10:53 PM PST 23
Peak memory 283044 kb
Host smart-2b4e754c-8fbe-416d-9fb1-38af451d8dd7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2943157329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.2943157329
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.521688632
Short name T105
Test name
Test status
Simulation time 128119539 ps
CPU time 4.26 seconds
Started Dec 27 12:29:46 PM PST 23
Finished Dec 27 12:30:42 PM PST 23
Peak memory 221376 kb
Host smart-8c809301-e5c9-49a0-9e13-7f0d350415e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521688632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_e
rr.521688632
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.1540586453
Short name T9
Test name
Test status
Simulation time 216791707 ps
CPU time 7.78 seconds
Started Dec 27 01:02:02 PM PST 23
Finished Dec 27 01:02:11 PM PST 23
Peak memory 218176 kb
Host smart-f1c67c3f-1329-4418-96a7-362e137daabe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540586453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.1540586453
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1793886173
Short name T30
Test name
Test status
Simulation time 41968465 ps
CPU time 0.92 seconds
Started Dec 27 01:02:06 PM PST 23
Finished Dec 27 01:02:10 PM PST 23
Peak memory 208416 kb
Host smart-fae55838-1d05-42de-bc0b-fbc6f960d770
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793886173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.1793886173
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3911969131
Short name T137
Test name
Test status
Simulation time 129643712 ps
CPU time 4.09 seconds
Started Dec 27 12:29:56 PM PST 23
Finished Dec 27 12:30:52 PM PST 23
Peak memory 217620 kb
Host smart-ed8fc46c-ed98-459b-b601-0fd2bb88dcbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911969131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.3911969131
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1603043836
Short name T384
Test name
Test status
Simulation time 2943052968 ps
CPU time 20.32 seconds
Started Dec 27 01:01:00 PM PST 23
Finished Dec 27 01:01:24 PM PST 23
Peak memory 251132 kb
Host smart-ee627e61-b1d7-49ef-8b88-610b887b587d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603043836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1603043836
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3291986927
Short name T111
Test name
Test status
Simulation time 50008284 ps
CPU time 0.86 seconds
Started Dec 27 12:30:15 PM PST 23
Finished Dec 27 12:31:10 PM PST 23
Peak memory 209516 kb
Host smart-a17350f2-f1f8-4bea-a91f-0e1c4333fac1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291986927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.3291986927
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.824707246
Short name T143
Test name
Test status
Simulation time 940344682 ps
CPU time 2.91 seconds
Started Dec 27 12:30:33 PM PST 23
Finished Dec 27 12:31:33 PM PST 23
Peak memory 222104 kb
Host smart-22c6da38-c315-4503-ae14-b67470625d8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824707246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg_
err.824707246
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.331661200
Short name T442
Test name
Test status
Simulation time 38186953 ps
CPU time 0.77 seconds
Started Dec 27 01:01:47 PM PST 23
Finished Dec 27 01:01:49 PM PST 23
Peak memory 207916 kb
Host smart-efc6a480-1c31-4d3b-8ee0-14ac1dd76ecb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331661200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct
rl_volatile_unlock_smoke.331661200
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.4182148249
Short name T133
Test name
Test status
Simulation time 79467820 ps
CPU time 2.55 seconds
Started Dec 27 12:29:57 PM PST 23
Finished Dec 27 12:30:52 PM PST 23
Peak memory 221656 kb
Host smart-53a2d917-264b-43a1-a5a0-08db8d56cc76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182148249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.4182148249
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.112021469
Short name T136
Test name
Test status
Simulation time 164279529 ps
CPU time 3.63 seconds
Started Dec 27 12:30:12 PM PST 23
Finished Dec 27 12:31:08 PM PST 23
Peak memory 217708 kb
Host smart-bdbb34e0-1248-489b-8e76-282d1b5df96a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112021469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg_
err.112021469
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.3042123624
Short name T180
Test name
Test status
Simulation time 36491092 ps
CPU time 0.8 seconds
Started Dec 27 01:01:01 PM PST 23
Finished Dec 27 01:01:05 PM PST 23
Peak memory 209384 kb
Host smart-3dd49f7f-5bca-4fb1-82b6-a7587855b69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042123624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.3042123624
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.3030522667
Short name T469
Test name
Test status
Simulation time 422770295 ps
CPU time 6.56 seconds
Started Dec 27 01:01:05 PM PST 23
Finished Dec 27 01:01:14 PM PST 23
Peak memory 218152 kb
Host smart-0eea34ec-9188-43f4-bb7f-2886bef5541a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030522667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3030522667
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.3927777431
Short name T179
Test name
Test status
Simulation time 17129523 ps
CPU time 0.79 seconds
Started Dec 27 01:01:12 PM PST 23
Finished Dec 27 01:01:17 PM PST 23
Peak memory 209436 kb
Host smart-0dd77274-a0e1-4a27-b3ab-fa41936e35d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927777431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3927777431
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2410333471
Short name T182
Test name
Test status
Simulation time 37486436 ps
CPU time 0.8 seconds
Started Dec 27 01:01:07 PM PST 23
Finished Dec 27 01:01:10 PM PST 23
Peak memory 208136 kb
Host smart-00ca1988-b698-4271-bd79-7f4377974fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410333471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2410333471
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.3659338543
Short name T181
Test name
Test status
Simulation time 21059719 ps
CPU time 0.75 seconds
Started Dec 27 01:01:24 PM PST 23
Finished Dec 27 01:01:32 PM PST 23
Peak memory 209412 kb
Host smart-7bc23551-22b0-493f-b4ea-2312f0519052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659338543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.3659338543
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1620692956
Short name T93
Test name
Test status
Simulation time 177263527 ps
CPU time 3.2 seconds
Started Dec 27 12:30:33 PM PST 23
Finished Dec 27 12:31:34 PM PST 23
Peak memory 217688 kb
Host smart-d9a00014-0b1d-487e-b162-482994250911
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620692956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.1620692956
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.1649126852
Short name T348
Test name
Test status
Simulation time 1613099006 ps
CPU time 45.07 seconds
Started Dec 27 01:02:20 PM PST 23
Finished Dec 27 01:03:10 PM PST 23
Peak memory 267404 kb
Host smart-7cd9856e-122f-4203-83ec-450fb545fadf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649126852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.1649126852
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2894485740
Short name T145
Test name
Test status
Simulation time 78350718 ps
CPU time 3.32 seconds
Started Dec 27 12:30:23 PM PST 23
Finished Dec 27 12:31:24 PM PST 23
Peak memory 217648 kb
Host smart-ce2feede-5df4-4399-bd6f-60288d9c14c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894485740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.2894485740
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3272839814
Short name T134
Test name
Test status
Simulation time 397731799 ps
CPU time 4.11 seconds
Started Dec 27 12:29:57 PM PST 23
Finished Dec 27 12:30:53 PM PST 23
Peak memory 213268 kb
Host smart-90ee321e-5298-4731-b831-e09694809445
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272839814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.3272839814
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.2939308827
Short name T51
Test name
Test status
Simulation time 732828589 ps
CPU time 13.84 seconds
Started Dec 27 01:02:04 PM PST 23
Finished Dec 27 01:02:20 PM PST 23
Peak memory 218208 kb
Host smart-806f6e47-d4c2-40a0-91f2-2d8e93259884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939308827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.2939308827
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1279135176
Short name T127
Test name
Test status
Simulation time 3543546277 ps
CPU time 8.22 seconds
Started Dec 27 12:31:11 PM PST 23
Finished Dec 27 12:32:08 PM PST 23
Peak memory 208120 kb
Host smart-9bb850c2-4bc0-4b05-bf14-5178c76235aa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279135176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.1279135176
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1123563615
Short name T108
Test name
Test status
Simulation time 339586752 ps
CPU time 2.54 seconds
Started Dec 27 12:29:46 PM PST 23
Finished Dec 27 12:30:41 PM PST 23
Peak memory 217608 kb
Host smart-9a3cad1b-c397-4610-be14-26ed6f622614
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123563615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.1123563615
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3813122002
Short name T128
Test name
Test status
Simulation time 420101809 ps
CPU time 2.86 seconds
Started Dec 27 12:30:12 PM PST 23
Finished Dec 27 12:31:08 PM PST 23
Peak memory 217612 kb
Host smart-671c43c2-5cbd-4e6d-8e48-3c94f357ad26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813122002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.3813122002
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2675403810
Short name T161
Test name
Test status
Simulation time 100564602 ps
CPU time 1.1 seconds
Started Dec 27 12:31:52 PM PST 23
Finished Dec 27 12:32:39 PM PST 23
Peak memory 209044 kb
Host smart-b6dc1b02-da7f-4759-8430-0759aa3cbb44
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675403810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.2675403810
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3326603126
Short name T203
Test name
Test status
Simulation time 19598462 ps
CPU time 1.22 seconds
Started Dec 27 12:31:55 PM PST 23
Finished Dec 27 12:32:42 PM PST 23
Peak memory 209088 kb
Host smart-4a77a8ec-6d66-4457-b51d-6ca6c5ec0a91
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326603126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.3326603126
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1546619672
Short name T166
Test name
Test status
Simulation time 44305493 ps
CPU time 0.84 seconds
Started Dec 27 12:30:42 PM PST 23
Finished Dec 27 12:31:40 PM PST 23
Peak memory 209580 kb
Host smart-2e52f1d3-0b4d-48b0-b87f-a5ce24d7f14d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546619672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.1546619672
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1764188546
Short name T200
Test name
Test status
Simulation time 16876477 ps
CPU time 1.34 seconds
Started Dec 27 12:29:46 PM PST 23
Finished Dec 27 12:30:39 PM PST 23
Peak memory 219508 kb
Host smart-c48c609d-ff7e-4957-949c-92359d086275
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764188546 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.1764188546
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3945576070
Short name T162
Test name
Test status
Simulation time 13485432 ps
CPU time 0.95 seconds
Started Dec 27 12:29:48 PM PST 23
Finished Dec 27 12:30:40 PM PST 23
Peak memory 209384 kb
Host smart-34b74709-7e13-49b9-8f5d-44af0bdb6433
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945576070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3945576070
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2204043547
Short name T219
Test name
Test status
Simulation time 180342954 ps
CPU time 1.63 seconds
Started Dec 27 12:29:36 PM PST 23
Finished Dec 27 12:30:32 PM PST 23
Peak memory 209380 kb
Host smart-60902ef1-239c-4e89-912f-02ff472e8f06
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204043547 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.2204043547
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1332412773
Short name T982
Test name
Test status
Simulation time 991168629 ps
CPU time 20.94 seconds
Started Dec 27 12:30:22 PM PST 23
Finished Dec 27 12:31:40 PM PST 23
Peak memory 209368 kb
Host smart-b6a4c8ba-87e0-4ef0-a481-3a8a7644be47
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332412773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.1332412773
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3156857934
Short name T197
Test name
Test status
Simulation time 5402999289 ps
CPU time 15.02 seconds
Started Dec 27 12:29:21 PM PST 23
Finished Dec 27 12:30:32 PM PST 23
Peak memory 209404 kb
Host smart-0d7d50a1-fe53-469b-af5c-cd5a1e3e96fe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156857934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.3156857934
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.831923482
Short name T295
Test name
Test status
Simulation time 863212846 ps
CPU time 4.86 seconds
Started Dec 27 12:29:38 PM PST 23
Finished Dec 27 12:30:37 PM PST 23
Peak memory 210860 kb
Host smart-9340f3a0-a189-40d1-b9aa-d50d60b6ef1e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831923482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.831923482
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2518200739
Short name T107
Test name
Test status
Simulation time 139752247 ps
CPU time 1.62 seconds
Started Dec 27 12:30:27 PM PST 23
Finished Dec 27 12:31:29 PM PST 23
Peak memory 219772 kb
Host smart-e1e15791-f55c-43b1-b366-164b6e55860d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251820
0739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2518200739
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1276756757
Short name T253
Test name
Test status
Simulation time 119098618 ps
CPU time 2.03 seconds
Started Dec 27 12:29:43 PM PST 23
Finished Dec 27 12:30:38 PM PST 23
Peak memory 209472 kb
Host smart-3374acd0-1b64-4e41-b474-f6f4074fa11b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276756757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.1276756757
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.497372896
Short name T222
Test name
Test status
Simulation time 45515800 ps
CPU time 1.88 seconds
Started Dec 27 12:30:35 PM PST 23
Finished Dec 27 12:31:34 PM PST 23
Peak memory 211488 kb
Host smart-d19b8dad-3f14-47ee-aa54-f3dafebb248b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497372896 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.497372896
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1876288684
Short name T211
Test name
Test status
Simulation time 43048481 ps
CPU time 1.04 seconds
Started Dec 27 12:30:02 PM PST 23
Finished Dec 27 12:30:55 PM PST 23
Peak memory 209576 kb
Host smart-998153ce-1523-4815-9395-3ab52665e5a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876288684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.1876288684
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3224208808
Short name T131
Test name
Test status
Simulation time 128444758 ps
CPU time 3.41 seconds
Started Dec 27 12:30:15 PM PST 23
Finished Dec 27 12:31:12 PM PST 23
Peak memory 217596 kb
Host smart-0d0eecaa-701e-42cd-b2a6-4268faff65fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224208808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.3224208808
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1983046342
Short name T238
Test name
Test status
Simulation time 54615255 ps
CPU time 1.94 seconds
Started Dec 27 12:29:49 PM PST 23
Finished Dec 27 12:30:42 PM PST 23
Peak memory 209476 kb
Host smart-6298ff2b-fbcd-4a5f-bb30-d37ea0e53510
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983046342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.1983046342
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.343492456
Short name T296
Test name
Test status
Simulation time 66543023 ps
CPU time 0.99 seconds
Started Dec 27 12:29:59 PM PST 23
Finished Dec 27 12:30:53 PM PST 23
Peak memory 209736 kb
Host smart-b5c0bb0f-73ad-4c1a-ab03-7f17aa84cd5d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343492456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_reset
.343492456
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2228445181
Short name T213
Test name
Test status
Simulation time 202090844 ps
CPU time 1.24 seconds
Started Dec 27 12:29:46 PM PST 23
Finished Dec 27 12:30:39 PM PST 23
Peak memory 218824 kb
Host smart-07137c5d-d0c3-41d8-a239-55f32ff5fc25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228445181 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2228445181
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.613930119
Short name T278
Test name
Test status
Simulation time 22694219 ps
CPU time 0.91 seconds
Started Dec 27 12:31:42 PM PST 23
Finished Dec 27 12:32:32 PM PST 23
Peak memory 209116 kb
Host smart-c1d87696-e607-443b-8a26-7fc5d79c477a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613930119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.613930119
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1083518614
Short name T148
Test name
Test status
Simulation time 444121416 ps
CPU time 1.18 seconds
Started Dec 27 12:29:54 PM PST 23
Finished Dec 27 12:30:48 PM PST 23
Peak memory 209312 kb
Host smart-06a06ceb-8279-4576-8ba8-6c85245bab4f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083518614 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1083518614
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2242250377
Short name T155
Test name
Test status
Simulation time 913467219 ps
CPU time 4.19 seconds
Started Dec 27 12:29:43 PM PST 23
Finished Dec 27 12:30:40 PM PST 23
Peak memory 209396 kb
Host smart-0c40a409-9424-4c09-92c6-c5bc6b085fee
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242250377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.2242250377
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3127974268
Short name T251
Test name
Test status
Simulation time 345516158 ps
CPU time 3.91 seconds
Started Dec 27 12:29:44 PM PST 23
Finished Dec 27 12:30:41 PM PST 23
Peak memory 208404 kb
Host smart-47ddf105-0cef-4472-9836-251a4a344284
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127974268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.3127974268
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2532048260
Short name T276
Test name
Test status
Simulation time 112747054 ps
CPU time 1.23 seconds
Started Dec 27 12:32:06 PM PST 23
Finished Dec 27 12:32:51 PM PST 23
Peak memory 210240 kb
Host smart-ec72336f-1987-430e-bb18-71a367827499
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532048260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.2532048260
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3349076187
Short name T267
Test name
Test status
Simulation time 415795519 ps
CPU time 1.23 seconds
Started Dec 27 12:29:39 PM PST 23
Finished Dec 27 12:30:35 PM PST 23
Peak memory 217604 kb
Host smart-2e4cfe20-8d9c-47dc-8dd8-273db9fe61cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334907
6187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3349076187
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.4223924340
Short name T226
Test name
Test status
Simulation time 64478789 ps
CPU time 1.31 seconds
Started Dec 27 12:29:45 PM PST 23
Finished Dec 27 12:30:39 PM PST 23
Peak memory 209344 kb
Host smart-0f297897-084f-41a9-af80-21c32dcb85fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223924340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.4223924340
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2760851597
Short name T129
Test name
Test status
Simulation time 26633445 ps
CPU time 1.05 seconds
Started Dec 27 12:31:05 PM PST 23
Finished Dec 27 12:31:56 PM PST 23
Peak memory 209524 kb
Host smart-e97328b5-621c-4f6e-9ec3-d8f5b3333e41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760851597 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.2760851597
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.434719093
Short name T177
Test name
Test status
Simulation time 194895295 ps
CPU time 1.36 seconds
Started Dec 27 12:29:34 PM PST 23
Finished Dec 27 12:30:30 PM PST 23
Peak memory 209628 kb
Host smart-7a10f8b0-fcc2-48cb-96a6-3934ab90e12b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434719093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
same_csr_outstanding.434719093
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.343487729
Short name T254
Test name
Test status
Simulation time 37415918 ps
CPU time 2.07 seconds
Started Dec 27 12:31:35 PM PST 23
Finished Dec 27 12:32:29 PM PST 23
Peak memory 217748 kb
Host smart-de026920-a3aa-4efd-a057-5ae10ed63369
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343487729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.343487729
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1245179217
Short name T204
Test name
Test status
Simulation time 20928968 ps
CPU time 1.41 seconds
Started Dec 27 12:30:08 PM PST 23
Finished Dec 27 12:31:01 PM PST 23
Peak memory 218728 kb
Host smart-8ebb92ab-e74c-475c-8b53-f2a8250555b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245179217 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.1245179217
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3201004843
Short name T115
Test name
Test status
Simulation time 32736612 ps
CPU time 0.88 seconds
Started Dec 27 12:29:49 PM PST 23
Finished Dec 27 12:30:41 PM PST 23
Peak memory 209480 kb
Host smart-3e99bdc8-b8f8-4184-9cc1-783a42a1e1bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201004843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.3201004843
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3072985536
Short name T216
Test name
Test status
Simulation time 285814704 ps
CPU time 2.91 seconds
Started Dec 27 12:30:04 PM PST 23
Finished Dec 27 12:30:59 PM PST 23
Peak memory 217580 kb
Host smart-95c1a8e4-9ae2-4f2c-a707-55d2d0f634f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072985536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.3072985536
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3700635772
Short name T174
Test name
Test status
Simulation time 60038870 ps
CPU time 0.84 seconds
Started Dec 27 12:29:50 PM PST 23
Finished Dec 27 12:30:42 PM PST 23
Peak memory 208808 kb
Host smart-51cc629f-ed4b-493d-afe1-e116202ad966
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700635772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3700635772
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1764473644
Short name T272
Test name
Test status
Simulation time 59087508 ps
CPU time 1.15 seconds
Started Dec 27 12:30:08 PM PST 23
Finished Dec 27 12:31:01 PM PST 23
Peak memory 209012 kb
Host smart-6760b18e-94b2-410d-b5e5-f6247512d87f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764473644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1764473644
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.771219348
Short name T208
Test name
Test status
Simulation time 152136493 ps
CPU time 3.37 seconds
Started Dec 27 12:31:50 PM PST 23
Finished Dec 27 12:32:40 PM PST 23
Peak memory 217384 kb
Host smart-c6b67113-a89a-4ddf-aadd-7ef514517360
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771219348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.771219348
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1886798476
Short name T146
Test name
Test status
Simulation time 45913549 ps
CPU time 1.91 seconds
Started Dec 27 12:32:12 PM PST 23
Finished Dec 27 12:32:58 PM PST 23
Peak memory 221188 kb
Host smart-7738a9c3-6446-4165-a78f-24f681097724
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886798476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.1886798476
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1533167904
Short name T209
Test name
Test status
Simulation time 91691441 ps
CPU time 1.03 seconds
Started Dec 27 12:29:51 PM PST 23
Finished Dec 27 12:30:43 PM PST 23
Peak memory 217872 kb
Host smart-9523a4ae-a823-4639-aa01-7324e361468c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533167904 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.1533167904
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2360436105
Short name T170
Test name
Test status
Simulation time 11280737 ps
CPU time 0.86 seconds
Started Dec 27 12:29:53 PM PST 23
Finished Dec 27 12:30:45 PM PST 23
Peak memory 208828 kb
Host smart-751a8e35-bfc7-42b2-ae39-e54c97c0d837
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360436105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.2360436105
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.753832291
Short name T96
Test name
Test status
Simulation time 17875593 ps
CPU time 1.08 seconds
Started Dec 27 12:29:48 PM PST 23
Finished Dec 27 12:30:41 PM PST 23
Peak memory 208956 kb
Host smart-fbad1b0d-1516-4028-a666-2981396d848d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753832291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_same_csr_outstanding.753832291
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.729964409
Short name T265
Test name
Test status
Simulation time 356579543 ps
CPU time 2.24 seconds
Started Dec 27 12:30:34 PM PST 23
Finished Dec 27 12:31:34 PM PST 23
Peak memory 217508 kb
Host smart-f7cc8e5a-fa1d-4e5b-a816-f3a091ea2a1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729964409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.729964409
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3460830161
Short name T225
Test name
Test status
Simulation time 20356310 ps
CPU time 1.41 seconds
Started Dec 27 12:29:45 PM PST 23
Finished Dec 27 12:30:39 PM PST 23
Peak memory 217672 kb
Host smart-2d289d20-b86d-4e72-9961-7d37bcf19d64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460830161 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.3460830161
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2974280283
Short name T277
Test name
Test status
Simulation time 14388664 ps
CPU time 0.82 seconds
Started Dec 27 12:30:13 PM PST 23
Finished Dec 27 12:31:06 PM PST 23
Peak memory 209412 kb
Host smart-9b4a00b2-7d70-4439-a163-14bf40cf0262
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974280283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.2974280283
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.4127962392
Short name T268
Test name
Test status
Simulation time 47641545 ps
CPU time 1.53 seconds
Started Dec 27 12:30:17 PM PST 23
Finished Dec 27 12:31:13 PM PST 23
Peak memory 211124 kb
Host smart-4aa3d77b-3f43-4abe-9ded-91030f773f16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127962392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.4127962392
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2743944659
Short name T248
Test name
Test status
Simulation time 119350818 ps
CPU time 4.43 seconds
Started Dec 27 12:30:13 PM PST 23
Finished Dec 27 12:31:11 PM PST 23
Peak memory 217536 kb
Host smart-64dda673-bd50-48a5-91c7-74550ae310a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743944659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.2743944659
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3811681597
Short name T116
Test name
Test status
Simulation time 14326389 ps
CPU time 1.07 seconds
Started Dec 27 12:29:48 PM PST 23
Finished Dec 27 12:30:41 PM PST 23
Peak memory 209576 kb
Host smart-31e0e258-18e7-4776-8cf6-521bea2ce55d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811681597 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.3811681597
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3652989726
Short name T175
Test name
Test status
Simulation time 25119447 ps
CPU time 0.78 seconds
Started Dec 27 12:32:27 PM PST 23
Finished Dec 27 12:33:08 PM PST 23
Peak memory 208104 kb
Host smart-b5b2d5fe-6425-4285-9c61-009b5b35901e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652989726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.3652989726
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.641571978
Short name T285
Test name
Test status
Simulation time 37289344 ps
CPU time 1.26 seconds
Started Dec 27 12:30:32 PM PST 23
Finished Dec 27 12:31:30 PM PST 23
Peak memory 208920 kb
Host smart-890c0c51-a8b4-4add-bcff-ce201f7d232f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641571978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_same_csr_outstanding.641571978
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.804988049
Short name T289
Test name
Test status
Simulation time 234581120 ps
CPU time 4.26 seconds
Started Dec 27 12:29:48 PM PST 23
Finished Dec 27 12:30:45 PM PST 23
Peak memory 217632 kb
Host smart-8fc127d2-4568-4634-b59f-c526df5a7d78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804988049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.804988049
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2611893646
Short name T245
Test name
Test status
Simulation time 99253653 ps
CPU time 2.01 seconds
Started Dec 27 12:30:16 PM PST 23
Finished Dec 27 12:31:12 PM PST 23
Peak memory 219508 kb
Host smart-6472c129-9cd3-4125-b013-c291ca095065
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611893646 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2611893646
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.997156768
Short name T241
Test name
Test status
Simulation time 98351335 ps
CPU time 1.4 seconds
Started Dec 27 12:30:30 PM PST 23
Finished Dec 27 12:31:28 PM PST 23
Peak memory 209428 kb
Host smart-cb9daec1-571a-419a-b7af-aa1b378f77fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997156768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_same_csr_outstanding.997156768
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1923236031
Short name T132
Test name
Test status
Simulation time 62913438 ps
CPU time 2.22 seconds
Started Dec 27 12:31:26 PM PST 23
Finished Dec 27 12:32:24 PM PST 23
Peak memory 221632 kb
Host smart-5b859735-393a-482f-8eb6-ca067242a1b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923236031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.1923236031
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3760090722
Short name T205
Test name
Test status
Simulation time 21163854 ps
CPU time 1.26 seconds
Started Dec 27 12:30:34 PM PST 23
Finished Dec 27 12:31:33 PM PST 23
Peak memory 218744 kb
Host smart-fa0fff6e-899c-43a4-b9ff-da646d947159
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760090722 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.3760090722
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2294582744
Short name T223
Test name
Test status
Simulation time 16775322 ps
CPU time 0.91 seconds
Started Dec 27 12:31:11 PM PST 23
Finished Dec 27 12:32:00 PM PST 23
Peak memory 209524 kb
Host smart-101b370d-c68f-4ba2-b56e-7bebd08e6390
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294582744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.2294582744
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1580505293
Short name T261
Test name
Test status
Simulation time 48181078 ps
CPU time 1.27 seconds
Started Dec 27 12:29:52 PM PST 23
Finished Dec 27 12:30:45 PM PST 23
Peak memory 209336 kb
Host smart-d87b716e-cb87-44b8-a1e4-425ee878bf46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580505293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.1580505293
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1217456873
Short name T246
Test name
Test status
Simulation time 230701260 ps
CPU time 3.32 seconds
Started Dec 27 12:29:51 PM PST 23
Finished Dec 27 12:30:45 PM PST 23
Peak memory 217612 kb
Host smart-922e0faa-233b-4540-936a-5553e27d4578
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217456873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.1217456873
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2069641408
Short name T229
Test name
Test status
Simulation time 141914576 ps
CPU time 1.09 seconds
Started Dec 27 12:30:29 PM PST 23
Finished Dec 27 12:31:26 PM PST 23
Peak memory 218988 kb
Host smart-0f17f914-5f59-4a1c-af13-8fc1881cfd71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069641408 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2069641408
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1267196875
Short name T172
Test name
Test status
Simulation time 13223679 ps
CPU time 0.97 seconds
Started Dec 27 12:30:02 PM PST 23
Finished Dec 27 12:30:55 PM PST 23
Peak memory 208508 kb
Host smart-f8e29c21-46c0-4ed8-8431-fe60ad1f1e6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267196875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.1267196875
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1863165718
Short name T288
Test name
Test status
Simulation time 172031960 ps
CPU time 1.8 seconds
Started Dec 27 12:29:58 PM PST 23
Finished Dec 27 12:30:52 PM PST 23
Peak memory 209408 kb
Host smart-500d8ad3-9bda-4c12-b182-1d8abd4664bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863165718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.1863165718
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3556617471
Short name T255
Test name
Test status
Simulation time 408827573 ps
CPU time 3.93 seconds
Started Dec 27 12:30:14 PM PST 23
Finished Dec 27 12:31:12 PM PST 23
Peak memory 217540 kb
Host smart-5bdd6cb8-bca8-4061-9be0-c23dcd256217
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556617471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.3556617471
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3170765226
Short name T263
Test name
Test status
Simulation time 22504869 ps
CPU time 1.59 seconds
Started Dec 27 12:31:35 PM PST 23
Finished Dec 27 12:32:28 PM PST 23
Peak memory 219628 kb
Host smart-66970898-ee5f-4f20-a979-cbdbabd0c4f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170765226 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.3170765226
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.766631013
Short name T297
Test name
Test status
Simulation time 223381300 ps
CPU time 0.98 seconds
Started Dec 27 12:31:20 PM PST 23
Finished Dec 27 12:32:11 PM PST 23
Peak memory 209464 kb
Host smart-0e68fbd3-06a9-49f7-8f8f-954affd86a33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766631013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.766631013
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.592591205
Short name T215
Test name
Test status
Simulation time 139774526 ps
CPU time 1.01 seconds
Started Dec 27 12:30:14 PM PST 23
Finished Dec 27 12:31:08 PM PST 23
Peak memory 209428 kb
Host smart-3c23483e-1986-484d-aa38-90bd8f4e862c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592591205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_same_csr_outstanding.592591205
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1118344358
Short name T95
Test name
Test status
Simulation time 871087810 ps
CPU time 2.22 seconds
Started Dec 27 12:30:18 PM PST 23
Finished Dec 27 12:31:15 PM PST 23
Peak memory 217560 kb
Host smart-badac5f2-75ea-4a69-a502-2992f9bc5ec4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118344358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.1118344358
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2216729381
Short name T270
Test name
Test status
Simulation time 28505452 ps
CPU time 1.11 seconds
Started Dec 27 12:30:50 PM PST 23
Finished Dec 27 12:31:45 PM PST 23
Peak memory 217640 kb
Host smart-5f1c864a-19e4-4c00-b1c8-022575ce3d5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216729381 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2216729381
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2417198078
Short name T167
Test name
Test status
Simulation time 14621817 ps
CPU time 0.99 seconds
Started Dec 27 12:30:31 PM PST 23
Finished Dec 27 12:31:30 PM PST 23
Peak memory 209416 kb
Host smart-5fd7bcae-7f41-4ccd-9b23-fb182d88eb38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417198078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.2417198078
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3126853844
Short name T243
Test name
Test status
Simulation time 288321338 ps
CPU time 1.12 seconds
Started Dec 27 12:30:28 PM PST 23
Finished Dec 27 12:31:26 PM PST 23
Peak memory 208508 kb
Host smart-797205b2-a2c3-4a68-8965-7f197e387a11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126853844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.3126853844
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1540245955
Short name T140
Test name
Test status
Simulation time 473336527 ps
CPU time 2.75 seconds
Started Dec 27 12:31:16 PM PST 23
Finished Dec 27 12:32:08 PM PST 23
Peak memory 221876 kb
Host smart-b78732c0-2094-43a4-9f69-afc7bddd2eb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540245955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.1540245955
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1636966244
Short name T169
Test name
Test status
Simulation time 34195541 ps
CPU time 1.59 seconds
Started Dec 27 12:29:46 PM PST 23
Finished Dec 27 12:30:40 PM PST 23
Peak memory 208248 kb
Host smart-38149c30-5a97-49e8-b0aa-924867b7c7a6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636966244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.1636966244
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1649754912
Short name T157
Test name
Test status
Simulation time 178481893 ps
CPU time 3.02 seconds
Started Dec 27 12:29:47 PM PST 23
Finished Dec 27 12:30:41 PM PST 23
Peak memory 209580 kb
Host smart-d9fdb825-18b4-49e9-8346-386dc846bb32
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649754912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.1649754912
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1765231905
Short name T247
Test name
Test status
Simulation time 268040243 ps
CPU time 0.92 seconds
Started Dec 27 12:31:59 PM PST 23
Finished Dec 27 12:32:45 PM PST 23
Peak memory 208964 kb
Host smart-34b54601-34de-4dea-8159-f3d7f1d2a2c0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765231905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.1765231905
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1488401022
Short name T228
Test name
Test status
Simulation time 113584349 ps
CPU time 1.02 seconds
Started Dec 27 12:32:15 PM PST 23
Finished Dec 27 12:33:00 PM PST 23
Peak memory 218544 kb
Host smart-c6c3ed4f-0b7a-4ac9-a84a-170d1cbaaca4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488401022 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1488401022
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1682522435
Short name T171
Test name
Test status
Simulation time 16224140 ps
CPU time 0.9 seconds
Started Dec 27 12:29:49 PM PST 23
Finished Dec 27 12:30:42 PM PST 23
Peak memory 208924 kb
Host smart-42033aa7-ff90-4b46-8b6d-b7b949ff3542
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682522435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.1682522435
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.740623806
Short name T202
Test name
Test status
Simulation time 81892191 ps
CPU time 0.81 seconds
Started Dec 27 12:31:48 PM PST 23
Finished Dec 27 12:32:37 PM PST 23
Peak memory 208972 kb
Host smart-4ecc3ab3-57de-4c6c-bb55-6938d3d205ef
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740623806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.lc_ctrl_jtag_alert_test.740623806
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.874597123
Short name T282
Test name
Test status
Simulation time 3614962500 ps
CPU time 7.14 seconds
Started Dec 27 12:31:13 PM PST 23
Finished Dec 27 12:32:10 PM PST 23
Peak memory 207416 kb
Host smart-86c7ee56-b783-412d-aa92-e903225f1170
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874597123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.874597123
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.316568299
Short name T207
Test name
Test status
Simulation time 165358010 ps
CPU time 1.12 seconds
Started Dec 27 12:29:46 PM PST 23
Finished Dec 27 12:30:39 PM PST 23
Peak memory 210484 kb
Host smart-282d3ca5-a4d6-40a0-b0c5-cfdc62ce47ce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316568299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.316568299
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3830189480
Short name T152
Test name
Test status
Simulation time 220266641 ps
CPU time 1.82 seconds
Started Dec 27 12:31:41 PM PST 23
Finished Dec 27 12:32:32 PM PST 23
Peak memory 218400 kb
Host smart-de58defc-341f-464a-b82a-435ebebc955c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383018
9480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3830189480
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2011829445
Short name T262
Test name
Test status
Simulation time 128623963 ps
CPU time 1.34 seconds
Started Dec 27 12:31:59 PM PST 23
Finished Dec 27 12:32:46 PM PST 23
Peak memory 209004 kb
Host smart-9962aeb4-464e-472f-862d-d06f9c4d81ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011829445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.2011829445
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2265683292
Short name T279
Test name
Test status
Simulation time 48062237 ps
CPU time 1.04 seconds
Started Dec 27 12:29:46 PM PST 23
Finished Dec 27 12:30:39 PM PST 23
Peak memory 209500 kb
Host smart-fb677a82-72d6-473c-b137-1be3976b115c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265683292 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.2265683292
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.680520909
Short name T242
Test name
Test status
Simulation time 156193419 ps
CPU time 1.33 seconds
Started Dec 27 12:30:40 PM PST 23
Finished Dec 27 12:31:37 PM PST 23
Peak memory 209520 kb
Host smart-6144a5d9-e741-4c2a-a66c-cfe9b6d78352
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680520909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
same_csr_outstanding.680520909
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2296660966
Short name T271
Test name
Test status
Simulation time 78121622 ps
CPU time 2.87 seconds
Started Dec 27 12:29:41 PM PST 23
Finished Dec 27 12:30:37 PM PST 23
Peak memory 217756 kb
Host smart-19f112ea-a130-4312-a199-36549e7bda64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296660966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.2296660966
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2809118974
Short name T141
Test name
Test status
Simulation time 424492218 ps
CPU time 3.64 seconds
Started Dec 27 12:29:43 PM PST 23
Finished Dec 27 12:30:39 PM PST 23
Peak memory 217648 kb
Host smart-971cad98-c1aa-44f6-a9ae-8bf32384f602
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809118974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2809118974
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1069524268
Short name T244
Test name
Test status
Simulation time 24072708 ps
CPU time 1.11 seconds
Started Dec 27 12:29:47 PM PST 23
Finished Dec 27 12:30:40 PM PST 23
Peak memory 209476 kb
Host smart-313690aa-2f60-4f17-89ee-2181e6f37e3b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069524268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.1069524268
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1199085230
Short name T158
Test name
Test status
Simulation time 245093609 ps
CPU time 2.4 seconds
Started Dec 27 12:30:21 PM PST 23
Finished Dec 27 12:31:20 PM PST 23
Peak memory 209496 kb
Host smart-edb47356-d5ea-4a6c-a459-4ccf8219c2f3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199085230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.1199085230
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2428438033
Short name T110
Test name
Test status
Simulation time 72952830 ps
CPU time 0.98 seconds
Started Dec 27 12:30:20 PM PST 23
Finished Dec 27 12:31:15 PM PST 23
Peak memory 211232 kb
Host smart-000842f8-e490-4a75-b6bf-b8dd9d1a289c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428438033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.2428438033
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.971536688
Short name T104
Test name
Test status
Simulation time 54098063 ps
CPU time 1.76 seconds
Started Dec 27 12:32:22 PM PST 23
Finished Dec 27 12:33:06 PM PST 23
Peak memory 218648 kb
Host smart-8d4ab507-36c5-4ee4-8a28-0125cf404b86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971536688 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.971536688
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3092986574
Short name T173
Test name
Test status
Simulation time 35796508 ps
CPU time 0.9 seconds
Started Dec 27 12:29:52 PM PST 23
Finished Dec 27 12:30:45 PM PST 23
Peak memory 209500 kb
Host smart-eb2bc1b3-4743-43b2-8d77-40a1e0c9b995
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092986574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.3092986574
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.605009467
Short name T90
Test name
Test status
Simulation time 120152451 ps
CPU time 1.19 seconds
Started Dec 27 12:30:08 PM PST 23
Finished Dec 27 12:31:01 PM PST 23
Peak memory 209248 kb
Host smart-5241096e-08e4-4f8c-b992-530ffddadb35
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605009467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.lc_ctrl_jtag_alert_test.605009467
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.933072043
Short name T290
Test name
Test status
Simulation time 1117099611 ps
CPU time 6.01 seconds
Started Dec 27 12:29:49 PM PST 23
Finished Dec 27 12:30:47 PM PST 23
Peak memory 209208 kb
Host smart-fb5e40aa-eca3-4973-a88e-c21d599860b9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933072043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.933072043
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.255510235
Short name T94
Test name
Test status
Simulation time 1614711889 ps
CPU time 9.71 seconds
Started Dec 27 12:29:45 PM PST 23
Finished Dec 27 12:30:47 PM PST 23
Peak memory 209340 kb
Host smart-411a50cd-3a9a-4648-b519-ad4aec416e5b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255510235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.255510235
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2875165210
Short name T154
Test name
Test status
Simulation time 518405482 ps
CPU time 1.79 seconds
Started Dec 27 12:32:27 PM PST 23
Finished Dec 27 12:33:09 PM PST 23
Peak memory 210496 kb
Host smart-cc1f0f59-f821-452c-8cb1-9fb95fd25e01
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875165210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.2875165210
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2491451452
Short name T293
Test name
Test status
Simulation time 784470201 ps
CPU time 2.92 seconds
Started Dec 27 12:29:43 PM PST 23
Finished Dec 27 12:30:39 PM PST 23
Peak memory 218472 kb
Host smart-3581e04d-d61b-414b-bd0b-56c766cb4e16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249145
1452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2491451452
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1973155788
Short name T231
Test name
Test status
Simulation time 43369320 ps
CPU time 1.58 seconds
Started Dec 27 12:29:47 PM PST 23
Finished Dec 27 12:30:41 PM PST 23
Peak memory 209244 kb
Host smart-914fcd96-1af6-46cc-8114-8aba6640c5a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973155788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.1973155788
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3587576821
Short name T232
Test name
Test status
Simulation time 34566641 ps
CPU time 1.71 seconds
Started Dec 27 12:29:59 PM PST 23
Finished Dec 27 12:30:53 PM PST 23
Peak memory 209392 kb
Host smart-0d9c9c16-fa87-49c4-8eca-1b9893cf2843
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587576821 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3587576821
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2453306524
Short name T97
Test name
Test status
Simulation time 42513079 ps
CPU time 1.26 seconds
Started Dec 27 12:30:38 PM PST 23
Finished Dec 27 12:31:36 PM PST 23
Peak memory 209392 kb
Host smart-15d039cc-929e-4e22-8f1e-40ceb4e03b80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453306524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.2453306524
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2003453903
Short name T227
Test name
Test status
Simulation time 68889009 ps
CPU time 2.64 seconds
Started Dec 27 12:30:21 PM PST 23
Finished Dec 27 12:31:20 PM PST 23
Peak memory 217572 kb
Host smart-4f7bea4f-2c2d-49ef-b8af-1bd0947e3b8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003453903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.2003453903
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.544486355
Short name T283
Test name
Test status
Simulation time 79139561 ps
CPU time 1.74 seconds
Started Dec 27 12:30:06 PM PST 23
Finished Dec 27 12:30:59 PM PST 23
Peak memory 221424 kb
Host smart-97e8ed69-dd77-4943-85e7-47cf7ff0b9e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544486355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_e
rr.544486355
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2699119471
Short name T165
Test name
Test status
Simulation time 17783832 ps
CPU time 1.14 seconds
Started Dec 27 12:29:54 PM PST 23
Finished Dec 27 12:30:47 PM PST 23
Peak memory 209396 kb
Host smart-a38b22f8-150d-46f6-b69f-b79032a0348f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699119471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.2699119471
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1991299553
Short name T194
Test name
Test status
Simulation time 82396170 ps
CPU time 1.39 seconds
Started Dec 27 12:29:47 PM PST 23
Finished Dec 27 12:30:40 PM PST 23
Peak memory 209488 kb
Host smart-eba9a714-bdfb-4b87-bf73-b806d421608e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991299553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.1991299553
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1291368943
Short name T168
Test name
Test status
Simulation time 26064844 ps
CPU time 0.99 seconds
Started Dec 27 12:29:56 PM PST 23
Finished Dec 27 12:30:49 PM PST 23
Peak memory 209680 kb
Host smart-5da4a030-8d0a-40fc-8612-a2c54ae071d5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291368943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.1291368943
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1289916234
Short name T292
Test name
Test status
Simulation time 30436137 ps
CPU time 1.9 seconds
Started Dec 27 12:29:48 PM PST 23
Finished Dec 27 12:30:42 PM PST 23
Peak memory 219312 kb
Host smart-68faf2a0-bdbd-43cf-9d0c-871f609edb1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289916234 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.1289916234
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1052156331
Short name T198
Test name
Test status
Simulation time 27506992 ps
CPU time 0.99 seconds
Started Dec 27 12:30:11 PM PST 23
Finished Dec 27 12:31:05 PM PST 23
Peak memory 209440 kb
Host smart-d597ea57-1760-482b-9181-88721af6094e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052156331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.1052156331
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3575382386
Short name T201
Test name
Test status
Simulation time 29907521 ps
CPU time 1.02 seconds
Started Dec 27 12:30:38 PM PST 23
Finished Dec 27 12:31:35 PM PST 23
Peak memory 207644 kb
Host smart-9dd5f5fc-5976-4a95-9b21-f94b60083331
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575382386 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.3575382386
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2398315038
Short name T291
Test name
Test status
Simulation time 794058760 ps
CPU time 3.45 seconds
Started Dec 27 12:29:46 PM PST 23
Finished Dec 27 12:30:42 PM PST 23
Peak memory 208340 kb
Host smart-c8845b9f-d3e8-4b1c-bf4f-0ebe24e65180
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398315038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.2398315038
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1943291734
Short name T280
Test name
Test status
Simulation time 6414234303 ps
CPU time 37.07 seconds
Started Dec 27 12:30:26 PM PST 23
Finished Dec 27 12:31:59 PM PST 23
Peak memory 209504 kb
Host smart-19d9c79f-71f9-4cdd-b323-26efe83bf4f1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943291734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.1943291734
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3472602137
Short name T273
Test name
Test status
Simulation time 61855057 ps
CPU time 1.13 seconds
Started Dec 27 12:29:45 PM PST 23
Finished Dec 27 12:30:39 PM PST 23
Peak memory 218036 kb
Host smart-6476dab7-2cf1-4b66-a8f0-b3da2867a041
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347260
2137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3472602137
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3881566173
Short name T149
Test name
Test status
Simulation time 85867477 ps
CPU time 1.39 seconds
Started Dec 27 12:29:47 PM PST 23
Finished Dec 27 12:30:40 PM PST 23
Peak memory 209368 kb
Host smart-84bc83e1-a027-4209-b48f-2c921ad9a11d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881566173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.3881566173
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1771499285
Short name T250
Test name
Test status
Simulation time 46480449 ps
CPU time 1.88 seconds
Started Dec 27 12:32:01 PM PST 23
Finished Dec 27 12:32:53 PM PST 23
Peak memory 210928 kb
Host smart-3ae25faa-2d79-4bb3-a45b-e331b250b0ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771499285 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.1771499285
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.59432761
Short name T266
Test name
Test status
Simulation time 28269092 ps
CPU time 0.97 seconds
Started Dec 27 12:30:23 PM PST 23
Finished Dec 27 12:31:22 PM PST 23
Peak memory 209548 kb
Host smart-f3c76442-affe-4fef-874a-f032c029164b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59432761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_s
ame_csr_outstanding.59432761
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1085385582
Short name T286
Test name
Test status
Simulation time 80954775 ps
CPU time 1.63 seconds
Started Dec 27 12:29:50 PM PST 23
Finished Dec 27 12:30:43 PM PST 23
Peak memory 218408 kb
Host smart-028d518e-a15a-4179-9723-c5f0a2a2cc4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085385582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1085385582
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2308825931
Short name T239
Test name
Test status
Simulation time 61830311 ps
CPU time 1.1 seconds
Started Dec 27 12:30:05 PM PST 23
Finished Dec 27 12:30:58 PM PST 23
Peak memory 217720 kb
Host smart-41468d16-843e-4a47-b5cd-d534606e0e1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308825931 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.2308825931
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3385583804
Short name T178
Test name
Test status
Simulation time 165714324 ps
CPU time 0.81 seconds
Started Dec 27 12:30:21 PM PST 23
Finished Dec 27 12:31:18 PM PST 23
Peak memory 208792 kb
Host smart-15b36448-65b5-4e62-baf0-082b15ce7376
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385583804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.3385583804
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1342008958
Short name T281
Test name
Test status
Simulation time 112123204 ps
CPU time 1.37 seconds
Started Dec 27 12:31:09 PM PST 23
Finished Dec 27 12:31:59 PM PST 23
Peak memory 209320 kb
Host smart-b0132647-a413-42c1-836b-3338504a26c3
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342008958 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1342008958
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.717041347
Short name T217
Test name
Test status
Simulation time 930144502 ps
CPU time 18.9 seconds
Started Dec 27 12:29:48 PM PST 23
Finished Dec 27 12:30:59 PM PST 23
Peak memory 208404 kb
Host smart-b230126c-ee1b-43ed-9e6d-288bb5ff9329
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717041347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.717041347
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3281139414
Short name T195
Test name
Test status
Simulation time 4425362322 ps
CPU time 11.77 seconds
Started Dec 27 12:29:51 PM PST 23
Finished Dec 27 12:30:54 PM PST 23
Peak memory 209524 kb
Host smart-0b699005-62e6-4374-a428-ffabd11e28eb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281139414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.3281139414
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1193897902
Short name T218
Test name
Test status
Simulation time 67433331 ps
CPU time 2.15 seconds
Started Dec 27 12:29:58 PM PST 23
Finished Dec 27 12:30:52 PM PST 23
Peak memory 210456 kb
Host smart-88bf91a4-4a8a-415a-b037-342482d01527
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193897902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.1193897902
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3879616348
Short name T294
Test name
Test status
Simulation time 116729426 ps
CPU time 1.09 seconds
Started Dec 27 12:29:48 PM PST 23
Finished Dec 27 12:30:41 PM PST 23
Peak memory 209396 kb
Host smart-c8be6fa9-ad9d-4db8-b9d1-0855f5dd62ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387961
6348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3879616348
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.422493722
Short name T258
Test name
Test status
Simulation time 56879620 ps
CPU time 1.81 seconds
Started Dec 27 12:29:42 PM PST 23
Finished Dec 27 12:30:37 PM PST 23
Peak memory 209288 kb
Host smart-78371b20-ee7b-462f-9000-98232c4902ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422493722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.422493722
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3568943528
Short name T235
Test name
Test status
Simulation time 48614088 ps
CPU time 1.42 seconds
Started Dec 27 12:29:58 PM PST 23
Finished Dec 27 12:30:52 PM PST 23
Peak memory 209256 kb
Host smart-efefdc1b-2485-427c-b37e-ff957c816aaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568943528 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3568943528
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3386977620
Short name T92
Test name
Test status
Simulation time 26202241 ps
CPU time 1 seconds
Started Dec 27 12:31:00 PM PST 23
Finished Dec 27 12:31:52 PM PST 23
Peak memory 208840 kb
Host smart-f2b25557-90bf-42c0-9ebf-db08384d2922
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386977620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.3386977620
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3817029561
Short name T234
Test name
Test status
Simulation time 144855690 ps
CPU time 1.79 seconds
Started Dec 27 12:31:04 PM PST 23
Finished Dec 27 12:31:56 PM PST 23
Peak memory 217568 kb
Host smart-789668a3-cbeb-4314-9d0e-9df1d700e7b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817029561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.3817029561
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3741097804
Short name T138
Test name
Test status
Simulation time 749253906 ps
CPU time 3.7 seconds
Started Dec 27 12:29:46 PM PST 23
Finished Dec 27 12:30:42 PM PST 23
Peak memory 217680 kb
Host smart-c9e3e470-1329-4141-a108-8965d481bffc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741097804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.3741097804
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3417033943
Short name T112
Test name
Test status
Simulation time 56753242 ps
CPU time 1 seconds
Started Dec 27 12:29:54 PM PST 23
Finished Dec 27 12:30:47 PM PST 23
Peak memory 219188 kb
Host smart-779b6df0-447f-47dc-b73f-1a894eef3972
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417033943 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.3417033943
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.853231566
Short name T164
Test name
Test status
Simulation time 35794085 ps
CPU time 0.83 seconds
Started Dec 27 12:31:49 PM PST 23
Finished Dec 27 12:32:37 PM PST 23
Peak memory 209036 kb
Host smart-1ef24d35-2b24-4f7a-ad64-2c8c25ee922a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853231566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.853231566
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2318335577
Short name T233
Test name
Test status
Simulation time 316469602 ps
CPU time 1.34 seconds
Started Dec 27 12:29:51 PM PST 23
Finished Dec 27 12:30:44 PM PST 23
Peak memory 209296 kb
Host smart-4a2c9acb-0bf8-4a7c-bfec-b08dec762bee
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318335577 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.2318335577
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1854390971
Short name T230
Test name
Test status
Simulation time 1493879433 ps
CPU time 11.3 seconds
Started Dec 27 12:30:03 PM PST 23
Finished Dec 27 12:31:06 PM PST 23
Peak memory 208448 kb
Host smart-4c7d6d46-48dd-4daf-91af-5485d9dfa076
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854390971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.1854390971
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1409855872
Short name T257
Test name
Test status
Simulation time 678724528 ps
CPU time 11.04 seconds
Started Dec 27 12:29:50 PM PST 23
Finished Dec 27 12:30:53 PM PST 23
Peak memory 208484 kb
Host smart-6dbde08d-65b5-407d-9536-4dbceaa44d83
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409855872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1409855872
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2489908911
Short name T153
Test name
Test status
Simulation time 179909161 ps
CPU time 1.16 seconds
Started Dec 27 12:29:48 PM PST 23
Finished Dec 27 12:30:41 PM PST 23
Peak memory 210632 kb
Host smart-772bdc3e-46c1-4468-bf0d-ef2ea6c3cfd7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489908911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.2489908911
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1091590535
Short name T240
Test name
Test status
Simulation time 49116497 ps
CPU time 1.89 seconds
Started Dec 27 12:30:05 PM PST 23
Finished Dec 27 12:30:59 PM PST 23
Peak memory 218116 kb
Host smart-d30ea3f8-1686-4350-840e-d86b3141c155
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109159
0535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1091590535
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2499975360
Short name T252
Test name
Test status
Simulation time 228467604 ps
CPU time 1.94 seconds
Started Dec 27 12:29:44 PM PST 23
Finished Dec 27 12:30:39 PM PST 23
Peak memory 209340 kb
Host smart-2cf32ae7-bd0e-4f6c-a02d-485712da0ee7
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499975360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.2499975360
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1439859480
Short name T163
Test name
Test status
Simulation time 57575912 ps
CPU time 0.95 seconds
Started Dec 27 12:30:11 PM PST 23
Finished Dec 27 12:31:12 PM PST 23
Peak memory 209436 kb
Host smart-d0d08175-4e30-430a-a030-77556f828a93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439859480 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.1439859480
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2712840248
Short name T159
Test name
Test status
Simulation time 29552780 ps
CPU time 0.95 seconds
Started Dec 27 12:30:04 PM PST 23
Finished Dec 27 12:30:56 PM PST 23
Peak memory 209472 kb
Host smart-1b39e5e8-2ba9-4acd-9899-ef7809d1ee5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712840248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.2712840248
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3874144102
Short name T126
Test name
Test status
Simulation time 110190397 ps
CPU time 1.84 seconds
Started Dec 27 12:30:17 PM PST 23
Finished Dec 27 12:31:14 PM PST 23
Peak memory 218664 kb
Host smart-cdab72ef-a40c-4f75-9333-655f4e37c5ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874144102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.3874144102
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.412335910
Short name T269
Test name
Test status
Simulation time 73285123 ps
CPU time 1.62 seconds
Started Dec 27 12:30:16 PM PST 23
Finished Dec 27 12:31:11 PM PST 23
Peak memory 223000 kb
Host smart-9ccb966f-924c-4273-b5b4-d5b3af29326b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412335910 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.412335910
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3985622672
Short name T196
Test name
Test status
Simulation time 17975515 ps
CPU time 0.86 seconds
Started Dec 27 12:30:28 PM PST 23
Finished Dec 27 12:31:26 PM PST 23
Peak memory 209444 kb
Host smart-3e3c1ee5-246a-4e1e-86ad-2c48708a512e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985622672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.3985622672
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2104790653
Short name T147
Test name
Test status
Simulation time 240852819 ps
CPU time 1.51 seconds
Started Dec 27 12:29:49 PM PST 23
Finished Dec 27 12:30:42 PM PST 23
Peak memory 209312 kb
Host smart-493c85f2-697a-4625-9789-0298d4a0ac6e
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104790653 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2104790653
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.551249350
Short name T220
Test name
Test status
Simulation time 1323720525 ps
CPU time 8.08 seconds
Started Dec 27 12:30:26 PM PST 23
Finished Dec 27 12:31:30 PM PST 23
Peak memory 208332 kb
Host smart-223ff19d-a916-40cb-81f9-0f0f78e1b08f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551249350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.551249350
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.179893191
Short name T206
Test name
Test status
Simulation time 2850175432 ps
CPU time 6.22 seconds
Started Dec 27 12:29:45 PM PST 23
Finished Dec 27 12:30:44 PM PST 23
Peak memory 208416 kb
Host smart-671ecce0-672f-41b0-b841-8cff3460797b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179893191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.179893191
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.4142241424
Short name T130
Test name
Test status
Simulation time 283617531 ps
CPU time 1.36 seconds
Started Dec 27 12:30:10 PM PST 23
Finished Dec 27 12:31:04 PM PST 23
Peak memory 210608 kb
Host smart-c46a49df-5809-4362-9066-4cb34179e1e8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142241424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.4142241424
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2318557625
Short name T237
Test name
Test status
Simulation time 200868157 ps
CPU time 1.53 seconds
Started Dec 27 12:29:43 PM PST 23
Finished Dec 27 12:30:38 PM PST 23
Peak memory 217840 kb
Host smart-7aa2a0c9-e1ba-43b9-bf60-73c19f85512e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231855
7625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2318557625
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1321430616
Short name T259
Test name
Test status
Simulation time 143906696 ps
CPU time 1.38 seconds
Started Dec 27 12:30:19 PM PST 23
Finished Dec 27 12:31:15 PM PST 23
Peak memory 209336 kb
Host smart-1e064f45-dce7-41d0-b6eb-70d964240960
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321430616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.1321430616
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1265477362
Short name T224
Test name
Test status
Simulation time 19419242 ps
CPU time 1.11 seconds
Started Dec 27 12:30:16 PM PST 23
Finished Dec 27 12:31:11 PM PST 23
Peak memory 209460 kb
Host smart-831cd493-d3cd-435b-8737-5bfc92453367
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265477362 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1265477362
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.4221746354
Short name T274
Test name
Test status
Simulation time 21924665 ps
CPU time 0.95 seconds
Started Dec 27 12:29:47 PM PST 23
Finished Dec 27 12:30:40 PM PST 23
Peak memory 209444 kb
Host smart-3e83257a-1126-4ddc-87a5-54e45fd0321f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221746354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.4221746354
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3726952438
Short name T249
Test name
Test status
Simulation time 32142248 ps
CPU time 2.16 seconds
Started Dec 27 12:30:30 PM PST 23
Finished Dec 27 12:31:29 PM PST 23
Peak memory 217680 kb
Host smart-d91821ca-1be4-4ab9-867f-05b921b9a184
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726952438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3726952438
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1906225507
Short name T214
Test name
Test status
Simulation time 48026619 ps
CPU time 1.07 seconds
Started Dec 27 12:30:12 PM PST 23
Finished Dec 27 12:31:07 PM PST 23
Peak memory 217556 kb
Host smart-d1ca8516-8d01-43cc-b68e-6930695f850e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906225507 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.1906225507
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3415660453
Short name T983
Test name
Test status
Simulation time 14146026 ps
CPU time 0.95 seconds
Started Dec 27 12:32:02 PM PST 23
Finished Dec 27 12:32:48 PM PST 23
Peak memory 209140 kb
Host smart-2fd8045b-219b-4b17-ada4-e2b6258be9bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415660453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3415660453
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1136378121
Short name T264
Test name
Test status
Simulation time 497805813 ps
CPU time 8.42 seconds
Started Dec 27 12:29:47 PM PST 23
Finished Dec 27 12:30:48 PM PST 23
Peak memory 209432 kb
Host smart-85a5dbc6-527e-4246-8335-dd5340fce0c2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136378121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.1136378121
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3936251143
Short name T210
Test name
Test status
Simulation time 1073293984 ps
CPU time 22.69 seconds
Started Dec 27 12:32:29 PM PST 23
Finished Dec 27 12:33:31 PM PST 23
Peak memory 208216 kb
Host smart-4d6e7aea-0705-4890-8925-72c2b9bfe817
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936251143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3936251143
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.4099075335
Short name T287
Test name
Test status
Simulation time 200515425 ps
CPU time 1.71 seconds
Started Dec 27 12:30:11 PM PST 23
Finished Dec 27 12:31:05 PM PST 23
Peak memory 210700 kb
Host smart-37bd9875-0f94-47b9-ad36-425d14a5d91e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099075335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.4099075335
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2692906343
Short name T212
Test name
Test status
Simulation time 35978663 ps
CPU time 0.97 seconds
Started Dec 27 12:29:51 PM PST 23
Finished Dec 27 12:30:43 PM PST 23
Peak memory 209312 kb
Host smart-2b4d7d6b-5755-4770-8904-63ee67f71a5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692906343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.2692906343
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1776769332
Short name T298
Test name
Test status
Simulation time 187907305 ps
CPU time 1.32 seconds
Started Dec 27 12:30:16 PM PST 23
Finished Dec 27 12:31:11 PM PST 23
Peak memory 210956 kb
Host smart-83271e5a-8d5f-4e3a-8e91-bed91d483bbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776769332 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.1776769332
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2254690543
Short name T256
Test name
Test status
Simulation time 80534419 ps
CPU time 0.97 seconds
Started Dec 27 12:30:29 PM PST 23
Finished Dec 27 12:31:27 PM PST 23
Peak memory 208932 kb
Host smart-578da0de-94e8-4806-8d47-58250562f12f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254690543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.2254690543
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.650183822
Short name T236
Test name
Test status
Simulation time 735727957 ps
CPU time 4.98 seconds
Started Dec 27 12:30:17 PM PST 23
Finished Dec 27 12:31:17 PM PST 23
Peak memory 217672 kb
Host smart-27149f02-b10e-4bfd-aa06-2f6856491271
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650183822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.650183822
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3825152042
Short name T144
Test name
Test status
Simulation time 366113581 ps
CPU time 2.14 seconds
Started Dec 27 12:30:31 PM PST 23
Finished Dec 27 12:31:30 PM PST 23
Peak memory 221796 kb
Host smart-14bce1cc-e28d-48f7-b28f-dde13bfb9e27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825152042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.3825152042
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3823218437
Short name T275
Test name
Test status
Simulation time 13055393 ps
CPU time 0.91 seconds
Started Dec 27 12:29:46 PM PST 23
Finished Dec 27 12:30:39 PM PST 23
Peak memory 208308 kb
Host smart-58366321-8f71-41d3-99af-fb7c81f9076f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823218437 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.3823218437
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2354014755
Short name T176
Test name
Test status
Simulation time 14086596 ps
CPU time 1.06 seconds
Started Dec 27 12:30:42 PM PST 23
Finished Dec 27 12:31:40 PM PST 23
Peak memory 209408 kb
Host smart-8aad5fc4-c23c-492c-95b5-f5692fc09d8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354014755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.2354014755
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3403083739
Short name T150
Test name
Test status
Simulation time 1125441014 ps
CPU time 2.27 seconds
Started Dec 27 12:32:01 PM PST 23
Finished Dec 27 12:32:49 PM PST 23
Peak memory 208980 kb
Host smart-94aff380-06fd-4d41-8970-434d2a9b02e0
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403083739 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.3403083739
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2733496554
Short name T151
Test name
Test status
Simulation time 2544842181 ps
CPU time 4.87 seconds
Started Dec 27 12:30:19 PM PST 23
Finished Dec 27 12:31:18 PM PST 23
Peak memory 209480 kb
Host smart-e3f99cab-9298-4b89-80a2-f2117eb5f3f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733496554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2733496554
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2462693602
Short name T260
Test name
Test status
Simulation time 2884481809 ps
CPU time 6.54 seconds
Started Dec 27 12:29:49 PM PST 23
Finished Dec 27 12:30:47 PM PST 23
Peak memory 209384 kb
Host smart-02f23e2d-9556-49ed-8a9f-d34bb3559811
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462693602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.2462693602
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2320865488
Short name T109
Test name
Test status
Simulation time 219588949 ps
CPU time 1.16 seconds
Started Dec 27 12:32:47 PM PST 23
Finished Dec 27 12:33:24 PM PST 23
Peak memory 210108 kb
Host smart-41c8dc82-6e43-4c82-86ac-62c32404c408
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320865488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.2320865488
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1309067078
Short name T199
Test name
Test status
Simulation time 148194578 ps
CPU time 1.77 seconds
Started Dec 27 12:29:51 PM PST 23
Finished Dec 27 12:30:44 PM PST 23
Peak memory 218620 kb
Host smart-c3ce9252-4dd3-40b6-ac6d-52ee15fd513d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130906
7078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1309067078
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2715341719
Short name T284
Test name
Test status
Simulation time 337516717 ps
CPU time 1.3 seconds
Started Dec 27 12:29:48 PM PST 23
Finished Dec 27 12:30:42 PM PST 23
Peak memory 209256 kb
Host smart-b47c3df2-43d7-4ba5-aeba-a73b3ee593af
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715341719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.2715341719
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.127848788
Short name T221
Test name
Test status
Simulation time 337811383 ps
CPU time 1.25 seconds
Started Dec 27 12:29:47 PM PST 23
Finished Dec 27 12:30:41 PM PST 23
Peak memory 209400 kb
Host smart-74989353-659e-4887-8c51-4b1a9a6649ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127848788 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.127848788
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.800978873
Short name T113
Test name
Test status
Simulation time 160269654 ps
CPU time 1.7 seconds
Started Dec 27 12:29:52 PM PST 23
Finished Dec 27 12:30:45 PM PST 23
Peak memory 211232 kb
Host smart-dcabbad6-8b3e-49d6-9ced-b3da89840e4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800978873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
same_csr_outstanding.800978873
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1156666481
Short name T135
Test name
Test status
Simulation time 24112207 ps
CPU time 1.73 seconds
Started Dec 27 12:30:11 PM PST 23
Finished Dec 27 12:31:06 PM PST 23
Peak memory 217552 kb
Host smart-8620b329-7a56-45df-80c1-c603123a523e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156666481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.1156666481
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1916347786
Short name T142
Test name
Test status
Simulation time 223557114 ps
CPU time 1.78 seconds
Started Dec 27 12:29:50 PM PST 23
Finished Dec 27 12:30:43 PM PST 23
Peak memory 221452 kb
Host smart-6a8023a1-adc4-4873-be9a-256f1caa4d30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916347786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.1916347786
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.3810711765
Short name T548
Test name
Test status
Simulation time 18158167 ps
CPU time 0.94 seconds
Started Dec 27 01:01:11 PM PST 23
Finished Dec 27 01:01:15 PM PST 23
Peak memory 209628 kb
Host smart-570c7469-95ee-4bd9-aa1e-762adddf5ef5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810711765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.3810711765
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.2049035361
Short name T309
Test name
Test status
Simulation time 599545187 ps
CPU time 17.88 seconds
Started Dec 27 01:00:49 PM PST 23
Finished Dec 27 01:01:16 PM PST 23
Peak memory 218116 kb
Host smart-03f82bfa-41d4-4f48-90c2-4eff03d0ae3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049035361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.2049035361
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.3572598081
Short name T20
Test name
Test status
Simulation time 1415064953 ps
CPU time 6.23 seconds
Started Dec 27 01:00:52 PM PST 23
Finished Dec 27 01:01:06 PM PST 23
Peak memory 209720 kb
Host smart-73d049d5-3772-4cb7-b74d-5e055cc65050
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572598081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_ac
cess.3572598081
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.3634572939
Short name T727
Test name
Test status
Simulation time 10853479572 ps
CPU time 40.68 seconds
Started Dec 27 01:01:04 PM PST 23
Finished Dec 27 01:01:48 PM PST 23
Peak memory 218468 kb
Host smart-f73348a1-c6f7-48d7-9d7d-faf3c5ab7eaf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634572939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.3634572939
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.1984533426
Short name T888
Test name
Test status
Simulation time 244508849 ps
CPU time 6.87 seconds
Started Dec 27 01:01:07 PM PST 23
Finished Dec 27 01:01:17 PM PST 23
Peak memory 217968 kb
Host smart-b40e5155-7017-46cb-bbcd-7647e008a043
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984533426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
priority.1984533426
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.862894732
Short name T478
Test name
Test status
Simulation time 700726218 ps
CPU time 4.29 seconds
Started Dec 27 01:01:01 PM PST 23
Finished Dec 27 01:01:08 PM PST 23
Peak memory 218136 kb
Host smart-4d0b647c-48a6-437f-8095-56d4458eece4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862894732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
prog_failure.862894732
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3367203770
Short name T763
Test name
Test status
Simulation time 7672599528 ps
CPU time 34.65 seconds
Started Dec 27 01:00:54 PM PST 23
Finished Dec 27 01:01:36 PM PST 23
Peak memory 213844 kb
Host smart-69dccd4b-999a-4f0e-b3e3-6a1e329c7e39
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367203770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.3367203770
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.3755561294
Short name T304
Test name
Test status
Simulation time 150054432 ps
CPU time 4.39 seconds
Started Dec 27 01:00:59 PM PST 23
Finished Dec 27 01:01:07 PM PST 23
Peak memory 212752 kb
Host smart-49ed9820-7994-416b-b8a0-3fc26a3bcf16
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755561294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
3755561294
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.4012968387
Short name T660
Test name
Test status
Simulation time 4465067131 ps
CPU time 42.93 seconds
Started Dec 27 01:00:58 PM PST 23
Finished Dec 27 01:01:45 PM PST 23
Peak memory 252740 kb
Host smart-65620916-9cec-40c5-b8f4-9ab939e80abe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012968387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.4012968387
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.3414342156
Short name T447
Test name
Test status
Simulation time 2241269864 ps
CPU time 19.71 seconds
Started Dec 27 01:00:54 PM PST 23
Finished Dec 27 01:01:21 PM PST 23
Peak memory 251096 kb
Host smart-2435122d-5e4a-4524-ad4f-34c1df8d7f27
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414342156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.3414342156
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.874596342
Short name T859
Test name
Test status
Simulation time 262918985 ps
CPU time 2.36 seconds
Started Dec 27 01:00:59 PM PST 23
Finished Dec 27 01:01:06 PM PST 23
Peak memory 218176 kb
Host smart-98808f33-2438-438a-9a48-1ccc5d2ac274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874596342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.874596342
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.3848222306
Short name T750
Test name
Test status
Simulation time 554795602 ps
CPU time 11.78 seconds
Started Dec 27 01:00:50 PM PST 23
Finished Dec 27 01:01:10 PM PST 23
Peak memory 214336 kb
Host smart-9233db18-be4f-4150-931e-021449740183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848222306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.3848222306
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.4037178882
Short name T120
Test name
Test status
Simulation time 134290109 ps
CPU time 22.21 seconds
Started Dec 27 01:00:53 PM PST 23
Finished Dec 27 01:01:23 PM PST 23
Peak memory 280936 kb
Host smart-c9807d16-a876-4eba-b1cb-40b3530e291d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037178882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.4037178882
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.151141161
Short name T926
Test name
Test status
Simulation time 807595901 ps
CPU time 8.87 seconds
Started Dec 27 01:01:03 PM PST 23
Finished Dec 27 01:01:15 PM PST 23
Peak memory 218224 kb
Host smart-1a70dfbd-d322-4801-ae93-2cf235e78254
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151141161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.151141161
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.1554888743
Short name T531
Test name
Test status
Simulation time 295553186 ps
CPU time 9.6 seconds
Started Dec 27 01:01:05 PM PST 23
Finished Dec 27 01:01:18 PM PST 23
Peak memory 218160 kb
Host smart-9305cc4a-886e-471d-8e29-1a76a484d8f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554888743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.1554888743
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.1117335774
Short name T979
Test name
Test status
Simulation time 245156993 ps
CPU time 9.51 seconds
Started Dec 27 01:01:01 PM PST 23
Finished Dec 27 01:01:14 PM PST 23
Peak memory 218164 kb
Host smart-82e8ef4c-cd39-4a43-8932-ed85b7dfdbdc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117335774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.1
117335774
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.3906545540
Short name T600
Test name
Test status
Simulation time 437844804 ps
CPU time 9.88 seconds
Started Dec 27 01:00:37 PM PST 23
Finished Dec 27 01:00:54 PM PST 23
Peak memory 218184 kb
Host smart-0b1eaffe-0d5e-4e1f-8c4a-7df7a0bf2729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906545540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.3906545540
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.3728269409
Short name T846
Test name
Test status
Simulation time 652461521 ps
CPU time 10.43 seconds
Started Dec 27 01:00:49 PM PST 23
Finished Dec 27 01:01:09 PM PST 23
Peak memory 214064 kb
Host smart-0e472fb6-33a1-4405-9405-0778b8191f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728269409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.3728269409
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.3018312450
Short name T26
Test name
Test status
Simulation time 621319035 ps
CPU time 25.41 seconds
Started Dec 27 01:01:00 PM PST 23
Finished Dec 27 01:01:29 PM PST 23
Peak memory 251056 kb
Host smart-83ace0e7-dda0-4516-97ba-b4efe221829f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018312450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.3018312450
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.563180055
Short name T328
Test name
Test status
Simulation time 57562970 ps
CPU time 6.32 seconds
Started Dec 27 01:00:41 PM PST 23
Finished Dec 27 01:00:56 PM PST 23
Peak memory 250556 kb
Host smart-9d2a2766-f6fc-4882-a827-dce3d8cc3599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563180055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.563180055
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.1410506380
Short name T696
Test name
Test status
Simulation time 28292900548 ps
CPU time 225.2 seconds
Started Dec 27 01:01:02 PM PST 23
Finished Dec 27 01:04:51 PM PST 23
Peak memory 283976 kb
Host smart-132b7382-8b43-4bfd-afea-7d8825bbd80f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410506380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.1410506380
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.314270665
Short name T644
Test name
Test status
Simulation time 37606242 ps
CPU time 0.75 seconds
Started Dec 27 01:00:51 PM PST 23
Finished Dec 27 01:00:59 PM PST 23
Peak memory 207988 kb
Host smart-1593fb83-cf34-4de0-a84f-aded4922f81e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314270665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctr
l_volatile_unlock_smoke.314270665
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.1520084370
Short name T508
Test name
Test status
Simulation time 116194066 ps
CPU time 0.89 seconds
Started Dec 27 01:01:06 PM PST 23
Finished Dec 27 01:01:09 PM PST 23
Peak memory 209656 kb
Host smart-8e6a305b-9e70-4e25-af00-4f19d1d13e48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520084370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.1520084370
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.2560912597
Short name T68
Test name
Test status
Simulation time 49905070 ps
CPU time 0.86 seconds
Started Dec 27 01:01:03 PM PST 23
Finished Dec 27 01:01:08 PM PST 23
Peak memory 209664 kb
Host smart-7dcb8e01-1088-4b0d-b4e9-b3d0fd6398f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560912597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.2560912597
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1034896483
Short name T739
Test name
Test status
Simulation time 346541650 ps
CPU time 11.51 seconds
Started Dec 27 01:01:04 PM PST 23
Finished Dec 27 01:01:19 PM PST 23
Peak memory 218104 kb
Host smart-e802f5c1-1e5d-43ec-85cb-210711079761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034896483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1034896483
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.3579008235
Short name T753
Test name
Test status
Simulation time 1753763483 ps
CPU time 11.23 seconds
Started Dec 27 01:01:07 PM PST 23
Finished Dec 27 01:01:20 PM PST 23
Peak memory 209588 kb
Host smart-fab4019d-fa94-4b13-bde6-0d58093f8be0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579008235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_ac
cess.3579008235
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.2184395126
Short name T98
Test name
Test status
Simulation time 30400008544 ps
CPU time 28.54 seconds
Started Dec 27 01:01:06 PM PST 23
Finished Dec 27 01:01:37 PM PST 23
Peak memory 218428 kb
Host smart-3aebca6e-fd44-4790-b981-e94df057edee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184395126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.2184395126
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2226402721
Short name T349
Test name
Test status
Simulation time 805708687 ps
CPU time 5.6 seconds
Started Dec 27 01:01:08 PM PST 23
Finished Dec 27 01:01:18 PM PST 23
Peak memory 217960 kb
Host smart-baa13e88-1d38-4c2e-859d-e0576213620d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226402721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_
priority.2226402721
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.1319275736
Short name T639
Test name
Test status
Simulation time 321632547 ps
CPU time 5.09 seconds
Started Dec 27 01:01:12 PM PST 23
Finished Dec 27 01:01:21 PM PST 23
Peak memory 218080 kb
Host smart-1cd0a112-138f-4b00-99d9-59dfe4bd8146
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319275736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.1319275736
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3782488883
Short name T319
Test name
Test status
Simulation time 3906873729 ps
CPU time 27.69 seconds
Started Dec 27 01:01:08 PM PST 23
Finished Dec 27 01:01:39 PM PST 23
Peak memory 213744 kb
Host smart-735bda92-a309-4a0a-871d-28e2aec9d00b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782488883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.3782488883
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.1556178390
Short name T499
Test name
Test status
Simulation time 752050305 ps
CPU time 19 seconds
Started Dec 27 01:01:12 PM PST 23
Finished Dec 27 01:01:35 PM PST 23
Peak memory 213500 kb
Host smart-cfec0f8b-61da-4b39-adce-04096176835e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556178390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
1556178390
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.2201588413
Short name T483
Test name
Test status
Simulation time 12725839781 ps
CPU time 35.23 seconds
Started Dec 27 01:00:59 PM PST 23
Finished Dec 27 01:01:38 PM PST 23
Peak memory 268228 kb
Host smart-db51e614-dce0-4978-8bb6-d9ca1b1ac533
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201588413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.2201588413
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.4211930642
Short name T668
Test name
Test status
Simulation time 252793813 ps
CPU time 3.7 seconds
Started Dec 27 01:01:02 PM PST 23
Finished Dec 27 01:01:08 PM PST 23
Peak memory 218196 kb
Host smart-bf981ea5-02e2-4fc2-9266-a7f4da00a0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211930642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.4211930642
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.2070718432
Short name T482
Test name
Test status
Simulation time 1355863837 ps
CPU time 8.06 seconds
Started Dec 27 01:01:07 PM PST 23
Finished Dec 27 01:01:17 PM PST 23
Peak memory 214104 kb
Host smart-4703fbee-ee65-466c-8c8a-41456e2bab5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070718432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.2070718432
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.4116941075
Short name T119
Test name
Test status
Simulation time 226469513 ps
CPU time 36.23 seconds
Started Dec 27 01:01:03 PM PST 23
Finished Dec 27 01:01:43 PM PST 23
Peak memory 273520 kb
Host smart-86f365b7-1f98-4899-bb90-5bbdae115429
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116941075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.4116941075
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.4213368034
Short name T411
Test name
Test status
Simulation time 304421700 ps
CPU time 9.12 seconds
Started Dec 27 01:01:08 PM PST 23
Finished Dec 27 01:01:22 PM PST 23
Peak memory 218120 kb
Host smart-918b9130-693a-4a12-9702-92abffc8e7da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213368034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.4213368034
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.1637586006
Short name T87
Test name
Test status
Simulation time 323466773 ps
CPU time 11.69 seconds
Started Dec 27 01:01:12 PM PST 23
Finished Dec 27 01:01:29 PM PST 23
Peak memory 218168 kb
Host smart-f82e6856-72f0-431f-97e2-fe4045885cef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637586006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.1637586006
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.441335729
Short name T460
Test name
Test status
Simulation time 1182596774 ps
CPU time 7.84 seconds
Started Dec 27 01:01:09 PM PST 23
Finished Dec 27 01:01:21 PM PST 23
Peak memory 218140 kb
Host smart-393cd32e-0596-44a3-ad59-6ea28656158c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441335729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.441335729
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.2371729848
Short name T326
Test name
Test status
Simulation time 25586162 ps
CPU time 1.33 seconds
Started Dec 27 01:01:09 PM PST 23
Finished Dec 27 01:01:14 PM PST 23
Peak memory 213092 kb
Host smart-a2610c93-7a29-4297-a7e4-a84b4c84f0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371729848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.2371729848
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.3358054367
Short name T401
Test name
Test status
Simulation time 325394873 ps
CPU time 32.82 seconds
Started Dec 27 01:00:58 PM PST 23
Finished Dec 27 01:01:35 PM PST 23
Peak memory 251156 kb
Host smart-7fe23374-c68f-4467-9418-d01955ce8bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358054367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.3358054367
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.813008873
Short name T10
Test name
Test status
Simulation time 100387356 ps
CPU time 7.47 seconds
Started Dec 27 01:00:59 PM PST 23
Finished Dec 27 01:01:11 PM PST 23
Peak memory 250032 kb
Host smart-80fdd8cd-6778-49f9-9354-c9ef76688c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813008873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.813008873
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.942495670
Short name T369
Test name
Test status
Simulation time 39878978637 ps
CPU time 206.65 seconds
Started Dec 27 01:01:03 PM PST 23
Finished Dec 27 01:04:34 PM PST 23
Peak memory 283924 kb
Host smart-8528f9c6-ab05-4746-97d4-0f77f218928b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942495670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.942495670
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.405240367
Short name T553
Test name
Test status
Simulation time 28710630 ps
CPU time 0.94 seconds
Started Dec 27 01:00:57 PM PST 23
Finished Dec 27 01:01:03 PM PST 23
Peak memory 211332 kb
Host smart-9fa3b2b3-6a7b-496f-8843-a6b8c6af26cf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405240367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctr
l_volatile_unlock_smoke.405240367
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.4007633829
Short name T354
Test name
Test status
Simulation time 69222961 ps
CPU time 0.97 seconds
Started Dec 27 01:01:33 PM PST 23
Finished Dec 27 01:01:36 PM PST 23
Peak memory 209616 kb
Host smart-6410deb7-9ef5-4e66-94bb-883e74fcfe9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007633829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.4007633829
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.2398929659
Short name T474
Test name
Test status
Simulation time 1331124748 ps
CPU time 15.75 seconds
Started Dec 27 01:01:29 PM PST 23
Finished Dec 27 01:01:49 PM PST 23
Peak memory 218120 kb
Host smart-3fa7f517-b526-4631-8c68-a3320a9ec45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398929659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.2398929659
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.1210988423
Short name T626
Test name
Test status
Simulation time 196302809 ps
CPU time 5.17 seconds
Started Dec 27 01:01:30 PM PST 23
Finished Dec 27 01:01:40 PM PST 23
Peak memory 209624 kb
Host smart-3f06f59f-450c-4bc6-90d0-1d63512072da
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210988423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_a
ccess.1210988423
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.4259451160
Short name T805
Test name
Test status
Simulation time 6357489978 ps
CPU time 51.84 seconds
Started Dec 27 01:01:26 PM PST 23
Finished Dec 27 01:02:25 PM PST 23
Peak memory 219164 kb
Host smart-12962129-22da-4983-a88e-575206c4d9ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259451160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.4259451160
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1974172192
Short name T405
Test name
Test status
Simulation time 947365394 ps
CPU time 8.66 seconds
Started Dec 27 01:01:28 PM PST 23
Finished Dec 27 01:01:42 PM PST 23
Peak memory 218048 kb
Host smart-09972f4a-a85f-47f2-83ed-0fdaeeed8407
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974172192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.1974172192
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.1260378096
Short name T790
Test name
Test status
Simulation time 145959854 ps
CPU time 5.11 seconds
Started Dec 27 01:01:26 PM PST 23
Finished Dec 27 01:01:38 PM PST 23
Peak memory 213060 kb
Host smart-543bd15d-72b0-460e-b312-8036c726a40a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260378096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.1260378096
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2595261803
Short name T361
Test name
Test status
Simulation time 6090910801 ps
CPU time 38.2 seconds
Started Dec 27 01:01:27 PM PST 23
Finished Dec 27 01:02:11 PM PST 23
Peak memory 279344 kb
Host smart-7f75754a-6cec-4d0d-b5ee-3af5eefac075
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595261803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.2595261803
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.4014871719
Short name T615
Test name
Test status
Simulation time 3382845950 ps
CPU time 23.25 seconds
Started Dec 27 01:01:27 PM PST 23
Finished Dec 27 01:01:56 PM PST 23
Peak memory 251180 kb
Host smart-685404fa-2805-476d-85a2-1b65963e40ec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014871719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.4014871719
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.3076519696
Short name T7
Test name
Test status
Simulation time 20204512 ps
CPU time 1.6 seconds
Started Dec 27 01:01:25 PM PST 23
Finished Dec 27 01:01:34 PM PST 23
Peak memory 218200 kb
Host smart-e31e58b0-b94b-4c9e-ab39-b6d84d19d79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076519696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.3076519696
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.3281015012
Short name T43
Test name
Test status
Simulation time 1375592223 ps
CPU time 10.13 seconds
Started Dec 27 01:01:27 PM PST 23
Finished Dec 27 01:01:43 PM PST 23
Peak memory 219144 kb
Host smart-425b6616-36a6-48f3-929b-d5201167ab52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281015012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.3281015012
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1123947131
Short name T645
Test name
Test status
Simulation time 3302463722 ps
CPU time 8.92 seconds
Started Dec 27 01:01:28 PM PST 23
Finished Dec 27 01:01:42 PM PST 23
Peak memory 218220 kb
Host smart-72c482a2-535a-4780-83c6-9b2b92d7a55b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123947131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.1123947131
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1173018856
Short name T887
Test name
Test status
Simulation time 334589104 ps
CPU time 13.24 seconds
Started Dec 27 01:01:32 PM PST 23
Finished Dec 27 01:01:48 PM PST 23
Peak memory 218156 kb
Host smart-a2848232-f608-4b2b-8808-cfd5d8817f4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173018856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
1173018856
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.802856040
Short name T795
Test name
Test status
Simulation time 244244165 ps
CPU time 9.63 seconds
Started Dec 27 01:01:26 PM PST 23
Finished Dec 27 01:01:43 PM PST 23
Peak memory 218220 kb
Host smart-8fbea3d3-8048-42f9-a9e1-2149c113b15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802856040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.802856040
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.2671658202
Short name T470
Test name
Test status
Simulation time 169700792 ps
CPU time 3.13 seconds
Started Dec 27 01:01:32 PM PST 23
Finished Dec 27 01:01:38 PM PST 23
Peak memory 214008 kb
Host smart-a8f37db7-bb0a-4830-9e8c-33598852df04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671658202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.2671658202
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.4152292204
Short name T417
Test name
Test status
Simulation time 923025446 ps
CPU time 20.55 seconds
Started Dec 27 01:01:27 PM PST 23
Finished Dec 27 01:01:53 PM PST 23
Peak memory 251012 kb
Host smart-84958ab2-f824-47b8-a81a-beb5f74d3647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152292204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.4152292204
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.3476501433
Short name T629
Test name
Test status
Simulation time 348974306 ps
CPU time 6.97 seconds
Started Dec 27 01:01:28 PM PST 23
Finished Dec 27 01:01:40 PM PST 23
Peak memory 250604 kb
Host smart-8f875873-d4df-4b2a-b615-30cba52c1cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476501433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.3476501433
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.889264229
Short name T692
Test name
Test status
Simulation time 7058709147 ps
CPU time 278.97 seconds
Started Dec 27 01:01:29 PM PST 23
Finished Dec 27 01:06:13 PM PST 23
Peak memory 267616 kb
Host smart-2d340e1c-07d4-468e-869f-a53dd9654dd2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889264229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.889264229
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2315801215
Short name T654
Test name
Test status
Simulation time 35567168 ps
CPU time 0.76 seconds
Started Dec 27 01:01:27 PM PST 23
Finished Dec 27 01:01:34 PM PST 23
Peak memory 208156 kb
Host smart-72f03340-99fa-4d6e-a6be-daa4671e34b2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315801215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.2315801215
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.429875575
Short name T841
Test name
Test status
Simulation time 45082508 ps
CPU time 0.84 seconds
Started Dec 27 01:01:47 PM PST 23
Finished Dec 27 01:01:50 PM PST 23
Peak memory 208236 kb
Host smart-e4e506b0-c0ef-4fdf-b7b0-ec9bed09ef30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429875575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.429875575
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.2913874465
Short name T770
Test name
Test status
Simulation time 2660628087 ps
CPU time 12.46 seconds
Started Dec 27 01:02:01 PM PST 23
Finished Dec 27 01:02:14 PM PST 23
Peak memory 218160 kb
Host smart-6fd6328d-4863-4147-8a68-2a2bd4d1f3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913874465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.2913874465
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.39154843
Short name T22
Test name
Test status
Simulation time 1197897742 ps
CPU time 6.39 seconds
Started Dec 27 01:01:40 PM PST 23
Finished Dec 27 01:01:48 PM PST 23
Peak memory 209624 kb
Host smart-e3218185-2245-4af3-99e3-10d4542e68e2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39154843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jta
g_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_acc
ess.39154843
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.4062367060
Short name T45
Test name
Test status
Simulation time 3649927061 ps
CPU time 49.09 seconds
Started Dec 27 01:01:51 PM PST 23
Finished Dec 27 01:02:41 PM PST 23
Peak memory 219504 kb
Host smart-4493116f-814d-43a9-9a84-8eca53d6171b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062367060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.4062367060
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.3454072392
Short name T827
Test name
Test status
Simulation time 1253962500 ps
CPU time 8.55 seconds
Started Dec 27 01:01:48 PM PST 23
Finished Dec 27 01:01:58 PM PST 23
Peak memory 218116 kb
Host smart-61c61da3-f137-4cd6-990e-9c8569773f75
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454072392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.3454072392
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.51908827
Short name T879
Test name
Test status
Simulation time 1858737601 ps
CPU time 5.77 seconds
Started Dec 27 01:01:47 PM PST 23
Finished Dec 27 01:01:53 PM PST 23
Peak memory 213576 kb
Host smart-025e3dec-85e1-49da-a7d0-52d54e776a7a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51908827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke.51908827
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.1260197457
Short name T419
Test name
Test status
Simulation time 6769289969 ps
CPU time 57.09 seconds
Started Dec 27 01:01:50 PM PST 23
Finished Dec 27 01:02:48 PM PST 23
Peak memory 251140 kb
Host smart-1092d43d-ffe9-445b-9ded-e9bfb00c8aff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260197457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.1260197457
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.2396672002
Short name T468
Test name
Test status
Simulation time 3956102259 ps
CPU time 21.27 seconds
Started Dec 27 01:01:40 PM PST 23
Finished Dec 27 01:02:02 PM PST 23
Peak memory 251184 kb
Host smart-02684a53-19ef-4a17-bf19-b2629afed60e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396672002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.2396672002
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.1267581252
Short name T648
Test name
Test status
Simulation time 48491889 ps
CPU time 1.42 seconds
Started Dec 27 01:01:48 PM PST 23
Finished Dec 27 01:01:51 PM PST 23
Peak memory 218100 kb
Host smart-5b301820-2c8d-44a6-b5de-4c57666529a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267581252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.1267581252
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.2483886907
Short name T381
Test name
Test status
Simulation time 1525135781 ps
CPU time 11.56 seconds
Started Dec 27 01:01:41 PM PST 23
Finished Dec 27 01:01:54 PM PST 23
Peak memory 218168 kb
Host smart-2ed56b84-007c-4eba-ad58-97ad583de6b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483886907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.2483886907
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.3118802360
Short name T299
Test name
Test status
Simulation time 1089026036 ps
CPU time 10.56 seconds
Started Dec 27 01:01:49 PM PST 23
Finished Dec 27 01:02:01 PM PST 23
Peak memory 218028 kb
Host smart-37a06088-ae14-4417-ac19-30e405c450f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118802360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.3118802360
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.3782168373
Short name T689
Test name
Test status
Simulation time 1934220554 ps
CPU time 10.84 seconds
Started Dec 27 01:01:49 PM PST 23
Finished Dec 27 01:02:01 PM PST 23
Peak memory 218160 kb
Host smart-0ce1299a-0370-4825-84f5-78af27331293
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782168373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
3782168373
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.397201090
Short name T367
Test name
Test status
Simulation time 631940067 ps
CPU time 9.94 seconds
Started Dec 27 01:01:59 PM PST 23
Finished Dec 27 01:02:10 PM PST 23
Peak memory 218228 kb
Host smart-169fb8e0-a480-4e37-ba33-67b21f46a9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397201090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.397201090
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.4044586786
Short name T620
Test name
Test status
Simulation time 68023189 ps
CPU time 1.82 seconds
Started Dec 27 01:01:28 PM PST 23
Finished Dec 27 01:01:35 PM PST 23
Peak memory 213712 kb
Host smart-f41e0e62-534e-4163-8777-6f2366357211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044586786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.4044586786
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.508585899
Short name T910
Test name
Test status
Simulation time 1195899333 ps
CPU time 30.85 seconds
Started Dec 27 01:01:28 PM PST 23
Finished Dec 27 01:02:04 PM PST 23
Peak memory 247216 kb
Host smart-2839af62-96f5-4c02-bb2f-07f5cb95d7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508585899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.508585899
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.90528146
Short name T793
Test name
Test status
Simulation time 189310665 ps
CPU time 3.03 seconds
Started Dec 27 01:02:04 PM PST 23
Finished Dec 27 01:02:08 PM PST 23
Peak memory 226560 kb
Host smart-6aa35197-d6b6-4daf-b28e-161112916f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90528146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.90528146
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.423768053
Short name T511
Test name
Test status
Simulation time 9035381430 ps
CPU time 185.36 seconds
Started Dec 27 01:01:47 PM PST 23
Finished Dec 27 01:04:53 PM PST 23
Peak memory 277200 kb
Host smart-bed428fd-8462-435a-88fe-41493860ae7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423768053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.423768053
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.751090387
Short name T941
Test name
Test status
Simulation time 44794996 ps
CPU time 0.78 seconds
Started Dec 27 01:01:29 PM PST 23
Finished Dec 27 01:01:35 PM PST 23
Peak memory 208100 kb
Host smart-87d4adda-035d-42fd-98fc-da7335c464c0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751090387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ct
rl_volatile_unlock_smoke.751090387
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.3681997145
Short name T754
Test name
Test status
Simulation time 14754020 ps
CPU time 1.05 seconds
Started Dec 27 01:01:47 PM PST 23
Finished Dec 27 01:01:49 PM PST 23
Peak memory 208464 kb
Host smart-12fb1e52-3e39-4256-8894-53f75c149d13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681997145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.3681997145
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.1139542842
Short name T34
Test name
Test status
Simulation time 2587075779 ps
CPU time 14.56 seconds
Started Dec 27 01:02:01 PM PST 23
Finished Dec 27 01:02:16 PM PST 23
Peak memory 218296 kb
Host smart-b021117c-3aa0-42b6-958b-08cb14928248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139542842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.1139542842
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.1328543601
Short name T647
Test name
Test status
Simulation time 141878495 ps
CPU time 1.27 seconds
Started Dec 27 01:01:40 PM PST 23
Finished Dec 27 01:01:43 PM PST 23
Peak memory 209684 kb
Host smart-25ea4e82-189d-4968-af13-1b6a8c8c869c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328543601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_a
ccess.1328543601
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.7413843
Short name T399
Test name
Test status
Simulation time 26431114858 ps
CPU time 63.28 seconds
Started Dec 27 01:01:41 PM PST 23
Finished Dec 27 01:02:45 PM PST 23
Peak memory 219256 kb
Host smart-28db2d36-8961-4bc0-ad6e-47e1724a7b11
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7413843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc
_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_erro
rs.7413843
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.4285172926
Short name T585
Test name
Test status
Simulation time 245330912 ps
CPU time 7.85 seconds
Started Dec 27 01:01:52 PM PST 23
Finished Dec 27 01:02:00 PM PST 23
Peak memory 218124 kb
Host smart-86da53fb-a95f-474e-9fae-e1c749519bb3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285172926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.4285172926
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.1140515548
Short name T78
Test name
Test status
Simulation time 1219660580 ps
CPU time 8.25 seconds
Started Dec 27 01:01:46 PM PST 23
Finished Dec 27 01:01:55 PM PST 23
Peak memory 213384 kb
Host smart-55188268-93ec-40a3-b219-c8cd69013724
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140515548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.1140515548
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.1174042478
Short name T16
Test name
Test status
Simulation time 4610310663 ps
CPU time 37.03 seconds
Started Dec 27 01:02:04 PM PST 23
Finished Dec 27 01:02:44 PM PST 23
Peak memory 283832 kb
Host smart-5f497a50-cd63-4ab5-a8c9-8ca9813df985
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174042478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.1174042478
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.985164696
Short name T643
Test name
Test status
Simulation time 666721419 ps
CPU time 17.26 seconds
Started Dec 27 01:01:47 PM PST 23
Finished Dec 27 01:02:05 PM PST 23
Peak memory 222980 kb
Host smart-9b9b36db-b288-4d53-965b-389541b9c1e6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985164696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_
jtag_state_post_trans.985164696
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.1672631053
Short name T858
Test name
Test status
Simulation time 316475153 ps
CPU time 2.11 seconds
Started Dec 27 01:01:50 PM PST 23
Finished Dec 27 01:01:53 PM PST 23
Peak memory 218176 kb
Host smart-240ed3ab-57bb-4a19-ac94-9622be433337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672631053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.1672631053
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.4112823856
Short name T496
Test name
Test status
Simulation time 324325152 ps
CPU time 16.82 seconds
Started Dec 27 01:01:59 PM PST 23
Finished Dec 27 01:02:17 PM PST 23
Peak memory 219136 kb
Host smart-d48b674f-07a4-4904-87f4-e71cdcd81756
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112823856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.4112823856
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.4183226353
Short name T486
Test name
Test status
Simulation time 1085273316 ps
CPU time 9.53 seconds
Started Dec 27 01:01:48 PM PST 23
Finished Dec 27 01:01:59 PM PST 23
Peak memory 218148 kb
Host smart-9a320659-90db-469f-9b35-a57fa4d2340a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183226353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.4183226353
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3350701421
Short name T501
Test name
Test status
Simulation time 294662901 ps
CPU time 13.31 seconds
Started Dec 27 01:01:51 PM PST 23
Finished Dec 27 01:02:05 PM PST 23
Peak memory 218132 kb
Host smart-3fd18469-226e-4566-9986-5f5a6f140787
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350701421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
3350701421
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.163705560
Short name T446
Test name
Test status
Simulation time 439995021 ps
CPU time 12.01 seconds
Started Dec 27 01:01:47 PM PST 23
Finished Dec 27 01:02:00 PM PST 23
Peak memory 218232 kb
Host smart-5edfa930-1ccb-4f1e-bd64-0ef26464af66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163705560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.163705560
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.2556408885
Short name T357
Test name
Test status
Simulation time 213620785 ps
CPU time 5.7 seconds
Started Dec 27 01:01:51 PM PST 23
Finished Dec 27 01:01:57 PM PST 23
Peak memory 214532 kb
Host smart-18824e29-e02a-449d-9571-7f0a17ddd5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556408885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.2556408885
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.2656767192
Short name T614
Test name
Test status
Simulation time 241441520 ps
CPU time 27.59 seconds
Started Dec 27 01:01:40 PM PST 23
Finished Dec 27 01:02:09 PM PST 23
Peak memory 251072 kb
Host smart-84c1b914-0827-4062-b0ae-0c72239d11e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656767192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.2656767192
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.826213049
Short name T726
Test name
Test status
Simulation time 1486463641 ps
CPU time 9.77 seconds
Started Dec 27 01:02:02 PM PST 23
Finished Dec 27 01:02:12 PM PST 23
Peak memory 251224 kb
Host smart-0c0e2116-9ea2-4929-8dea-081b0f1652dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826213049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.826213049
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.940379299
Short name T869
Test name
Test status
Simulation time 7674365310 ps
CPU time 42.09 seconds
Started Dec 27 01:01:48 PM PST 23
Finished Dec 27 01:02:31 PM PST 23
Peak memory 251232 kb
Host smart-5d3f3a49-590e-46fa-9ab3-5d4b2dfe9e0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940379299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.940379299
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3974201683
Short name T611
Test name
Test status
Simulation time 44411688 ps
CPU time 0.79 seconds
Started Dec 27 01:01:44 PM PST 23
Finished Dec 27 01:01:45 PM PST 23
Peak memory 208164 kb
Host smart-bdb31864-245f-469e-b4a2-efe6940cdfa6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974201683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3974201683
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.161116524
Short name T973
Test name
Test status
Simulation time 83005332 ps
CPU time 0.91 seconds
Started Dec 27 01:01:58 PM PST 23
Finished Dec 27 01:02:00 PM PST 23
Peak memory 209732 kb
Host smart-05185da2-66e5-4e63-950a-de7210ef730d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161116524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.161116524
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.3403865686
Short name T829
Test name
Test status
Simulation time 877263630 ps
CPU time 16.44 seconds
Started Dec 27 01:01:41 PM PST 23
Finished Dec 27 01:01:59 PM PST 23
Peak memory 218176 kb
Host smart-ae86c0ba-1047-4e4b-9f9c-8c506a7aa08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403865686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.3403865686
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.2900154469
Short name T17
Test name
Test status
Simulation time 942287878 ps
CPU time 9.05 seconds
Started Dec 27 01:02:03 PM PST 23
Finished Dec 27 01:02:13 PM PST 23
Peak memory 209628 kb
Host smart-140a9687-e57f-4bd2-8e77-46b922761e11
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900154469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_a
ccess.2900154469
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.2181338049
Short name T308
Test name
Test status
Simulation time 8771415548 ps
CPU time 45.13 seconds
Started Dec 27 01:01:47 PM PST 23
Finished Dec 27 01:02:33 PM PST 23
Peak memory 218172 kb
Host smart-22d40bd0-7db8-4630-81bc-7f5dfc92f630
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181338049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.2181338049
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.3551628504
Short name T364
Test name
Test status
Simulation time 497018634 ps
CPU time 2.85 seconds
Started Dec 27 01:01:50 PM PST 23
Finished Dec 27 01:01:53 PM PST 23
Peak memory 218156 kb
Host smart-08ad8aac-8674-4eae-87a5-3850290ddd32
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551628504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.3551628504
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.526275828
Short name T898
Test name
Test status
Simulation time 274431744 ps
CPU time 7.29 seconds
Started Dec 27 01:01:48 PM PST 23
Finished Dec 27 01:01:57 PM PST 23
Peak memory 213068 kb
Host smart-bdf75608-530f-4f16-ae9e-acb42deb7448
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526275828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke.
526275828
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.1710731430
Short name T669
Test name
Test status
Simulation time 1602762307 ps
CPU time 49.37 seconds
Started Dec 27 01:01:48 PM PST 23
Finished Dec 27 01:02:39 PM PST 23
Peak memory 267492 kb
Host smart-54f22816-b3c6-4c7f-84bc-eabc4847edbd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710731430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.1710731430
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.1228487382
Short name T685
Test name
Test status
Simulation time 333212253 ps
CPU time 13.77 seconds
Started Dec 27 01:01:47 PM PST 23
Finished Dec 27 01:02:02 PM PST 23
Peak memory 246712 kb
Host smart-bfe135eb-c098-47ba-af09-0ff4bd65a7f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228487382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.1228487382
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.370937608
Short name T832
Test name
Test status
Simulation time 63890637 ps
CPU time 2.55 seconds
Started Dec 27 01:01:47 PM PST 23
Finished Dec 27 01:01:51 PM PST 23
Peak memory 218196 kb
Host smart-99da2b78-0614-4c44-b564-7904ff0f25d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370937608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.370937608
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.1229630529
Short name T894
Test name
Test status
Simulation time 317109660 ps
CPU time 16.69 seconds
Started Dec 27 01:02:00 PM PST 23
Finished Dec 27 01:02:17 PM PST 23
Peak memory 218832 kb
Host smart-8127d0da-4df3-4c90-a05e-e7f0fcab2c3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229630529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.1229630529
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.3375377192
Short name T745
Test name
Test status
Simulation time 468559073 ps
CPU time 10.68 seconds
Started Dec 27 01:02:03 PM PST 23
Finished Dec 27 01:02:14 PM PST 23
Peak memory 218112 kb
Host smart-e82badaa-5be8-45ec-9d6a-f6ab1222b366
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375377192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
3375377192
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.879904572
Short name T403
Test name
Test status
Simulation time 1296760654 ps
CPU time 9.16 seconds
Started Dec 27 01:01:48 PM PST 23
Finished Dec 27 01:01:59 PM PST 23
Peak memory 218096 kb
Host smart-76aaa1f6-b901-40cd-88db-b14d969c9735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879904572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.879904572
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.1119106791
Short name T71
Test name
Test status
Simulation time 113958173 ps
CPU time 2.75 seconds
Started Dec 27 01:01:34 PM PST 23
Finished Dec 27 01:01:39 PM PST 23
Peak memory 214208 kb
Host smart-6a72c887-15ce-4753-9bfd-603ff2b0ff1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119106791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.1119106791
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.3874128052
Short name T741
Test name
Test status
Simulation time 257068062 ps
CPU time 32.09 seconds
Started Dec 27 01:02:00 PM PST 23
Finished Dec 27 01:02:33 PM PST 23
Peak memory 251132 kb
Host smart-3bda7675-d31e-4946-95a8-25a706ebee2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874128052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.3874128052
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.1445620909
Short name T657
Test name
Test status
Simulation time 221274744 ps
CPU time 3.72 seconds
Started Dec 27 01:01:41 PM PST 23
Finished Dec 27 01:01:46 PM PST 23
Peak memory 221984 kb
Host smart-ba031534-129b-40f0-a882-0b16726da636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445620909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1445620909
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.1401840707
Short name T425
Test name
Test status
Simulation time 686665028 ps
CPU time 10.12 seconds
Started Dec 27 01:01:58 PM PST 23
Finished Dec 27 01:02:09 PM PST 23
Peak memory 243488 kb
Host smart-cb22595f-e22a-452b-acb6-cf2092ccf0ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401840707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.1401840707
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.3664584642
Short name T596
Test name
Test status
Simulation time 32478558 ps
CPU time 1.1 seconds
Started Dec 27 01:02:19 PM PST 23
Finished Dec 27 01:02:24 PM PST 23
Peak memory 209720 kb
Host smart-3a89232c-3d4b-4c2d-ae37-d4608e471cfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664584642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.3664584642
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.2384367563
Short name T636
Test name
Test status
Simulation time 1531823660 ps
CPU time 17.65 seconds
Started Dec 27 01:02:19 PM PST 23
Finished Dec 27 01:02:41 PM PST 23
Peak memory 209672 kb
Host smart-0c0bf922-e796-4f0e-9751-9500544d54da
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384367563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_a
ccess.2384367563
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.2787620839
Short name T577
Test name
Test status
Simulation time 3634550563 ps
CPU time 16.83 seconds
Started Dec 27 01:02:17 PM PST 23
Finished Dec 27 01:02:36 PM PST 23
Peak memory 218400 kb
Host smart-67ccff18-2d6c-4698-bbd2-035fbc1e3f19
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787620839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.2787620839
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.391269813
Short name T339
Test name
Test status
Simulation time 727629143 ps
CPU time 6.36 seconds
Started Dec 27 01:02:17 PM PST 23
Finished Dec 27 01:02:26 PM PST 23
Peak memory 218160 kb
Host smart-e24ee34c-b4b2-4d4d-b030-3c189334c272
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391269813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag
_prog_failure.391269813
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1845773913
Short name T73
Test name
Test status
Simulation time 427409638 ps
CPU time 12.44 seconds
Started Dec 27 01:02:15 PM PST 23
Finished Dec 27 01:02:28 PM PST 23
Peak memory 213480 kb
Host smart-5ba4fe81-34f1-4a32-862e-b996cfbb6fd1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845773913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1845773913
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.384145009
Short name T897
Test name
Test status
Simulation time 1940480718 ps
CPU time 28.96 seconds
Started Dec 27 01:02:17 PM PST 23
Finished Dec 27 01:02:49 PM PST 23
Peak memory 251004 kb
Host smart-227b2c47-2d28-49a0-877a-0cceaa9c2bd7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384145009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_state_failure.384145009
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.4066255195
Short name T432
Test name
Test status
Simulation time 967044043 ps
CPU time 21.14 seconds
Started Dec 27 01:02:04 PM PST 23
Finished Dec 27 01:02:27 PM PST 23
Peak memory 245944 kb
Host smart-37811e45-69de-430b-8282-43a2e51f34aa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066255195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.4066255195
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.4072237315
Short name T809
Test name
Test status
Simulation time 111141126 ps
CPU time 1.89 seconds
Started Dec 27 01:02:03 PM PST 23
Finished Dec 27 01:02:06 PM PST 23
Peak memory 218304 kb
Host smart-1748f548-f9b6-4516-8d05-d4c5b705763f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072237315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.4072237315
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.2250788555
Short name T694
Test name
Test status
Simulation time 443050982 ps
CPU time 13.86 seconds
Started Dec 27 01:02:21 PM PST 23
Finished Dec 27 01:02:39 PM PST 23
Peak memory 219108 kb
Host smart-0c84fd37-f62f-49c6-bb10-5cd9a6fb40d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250788555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.2250788555
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.3120926466
Short name T824
Test name
Test status
Simulation time 3894160795 ps
CPU time 14.3 seconds
Started Dec 27 01:02:16 PM PST 23
Finished Dec 27 01:02:33 PM PST 23
Peak memory 218192 kb
Host smart-b8181902-9470-4c5c-ae1e-e1c1cba7a85d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120926466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.3120926466
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.2303158530
Short name T322
Test name
Test status
Simulation time 2284925663 ps
CPU time 12.55 seconds
Started Dec 27 01:02:18 PM PST 23
Finished Dec 27 01:02:34 PM PST 23
Peak memory 218248 kb
Host smart-bec11470-d3ab-4f40-9c0a-89a3437918d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303158530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
2303158530
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.3351168613
Short name T775
Test name
Test status
Simulation time 381074224 ps
CPU time 8.81 seconds
Started Dec 27 01:02:18 PM PST 23
Finished Dec 27 01:02:29 PM PST 23
Peak memory 218184 kb
Host smart-9200c9e4-35d1-426d-aac3-2e31c3532fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351168613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.3351168613
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.4274898839
Short name T56
Test name
Test status
Simulation time 426406239 ps
CPU time 2.78 seconds
Started Dec 27 01:01:52 PM PST 23
Finished Dec 27 01:01:56 PM PST 23
Peak memory 214116 kb
Host smart-4b12894b-e56c-4c05-b5bb-20bf17ed4905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274898839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.4274898839
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.366938031
Short name T433
Test name
Test status
Simulation time 1492775096 ps
CPU time 27.72 seconds
Started Dec 27 01:02:00 PM PST 23
Finished Dec 27 01:02:29 PM PST 23
Peak memory 251140 kb
Host smart-066a9ad5-72eb-43a8-82fd-822a3880ea32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366938031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.366938031
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.1625699743
Short name T343
Test name
Test status
Simulation time 184219891 ps
CPU time 6.4 seconds
Started Dec 27 01:02:06 PM PST 23
Finished Dec 27 01:02:15 PM PST 23
Peak memory 243936 kb
Host smart-87c1acd4-0c38-4d3a-ad1d-23697de7b57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625699743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.1625699743
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1049888838
Short name T788
Test name
Test status
Simulation time 35148153 ps
CPU time 0.73 seconds
Started Dec 27 01:01:49 PM PST 23
Finished Dec 27 01:01:51 PM PST 23
Peak memory 208084 kb
Host smart-c6db2afb-392d-4f20-93a4-e4c107fc30df
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049888838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.1049888838
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.568452750
Short name T378
Test name
Test status
Simulation time 16528963 ps
CPU time 1.07 seconds
Started Dec 27 01:02:07 PM PST 23
Finished Dec 27 01:02:10 PM PST 23
Peak memory 209704 kb
Host smart-7148895b-3ded-4dce-8f74-46db2af84cc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568452750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.568452750
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.76451565
Short name T46
Test name
Test status
Simulation time 1614864606 ps
CPU time 16.1 seconds
Started Dec 27 01:02:04 PM PST 23
Finished Dec 27 01:02:23 PM PST 23
Peak memory 218220 kb
Host smart-2ae9d675-e781-4f33-9b94-28f2a8c13860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76451565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.76451565
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.1908332134
Short name T18
Test name
Test status
Simulation time 847383616 ps
CPU time 7.11 seconds
Started Dec 27 01:02:00 PM PST 23
Finished Dec 27 01:02:08 PM PST 23
Peak memory 209640 kb
Host smart-62152ac5-55e7-4377-a22c-ed3b9c81811a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908332134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_a
ccess.1908332134
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.2446896730
Short name T800
Test name
Test status
Simulation time 16029682614 ps
CPU time 48.22 seconds
Started Dec 27 01:01:49 PM PST 23
Finished Dec 27 01:02:39 PM PST 23
Peak memory 218688 kb
Host smart-a78ff115-48f2-4fa0-8931-f1a4b3586736
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446896730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.2446896730
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.4197672624
Short name T498
Test name
Test status
Simulation time 5535255005 ps
CPU time 11.81 seconds
Started Dec 27 01:01:52 PM PST 23
Finished Dec 27 01:02:05 PM PST 23
Peak memory 218200 kb
Host smart-add4c824-c952-4218-8f7e-4d70098bc6f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197672624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.4197672624
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.249028738
Short name T66
Test name
Test status
Simulation time 1472967464 ps
CPU time 4.85 seconds
Started Dec 27 01:02:00 PM PST 23
Finished Dec 27 01:02:06 PM PST 23
Peak memory 213060 kb
Host smart-b08b1441-3cdc-4243-a0bb-69f5d0ec770b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249028738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke.
249028738
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.2765889246
Short name T332
Test name
Test status
Simulation time 2745843511 ps
CPU time 41.62 seconds
Started Dec 27 01:01:47 PM PST 23
Finished Dec 27 01:02:30 PM PST 23
Peak memory 251152 kb
Host smart-92998dee-5f42-4698-b2ff-a57f6398ce56
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765889246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.2765889246
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.366812843
Short name T376
Test name
Test status
Simulation time 330944019 ps
CPU time 9.57 seconds
Started Dec 27 01:01:49 PM PST 23
Finished Dec 27 01:02:00 PM PST 23
Peak memory 244900 kb
Host smart-87dc2e61-7a1d-4522-babc-cc70af7ba26a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366812843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_
jtag_state_post_trans.366812843
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.1948091951
Short name T617
Test name
Test status
Simulation time 108044727 ps
CPU time 3.01 seconds
Started Dec 27 01:01:49 PM PST 23
Finished Dec 27 01:01:53 PM PST 23
Peak memory 218260 kb
Host smart-b577fc5f-dffb-41aa-8a23-5a9754e4deca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948091951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1948091951
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.2360624929
Short name T566
Test name
Test status
Simulation time 505636486 ps
CPU time 10.11 seconds
Started Dec 27 01:01:52 PM PST 23
Finished Dec 27 01:02:03 PM PST 23
Peak memory 218128 kb
Host smart-1ca87c4a-ca32-44c8-b554-3b9eaadae06a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360624929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.2360624929
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.3473151912
Short name T321
Test name
Test status
Simulation time 320828619 ps
CPU time 13.4 seconds
Started Dec 27 01:01:48 PM PST 23
Finished Dec 27 01:02:03 PM PST 23
Peak memory 218136 kb
Host smart-941879dc-dfd7-4b34-a87b-09f42c608eb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473151912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.3473151912
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.2595920168
Short name T704
Test name
Test status
Simulation time 242158902 ps
CPU time 7.5 seconds
Started Dec 27 01:01:59 PM PST 23
Finished Dec 27 01:02:07 PM PST 23
Peak memory 218112 kb
Host smart-6d3c2056-2b55-411c-9bf7-433eb9a5ecc8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595920168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
2595920168
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.1519007252
Short name T970
Test name
Test status
Simulation time 245308502 ps
CPU time 9.64 seconds
Started Dec 27 01:01:49 PM PST 23
Finished Dec 27 01:02:00 PM PST 23
Peak memory 218136 kb
Host smart-4aab72ee-df50-46ed-9468-1671dea3d008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519007252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.1519007252
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.380360075
Short name T437
Test name
Test status
Simulation time 538611380 ps
CPU time 4.1 seconds
Started Dec 27 01:02:19 PM PST 23
Finished Dec 27 01:02:27 PM PST 23
Peak memory 214032 kb
Host smart-eb2adbba-bf79-4c12-987f-c15ff235780c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380360075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.380360075
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.676752765
Short name T402
Test name
Test status
Simulation time 251076020 ps
CPU time 27.25 seconds
Started Dec 27 01:02:00 PM PST 23
Finished Dec 27 01:02:29 PM PST 23
Peak memory 251012 kb
Host smart-cebb32d5-cc8b-4ac7-9af8-56862761cd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676752765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.676752765
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.3440130548
Short name T327
Test name
Test status
Simulation time 120963690 ps
CPU time 6.56 seconds
Started Dec 27 01:01:49 PM PST 23
Finished Dec 27 01:01:57 PM PST 23
Peak memory 246400 kb
Host smart-a71242ed-5e21-414d-905d-5e44e813c2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440130548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.3440130548
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.366340530
Short name T836
Test name
Test status
Simulation time 9836793834 ps
CPU time 79.33 seconds
Started Dec 27 01:02:01 PM PST 23
Finished Dec 27 01:03:21 PM PST 23
Peak memory 250504 kb
Host smart-269c7e50-d72d-48e8-93e5-b57ab778c26e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366340530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.366340530
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.3372032985
Short name T122
Test name
Test status
Simulation time 103442804736 ps
CPU time 6303.7 seconds
Started Dec 27 01:02:09 PM PST 23
Finished Dec 27 02:47:15 PM PST 23
Peak memory 1155112 kb
Host smart-2654ad3f-2d73-4182-9a3b-915facbd4e2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3372032985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.3372032985
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.637180692
Short name T764
Test name
Test status
Simulation time 153561324 ps
CPU time 1.16 seconds
Started Dec 27 01:01:59 PM PST 23
Finished Dec 27 01:02:00 PM PST 23
Peak memory 212696 kb
Host smart-29657d39-b4c7-4188-ba84-31c3d98efb28
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637180692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ct
rl_volatile_unlock_smoke.637180692
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.589864015
Short name T398
Test name
Test status
Simulation time 68437290 ps
CPU time 1.11 seconds
Started Dec 27 01:02:21 PM PST 23
Finished Dec 27 01:02:28 PM PST 23
Peak memory 209724 kb
Host smart-a485dc6c-5994-4180-90bf-031b190847df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589864015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.589864015
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.4146663115
Short name T948
Test name
Test status
Simulation time 1172392538 ps
CPU time 16.28 seconds
Started Dec 27 01:02:14 PM PST 23
Finished Dec 27 01:02:31 PM PST 23
Peak memory 218056 kb
Host smart-117fc36a-3b70-43c3-8509-489940d04509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146663115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.4146663115
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.2530882321
Short name T616
Test name
Test status
Simulation time 1615234745 ps
CPU time 18.32 seconds
Started Dec 27 01:02:20 PM PST 23
Finished Dec 27 01:02:42 PM PST 23
Peak memory 209688 kb
Host smart-f612a7c0-eeff-4e9b-a969-c24709d4bbd7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530882321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_a
ccess.2530882321
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.2036325201
Short name T313
Test name
Test status
Simulation time 15113670125 ps
CPU time 46.3 seconds
Started Dec 27 01:02:20 PM PST 23
Finished Dec 27 01:03:11 PM PST 23
Peak memory 218868 kb
Host smart-742cae43-e103-4e71-844c-43f9489e8c19
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036325201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.2036325201
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1736726041
Short name T421
Test name
Test status
Simulation time 144404103 ps
CPU time 3.62 seconds
Started Dec 27 01:02:20 PM PST 23
Finished Dec 27 01:02:28 PM PST 23
Peak memory 218088 kb
Host smart-5c619f2f-47a1-4866-a40a-69ef3dc8accf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736726041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1736726041
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.902292765
Short name T477
Test name
Test status
Simulation time 841595431 ps
CPU time 3.85 seconds
Started Dec 27 01:02:17 PM PST 23
Finished Dec 27 01:02:23 PM PST 23
Peak memory 213168 kb
Host smart-e125e0b6-9579-4cc2-b894-b55370b30d82
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902292765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke.
902292765
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3829032756
Short name T193
Test name
Test status
Simulation time 1572509018 ps
CPU time 17.63 seconds
Started Dec 27 01:02:05 PM PST 23
Finished Dec 27 01:02:25 PM PST 23
Peak memory 245592 kb
Host smart-3428f4f6-2e48-4127-97e7-a8d1290b6a10
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829032756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3829032756
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.581982599
Short name T410
Test name
Test status
Simulation time 371751327 ps
CPU time 3.41 seconds
Started Dec 27 01:02:05 PM PST 23
Finished Dec 27 01:02:12 PM PST 23
Peak memory 218120 kb
Host smart-1d524b6e-3b47-46d7-96ed-8831bd10776b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581982599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.581982599
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.874472137
Short name T340
Test name
Test status
Simulation time 482000718 ps
CPU time 11.79 seconds
Started Dec 27 01:02:16 PM PST 23
Finished Dec 27 01:02:30 PM PST 23
Peak memory 218128 kb
Host smart-df46eec3-5d71-47b9-a5e1-f2dc86c7da46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874472137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.874472137
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.3566444061
Short name T623
Test name
Test status
Simulation time 845261479 ps
CPU time 15.44 seconds
Started Dec 27 01:02:21 PM PST 23
Finished Dec 27 01:02:43 PM PST 23
Peak memory 218164 kb
Host smart-c2dc8f70-17ba-4c88-81d3-44fcebeb8d20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566444061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.3566444061
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.1786736611
Short name T526
Test name
Test status
Simulation time 1041661929 ps
CPU time 11.55 seconds
Started Dec 27 01:02:20 PM PST 23
Finished Dec 27 01:02:36 PM PST 23
Peak memory 218168 kb
Host smart-4c2f0c61-701e-45d2-b146-182d8eb28e8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786736611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
1786736611
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.1294019166
Short name T911
Test name
Test status
Simulation time 1590266074 ps
CPU time 9.35 seconds
Started Dec 27 01:02:18 PM PST 23
Finished Dec 27 01:02:31 PM PST 23
Peak memory 218184 kb
Host smart-1978c923-aa1e-4277-aa32-d54dc91705f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294019166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.1294019166
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.2090932601
Short name T60
Test name
Test status
Simulation time 301331673 ps
CPU time 5.85 seconds
Started Dec 27 01:02:05 PM PST 23
Finished Dec 27 01:02:14 PM PST 23
Peak memory 214520 kb
Host smart-16620dd9-2010-4e9a-89d7-3c13eb5fa8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090932601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.2090932601
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.3823609500
Short name T900
Test name
Test status
Simulation time 695975692 ps
CPU time 31.01 seconds
Started Dec 27 01:02:03 PM PST 23
Finished Dec 27 01:02:36 PM PST 23
Peak memory 251076 kb
Host smart-4eca6ec4-b725-4775-b1c4-3e7165267769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823609500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.3823609500
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.3105942551
Short name T821
Test name
Test status
Simulation time 150052338 ps
CPU time 8.14 seconds
Started Dec 27 01:02:02 PM PST 23
Finished Dec 27 01:02:11 PM PST 23
Peak memory 251172 kb
Host smart-aa259e35-862e-4353-b9cf-eb1476c052fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105942551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.3105942551
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.2310834731
Short name T581
Test name
Test status
Simulation time 4770705061 ps
CPU time 45.42 seconds
Started Dec 27 01:02:18 PM PST 23
Finished Dec 27 01:03:06 PM PST 23
Peak memory 267684 kb
Host smart-e3a428bb-d226-425f-8285-4bdbba71e148
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310834731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.2310834731
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.828173069
Short name T676
Test name
Test status
Simulation time 35958352 ps
CPU time 1.06 seconds
Started Dec 27 01:02:03 PM PST 23
Finished Dec 27 01:02:06 PM PST 23
Peak memory 212600 kb
Host smart-fa7725a6-e63b-491f-811d-40888de570ea
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828173069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct
rl_volatile_unlock_smoke.828173069
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.1993330173
Short name T418
Test name
Test status
Simulation time 100324256 ps
CPU time 0.84 seconds
Started Dec 27 01:02:03 PM PST 23
Finished Dec 27 01:02:04 PM PST 23
Peak memory 209592 kb
Host smart-d80851e6-a85f-4a7e-b0d1-391f3a42629b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993330173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.1993330173
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.71498474
Short name T978
Test name
Test status
Simulation time 1782554477 ps
CPU time 13.8 seconds
Started Dec 27 01:01:47 PM PST 23
Finished Dec 27 01:02:03 PM PST 23
Peak memory 218176 kb
Host smart-b9b2fe02-fd86-419d-b882-126137885929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71498474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.71498474
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.3181600864
Short name T871
Test name
Test status
Simulation time 592426795 ps
CPU time 14.12 seconds
Started Dec 27 01:01:47 PM PST 23
Finished Dec 27 01:02:02 PM PST 23
Peak memory 209684 kb
Host smart-fb43ae9f-5580-4fa4-9bab-d205e52eab34
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181600864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_a
ccess.3181600864
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.410878291
Short name T603
Test name
Test status
Simulation time 4628896038 ps
CPU time 36.69 seconds
Started Dec 27 01:02:04 PM PST 23
Finished Dec 27 01:02:44 PM PST 23
Peak memory 218324 kb
Host smart-2ed8d20f-49fb-4c6c-8c85-3c52ff87b9e2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410878291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_er
rors.410878291
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.3348281206
Short name T57
Test name
Test status
Simulation time 442901470 ps
CPU time 7.95 seconds
Started Dec 27 01:02:01 PM PST 23
Finished Dec 27 01:02:10 PM PST 23
Peak memory 218164 kb
Host smart-11942d95-b6f2-4749-b4d2-7a5760356ab8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348281206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.3348281206
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.813116006
Short name T587
Test name
Test status
Simulation time 2734552147 ps
CPU time 7.65 seconds
Started Dec 27 01:02:00 PM PST 23
Finished Dec 27 01:02:08 PM PST 23
Peak memory 213700 kb
Host smart-7ea7cdce-b130-4e6d-9aab-b38fbefd03b0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813116006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.
813116006
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2724409094
Short name T906
Test name
Test status
Simulation time 9984340227 ps
CPU time 61.61 seconds
Started Dec 27 01:01:51 PM PST 23
Finished Dec 27 01:02:53 PM PST 23
Peak memory 251172 kb
Host smart-f8cd5f73-c2b5-4951-a584-b6b709ab1132
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724409094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.2724409094
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.707681376
Short name T368
Test name
Test status
Simulation time 391539944 ps
CPU time 11.7 seconds
Started Dec 27 01:01:48 PM PST 23
Finished Dec 27 01:02:02 PM PST 23
Peak memory 250108 kb
Host smart-0c723ccf-4192-464e-b582-f273141a8701
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707681376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_
jtag_state_post_trans.707681376
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.3656344151
Short name T522
Test name
Test status
Simulation time 31628354 ps
CPU time 1.49 seconds
Started Dec 27 01:02:00 PM PST 23
Finished Dec 27 01:02:03 PM PST 23
Peak memory 218160 kb
Host smart-7a8fdd4d-5600-4902-aa54-375aaae182a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656344151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.3656344151
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.3789617065
Short name T820
Test name
Test status
Simulation time 1042284211 ps
CPU time 13.21 seconds
Started Dec 27 01:02:02 PM PST 23
Finished Dec 27 01:02:16 PM PST 23
Peak memory 218136 kb
Host smart-b82de0c3-66d8-4984-9bf0-6085f2ace68e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789617065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.3789617065
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.3670940884
Short name T774
Test name
Test status
Simulation time 2073461499 ps
CPU time 14.96 seconds
Started Dec 27 01:01:51 PM PST 23
Finished Dec 27 01:02:07 PM PST 23
Peak memory 218048 kb
Host smart-5bdc6927-f43a-4567-a758-55c3d6717f8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670940884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.3670940884
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.4274289173
Short name T487
Test name
Test status
Simulation time 1048095605 ps
CPU time 10.84 seconds
Started Dec 27 01:01:49 PM PST 23
Finished Dec 27 01:02:01 PM PST 23
Peak memory 218136 kb
Host smart-aee5be97-1c0e-438a-a6ea-35485bdd226d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274289173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
4274289173
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.2701575959
Short name T940
Test name
Test status
Simulation time 297359328 ps
CPU time 9.61 seconds
Started Dec 27 01:01:47 PM PST 23
Finished Dec 27 01:01:57 PM PST 23
Peak memory 218124 kb
Host smart-a0456b57-efe1-457e-97ae-8bee34e4ea3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701575959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.2701575959
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.2936980011
Short name T458
Test name
Test status
Simulation time 34746062 ps
CPU time 2.48 seconds
Started Dec 27 01:01:49 PM PST 23
Finished Dec 27 01:01:53 PM PST 23
Peak memory 214224 kb
Host smart-7912db49-efae-4a7e-8e4b-cc0d6e5a2f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936980011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2936980011
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.4041955817
Short name T835
Test name
Test status
Simulation time 242552254 ps
CPU time 27.83 seconds
Started Dec 27 01:01:59 PM PST 23
Finished Dec 27 01:02:28 PM PST 23
Peak memory 251140 kb
Host smart-5d35a604-3a8c-4c04-9302-9fc6e163633b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041955817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.4041955817
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.2249406102
Short name T766
Test name
Test status
Simulation time 305014225 ps
CPU time 2.93 seconds
Started Dec 27 01:01:50 PM PST 23
Finished Dec 27 01:01:54 PM PST 23
Peak memory 221984 kb
Host smart-3dd06da2-f884-4645-8956-82ccb2c0e1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249406102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.2249406102
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.2840078205
Short name T452
Test name
Test status
Simulation time 134979440963 ps
CPU time 408.13 seconds
Started Dec 27 01:02:02 PM PST 23
Finished Dec 27 01:08:51 PM PST 23
Peak memory 283932 kb
Host smart-e053be7e-ed5d-498d-9be7-8c44d2e9cd9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840078205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.2840078205
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.633051904
Short name T756
Test name
Test status
Simulation time 10329401 ps
CPU time 0.76 seconds
Started Dec 27 01:01:59 PM PST 23
Finished Dec 27 01:02:01 PM PST 23
Peak memory 208076 kb
Host smart-061f628a-4832-47c1-91e4-88e924b6890f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633051904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ct
rl_volatile_unlock_smoke.633051904
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.2859974583
Short name T974
Test name
Test status
Simulation time 12474703 ps
CPU time 0.82 seconds
Started Dec 27 01:02:10 PM PST 23
Finished Dec 27 01:02:12 PM PST 23
Peak memory 209588 kb
Host smart-2f85557d-6a6a-4f7a-b32f-f90ca7ec1026
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859974583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.2859974583
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.2806439712
Short name T462
Test name
Test status
Simulation time 321039937 ps
CPU time 13.67 seconds
Started Dec 27 01:01:47 PM PST 23
Finished Dec 27 01:02:02 PM PST 23
Peak memory 218240 kb
Host smart-2f126ce9-3ada-4207-8933-33b388161c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806439712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.2806439712
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.4173592119
Short name T396
Test name
Test status
Simulation time 6670774857 ps
CPU time 108.3 seconds
Started Dec 27 01:02:06 PM PST 23
Finished Dec 27 01:03:57 PM PST 23
Peak memory 218652 kb
Host smart-8ca0176c-aee2-4aa3-940d-03dbc9bc7ed3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173592119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.4173592119
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.945736478
Short name T864
Test name
Test status
Simulation time 2595265902 ps
CPU time 7.22 seconds
Started Dec 27 01:02:19 PM PST 23
Finished Dec 27 01:02:30 PM PST 23
Peak memory 218168 kb
Host smart-b8b335b5-f2b6-4cc9-888a-c55e56815c6f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945736478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag
_prog_failure.945736478
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.4215033698
Short name T812
Test name
Test status
Simulation time 685960229 ps
CPU time 5.6 seconds
Started Dec 27 01:02:18 PM PST 23
Finished Dec 27 01:02:27 PM PST 23
Peak memory 213444 kb
Host smart-ca14b03a-57b0-4bf6-9291-9649ae2bd24e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215033698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.4215033698
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.517173460
Short name T125
Test name
Test status
Simulation time 1418958488 ps
CPU time 32.96 seconds
Started Dec 27 01:02:02 PM PST 23
Finished Dec 27 01:02:36 PM PST 23
Peak memory 251068 kb
Host smart-a4e5d915-a375-4f05-a821-8507f7991a03
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517173460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_state_failure.517173460
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.999135674
Short name T737
Test name
Test status
Simulation time 877125919 ps
CPU time 17.09 seconds
Started Dec 27 01:02:05 PM PST 23
Finished Dec 27 01:02:25 PM PST 23
Peak memory 245544 kb
Host smart-0eb7c61f-3f95-4d05-bf3b-3a97eee4ad1c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999135674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_
jtag_state_post_trans.999135674
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.92937242
Short name T576
Test name
Test status
Simulation time 697641057 ps
CPU time 4.08 seconds
Started Dec 27 01:01:47 PM PST 23
Finished Dec 27 01:01:53 PM PST 23
Peak memory 218164 kb
Host smart-88d04d26-4471-4ccf-87d0-c50298676823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92937242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.92937242
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.1999515079
Short name T965
Test name
Test status
Simulation time 262711127 ps
CPU time 8.36 seconds
Started Dec 27 01:02:04 PM PST 23
Finished Dec 27 01:02:16 PM PST 23
Peak memory 218220 kb
Host smart-4544c59f-def1-4c54-96b9-6e22212dec5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999515079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.1999515079
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.575902783
Short name T554
Test name
Test status
Simulation time 464923639 ps
CPU time 9.78 seconds
Started Dec 27 01:02:20 PM PST 23
Finished Dec 27 01:02:33 PM PST 23
Peak memory 218040 kb
Host smart-dd437bf5-01f0-4ba2-b424-9e6d38871a62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575902783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_di
gest.575902783
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.4007284542
Short name T542
Test name
Test status
Simulation time 895786723 ps
CPU time 15.29 seconds
Started Dec 27 01:02:01 PM PST 23
Finished Dec 27 01:02:18 PM PST 23
Peak memory 218164 kb
Host smart-3696764d-4f0a-4e5e-9f41-8c914c62fcb7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007284542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
4007284542
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.23316271
Short name T631
Test name
Test status
Simulation time 708948451 ps
CPU time 14.33 seconds
Started Dec 27 01:02:17 PM PST 23
Finished Dec 27 01:02:34 PM PST 23
Peak memory 218216 kb
Host smart-8d93df99-341d-4a57-a5c1-f27f98e7b56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23316271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.23316271
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.3501892986
Short name T882
Test name
Test status
Simulation time 139523189 ps
CPU time 4.28 seconds
Started Dec 27 01:01:52 PM PST 23
Finished Dec 27 01:01:57 PM PST 23
Peak memory 213940 kb
Host smart-26e41609-9298-4c55-adb9-87eb2ee55a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501892986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.3501892986
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.2898092100
Short name T63
Test name
Test status
Simulation time 110641277 ps
CPU time 6.73 seconds
Started Dec 27 01:01:49 PM PST 23
Finished Dec 27 01:01:57 PM PST 23
Peak memory 246636 kb
Host smart-5fe54df8-36fc-4298-a7f4-37f7d43cf5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898092100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2898092100
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.3354662806
Short name T591
Test name
Test status
Simulation time 13465912341 ps
CPU time 251.92 seconds
Started Dec 27 01:02:04 PM PST 23
Finished Dec 27 01:06:18 PM PST 23
Peak memory 251260 kb
Host smart-b6e36392-a1f1-4706-800f-3bde471f16aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354662806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.3354662806
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2039103059
Short name T709
Test name
Test status
Simulation time 151284262 ps
CPU time 0.9 seconds
Started Dec 27 01:02:05 PM PST 23
Finished Dec 27 01:02:09 PM PST 23
Peak memory 208260 kb
Host smart-5f9326db-ee58-4239-aa0b-025b31edf8f4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039103059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.2039103059
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.1526693534
Short name T738
Test name
Test status
Simulation time 20920952 ps
CPU time 0.92 seconds
Started Dec 27 01:02:18 PM PST 23
Finished Dec 27 01:02:22 PM PST 23
Peak memory 209724 kb
Host smart-e1d13d34-b4ce-4d93-bc22-0d3b6214445b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526693534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.1526693534
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.1900769647
Short name T903
Test name
Test status
Simulation time 263049463 ps
CPU time 9.9 seconds
Started Dec 27 01:02:16 PM PST 23
Finished Dec 27 01:02:29 PM PST 23
Peak memory 218148 kb
Host smart-9180e2e4-0d74-43b1-adf8-e82b0890ccfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900769647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.1900769647
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.174141109
Short name T761
Test name
Test status
Simulation time 2341441564 ps
CPU time 5.76 seconds
Started Dec 27 01:02:16 PM PST 23
Finished Dec 27 01:02:24 PM PST 23
Peak memory 209664 kb
Host smart-43d2170a-9010-4375-a53a-25f5646d3b2d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174141109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_ac
cess.174141109
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.1222423073
Short name T818
Test name
Test status
Simulation time 7204889199 ps
CPU time 25.91 seconds
Started Dec 27 01:02:04 PM PST 23
Finished Dec 27 01:02:33 PM PST 23
Peak memory 218428 kb
Host smart-2d0f113e-bf9e-4b34-a862-c6ed9b2f8016
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222423073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.1222423073
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.1639376144
Short name T191
Test name
Test status
Simulation time 1427237388 ps
CPU time 10.52 seconds
Started Dec 27 01:02:00 PM PST 23
Finished Dec 27 01:02:11 PM PST 23
Peak memory 218032 kb
Host smart-b7381a33-0fff-4c7e-8605-1c8633767354
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639376144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.1639376144
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.1669274053
Short name T2
Test name
Test status
Simulation time 2236473659 ps
CPU time 13.39 seconds
Started Dec 27 01:02:04 PM PST 23
Finished Dec 27 01:02:19 PM PST 23
Peak memory 213532 kb
Host smart-06bff13d-db8e-4ecb-9ef1-f8316d4a0907
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669274053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.1669274053
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3384170462
Short name T723
Test name
Test status
Simulation time 3929677499 ps
CPU time 43.02 seconds
Started Dec 27 01:02:02 PM PST 23
Finished Dec 27 01:02:46 PM PST 23
Peak memory 251032 kb
Host smart-526da044-f714-4317-8298-63a42845ef7e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384170462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.3384170462
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.2766330917
Short name T630
Test name
Test status
Simulation time 1276142852 ps
CPU time 15.06 seconds
Started Dec 27 01:02:06 PM PST 23
Finished Dec 27 01:02:24 PM PST 23
Peak memory 251048 kb
Host smart-0fff4c81-6b0e-4522-9dcd-e9434cc6b014
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766330917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.2766330917
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.3305990595
Short name T870
Test name
Test status
Simulation time 70459006 ps
CPU time 3.83 seconds
Started Dec 27 01:02:18 PM PST 23
Finished Dec 27 01:02:25 PM PST 23
Peak memory 218208 kb
Host smart-a42963c1-17ee-44d8-851b-51a01c3b4d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305990595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3305990595
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.2441181143
Short name T962
Test name
Test status
Simulation time 278013153 ps
CPU time 12.73 seconds
Started Dec 27 01:02:06 PM PST 23
Finished Dec 27 01:02:21 PM PST 23
Peak memory 218236 kb
Host smart-fb000369-08ad-47cc-a995-5c24b057ade4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441181143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.2441181143
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.1221524315
Short name T768
Test name
Test status
Simulation time 978761872 ps
CPU time 15.48 seconds
Started Dec 27 01:02:05 PM PST 23
Finished Dec 27 01:02:24 PM PST 23
Peak memory 218136 kb
Host smart-c30a322b-9c8a-44f9-a1c6-dcf7aa861b32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221524315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.1221524315
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.907581066
Short name T598
Test name
Test status
Simulation time 485800763 ps
CPU time 9.89 seconds
Started Dec 27 01:02:01 PM PST 23
Finished Dec 27 01:02:12 PM PST 23
Peak memory 218172 kb
Host smart-889000ee-893d-4736-ac46-b06f29f071aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907581066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.907581066
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.230887343
Short name T782
Test name
Test status
Simulation time 514282876 ps
CPU time 10.03 seconds
Started Dec 27 01:02:03 PM PST 23
Finished Dec 27 01:02:15 PM PST 23
Peak memory 218224 kb
Host smart-c4debdc8-2d87-4ca8-a717-a9e601cffedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230887343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.230887343
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.3224758250
Short name T455
Test name
Test status
Simulation time 39342319 ps
CPU time 2.11 seconds
Started Dec 27 01:02:16 PM PST 23
Finished Dec 27 01:02:21 PM PST 23
Peak memory 213636 kb
Host smart-eee73fb0-1f75-4208-a9c0-f51318374726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224758250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.3224758250
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.1917688257
Short name T574
Test name
Test status
Simulation time 1457544067 ps
CPU time 27.79 seconds
Started Dec 27 01:02:18 PM PST 23
Finished Dec 27 01:02:49 PM PST 23
Peak memory 245920 kb
Host smart-c4c1df6d-6c22-4138-a460-876355847ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917688257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.1917688257
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.1023921758
Short name T559
Test name
Test status
Simulation time 82001144 ps
CPU time 6.55 seconds
Started Dec 27 01:02:07 PM PST 23
Finished Dec 27 01:02:16 PM PST 23
Peak memory 250400 kb
Host smart-c7adca94-9c2f-4b4f-b33d-6a2aa8fff023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023921758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.1023921758
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.2811416921
Short name T934
Test name
Test status
Simulation time 2461981651 ps
CPU time 75.96 seconds
Started Dec 27 01:02:09 PM PST 23
Finished Dec 27 01:03:27 PM PST 23
Peak memory 282512 kb
Host smart-fd943b33-80ef-4099-ab3e-02bb92d2426f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811416921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.2811416921
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.936628170
Short name T362
Test name
Test status
Simulation time 12988090 ps
CPU time 0.81 seconds
Started Dec 27 01:02:04 PM PST 23
Finished Dec 27 01:02:08 PM PST 23
Peak memory 208608 kb
Host smart-f13eda66-4929-47c3-b0c2-e5ca0d08c618
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936628170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ct
rl_volatile_unlock_smoke.936628170
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.1710161838
Short name T426
Test name
Test status
Simulation time 34012996 ps
CPU time 0.91 seconds
Started Dec 27 01:01:04 PM PST 23
Finished Dec 27 01:01:08 PM PST 23
Peak memory 209624 kb
Host smart-bb178763-1833-4341-970a-287753e0fd6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710161838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.1710161838
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.1541007584
Short name T443
Test name
Test status
Simulation time 14288649 ps
CPU time 0.86 seconds
Started Dec 27 01:00:58 PM PST 23
Finished Dec 27 01:01:03 PM PST 23
Peak memory 209464 kb
Host smart-91563abc-fc51-4250-9f85-950b959dd3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541007584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.1541007584
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.3864855316
Short name T928
Test name
Test status
Simulation time 1479603942 ps
CPU time 10.89 seconds
Started Dec 27 01:01:05 PM PST 23
Finished Dec 27 01:01:19 PM PST 23
Peak memory 218096 kb
Host smart-316037d8-af3e-4e70-8d2d-bf5ad6281938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864855316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.3864855316
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.775082417
Short name T838
Test name
Test status
Simulation time 805563048 ps
CPU time 18.83 seconds
Started Dec 27 01:01:07 PM PST 23
Finished Dec 27 01:01:28 PM PST 23
Peak memory 209684 kb
Host smart-e95fc06e-c17d-45ff-a631-ac9df2e4a78c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775082417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_acc
ess.775082417
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.1429187931
Short name T48
Test name
Test status
Simulation time 3179987514 ps
CPU time 85.95 seconds
Started Dec 27 01:01:09 PM PST 23
Finished Dec 27 01:02:39 PM PST 23
Peak memory 219236 kb
Host smart-b61c05bf-59cc-4a11-a116-29966fd924a7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429187931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.1429187931
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.2397500501
Short name T708
Test name
Test status
Simulation time 919593043 ps
CPU time 11.61 seconds
Started Dec 27 01:00:52 PM PST 23
Finished Dec 27 01:01:11 PM PST 23
Peak memory 217968 kb
Host smart-5be6f10f-db43-449b-a39f-19f1ea1a110c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397500501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_
priority.2397500501
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3594812546
Short name T613
Test name
Test status
Simulation time 1164817822 ps
CPU time 8.8 seconds
Started Dec 27 01:01:12 PM PST 23
Finished Dec 27 01:01:26 PM PST 23
Peak memory 218140 kb
Host smart-a2bb80cb-8600-4739-86ad-8e2ef4286fda
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594812546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.3594812546
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.30386492
Short name T886
Test name
Test status
Simulation time 2613799276 ps
CPU time 35.56 seconds
Started Dec 27 01:01:05 PM PST 23
Finished Dec 27 01:01:44 PM PST 23
Peak memory 213704 kb
Host smart-b5c37ed8-5b7e-490c-85fc-a3bb15d898d5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30386492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jt
ag_regwen_during_op.30386492
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.2789366847
Short name T701
Test name
Test status
Simulation time 859224398 ps
CPU time 7.08 seconds
Started Dec 27 01:01:10 PM PST 23
Finished Dec 27 01:01:21 PM PST 23
Peak memory 213500 kb
Host smart-64a3841c-9619-41fc-a687-5216055a0048
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789366847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
2789366847
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.2265524056
Short name T314
Test name
Test status
Simulation time 7130973785 ps
CPU time 46.93 seconds
Started Dec 27 01:01:03 PM PST 23
Finished Dec 27 01:01:53 PM PST 23
Peak memory 276732 kb
Host smart-a3fd4cf5-d511-46f0-9b4d-3e4b9b970e1a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265524056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.2265524056
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.1277622290
Short name T429
Test name
Test status
Simulation time 4151183323 ps
CPU time 18.09 seconds
Started Dec 27 01:01:07 PM PST 23
Finished Dec 27 01:01:28 PM PST 23
Peak memory 250028 kb
Host smart-e5907749-034d-46f1-848f-cf883fe0192a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277622290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.1277622290
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.3695679760
Short name T779
Test name
Test status
Simulation time 25407683 ps
CPU time 1.68 seconds
Started Dec 27 01:01:02 PM PST 23
Finished Dec 27 01:01:07 PM PST 23
Peak memory 218220 kb
Host smart-ef8bf0cf-52d1-479c-88d3-11c49afed294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695679760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.3695679760
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2603332543
Short name T494
Test name
Test status
Simulation time 1119380893 ps
CPU time 10.35 seconds
Started Dec 27 01:01:09 PM PST 23
Finished Dec 27 01:01:24 PM PST 23
Peak memory 214108 kb
Host smart-9c15c1ed-911e-4191-af74-9c330c22d69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603332543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2603332543
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.3183582542
Short name T99
Test name
Test status
Simulation time 266206122 ps
CPU time 23.12 seconds
Started Dec 27 01:01:07 PM PST 23
Finished Dec 27 01:01:33 PM PST 23
Peak memory 272600 kb
Host smart-48bbd9b0-c3f2-4fe3-a02a-9724600d251f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183582542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.3183582542
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.471916251
Short name T673
Test name
Test status
Simulation time 751325510 ps
CPU time 10.7 seconds
Started Dec 27 01:01:11 PM PST 23
Finished Dec 27 01:01:25 PM PST 23
Peak memory 218140 kb
Host smart-7df51aae-57fb-4714-9ab4-fff3510a0fd8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471916251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.471916251
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.250079818
Short name T571
Test name
Test status
Simulation time 722163940 ps
CPU time 6.63 seconds
Started Dec 27 01:01:14 PM PST 23
Finished Dec 27 01:01:25 PM PST 23
Peak memory 218072 kb
Host smart-308644f6-4051-44e0-ad1e-e1b8be8ddfcc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250079818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_dig
est.250079818
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.1889406350
Short name T691
Test name
Test status
Simulation time 266751791 ps
CPU time 6.95 seconds
Started Dec 27 01:01:08 PM PST 23
Finished Dec 27 01:01:19 PM PST 23
Peak memory 218080 kb
Host smart-0cd7ff30-a775-4a01-9f56-65bdb0f8cbbb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889406350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.1
889406350
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.2837854917
Short name T81
Test name
Test status
Simulation time 485010602 ps
CPU time 13.38 seconds
Started Dec 27 01:01:09 PM PST 23
Finished Dec 27 01:01:27 PM PST 23
Peak memory 218220 kb
Host smart-e32d54b3-a293-4cab-a0b1-8e1781ce05ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837854917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.2837854917
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.1331431924
Short name T70
Test name
Test status
Simulation time 35517629 ps
CPU time 2.48 seconds
Started Dec 27 01:01:02 PM PST 23
Finished Dec 27 01:01:07 PM PST 23
Peak memory 213412 kb
Host smart-c35617f2-4050-4e12-9b0a-9a8b64741f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331431924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.1331431924
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.445702447
Short name T772
Test name
Test status
Simulation time 1057246680 ps
CPU time 37.58 seconds
Started Dec 27 01:01:07 PM PST 23
Finished Dec 27 01:01:48 PM PST 23
Peak memory 251140 kb
Host smart-8f0eb6a1-d970-4f9b-8e0f-c569a4a5d280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445702447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.445702447
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.1248548720
Short name T8
Test name
Test status
Simulation time 70830393 ps
CPU time 6.56 seconds
Started Dec 27 01:01:17 PM PST 23
Finished Dec 27 01:01:29 PM PST 23
Peak memory 244092 kb
Host smart-3a7a28cc-1ab7-4529-a942-2377c5a1e792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248548720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.1248548720
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.4159274725
Short name T686
Test name
Test status
Simulation time 55883725046 ps
CPU time 254.11 seconds
Started Dec 27 01:01:15 PM PST 23
Finished Dec 27 01:05:34 PM PST 23
Peak memory 267616 kb
Host smart-67d607d6-3b86-48e9-b893-25968eb08c98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159274725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.4159274725
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.3556201437
Short name T953
Test name
Test status
Simulation time 20083727 ps
CPU time 0.88 seconds
Started Dec 27 01:00:59 PM PST 23
Finished Dec 27 01:01:04 PM PST 23
Peak memory 208648 kb
Host smart-b09a00bb-b1f8-47f9-b177-faeac08aeed0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556201437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.3556201437
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.3216310351
Short name T734
Test name
Test status
Simulation time 319305343 ps
CPU time 10.74 seconds
Started Dec 27 01:02:04 PM PST 23
Finished Dec 27 01:02:17 PM PST 23
Peak memory 218204 kb
Host smart-748c068c-84c9-489d-a487-7f5375b99962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216310351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.3216310351
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.3532803586
Short name T710
Test name
Test status
Simulation time 184472598 ps
CPU time 3.95 seconds
Started Dec 27 01:02:18 PM PST 23
Finished Dec 27 01:02:25 PM PST 23
Peak memory 209672 kb
Host smart-ede099b7-50a1-4e56-b0df-f952a9685180
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532803586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_a
ccess.3532803586
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.61371364
Short name T383
Test name
Test status
Simulation time 107853123 ps
CPU time 2.48 seconds
Started Dec 27 01:02:07 PM PST 23
Finished Dec 27 01:02:12 PM PST 23
Peak memory 218220 kb
Host smart-f9680ccd-f5c6-42be-8c3b-35f8cadb23a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61371364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.61371364
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.3188317214
Short name T666
Test name
Test status
Simulation time 612956060 ps
CPU time 10.93 seconds
Started Dec 27 01:02:16 PM PST 23
Finished Dec 27 01:02:30 PM PST 23
Peak memory 218204 kb
Host smart-619aa5b6-0e90-4d61-ae42-1b936ec782e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188317214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.3188317214
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.359221051
Short name T413
Test name
Test status
Simulation time 928042590 ps
CPU time 20.43 seconds
Started Dec 27 01:02:18 PM PST 23
Finished Dec 27 01:02:41 PM PST 23
Peak memory 218136 kb
Host smart-7dbd1280-dfa5-4f3c-8c53-8c932b119f98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359221051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_di
gest.359221051
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.598113964
Short name T854
Test name
Test status
Simulation time 196332433 ps
CPU time 6.36 seconds
Started Dec 27 01:02:17 PM PST 23
Finished Dec 27 01:02:26 PM PST 23
Peak memory 218052 kb
Host smart-f5b8f03c-d6ec-4509-844b-c0c9c207f5ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598113964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.598113964
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.1865098184
Short name T183
Test name
Test status
Simulation time 662939331 ps
CPU time 10.23 seconds
Started Dec 27 01:02:18 PM PST 23
Finished Dec 27 01:02:31 PM PST 23
Peak memory 218212 kb
Host smart-c4ec7333-849a-4956-800a-0c329580d379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865098184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.1865098184
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.1438985432
Short name T952
Test name
Test status
Simulation time 259935746 ps
CPU time 2.43 seconds
Started Dec 27 01:02:17 PM PST 23
Finished Dec 27 01:02:22 PM PST 23
Peak memory 213756 kb
Host smart-eaa2a20d-1cce-461e-94bb-26bbda961a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438985432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.1438985432
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.1734367608
Short name T530
Test name
Test status
Simulation time 448699576 ps
CPU time 34.68 seconds
Started Dec 27 01:02:11 PM PST 23
Finished Dec 27 01:02:46 PM PST 23
Peak memory 251084 kb
Host smart-f7aba43d-98bc-43ee-b95d-d12c25ea4e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734367608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.1734367608
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.2168091056
Short name T190
Test name
Test status
Simulation time 431910787 ps
CPU time 7.63 seconds
Started Dec 27 01:02:16 PM PST 23
Finished Dec 27 01:02:26 PM PST 23
Peak memory 251112 kb
Host smart-f4f1fae2-c30d-4eff-b6d0-e8c48868a61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168091056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.2168091056
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.3249480239
Short name T55
Test name
Test status
Simulation time 5574622388 ps
CPU time 69.82 seconds
Started Dec 27 01:02:22 PM PST 23
Finished Dec 27 01:03:37 PM PST 23
Peak memory 251292 kb
Host smart-5b75006a-23c2-4652-90fe-9041cf7f1050
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249480239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.3249480239
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.1526929316
Short name T719
Test name
Test status
Simulation time 17819427 ps
CPU time 1.16 seconds
Started Dec 27 01:02:16 PM PST 23
Finished Dec 27 01:02:19 PM PST 23
Peak memory 208472 kb
Host smart-abf087c4-6038-4dbe-87c4-9e5bfd45c728
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526929316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.1526929316
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.93691668
Short name T762
Test name
Test status
Simulation time 235601826 ps
CPU time 7.14 seconds
Started Dec 27 01:02:21 PM PST 23
Finished Dec 27 01:02:34 PM PST 23
Peak memory 218228 kb
Host smart-3b643ce8-2675-48d9-9c1b-cc44b50baf5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93691668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.93691668
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.854110089
Short name T21
Test name
Test status
Simulation time 285686102 ps
CPU time 4.75 seconds
Started Dec 27 01:02:32 PM PST 23
Finished Dec 27 01:02:43 PM PST 23
Peak memory 209668 kb
Host smart-d92d055d-1134-4dd7-9c4c-5c50f6edf363
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854110089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_ac
cess.854110089
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.2130465594
Short name T438
Test name
Test status
Simulation time 30969357 ps
CPU time 2.09 seconds
Started Dec 27 01:02:21 PM PST 23
Finished Dec 27 01:02:29 PM PST 23
Peak memory 218088 kb
Host smart-6a60614d-f6e6-4e22-86ac-349ca1c0714f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130465594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.2130465594
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.616531088
Short name T876
Test name
Test status
Simulation time 4209106767 ps
CPU time 13.64 seconds
Started Dec 27 01:02:21 PM PST 23
Finished Dec 27 01:02:41 PM PST 23
Peak memory 218288 kb
Host smart-9522c4b4-f78c-48b7-910a-d29466a12407
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616531088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.616531088
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.4069821594
Short name T908
Test name
Test status
Simulation time 916850868 ps
CPU time 9.47 seconds
Started Dec 27 01:02:21 PM PST 23
Finished Dec 27 01:02:36 PM PST 23
Peak memory 218152 kb
Host smart-e0cba097-10e5-4c6c-88b8-4506fe4de3c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069821594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.4069821594
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.1404941361
Short name T976
Test name
Test status
Simulation time 663351115 ps
CPU time 13.07 seconds
Started Dec 27 01:02:22 PM PST 23
Finished Dec 27 01:02:40 PM PST 23
Peak memory 218164 kb
Host smart-e0d74179-293d-4425-bc98-e0b25551acee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404941361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
1404941361
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.2384467666
Short name T860
Test name
Test status
Simulation time 1116830811 ps
CPU time 12.21 seconds
Started Dec 27 01:02:21 PM PST 23
Finished Dec 27 01:02:39 PM PST 23
Peak memory 218200 kb
Host smart-ecfe82fd-16c8-491a-a8da-86f9d08219e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384467666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.2384467666
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.3451871259
Short name T757
Test name
Test status
Simulation time 107974823 ps
CPU time 1.37 seconds
Started Dec 27 01:02:21 PM PST 23
Finished Dec 27 01:02:27 PM PST 23
Peak memory 213320 kb
Host smart-dd72f4f0-0987-4c72-909a-808d0b5b402e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451871259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.3451871259
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.1503829078
Short name T675
Test name
Test status
Simulation time 326232475 ps
CPU time 29.49 seconds
Started Dec 27 01:02:21 PM PST 23
Finished Dec 27 01:02:56 PM PST 23
Peak memory 251132 kb
Host smart-691c7b6c-f41f-49b1-88bb-4d1f7213102e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503829078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.1503829078
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.1610684445
Short name T967
Test name
Test status
Simulation time 74792929 ps
CPU time 3.6 seconds
Started Dec 27 01:02:21 PM PST 23
Finished Dec 27 01:02:30 PM PST 23
Peak memory 218204 kb
Host smart-5a99845b-16a9-4c45-ad6b-38ea78a53fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610684445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.1610684445
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.3689423620
Short name T453
Test name
Test status
Simulation time 6755000829 ps
CPU time 245.47 seconds
Started Dec 27 01:02:32 PM PST 23
Finished Dec 27 01:06:43 PM PST 23
Peak memory 283948 kb
Host smart-bcca2c59-2962-444b-9f2a-3219b6681b1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689423620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.3689423620
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.3311623375
Short name T485
Test name
Test status
Simulation time 37582907 ps
CPU time 0.78 seconds
Started Dec 27 01:02:20 PM PST 23
Finished Dec 27 01:02:25 PM PST 23
Peak memory 208024 kb
Host smart-7a78f7fc-20da-4d12-948c-6c0e89dd5f6a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311623375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.3311623375
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.2666904341
Short name T594
Test name
Test status
Simulation time 41128587 ps
CPU time 0.81 seconds
Started Dec 27 01:02:06 PM PST 23
Finished Dec 27 01:02:10 PM PST 23
Peak memory 208160 kb
Host smart-6cd0bae7-b716-4dbc-af60-731f083a4b14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666904341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.2666904341
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.1300517091
Short name T528
Test name
Test status
Simulation time 302861408 ps
CPU time 13.36 seconds
Started Dec 27 01:02:17 PM PST 23
Finished Dec 27 01:02:34 PM PST 23
Peak memory 218212 kb
Host smart-91adef3e-9e0d-4307-a708-45aa2aed7fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300517091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.1300517091
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.498232506
Short name T6
Test name
Test status
Simulation time 1533336839 ps
CPU time 9.72 seconds
Started Dec 27 01:02:05 PM PST 23
Finished Dec 27 01:02:18 PM PST 23
Peak memory 209644 kb
Host smart-02d8b88c-6d2d-4f9a-93ac-ff5d0e0278e9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498232506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_ac
cess.498232506
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.3647181213
Short name T725
Test name
Test status
Simulation time 76360299 ps
CPU time 3.87 seconds
Started Dec 27 01:02:04 PM PST 23
Finished Dec 27 01:02:11 PM PST 23
Peak memory 218164 kb
Host smart-6d622fa1-7ea8-4342-9733-20836b6a6b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647181213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.3647181213
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.4089851427
Short name T760
Test name
Test status
Simulation time 1733558346 ps
CPU time 13.35 seconds
Started Dec 27 01:02:18 PM PST 23
Finished Dec 27 01:02:35 PM PST 23
Peak memory 219260 kb
Host smart-b523ea69-4745-4e7f-a69f-f6f823e83e71
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089851427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.4089851427
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.2017418096
Short name T899
Test name
Test status
Simulation time 381890890 ps
CPU time 14.44 seconds
Started Dec 27 01:02:06 PM PST 23
Finished Dec 27 01:02:23 PM PST 23
Peak memory 218100 kb
Host smart-bc3092bf-1a24-4f4d-996c-0cd117c70245
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017418096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.2017418096
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.4087374681
Short name T625
Test name
Test status
Simulation time 462958521 ps
CPU time 15.17 seconds
Started Dec 27 01:02:16 PM PST 23
Finished Dec 27 01:02:34 PM PST 23
Peak memory 218156 kb
Host smart-69c57c49-7536-4c14-a1a4-09e99031da4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087374681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
4087374681
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.283452687
Short name T184
Test name
Test status
Simulation time 267088046 ps
CPU time 9.61 seconds
Started Dec 27 01:02:07 PM PST 23
Finished Dec 27 01:02:19 PM PST 23
Peak memory 218124 kb
Host smart-9e1375ec-4649-4787-a708-fda0970689aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283452687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.283452687
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.904300481
Short name T729
Test name
Test status
Simulation time 45097666 ps
CPU time 2.63 seconds
Started Dec 27 01:02:04 PM PST 23
Finished Dec 27 01:02:09 PM PST 23
Peak memory 213968 kb
Host smart-8c70bacc-e281-43d6-9392-bd70916c5b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904300481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.904300481
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.1197310451
Short name T365
Test name
Test status
Simulation time 4274801473 ps
CPU time 24.3 seconds
Started Dec 27 01:02:12 PM PST 23
Finished Dec 27 01:02:37 PM PST 23
Peak memory 251212 kb
Host smart-a4e0bad0-d244-4346-b2e6-6a93addfc98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197310451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.1197310451
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.4253341920
Short name T649
Test name
Test status
Simulation time 95352094 ps
CPU time 3.39 seconds
Started Dec 27 01:02:05 PM PST 23
Finished Dec 27 01:02:11 PM PST 23
Peak memory 222952 kb
Host smart-4b0dab95-2e31-4c6e-bf5f-4131d07ebd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253341920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.4253341920
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.2671631627
Short name T730
Test name
Test status
Simulation time 14255385555 ps
CPU time 112.24 seconds
Started Dec 27 01:02:17 PM PST 23
Finished Dec 27 01:04:12 PM PST 23
Peak memory 296648 kb
Host smart-60ace333-dbad-4f0b-b1c3-7617a939a283
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671631627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.2671631627
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.1388357609
Short name T939
Test name
Test status
Simulation time 17681129 ps
CPU time 0.87 seconds
Started Dec 27 01:02:18 PM PST 23
Finished Dec 27 01:02:22 PM PST 23
Peak memory 208288 kb
Host smart-da1c2738-076a-485b-bbeb-357a548fd470
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388357609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.1388357609
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.2319999385
Short name T670
Test name
Test status
Simulation time 72148793 ps
CPU time 0.87 seconds
Started Dec 27 01:02:18 PM PST 23
Finished Dec 27 01:02:22 PM PST 23
Peak memory 209692 kb
Host smart-40809d45-892b-4416-8d92-4e0898a2e951
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319999385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.2319999385
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.2231870723
Short name T796
Test name
Test status
Simulation time 2630028498 ps
CPU time 16.09 seconds
Started Dec 27 01:02:16 PM PST 23
Finished Dec 27 01:02:35 PM PST 23
Peak memory 218260 kb
Host smart-606a3ac6-2286-4a22-9d4c-7d4dcba9316c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231870723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.2231870723
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.2016455743
Short name T388
Test name
Test status
Simulation time 932749543 ps
CPU time 11.68 seconds
Started Dec 27 01:02:04 PM PST 23
Finished Dec 27 01:02:18 PM PST 23
Peak memory 209632 kb
Host smart-6b60f9f5-28f7-4ba9-b5f6-b2d01c7c25e1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016455743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_a
ccess.2016455743
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.2116334800
Short name T806
Test name
Test status
Simulation time 56660585 ps
CPU time 1.42 seconds
Started Dec 27 01:02:18 PM PST 23
Finished Dec 27 01:02:22 PM PST 23
Peak memory 218192 kb
Host smart-13590616-2e0e-467c-af19-02f5fd3c9b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116334800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.2116334800
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.166684459
Short name T658
Test name
Test status
Simulation time 481912079 ps
CPU time 11.02 seconds
Started Dec 27 01:02:05 PM PST 23
Finished Dec 27 01:02:19 PM PST 23
Peak memory 218204 kb
Host smart-a8c95963-baf4-4a75-ad94-fa6fe841dfc0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166684459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.166684459
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.3556854700
Short name T533
Test name
Test status
Simulation time 614490337 ps
CPU time 11.33 seconds
Started Dec 27 01:02:08 PM PST 23
Finished Dec 27 01:02:21 PM PST 23
Peak memory 218116 kb
Host smart-282df80e-21ca-4ffe-9b1e-8bd48aca5172
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556854700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.3556854700
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.1774615226
Short name T88
Test name
Test status
Simulation time 277360739 ps
CPU time 9.78 seconds
Started Dec 27 01:02:03 PM PST 23
Finished Dec 27 01:02:14 PM PST 23
Peak memory 218160 kb
Host smart-9c197962-9d81-49df-8a62-5ac5909762af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774615226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
1774615226
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.1351679184
Short name T492
Test name
Test status
Simulation time 1041898935 ps
CPU time 10.48 seconds
Started Dec 27 01:02:04 PM PST 23
Finished Dec 27 01:02:15 PM PST 23
Peak memory 218220 kb
Host smart-ba82f628-d1d1-434e-8993-259d77d79921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351679184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.1351679184
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.2441704337
Short name T422
Test name
Test status
Simulation time 196358582 ps
CPU time 2.22 seconds
Started Dec 27 01:02:03 PM PST 23
Finished Dec 27 01:02:06 PM PST 23
Peak memory 213752 kb
Host smart-dc3d6f83-828a-4842-a62f-0b191b20e860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441704337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.2441704337
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.4140424026
Short name T318
Test name
Test status
Simulation time 933672455 ps
CPU time 26.08 seconds
Started Dec 27 01:02:18 PM PST 23
Finished Dec 27 01:02:47 PM PST 23
Peak memory 251076 kb
Host smart-325604d7-6ff6-4e0f-b258-7858887c1ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140424026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.4140424026
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.3744656420
Short name T556
Test name
Test status
Simulation time 282360576 ps
CPU time 6.77 seconds
Started Dec 27 01:02:12 PM PST 23
Finished Dec 27 01:02:19 PM PST 23
Peak memory 250648 kb
Host smart-941dd9b1-4df5-4a04-9ba5-52779750e7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744656420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.3744656420
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.2544097373
Short name T75
Test name
Test status
Simulation time 2540646894 ps
CPU time 73.83 seconds
Started Dec 27 01:02:07 PM PST 23
Finished Dec 27 01:03:23 PM PST 23
Peak memory 219988 kb
Host smart-051be456-f511-4062-87e7-7e54a6613f36
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544097373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.2544097373
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1138276283
Short name T374
Test name
Test status
Simulation time 14661698 ps
CPU time 1.12 seconds
Started Dec 27 01:02:04 PM PST 23
Finished Dec 27 01:02:08 PM PST 23
Peak memory 211444 kb
Host smart-659aeb9a-e43e-4522-85fe-41befd47b2ba
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138276283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.1138276283
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.898456676
Short name T101
Test name
Test status
Simulation time 24551929 ps
CPU time 1.25 seconds
Started Dec 27 01:02:17 PM PST 23
Finished Dec 27 01:02:20 PM PST 23
Peak memory 209664 kb
Host smart-cd8436df-2efb-4d44-9724-48a09078b078
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898456676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.898456676
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.3482937389
Short name T671
Test name
Test status
Simulation time 324248679 ps
CPU time 12.52 seconds
Started Dec 27 01:02:18 PM PST 23
Finished Dec 27 01:02:33 PM PST 23
Peak memory 218212 kb
Host smart-3cd01539-3160-4356-87f8-215032f8862c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482937389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.3482937389
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.2157326799
Short name T480
Test name
Test status
Simulation time 67960692 ps
CPU time 1.6 seconds
Started Dec 27 01:02:17 PM PST 23
Finished Dec 27 01:02:21 PM PST 23
Peak memory 209632 kb
Host smart-ef2f381e-b4dc-4370-94eb-87ea08c195ee
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157326799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_a
ccess.2157326799
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.2561030860
Short name T488
Test name
Test status
Simulation time 85834327 ps
CPU time 2.38 seconds
Started Dec 27 01:02:20 PM PST 23
Finished Dec 27 01:02:26 PM PST 23
Peak memory 218188 kb
Host smart-768dea8d-97ee-430f-93c9-637a9eb31f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561030860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.2561030860
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.2145774961
Short name T933
Test name
Test status
Simulation time 398407847 ps
CPU time 17.62 seconds
Started Dec 27 01:02:20 PM PST 23
Finished Dec 27 01:02:42 PM PST 23
Peak memory 219148 kb
Host smart-0c39f6a7-cff7-4d84-b2de-97e4fd7181cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145774961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.2145774961
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.215403845
Short name T922
Test name
Test status
Simulation time 490358639 ps
CPU time 10.54 seconds
Started Dec 27 01:02:20 PM PST 23
Finished Dec 27 01:02:34 PM PST 23
Peak memory 218124 kb
Host smart-ec450443-cbe1-4ffa-bde8-92f59a5d1dd0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215403845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_di
gest.215403845
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.2013221588
Short name T813
Test name
Test status
Simulation time 176617140 ps
CPU time 5.98 seconds
Started Dec 27 01:02:19 PM PST 23
Finished Dec 27 01:02:29 PM PST 23
Peak memory 218156 kb
Host smart-9352603c-3507-45e4-a940-f34213d0dd98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013221588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
2013221588
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.2285010579
Short name T529
Test name
Test status
Simulation time 1368763472 ps
CPU time 10 seconds
Started Dec 27 01:02:21 PM PST 23
Finished Dec 27 01:02:36 PM PST 23
Peak memory 218080 kb
Host smart-1041ac17-3561-49fa-9bd4-0a56c47f33ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285010579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.2285010579
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.547179705
Short name T901
Test name
Test status
Simulation time 212929591 ps
CPU time 2.1 seconds
Started Dec 27 01:02:20 PM PST 23
Finished Dec 27 01:02:27 PM PST 23
Peak memory 213420 kb
Host smart-89a7f642-ae0b-43fc-a469-20584d06c960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547179705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.547179705
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.4009980430
Short name T544
Test name
Test status
Simulation time 300299426 ps
CPU time 26.72 seconds
Started Dec 27 01:02:15 PM PST 23
Finished Dec 27 01:02:44 PM PST 23
Peak memory 251092 kb
Host smart-1564d333-6170-45bc-868e-53f39bbd1cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009980430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.4009980430
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.71460084
Short name T408
Test name
Test status
Simulation time 66225733 ps
CPU time 7.82 seconds
Started Dec 27 01:02:21 PM PST 23
Finished Dec 27 01:02:34 PM PST 23
Peak memory 251152 kb
Host smart-d445e9a5-61c3-42a0-aa1b-03c55c78bb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71460084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.71460084
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.4180393994
Short name T543
Test name
Test status
Simulation time 2309355630 ps
CPU time 71.66 seconds
Started Dec 27 01:02:17 PM PST 23
Finished Dec 27 01:03:32 PM PST 23
Peak memory 251232 kb
Host smart-988b39b7-7eaa-4b3f-af81-f0cd363bb195
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180393994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.4180393994
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2531351039
Short name T431
Test name
Test status
Simulation time 13862424 ps
CPU time 0.82 seconds
Started Dec 27 01:02:11 PM PST 23
Finished Dec 27 01:02:13 PM PST 23
Peak memory 208076 kb
Host smart-d9d6ebd3-952b-4d9a-9660-508e6bd0efe3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531351039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.2531351039
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.3772538751
Short name T300
Test name
Test status
Simulation time 19634651 ps
CPU time 1.09 seconds
Started Dec 27 01:02:23 PM PST 23
Finished Dec 27 01:02:30 PM PST 23
Peak memory 209752 kb
Host smart-0fecb8c2-15c0-4d93-b5d1-8165b9ef8db9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772538751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.3772538751
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.4220966659
Short name T510
Test name
Test status
Simulation time 755964110 ps
CPU time 10 seconds
Started Dec 27 01:02:18 PM PST 23
Finished Dec 27 01:02:31 PM PST 23
Peak memory 218128 kb
Host smart-c3801612-eb4d-4254-8480-4d2245ea1925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220966659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.4220966659
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.812150849
Short name T828
Test name
Test status
Simulation time 3165320884 ps
CPU time 17.21 seconds
Started Dec 27 01:02:19 PM PST 23
Finished Dec 27 01:02:39 PM PST 23
Peak memory 217932 kb
Host smart-8a5c2208-b8a0-48d1-bd46-2532a93a2eb5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812150849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_ac
cess.812150849
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.796123910
Short name T843
Test name
Test status
Simulation time 295144188 ps
CPU time 3.65 seconds
Started Dec 27 01:02:16 PM PST 23
Finished Dec 27 01:02:23 PM PST 23
Peak memory 218108 kb
Host smart-ca0530bb-2cc5-4fe7-a0be-38e71a77b961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796123910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.796123910
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.58858372
Short name T667
Test name
Test status
Simulation time 536024536 ps
CPU time 11.47 seconds
Started Dec 27 01:02:22 PM PST 23
Finished Dec 27 01:02:39 PM PST 23
Peak memory 217764 kb
Host smart-ec3a9371-ae4a-4a8d-aab3-cf756ba3005e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58858372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_dig
est.58858372
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.2507527923
Short name T944
Test name
Test status
Simulation time 452878726 ps
CPU time 11.02 seconds
Started Dec 27 01:02:23 PM PST 23
Finished Dec 27 01:02:39 PM PST 23
Peak memory 218188 kb
Host smart-a13735e8-da23-428d-865f-f7604f8b526b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507527923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
2507527923
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.567464819
Short name T355
Test name
Test status
Simulation time 2225161580 ps
CPU time 7.33 seconds
Started Dec 27 01:02:21 PM PST 23
Finished Dec 27 01:02:35 PM PST 23
Peak memory 218192 kb
Host smart-b69526d6-f69b-4c25-9495-7ca73485db37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567464819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.567464819
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.1212704798
Short name T341
Test name
Test status
Simulation time 65002905 ps
CPU time 3.52 seconds
Started Dec 27 01:02:23 PM PST 23
Finished Dec 27 01:02:32 PM PST 23
Peak memory 214428 kb
Host smart-9e1c2cef-1fa9-4165-b05a-f71e6f5c9a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212704798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.1212704798
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.201377204
Short name T307
Test name
Test status
Simulation time 711848031 ps
CPU time 21.2 seconds
Started Dec 27 01:02:21 PM PST 23
Finished Dec 27 01:02:48 PM PST 23
Peak memory 251096 kb
Host smart-98138274-79c9-47f9-bf5e-7314747d7edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201377204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.201377204
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.288877935
Short name T551
Test name
Test status
Simulation time 140983339 ps
CPU time 7 seconds
Started Dec 27 01:02:25 PM PST 23
Finished Dec 27 01:02:38 PM PST 23
Peak memory 243852 kb
Host smart-99c57543-1a35-41db-a952-7645c12d81bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288877935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.288877935
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.2877588478
Short name T807
Test name
Test status
Simulation time 1175611242 ps
CPU time 30.59 seconds
Started Dec 27 01:02:34 PM PST 23
Finished Dec 27 01:03:11 PM PST 23
Peak memory 250936 kb
Host smart-5741ed45-c5f9-4644-badc-db41c1f0a565
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877588478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.2877588478
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1236725991
Short name T305
Test name
Test status
Simulation time 39790039 ps
CPU time 0.8 seconds
Started Dec 27 01:02:23 PM PST 23
Finished Dec 27 01:02:29 PM PST 23
Peak memory 208256 kb
Host smart-357db5e6-5a25-4b48-8212-205ecbd87d9e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236725991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.1236725991
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.3633637548
Short name T423
Test name
Test status
Simulation time 138891186 ps
CPU time 1.08 seconds
Started Dec 27 01:02:33 PM PST 23
Finished Dec 27 01:02:39 PM PST 23
Peak memory 209760 kb
Host smart-eac6d296-2ca1-479b-bf80-8bf82dcd5fa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633637548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.3633637548
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.3414437791
Short name T918
Test name
Test status
Simulation time 1606581245 ps
CPU time 13.89 seconds
Started Dec 27 01:02:37 PM PST 23
Finished Dec 27 01:02:57 PM PST 23
Peak memory 218116 kb
Host smart-d0badb30-0027-4209-b031-811bfd49fcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414437791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.3414437791
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.2371897836
Short name T467
Test name
Test status
Simulation time 429948734 ps
CPU time 6.01 seconds
Started Dec 27 01:02:33 PM PST 23
Finished Dec 27 01:02:44 PM PST 23
Peak memory 209572 kb
Host smart-e5aefba3-021e-49c9-91cf-f309fab11a43
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371897836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_a
ccess.2371897836
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.2054784540
Short name T844
Test name
Test status
Simulation time 92063585 ps
CPU time 4.05 seconds
Started Dec 27 01:02:31 PM PST 23
Finished Dec 27 01:02:40 PM PST 23
Peak memory 218184 kb
Host smart-d10cdd50-e982-498a-ae9c-b17b5ad596d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054784540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.2054784540
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.859696749
Short name T464
Test name
Test status
Simulation time 291310382 ps
CPU time 12.9 seconds
Started Dec 27 01:02:45 PM PST 23
Finished Dec 27 01:03:04 PM PST 23
Peak memory 219244 kb
Host smart-150864ce-798f-4921-aef3-ec3e7c06f14e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859696749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.859696749
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.4149346420
Short name T936
Test name
Test status
Simulation time 989854118 ps
CPU time 9.34 seconds
Started Dec 27 01:02:36 PM PST 23
Finished Dec 27 01:02:52 PM PST 23
Peak memory 218148 kb
Host smart-b45e5d1f-5f3e-43d5-9dff-ab2f2d83a384
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149346420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.4149346420
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1531913188
Short name T791
Test name
Test status
Simulation time 407858799 ps
CPU time 10.76 seconds
Started Dec 27 01:02:40 PM PST 23
Finished Dec 27 01:03:02 PM PST 23
Peak memory 218156 kb
Host smart-23acc2ae-fae5-4256-b601-f6d785b9a2e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531913188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
1531913188
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.2872442450
Short name T724
Test name
Test status
Simulation time 469037959 ps
CPU time 9.88 seconds
Started Dec 27 01:02:23 PM PST 23
Finished Dec 27 01:02:39 PM PST 23
Peak memory 218224 kb
Host smart-477d3c49-ea48-415a-b306-8629f6af779b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872442450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.2872442450
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.1068486111
Short name T848
Test name
Test status
Simulation time 524767031 ps
CPU time 2.96 seconds
Started Dec 27 01:02:36 PM PST 23
Finished Dec 27 01:02:45 PM PST 23
Peak memory 214016 kb
Host smart-a9bd9ba1-bd0a-4d25-a2cb-3e6e167ff018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068486111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.1068486111
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.2385975839
Short name T440
Test name
Test status
Simulation time 186489386 ps
CPU time 21.7 seconds
Started Dec 27 01:02:31 PM PST 23
Finished Dec 27 01:02:58 PM PST 23
Peak memory 251124 kb
Host smart-db8c73ff-7772-4a2d-8a2e-45f470fa6f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385975839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.2385975839
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.725816552
Short name T956
Test name
Test status
Simulation time 65244839 ps
CPU time 7.77 seconds
Started Dec 27 01:02:31 PM PST 23
Finished Dec 27 01:02:44 PM PST 23
Peak memory 251096 kb
Host smart-b92b9e79-321d-4151-b9eb-93239526fce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725816552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.725816552
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.1522179011
Short name T705
Test name
Test status
Simulation time 15793482299 ps
CPU time 503.18 seconds
Started Dec 27 01:02:41 PM PST 23
Finished Dec 27 01:11:09 PM PST 23
Peak memory 267652 kb
Host smart-b1cb957c-9db5-445e-b107-96ddd44c4c53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522179011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.1522179011
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1469241328
Short name T416
Test name
Test status
Simulation time 65996750 ps
CPU time 0.75 seconds
Started Dec 27 01:02:31 PM PST 23
Finished Dec 27 01:02:37 PM PST 23
Peak memory 207908 kb
Host smart-4931c445-c048-47d6-9e5d-68212321fca0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469241328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1469241328
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.3988437137
Short name T589
Test name
Test status
Simulation time 43339618 ps
CPU time 1.19 seconds
Started Dec 27 01:02:21 PM PST 23
Finished Dec 27 01:02:27 PM PST 23
Peak memory 208484 kb
Host smart-28d216d6-6ea9-4924-941f-66849d200b92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988437137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.3988437137
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.310981288
Short name T377
Test name
Test status
Simulation time 372709169 ps
CPU time 12.02 seconds
Started Dec 27 01:02:40 PM PST 23
Finished Dec 27 01:02:57 PM PST 23
Peak memory 218220 kb
Host smart-351a85fa-03e8-4bda-9e43-8b1372dddc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310981288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.310981288
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.3595427419
Short name T632
Test name
Test status
Simulation time 1377928221 ps
CPU time 11.78 seconds
Started Dec 27 01:02:21 PM PST 23
Finished Dec 27 01:02:38 PM PST 23
Peak memory 209740 kb
Host smart-94134e67-bc25-4e14-a61c-459ca494d75c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595427419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_a
ccess.3595427419
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.2259075890
Short name T896
Test name
Test status
Simulation time 544514206 ps
CPU time 2.78 seconds
Started Dec 27 01:02:44 PM PST 23
Finished Dec 27 01:02:53 PM PST 23
Peak memory 218212 kb
Host smart-e22236c3-4889-4006-aaac-c2d3da8ba045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259075890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.2259075890
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.3658696893
Short name T712
Test name
Test status
Simulation time 935900876 ps
CPU time 25.01 seconds
Started Dec 27 01:02:21 PM PST 23
Finished Dec 27 01:02:52 PM PST 23
Peak memory 218212 kb
Host smart-f6e12e9f-57d5-4f65-b399-3a28bd9b4d19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658696893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.3658696893
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.3732185871
Short name T960
Test name
Test status
Simulation time 602158215 ps
CPU time 9.16 seconds
Started Dec 27 01:02:21 PM PST 23
Finished Dec 27 01:02:36 PM PST 23
Peak memory 218152 kb
Host smart-f837b2af-8984-4f61-9b0c-2f835abd33da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732185871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.3732185871
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2141443099
Short name T785
Test name
Test status
Simulation time 1190846562 ps
CPU time 8.49 seconds
Started Dec 27 01:02:18 PM PST 23
Finished Dec 27 01:02:30 PM PST 23
Peak memory 218064 kb
Host smart-8f83da7e-88f1-44e0-b040-600948afc51d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141443099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
2141443099
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.429449038
Short name T586
Test name
Test status
Simulation time 540965244 ps
CPU time 6.93 seconds
Started Dec 27 01:02:18 PM PST 23
Finished Dec 27 01:02:28 PM PST 23
Peak memory 218188 kb
Host smart-ff7ca20a-c53f-4b2f-ba22-04b1e749655b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429449038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.429449038
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.2340977370
Short name T65
Test name
Test status
Simulation time 46164590 ps
CPU time 2.72 seconds
Started Dec 27 01:02:55 PM PST 23
Finished Dec 27 01:03:10 PM PST 23
Peak memory 217900 kb
Host smart-c4155ea3-fded-43bf-9e56-fb8d7e007908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340977370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.2340977370
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.569645396
Short name T505
Test name
Test status
Simulation time 276776317 ps
CPU time 32.76 seconds
Started Dec 27 01:02:54 PM PST 23
Finished Dec 27 01:03:39 PM PST 23
Peak memory 251140 kb
Host smart-72e8491b-13d2-43ff-87af-341f26250c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569645396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.569645396
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.508306482
Short name T520
Test name
Test status
Simulation time 87095562 ps
CPU time 7.11 seconds
Started Dec 27 01:02:35 PM PST 23
Finished Dec 27 01:02:48 PM PST 23
Peak memory 251152 kb
Host smart-0ef00874-734b-4b99-a64e-0a9db62d02a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508306482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.508306482
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.1782026272
Short name T561
Test name
Test status
Simulation time 3075781307 ps
CPU time 80.21 seconds
Started Dec 27 01:02:21 PM PST 23
Finished Dec 27 01:03:47 PM PST 23
Peak memory 251160 kb
Host smart-685e6438-7271-456d-987a-3a6fb5905015
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782026272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.1782026272
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2098662019
Short name T32
Test name
Test status
Simulation time 14275793 ps
CPU time 0.78 seconds
Started Dec 27 01:02:46 PM PST 23
Finished Dec 27 01:02:54 PM PST 23
Peak memory 208108 kb
Host smart-e136fa90-c968-4af4-b61c-b2f01c788e64
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098662019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.2098662019
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.227657829
Short name T715
Test name
Test status
Simulation time 60970982 ps
CPU time 1.21 seconds
Started Dec 27 01:02:35 PM PST 23
Finished Dec 27 01:02:43 PM PST 23
Peak memory 208396 kb
Host smart-0b77afa1-3465-4e86-ae0a-a9c2c8873570
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227657829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.227657829
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.2162637964
Short name T450
Test name
Test status
Simulation time 9638474956 ps
CPU time 15.35 seconds
Started Dec 27 01:02:21 PM PST 23
Finished Dec 27 01:02:42 PM PST 23
Peak memory 218260 kb
Host smart-96288ad6-cbb6-4805-aa8c-74855371f45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162637964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.2162637964
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.2784843966
Short name T608
Test name
Test status
Simulation time 2539187457 ps
CPU time 11.56 seconds
Started Dec 27 01:02:20 PM PST 23
Finished Dec 27 01:02:35 PM PST 23
Peak memory 209864 kb
Host smart-08cc94d2-e32e-440c-835c-475c7e10fb30
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784843966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_a
ccess.2784843966
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2267318022
Short name T923
Test name
Test status
Simulation time 1198860895 ps
CPU time 2.57 seconds
Started Dec 27 01:02:19 PM PST 23
Finished Dec 27 01:02:25 PM PST 23
Peak memory 218192 kb
Host smart-771eda9d-3c54-4a89-a06b-f0654175c709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267318022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2267318022
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.1587160958
Short name T799
Test name
Test status
Simulation time 2112934932 ps
CPU time 16.15 seconds
Started Dec 27 01:02:29 PM PST 23
Finished Dec 27 01:02:51 PM PST 23
Peak memory 218256 kb
Host smart-7cddfb20-3ca6-4217-a3a2-d360d7294ddd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587160958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.1587160958
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.4207606152
Short name T884
Test name
Test status
Simulation time 2439155176 ps
CPU time 8.57 seconds
Started Dec 27 01:02:30 PM PST 23
Finished Dec 27 01:02:44 PM PST 23
Peak memory 218124 kb
Host smart-f769eed0-d050-4ef2-a32d-1d6b2f47061a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207606152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.4207606152
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.76829240
Short name T733
Test name
Test status
Simulation time 3233742834 ps
CPU time 8.27 seconds
Started Dec 27 01:02:22 PM PST 23
Finished Dec 27 01:02:36 PM PST 23
Peak memory 217856 kb
Host smart-ec071a11-2760-4b0a-9c39-f14c5c7f0526
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76829240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.76829240
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.2317123731
Short name T663
Test name
Test status
Simulation time 2001276995 ps
CPU time 10.16 seconds
Started Dec 27 01:02:18 PM PST 23
Finished Dec 27 01:02:32 PM PST 23
Peak memory 218224 kb
Host smart-5a5b30d6-a070-4fc7-95bf-3a840f36c4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317123731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.2317123731
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.2914909130
Short name T72
Test name
Test status
Simulation time 19901110 ps
CPU time 1.19 seconds
Started Dec 27 01:02:19 PM PST 23
Finished Dec 27 01:02:24 PM PST 23
Peak memory 213016 kb
Host smart-85ebe480-b7c4-466d-a332-e4a8ae9ce140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914909130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.2914909130
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.4116395742
Short name T602
Test name
Test status
Simulation time 327579641 ps
CPU time 32.08 seconds
Started Dec 27 01:02:19 PM PST 23
Finished Dec 27 01:02:55 PM PST 23
Peak memory 251064 kb
Host smart-a82a965a-ce58-43d2-b9dc-cea67291ade2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116395742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.4116395742
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.2852956491
Short name T560
Test name
Test status
Simulation time 83268223 ps
CPU time 7.61 seconds
Started Dec 27 01:02:18 PM PST 23
Finished Dec 27 01:02:28 PM PST 23
Peak memory 250668 kb
Host smart-b1c47dbf-99bb-4275-911c-eb812e62c706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852956491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.2852956491
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.2698200362
Short name T889
Test name
Test status
Simulation time 7354537475 ps
CPU time 88.44 seconds
Started Dec 27 01:02:32 PM PST 23
Finished Dec 27 01:04:05 PM PST 23
Peak memory 259552 kb
Host smart-0803a68d-6681-4740-8a9f-2a4f5d85186f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698200362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.2698200362
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1883906843
Short name T393
Test name
Test status
Simulation time 47567944 ps
CPU time 1.02 seconds
Started Dec 27 01:02:18 PM PST 23
Finished Dec 27 01:02:22 PM PST 23
Peak memory 212584 kb
Host smart-79a9d13a-45e8-4591-b60e-b2ab00ebbca8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883906843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.1883906843
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.987193933
Short name T814
Test name
Test status
Simulation time 100714718 ps
CPU time 0.95 seconds
Started Dec 27 01:02:39 PM PST 23
Finished Dec 27 01:02:46 PM PST 23
Peak memory 209652 kb
Host smart-cfdfaddc-5800-4aad-b7e1-71ea25192c5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987193933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.987193933
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.1620213807
Short name T968
Test name
Test status
Simulation time 1515945647 ps
CPU time 15.64 seconds
Started Dec 27 01:02:52 PM PST 23
Finished Dec 27 01:03:15 PM PST 23
Peak memory 218216 kb
Host smart-4fc36676-5438-4000-8ab9-8d9ab5e78951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620213807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.1620213807
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.1715694765
Short name T363
Test name
Test status
Simulation time 757136954 ps
CPU time 4.06 seconds
Started Dec 27 01:02:36 PM PST 23
Finished Dec 27 01:02:46 PM PST 23
Peak memory 209668 kb
Host smart-142d13e2-f526-4ee4-9d2b-aed2f3a5eec7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715694765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_a
ccess.1715694765
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.2382681003
Short name T344
Test name
Test status
Simulation time 59647406 ps
CPU time 1.64 seconds
Started Dec 27 01:02:37 PM PST 23
Finished Dec 27 01:02:44 PM PST 23
Peak memory 218296 kb
Host smart-78f9ef7a-3bd6-4708-8ea8-03d87ce1cbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382681003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.2382681003
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.2924229852
Short name T702
Test name
Test status
Simulation time 640908617 ps
CPU time 10.54 seconds
Started Dec 27 01:02:40 PM PST 23
Finished Dec 27 01:02:56 PM PST 23
Peak memory 218556 kb
Host smart-b9c967b6-0e6a-47fc-89e2-1259347edede
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924229852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.2924229852
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.2296372115
Short name T855
Test name
Test status
Simulation time 852100018 ps
CPU time 22.86 seconds
Started Dec 27 01:02:45 PM PST 23
Finished Dec 27 01:03:14 PM PST 23
Peak memory 218080 kb
Host smart-2db9f347-c62e-49a2-a271-8d4e0759369f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296372115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.2296372115
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.3652980740
Short name T459
Test name
Test status
Simulation time 304913965 ps
CPU time 12.27 seconds
Started Dec 27 01:02:41 PM PST 23
Finished Dec 27 01:02:59 PM PST 23
Peak memory 218156 kb
Host smart-b18d218d-0e67-4476-9f48-b1fd0459dd28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652980740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
3652980740
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.1238097187
Short name T430
Test name
Test status
Simulation time 1183990951 ps
CPU time 8.15 seconds
Started Dec 27 01:02:27 PM PST 23
Finished Dec 27 01:02:40 PM PST 23
Peak memory 218200 kb
Host smart-b27e5db0-b41d-4d27-83cf-42291ff7caf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238097187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.1238097187
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.447357004
Short name T3
Test name
Test status
Simulation time 28610337 ps
CPU time 1.59 seconds
Started Dec 27 01:02:29 PM PST 23
Finished Dec 27 01:02:36 PM PST 23
Peak memory 213464 kb
Host smart-a25f1883-2134-4354-b83e-6cdf0f288cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447357004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.447357004
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.1179638119
Short name T323
Test name
Test status
Simulation time 568349078 ps
CPU time 25.68 seconds
Started Dec 27 01:02:24 PM PST 23
Finished Dec 27 01:02:56 PM PST 23
Peak memory 251168 kb
Host smart-a27e54ce-0187-413b-aef4-4525556ba20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179638119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.1179638119
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.3212280107
Short name T917
Test name
Test status
Simulation time 56369148 ps
CPU time 7.1 seconds
Started Dec 27 01:02:23 PM PST 23
Finished Dec 27 01:02:35 PM PST 23
Peak memory 246172 kb
Host smart-eff7c94a-2d3e-4ad6-ae2d-01e6f178c581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212280107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.3212280107
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.535558154
Short name T861
Test name
Test status
Simulation time 2094821720 ps
CPU time 64.42 seconds
Started Dec 27 01:02:37 PM PST 23
Finished Dec 27 01:03:48 PM PST 23
Peak memory 253260 kb
Host smart-282d1a6d-25d7-4b44-b087-647881874544
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535558154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.535558154
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.4082686266
Short name T892
Test name
Test status
Simulation time 37651078 ps
CPU time 0.89 seconds
Started Dec 27 01:02:36 PM PST 23
Finished Dec 27 01:02:47 PM PST 23
Peak memory 208184 kb
Host smart-61c53a3a-86be-4fcc-8c47-5f9c6b84b4a3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082686266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.4082686266
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.389244534
Short name T714
Test name
Test status
Simulation time 24012482 ps
CPU time 0.83 seconds
Started Dec 27 01:01:18 PM PST 23
Finished Dec 27 01:01:24 PM PST 23
Peak memory 209528 kb
Host smart-a39275fd-9c61-47e1-8bc6-adc3cba641f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389244534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.389244534
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.3491357903
Short name T465
Test name
Test status
Simulation time 937780782 ps
CPU time 11.05 seconds
Started Dec 27 01:01:17 PM PST 23
Finished Dec 27 01:01:33 PM PST 23
Peak memory 218224 kb
Host smart-b00faa87-f8d6-4b5b-b813-457acdff030c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491357903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.3491357903
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.922105827
Short name T862
Test name
Test status
Simulation time 589407909 ps
CPU time 4.32 seconds
Started Dec 27 01:01:10 PM PST 23
Finished Dec 27 01:01:18 PM PST 23
Peak memory 209628 kb
Host smart-66745fda-3385-4974-8ec2-1b576608d5d3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922105827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_acc
ess.922105827
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.3013598559
Short name T35
Test name
Test status
Simulation time 2154716213 ps
CPU time 25.76 seconds
Started Dec 27 01:01:09 PM PST 23
Finished Dec 27 01:01:39 PM PST 23
Peak memory 218216 kb
Host smart-cfeed024-3f1a-4454-b9e2-905f7534e840
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013598559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.3013598559
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.3652910968
Short name T500
Test name
Test status
Simulation time 224425835 ps
CPU time 2.58 seconds
Started Dec 27 01:01:10 PM PST 23
Finished Dec 27 01:01:16 PM PST 23
Peak memory 209660 kb
Host smart-ab9fa399-4acb-4da6-89e4-f737f203558d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652910968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_
priority.3652910968
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.3783088639
Short name T491
Test name
Test status
Simulation time 1173287375 ps
CPU time 5.72 seconds
Started Dec 27 01:01:16 PM PST 23
Finished Dec 27 01:01:26 PM PST 23
Peak memory 218084 kb
Host smart-5aee65b8-c104-40ee-a955-a2d9ac94484b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783088639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.3783088639
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2666882067
Short name T1
Test name
Test status
Simulation time 9233963632 ps
CPU time 18.84 seconds
Started Dec 27 01:01:11 PM PST 23
Finished Dec 27 01:01:34 PM PST 23
Peak memory 213856 kb
Host smart-cc9eaa54-b725-4600-a929-d73d815ca281
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666882067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.2666882067
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.663654227
Short name T783
Test name
Test status
Simulation time 2554297066 ps
CPU time 15.34 seconds
Started Dec 27 01:01:07 PM PST 23
Finished Dec 27 01:01:25 PM PST 23
Peak memory 214016 kb
Host smart-79979583-3830-4b6c-b742-746c31aa42cd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663654227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.663654227
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2152385628
Short name T601
Test name
Test status
Simulation time 5705256777 ps
CPU time 64.12 seconds
Started Dec 27 01:01:17 PM PST 23
Finished Dec 27 01:02:27 PM PST 23
Peak memory 253316 kb
Host smart-9caffa5c-4424-4468-ae5b-ff916c6e0fde
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152385628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.2152385628
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.3596490799
Short name T538
Test name
Test status
Simulation time 2635499877 ps
CPU time 14.8 seconds
Started Dec 27 01:01:17 PM PST 23
Finished Dec 27 01:01:37 PM PST 23
Peak memory 250336 kb
Host smart-a485cd75-9d88-4f54-9aa4-1e003c262239
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596490799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.3596490799
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.2198509155
Short name T618
Test name
Test status
Simulation time 101449795 ps
CPU time 1.71 seconds
Started Dec 27 01:01:13 PM PST 23
Finished Dec 27 01:01:20 PM PST 23
Peak memory 218228 kb
Host smart-bad8a872-f0ce-4b89-a22b-68e4aa5de3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198509155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.2198509155
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.3507836644
Short name T695
Test name
Test status
Simulation time 855863478 ps
CPU time 8.09 seconds
Started Dec 27 01:01:16 PM PST 23
Finished Dec 27 01:01:29 PM PST 23
Peak memory 214072 kb
Host smart-edb296d9-1479-4408-8fc9-48c7bde17bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507836644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.3507836644
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.546978507
Short name T100
Test name
Test status
Simulation time 238965089 ps
CPU time 24.31 seconds
Started Dec 27 01:01:14 PM PST 23
Finished Dec 27 01:01:43 PM PST 23
Peak memory 272644 kb
Host smart-7aa440e2-8a86-481c-805b-b4985ee6785c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546978507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.546978507
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.180956499
Short name T980
Test name
Test status
Simulation time 292625739 ps
CPU time 11.49 seconds
Started Dec 27 01:01:18 PM PST 23
Finished Dec 27 01:01:34 PM PST 23
Peak memory 218148 kb
Host smart-6981feb6-f076-4670-83ae-1bac29b38e7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180956499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.180956499
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.1809306165
Short name T904
Test name
Test status
Simulation time 1036357727 ps
CPU time 11.12 seconds
Started Dec 27 01:01:13 PM PST 23
Finished Dec 27 01:01:28 PM PST 23
Peak memory 218084 kb
Host smart-f906af90-4337-4172-9d93-b337dca7d438
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809306165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.1809306165
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.56652211
Short name T825
Test name
Test status
Simulation time 1172791968 ps
CPU time 10.06 seconds
Started Dec 27 01:01:12 PM PST 23
Finished Dec 27 01:01:26 PM PST 23
Peak memory 218092 kb
Host smart-1f78c6c9-440a-4e60-b5e3-dda504980d45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56652211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.56652211
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.1004006461
Short name T599
Test name
Test status
Simulation time 356686277 ps
CPU time 14.01 seconds
Started Dec 27 01:01:10 PM PST 23
Finished Dec 27 01:01:28 PM PST 23
Peak memory 218184 kb
Host smart-fb6ccc82-63d4-4608-b592-9fe0b727878f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004006461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.1004006461
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.2597437243
Short name T653
Test name
Test status
Simulation time 24318804 ps
CPU time 1.03 seconds
Started Dec 27 01:01:09 PM PST 23
Finished Dec 27 01:01:14 PM PST 23
Peak memory 211892 kb
Host smart-4c91bb07-8b4d-4283-8d22-9a699115ad64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597437243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.2597437243
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.3536365822
Short name T808
Test name
Test status
Simulation time 2068441263 ps
CPU time 27.38 seconds
Started Dec 27 01:01:11 PM PST 23
Finished Dec 27 01:01:42 PM PST 23
Peak memory 251064 kb
Host smart-b70b568c-4721-4532-909f-d33d64eb7405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536365822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3536365822
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.2239332690
Short name T335
Test name
Test status
Simulation time 70470798 ps
CPU time 9.08 seconds
Started Dec 27 01:01:10 PM PST 23
Finished Dec 27 01:01:23 PM PST 23
Peak memory 251148 kb
Host smart-f91801f3-a595-495c-a291-a2a84b9956f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239332690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.2239332690
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.35024711
Short name T963
Test name
Test status
Simulation time 15784584197 ps
CPU time 454.87 seconds
Started Dec 27 01:01:14 PM PST 23
Finished Dec 27 01:08:53 PM PST 23
Peak memory 251284 kb
Host smart-ce1cdc0f-ecd7-4b49-aecd-c4e5667c56ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35024711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.lc_ctrl_stress_all.35024711
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1183285706
Short name T938
Test name
Test status
Simulation time 12995343 ps
CPU time 0.95 seconds
Started Dec 27 01:01:11 PM PST 23
Finished Dec 27 01:01:16 PM PST 23
Peak memory 211488 kb
Host smart-e60cafa8-0e95-4442-b912-40e8a1888a66
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183285706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1183285706
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.932498396
Short name T622
Test name
Test status
Simulation time 24743131 ps
CPU time 1.27 seconds
Started Dec 27 01:02:28 PM PST 23
Finished Dec 27 01:02:34 PM PST 23
Peak memory 208536 kb
Host smart-7d171bd6-f4fb-4e44-a63f-498fea4c9c1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932498396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.932498396
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.2079071455
Short name T330
Test name
Test status
Simulation time 2033595597 ps
CPU time 14.27 seconds
Started Dec 27 01:02:42 PM PST 23
Finished Dec 27 01:03:02 PM PST 23
Peak memory 218168 kb
Host smart-470ccba3-dc73-4f32-9465-195270b5f92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079071455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.2079071455
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.2417754636
Short name T921
Test name
Test status
Simulation time 10200997640 ps
CPU time 12.81 seconds
Started Dec 27 01:02:19 PM PST 23
Finished Dec 27 01:02:36 PM PST 23
Peak memory 209716 kb
Host smart-df24816b-50b9-4e25-881c-bdd6305e8838
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417754636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_a
ccess.2417754636
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.2677991193
Short name T582
Test name
Test status
Simulation time 72806030 ps
CPU time 3.11 seconds
Started Dec 27 01:02:45 PM PST 23
Finished Dec 27 01:02:55 PM PST 23
Peak memory 218160 kb
Host smart-9114ce47-1cf4-4bb1-8b68-7cb339d56374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677991193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.2677991193
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.2980812470
Short name T749
Test name
Test status
Simulation time 251969480 ps
CPU time 11.55 seconds
Started Dec 27 01:02:18 PM PST 23
Finished Dec 27 01:02:33 PM PST 23
Peak memory 218160 kb
Host smart-ad1d7c1d-e8c3-421b-ac4a-55fc9e728a39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980812470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.2980812470
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.138959490
Short name T815
Test name
Test status
Simulation time 1696714578 ps
CPU time 11.46 seconds
Started Dec 27 01:02:20 PM PST 23
Finished Dec 27 01:02:35 PM PST 23
Peak memory 218200 kb
Host smart-a86d82d4-2053-4794-a1a9-745f5d1c6ad2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138959490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_di
gest.138959490
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1868089838
Short name T690
Test name
Test status
Simulation time 568221499 ps
CPU time 9.88 seconds
Started Dec 27 01:02:22 PM PST 23
Finished Dec 27 01:02:37 PM PST 23
Peak memory 218084 kb
Host smart-b5f23e60-e332-4132-8202-3ad61689bad3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868089838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
1868089838
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.2721580201
Short name T371
Test name
Test status
Simulation time 703963272 ps
CPU time 7.52 seconds
Started Dec 27 01:02:19 PM PST 23
Finished Dec 27 01:02:31 PM PST 23
Peak memory 218204 kb
Host smart-1d283de3-a587-4786-9755-4e7d6d5c8f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721580201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.2721580201
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.326014769
Short name T76
Test name
Test status
Simulation time 388173948 ps
CPU time 6.4 seconds
Started Dec 27 01:02:41 PM PST 23
Finished Dec 27 01:02:53 PM PST 23
Peak memory 214488 kb
Host smart-aa604f9a-9ec2-4821-99f1-fa5af3013f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326014769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.326014769
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.2159785558
Short name T680
Test name
Test status
Simulation time 1012965786 ps
CPU time 28.14 seconds
Started Dec 27 01:02:37 PM PST 23
Finished Dec 27 01:03:11 PM PST 23
Peak memory 251124 kb
Host smart-9f3da911-41c8-41ff-b41e-122b58b7b546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159785558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.2159785558
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.2904458210
Short name T693
Test name
Test status
Simulation time 60151276 ps
CPU time 7.49 seconds
Started Dec 27 01:02:49 PM PST 23
Finished Dec 27 01:03:04 PM PST 23
Peak memory 251140 kb
Host smart-98e3cbac-0105-441e-8ea5-73de4d7a54a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904458210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.2904458210
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.1815189374
Short name T803
Test name
Test status
Simulation time 27947158606 ps
CPU time 74.18 seconds
Started Dec 27 01:02:19 PM PST 23
Finished Dec 27 01:03:36 PM PST 23
Peak memory 269636 kb
Host smart-f69306b4-5f38-40ed-8bfd-cbd15fb60501
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815189374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.1815189374
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.640880475
Short name T713
Test name
Test status
Simulation time 50938954 ps
CPU time 1.04 seconds
Started Dec 27 01:02:55 PM PST 23
Finished Dec 27 01:03:08 PM PST 23
Peak memory 211388 kb
Host smart-7fe18506-04e5-447a-89d3-ea0091bd6fcb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640880475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ct
rl_volatile_unlock_smoke.640880475
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.4074371915
Short name T351
Test name
Test status
Simulation time 130626930 ps
CPU time 0.9 seconds
Started Dec 27 01:02:21 PM PST 23
Finished Dec 27 01:02:27 PM PST 23
Peak memory 209628 kb
Host smart-e956cb4e-ccd8-4711-95cf-144ccf7b5a45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074371915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.4074371915
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.1269225375
Short name T385
Test name
Test status
Simulation time 1193252990 ps
CPU time 10.78 seconds
Started Dec 27 01:02:22 PM PST 23
Finished Dec 27 01:02:38 PM PST 23
Peak memory 218140 kb
Host smart-c113586d-c10b-4ceb-ad45-648551710b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269225375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.1269225375
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.339144066
Short name T389
Test name
Test status
Simulation time 1191398112 ps
CPU time 9.16 seconds
Started Dec 27 01:02:22 PM PST 23
Finished Dec 27 01:02:37 PM PST 23
Peak memory 209660 kb
Host smart-0fcb7b9a-34c0-49db-9a55-4e632beff454
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339144066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_ac
cess.339144066
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.3667161614
Short name T562
Test name
Test status
Simulation time 66779676 ps
CPU time 2.94 seconds
Started Dec 27 01:02:23 PM PST 23
Finished Dec 27 01:02:32 PM PST 23
Peak memory 218240 kb
Host smart-f9871b1b-e611-41f2-b348-ad7fcf449b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667161614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.3667161614
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.4082240736
Short name T588
Test name
Test status
Simulation time 3290994752 ps
CPU time 10.51 seconds
Started Dec 27 01:02:23 PM PST 23
Finished Dec 27 01:02:40 PM PST 23
Peak memory 219328 kb
Host smart-62f9ca16-b9f3-4fd9-a36b-3a3eada8dd8d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082240736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.4082240736
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.784040338
Short name T414
Test name
Test status
Simulation time 393509501 ps
CPU time 8.42 seconds
Started Dec 27 01:02:32 PM PST 23
Finished Dec 27 01:02:46 PM PST 23
Peak memory 218028 kb
Host smart-fe018d3d-32ae-4130-a646-fbd4e3667af8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784040338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_di
gest.784040338
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.308913641
Short name T475
Test name
Test status
Simulation time 223822362 ps
CPU time 9.51 seconds
Started Dec 27 01:02:20 PM PST 23
Finished Dec 27 01:02:33 PM PST 23
Peak memory 218176 kb
Host smart-554caa58-addf-43ee-a656-a947669ed537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308913641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.308913641
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.640938190
Short name T751
Test name
Test status
Simulation time 577802958 ps
CPU time 2.75 seconds
Started Dec 27 01:02:21 PM PST 23
Finished Dec 27 01:02:30 PM PST 23
Peak memory 214088 kb
Host smart-f937f84b-50b8-4ede-b276-6a9e0419dbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640938190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.640938190
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.2200110915
Short name T716
Test name
Test status
Simulation time 557446631 ps
CPU time 24.35 seconds
Started Dec 27 01:02:27 PM PST 23
Finished Dec 27 01:02:57 PM PST 23
Peak memory 251088 kb
Host smart-19952eeb-3acb-4514-a924-15a4830b7713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200110915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.2200110915
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.2381324467
Short name T787
Test name
Test status
Simulation time 489499435 ps
CPU time 8 seconds
Started Dec 27 01:02:21 PM PST 23
Finished Dec 27 01:02:34 PM PST 23
Peak memory 251212 kb
Host smart-fede030e-3ff2-4cea-b510-b5c755f3d24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381324467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.2381324467
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.2280433136
Short name T54
Test name
Test status
Simulation time 8813050785 ps
CPU time 104.77 seconds
Started Dec 27 01:02:31 PM PST 23
Finished Dec 27 01:04:21 PM PST 23
Peak memory 249796 kb
Host smart-252f0db1-aaed-435c-ad92-3366c6931119
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280433136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.2280433136
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3607880216
Short name T610
Test name
Test status
Simulation time 11301942 ps
CPU time 0.94 seconds
Started Dec 27 01:02:18 PM PST 23
Finished Dec 27 01:02:22 PM PST 23
Peak memory 208564 kb
Host smart-0a3916ae-24c1-434f-9da9-33fb63fd5eeb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607880216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.3607880216
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.687476516
Short name T86
Test name
Test status
Simulation time 111893928 ps
CPU time 1.11 seconds
Started Dec 27 01:02:27 PM PST 23
Finished Dec 27 01:02:34 PM PST 23
Peak memory 209736 kb
Host smart-fedee90c-b565-4372-8a1e-a87869242507
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687476516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.687476516
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.3981210913
Short name T312
Test name
Test status
Simulation time 1477628118 ps
CPU time 13.22 seconds
Started Dec 27 01:02:44 PM PST 23
Finished Dec 27 01:03:02 PM PST 23
Peak memory 218156 kb
Host smart-49283e68-ffcc-46d1-9fa7-e32443663e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981210913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.3981210913
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.3548477845
Short name T572
Test name
Test status
Simulation time 458455108 ps
CPU time 11.95 seconds
Started Dec 27 01:02:19 PM PST 23
Finished Dec 27 01:02:35 PM PST 23
Peak memory 209684 kb
Host smart-31f700c7-5bc7-4eea-a7e3-79b1aca0a90d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548477845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_a
ccess.3548477845
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.3325913784
Short name T495
Test name
Test status
Simulation time 36350724 ps
CPU time 1.7 seconds
Started Dec 27 01:02:20 PM PST 23
Finished Dec 27 01:02:26 PM PST 23
Peak memory 218184 kb
Host smart-88e3211c-addb-4dbf-af2f-97c4afb420ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325913784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.3325913784
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.202643582
Short name T840
Test name
Test status
Simulation time 673109455 ps
CPU time 17.69 seconds
Started Dec 27 01:02:32 PM PST 23
Finished Dec 27 01:02:55 PM PST 23
Peak memory 218784 kb
Host smart-2be74ce9-0812-4a8c-933d-c301c27c1766
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202643582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.202643582
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.3832360255
Short name T604
Test name
Test status
Simulation time 882179599 ps
CPU time 12.62 seconds
Started Dec 27 01:02:21 PM PST 23
Finished Dec 27 01:02:38 PM PST 23
Peak memory 218040 kb
Host smart-66617520-0c17-4509-94e2-b7d03de80c39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832360255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.3832360255
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.766393339
Short name T493
Test name
Test status
Simulation time 164188924 ps
CPU time 7.54 seconds
Started Dec 27 01:02:34 PM PST 23
Finished Dec 27 01:02:47 PM PST 23
Peak memory 218052 kb
Host smart-c26c19f7-fff3-469c-85bd-b95f51d9713b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766393339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.766393339
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.4055915089
Short name T82
Test name
Test status
Simulation time 233698175 ps
CPU time 9.74 seconds
Started Dec 27 01:02:40 PM PST 23
Finished Dec 27 01:02:55 PM PST 23
Peak memory 218160 kb
Host smart-091fa7fe-ccab-44f2-8d66-9bc234aa17c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055915089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.4055915089
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.2128881868
Short name T845
Test name
Test status
Simulation time 37873892 ps
CPU time 2.5 seconds
Started Dec 27 01:02:28 PM PST 23
Finished Dec 27 01:02:36 PM PST 23
Peak memory 214084 kb
Host smart-b32d5160-54ed-445b-8528-f8fd3a4def67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128881868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2128881868
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.948636032
Short name T674
Test name
Test status
Simulation time 1738621476 ps
CPU time 35.96 seconds
Started Dec 27 01:02:33 PM PST 23
Finished Dec 27 01:03:14 PM PST 23
Peak memory 250948 kb
Host smart-33b0f0c1-e223-4f15-a1d3-251887482d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948636032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.948636032
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.1923309259
Short name T830
Test name
Test status
Simulation time 243760166 ps
CPU time 7.22 seconds
Started Dec 27 01:02:24 PM PST 23
Finished Dec 27 01:02:37 PM PST 23
Peak memory 250376 kb
Host smart-a1099793-fbab-47b8-8422-5e9b0baa29e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923309259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1923309259
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3892043760
Short name T672
Test name
Test status
Simulation time 10561740 ps
CPU time 0.88 seconds
Started Dec 27 01:02:29 PM PST 23
Finished Dec 27 01:02:35 PM PST 23
Peak memory 208180 kb
Host smart-c53eec46-b007-4dc4-bf4b-f148c6482d34
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892043760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.3892043760
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.317128185
Short name T439
Test name
Test status
Simulation time 73446357 ps
CPU time 1.11 seconds
Started Dec 27 01:02:41 PM PST 23
Finished Dec 27 01:02:48 PM PST 23
Peak memory 208428 kb
Host smart-bbad5aee-85eb-4d54-a560-a6cb747e9573
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317128185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.317128185
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.3003017196
Short name T570
Test name
Test status
Simulation time 162549569 ps
CPU time 2.53 seconds
Started Dec 27 01:02:41 PM PST 23
Finished Dec 27 01:02:49 PM PST 23
Peak memory 209580 kb
Host smart-73ba04ba-0637-4abd-8477-d203d73f9d93
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003017196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_a
ccess.3003017196
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.3773555473
Short name T345
Test name
Test status
Simulation time 221631959 ps
CPU time 3.16 seconds
Started Dec 27 01:02:30 PM PST 23
Finished Dec 27 01:02:44 PM PST 23
Peak memory 218108 kb
Host smart-1f262ef5-6d39-46d7-8d0d-efcfa9067f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773555473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.3773555473
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.1797766894
Short name T961
Test name
Test status
Simulation time 2156981529 ps
CPU time 13.65 seconds
Started Dec 27 01:02:36 PM PST 23
Finished Dec 27 01:02:56 PM PST 23
Peak memory 218292 kb
Host smart-34b527fd-f66f-42f0-b488-b88d4e4694db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797766894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.1797766894
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.3971422035
Short name T981
Test name
Test status
Simulation time 1025401584 ps
CPU time 12.45 seconds
Started Dec 27 01:02:35 PM PST 23
Finished Dec 27 01:02:54 PM PST 23
Peak memory 218152 kb
Host smart-5d78d685-cafa-49d9-8938-abdfbf823e95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971422035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.3971422035
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.2946352983
Short name T13
Test name
Test status
Simulation time 233829735 ps
CPU time 9.18 seconds
Started Dec 27 01:02:45 PM PST 23
Finished Dec 27 01:03:01 PM PST 23
Peak memory 218184 kb
Host smart-5722769e-e66b-439f-9e8f-ab802f49df32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946352983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
2946352983
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.2126360855
Short name T925
Test name
Test status
Simulation time 868764146 ps
CPU time 7.38 seconds
Started Dec 27 01:02:33 PM PST 23
Finished Dec 27 01:02:46 PM PST 23
Peak memory 218108 kb
Host smart-cd7c940c-e639-4e96-ae86-3b3f09412bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126360855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.2126360855
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.425564950
Short name T516
Test name
Test status
Simulation time 19045882 ps
CPU time 1.67 seconds
Started Dec 27 01:02:27 PM PST 23
Finished Dec 27 01:02:34 PM PST 23
Peak memory 213528 kb
Host smart-8bf4adc9-ffb6-4d5e-8c16-4ee4c228ef4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425564950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.425564950
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.3642465399
Short name T905
Test name
Test status
Simulation time 860870422 ps
CPU time 21.85 seconds
Started Dec 27 01:03:00 PM PST 23
Finished Dec 27 01:03:36 PM PST 23
Peak memory 251064 kb
Host smart-da1dd4cf-edbb-4d56-8337-0574cf9fe09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642465399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.3642465399
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.792192736
Short name T736
Test name
Test status
Simulation time 86142058 ps
CPU time 6.71 seconds
Started Dec 27 01:02:51 PM PST 23
Finished Dec 27 01:03:06 PM PST 23
Peak memory 250604 kb
Host smart-b8337cd3-a636-4ad7-b77f-75346bf854f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792192736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.792192736
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.2267056183
Short name T638
Test name
Test status
Simulation time 2758127563 ps
CPU time 49.89 seconds
Started Dec 27 01:02:35 PM PST 23
Finished Dec 27 01:03:31 PM PST 23
Peak memory 250008 kb
Host smart-c49cb549-7b69-4587-866c-310693662ff5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267056183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.2267056183
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.128344293
Short name T435
Test name
Test status
Simulation time 14806122 ps
CPU time 1.03 seconds
Started Dec 27 01:02:30 PM PST 23
Finished Dec 27 01:02:36 PM PST 23
Peak memory 212564 kb
Host smart-96fb87bf-92ec-4c8a-8140-150aa4bbec86
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128344293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ct
rl_volatile_unlock_smoke.128344293
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.3654028644
Short name T662
Test name
Test status
Simulation time 56665216 ps
CPU time 1.03 seconds
Started Dec 27 01:02:32 PM PST 23
Finished Dec 27 01:02:39 PM PST 23
Peak memory 209696 kb
Host smart-fd64ceff-cab8-4069-9eeb-ab4508c139f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654028644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.3654028644
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.2782226465
Short name T404
Test name
Test status
Simulation time 1541218146 ps
CPU time 12.33 seconds
Started Dec 27 01:02:41 PM PST 23
Finished Dec 27 01:02:59 PM PST 23
Peak memory 218224 kb
Host smart-280ada85-3980-428d-8326-e04cf6e296f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782226465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2782226465
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.4062891205
Short name T15
Test name
Test status
Simulation time 1684229365 ps
CPU time 11.58 seconds
Started Dec 27 01:02:54 PM PST 23
Finished Dec 27 01:03:17 PM PST 23
Peak memory 209676 kb
Host smart-e9a9cfbc-3a1e-4cb8-b158-0b522f973869
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062891205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_a
ccess.4062891205
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.1532488927
Short name T920
Test name
Test status
Simulation time 68601649 ps
CPU time 2.87 seconds
Started Dec 27 01:02:29 PM PST 23
Finished Dec 27 01:02:37 PM PST 23
Peak memory 218220 kb
Host smart-3a68169f-ae5d-478a-a571-606a6e48fc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532488927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.1532488927
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.1300688966
Short name T789
Test name
Test status
Simulation time 1446897315 ps
CPU time 14.14 seconds
Started Dec 27 01:02:31 PM PST 23
Finished Dec 27 01:02:50 PM PST 23
Peak memory 218544 kb
Host smart-bf26a207-0eaa-4752-aaff-023110770ef2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300688966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.1300688966
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.3571614224
Short name T958
Test name
Test status
Simulation time 619316797 ps
CPU time 8.96 seconds
Started Dec 27 01:02:49 PM PST 23
Finished Dec 27 01:03:05 PM PST 23
Peak memory 218148 kb
Host smart-e659b9f4-927a-41a5-97a0-3fac93375003
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571614224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.3571614224
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.2297241431
Short name T758
Test name
Test status
Simulation time 794550336 ps
CPU time 5.19 seconds
Started Dec 27 01:02:32 PM PST 23
Finished Dec 27 01:02:43 PM PST 23
Peak memory 218144 kb
Host smart-6cb21430-1156-4aea-bd5c-60081d0a08a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297241431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
2297241431
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.84352019
Short name T472
Test name
Test status
Simulation time 23261466 ps
CPU time 1.56 seconds
Started Dec 27 01:02:35 PM PST 23
Finished Dec 27 01:02:43 PM PST 23
Peak memory 213268 kb
Host smart-fb87a7b3-6ec8-462a-bb13-4e8abedafd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84352019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.84352019
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1339035262
Short name T949
Test name
Test status
Simulation time 2560093943 ps
CPU time 34.72 seconds
Started Dec 27 01:02:30 PM PST 23
Finished Dec 27 01:03:10 PM PST 23
Peak memory 250980 kb
Host smart-a9e86162-2202-4946-b304-18d3c7251688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339035262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1339035262
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.3108712817
Short name T463
Test name
Test status
Simulation time 342472126 ps
CPU time 8.7 seconds
Started Dec 27 01:02:23 PM PST 23
Finished Dec 27 01:02:37 PM PST 23
Peak memory 251224 kb
Host smart-8af86a6a-476c-4568-9952-642364f60da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108712817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.3108712817
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.1751791265
Short name T567
Test name
Test status
Simulation time 16709421406 ps
CPU time 81.82 seconds
Started Dec 27 01:02:36 PM PST 23
Finished Dec 27 01:04:04 PM PST 23
Peak memory 251284 kb
Host smart-43ca4dd5-19ad-4641-8b96-21a66d3cbb7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751791265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.1751791265
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.2990050360
Short name T867
Test name
Test status
Simulation time 865372208738 ps
CPU time 729.04 seconds
Started Dec 27 01:02:32 PM PST 23
Finished Dec 27 01:14:46 PM PST 23
Peak memory 325156 kb
Host smart-5bff4102-d6b9-4d35-91d3-f66b7e1363f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2990050360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.2990050360
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1541184069
Short name T445
Test name
Test status
Simulation time 31057867 ps
CPU time 1.13 seconds
Started Dec 27 01:02:31 PM PST 23
Finished Dec 27 01:02:37 PM PST 23
Peak memory 212708 kb
Host smart-45c68bec-94b2-44a7-a598-0b2b33d6e10c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541184069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.1541184069
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.2165874080
Short name T64
Test name
Test status
Simulation time 52441443 ps
CPU time 0.9 seconds
Started Dec 27 01:02:34 PM PST 23
Finished Dec 27 01:02:40 PM PST 23
Peak memory 209696 kb
Host smart-199cf18c-1bb2-4ec6-9c49-0ef60f50d67a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165874080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.2165874080
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.3993986536
Short name T52
Test name
Test status
Simulation time 250895387 ps
CPU time 9.94 seconds
Started Dec 27 01:02:35 PM PST 23
Finished Dec 27 01:02:51 PM PST 23
Peak memory 218184 kb
Host smart-85a19046-3103-43d1-aa9b-793e2b741ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993986536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.3993986536
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.885718889
Short name T360
Test name
Test status
Simulation time 390201013 ps
CPU time 4.85 seconds
Started Dec 27 01:02:39 PM PST 23
Finished Dec 27 01:02:49 PM PST 23
Peak memory 209708 kb
Host smart-6c08708b-2602-4c3f-8e65-1e8a8541b613
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885718889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_ac
cess.885718889
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.2619157207
Short name T356
Test name
Test status
Simulation time 185832151 ps
CPU time 2.71 seconds
Started Dec 27 01:02:34 PM PST 23
Finished Dec 27 01:02:42 PM PST 23
Peak memory 218212 kb
Host smart-f8539fe1-7571-4c89-8830-43875524440f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619157207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.2619157207
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.679944478
Short name T946
Test name
Test status
Simulation time 1165412007 ps
CPU time 14.56 seconds
Started Dec 27 01:02:39 PM PST 23
Finished Dec 27 01:03:00 PM PST 23
Peak memory 218160 kb
Host smart-e1ddf795-f29b-41f0-82bb-adb8c5a20416
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679944478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.679944478
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.2978424168
Short name T681
Test name
Test status
Simulation time 1288065043 ps
CPU time 9.81 seconds
Started Dec 27 01:02:42 PM PST 23
Finished Dec 27 01:02:57 PM PST 23
Peak memory 218132 kb
Host smart-f34d9fbc-2270-4ead-8706-fa2a12893c5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978424168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.2978424168
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.408135985
Short name T311
Test name
Test status
Simulation time 305999661 ps
CPU time 7.78 seconds
Started Dec 27 01:02:38 PM PST 23
Finished Dec 27 01:02:52 PM PST 23
Peak memory 218144 kb
Host smart-9a118c46-7601-4e61-90d2-844521e35d33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408135985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.408135985
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.1052759852
Short name T786
Test name
Test status
Simulation time 235279528 ps
CPU time 10.85 seconds
Started Dec 27 01:02:31 PM PST 23
Finished Dec 27 01:02:47 PM PST 23
Peak memory 218132 kb
Host smart-90be6e3a-8fb8-4d2b-8439-e7e52af083fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052759852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.1052759852
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.1003383002
Short name T568
Test name
Test status
Simulation time 24449333 ps
CPU time 1.9 seconds
Started Dec 27 01:02:44 PM PST 23
Finished Dec 27 01:02:52 PM PST 23
Peak memory 213432 kb
Host smart-4c189de1-8f9e-4c27-b0cc-775e4dafea62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003383002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.1003383002
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.1586790396
Short name T678
Test name
Test status
Simulation time 494468795 ps
CPU time 30.22 seconds
Started Dec 27 01:02:37 PM PST 23
Finished Dec 27 01:03:13 PM PST 23
Peak memory 251172 kb
Host smart-99f33edb-0167-4046-94e9-08a0f691f4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586790396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.1586790396
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.469384013
Short name T342
Test name
Test status
Simulation time 143422288 ps
CPU time 8.72 seconds
Started Dec 27 01:02:35 PM PST 23
Finished Dec 27 01:02:50 PM PST 23
Peak memory 251216 kb
Host smart-3846b02d-c812-4d45-8950-0271e1650dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469384013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.469384013
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.605972109
Short name T661
Test name
Test status
Simulation time 31577268107 ps
CPU time 206.32 seconds
Started Dec 27 01:02:56 PM PST 23
Finished Dec 27 01:06:34 PM PST 23
Peak memory 272660 kb
Host smart-41986d43-a39f-4fd7-9b2a-8d8ba31788d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605972109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.605972109
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1175729719
Short name T728
Test name
Test status
Simulation time 43074632 ps
CPU time 0.89 seconds
Started Dec 27 01:02:29 PM PST 23
Finished Dec 27 01:02:36 PM PST 23
Peak memory 208408 kb
Host smart-43758384-14be-4c44-9364-91db3af7c59e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175729719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.1175729719
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3317439900
Short name T535
Test name
Test status
Simulation time 101610842 ps
CPU time 0.84 seconds
Started Dec 27 01:02:41 PM PST 23
Finished Dec 27 01:02:47 PM PST 23
Peak memory 209492 kb
Host smart-183c4c75-9ed1-4191-bdd2-6f7cdee59901
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317439900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3317439900
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.77506847
Short name T874
Test name
Test status
Simulation time 2554114444 ps
CPU time 16.23 seconds
Started Dec 27 01:02:40 PM PST 23
Finished Dec 27 01:03:02 PM PST 23
Peak memory 218272 kb
Host smart-b250b134-1bc5-44d9-ad0e-0dd9e47524b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77506847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.77506847
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.2059356394
Short name T890
Test name
Test status
Simulation time 162334645 ps
CPU time 2.51 seconds
Started Dec 27 01:02:39 PM PST 23
Finished Dec 27 01:02:47 PM PST 23
Peak memory 209712 kb
Host smart-9b6ff0cb-1d25-48a1-8f10-687b855232e3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059356394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_a
ccess.2059356394
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.3541351419
Short name T532
Test name
Test status
Simulation time 877201972 ps
CPU time 2.95 seconds
Started Dec 27 01:02:41 PM PST 23
Finished Dec 27 01:02:49 PM PST 23
Peak memory 218204 kb
Host smart-17ba1aec-0bb3-4658-88a6-96e36c7b7c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541351419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.3541351419
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.4075724278
Short name T863
Test name
Test status
Simulation time 748324507 ps
CPU time 14.04 seconds
Started Dec 27 01:02:43 PM PST 23
Finished Dec 27 01:03:02 PM PST 23
Peak memory 218140 kb
Host smart-c0908c6d-e61f-4243-aa36-d6cd76ea109b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075724278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.4075724278
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.588123894
Short name T883
Test name
Test status
Simulation time 511830083 ps
CPU time 13.06 seconds
Started Dec 27 01:02:44 PM PST 23
Finished Dec 27 01:03:02 PM PST 23
Peak memory 218156 kb
Host smart-fba30755-d6e2-4da0-b5a4-07531a3ecd39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588123894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_di
gest.588123894
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.3892998364
Short name T310
Test name
Test status
Simulation time 1116916689 ps
CPU time 7.37 seconds
Started Dec 27 01:02:45 PM PST 23
Finished Dec 27 01:02:59 PM PST 23
Peak memory 218168 kb
Host smart-daa24cd4-cd85-4c82-8458-285ccf1b7afc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892998364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
3892998364
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.416775556
Short name T931
Test name
Test status
Simulation time 478887611 ps
CPU time 9.15 seconds
Started Dec 27 01:02:40 PM PST 23
Finished Dec 27 01:02:55 PM PST 23
Peak memory 218156 kb
Host smart-28e4b84f-3829-405f-84c2-8666bca48db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416775556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.416775556
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.2985661648
Short name T451
Test name
Test status
Simulation time 133190283 ps
CPU time 2.72 seconds
Started Dec 27 01:02:41 PM PST 23
Finished Dec 27 01:02:49 PM PST 23
Peak memory 213816 kb
Host smart-8ed838e8-8b90-4268-ad77-65b089e221c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985661648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.2985661648
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.437426035
Short name T929
Test name
Test status
Simulation time 2351056767 ps
CPU time 25.94 seconds
Started Dec 27 01:02:34 PM PST 23
Finished Dec 27 01:03:05 PM PST 23
Peak memory 251232 kb
Host smart-0d16aca3-5828-4682-b9f4-ab003f1941e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437426035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.437426035
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.1399264087
Short name T866
Test name
Test status
Simulation time 217291620 ps
CPU time 5.98 seconds
Started Dec 27 01:02:41 PM PST 23
Finished Dec 27 01:02:53 PM PST 23
Peak memory 245992 kb
Host smart-a4c9f7aa-cceb-4bdf-b6dd-714bf14880a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399264087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.1399264087
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.896110940
Short name T484
Test name
Test status
Simulation time 5245599634 ps
CPU time 57.59 seconds
Started Dec 27 01:02:39 PM PST 23
Finished Dec 27 01:03:43 PM PST 23
Peak memory 220960 kb
Host smart-a9390dd6-28bb-4223-afbd-e917f8606c21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896110940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.896110940
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1114729805
Short name T303
Test name
Test status
Simulation time 14337198 ps
CPU time 0.72 seconds
Started Dec 27 01:02:53 PM PST 23
Finished Dec 27 01:03:06 PM PST 23
Peak memory 207968 kb
Host smart-2cc72e33-7335-4901-ba93-bc2a7e2d59f1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114729805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.1114729805
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.3138781469
Short name T875
Test name
Test status
Simulation time 30449891 ps
CPU time 1.02 seconds
Started Dec 27 01:02:45 PM PST 23
Finished Dec 27 01:02:52 PM PST 23
Peak memory 209712 kb
Host smart-345d33fc-602c-44f8-bdf1-15478bd3d727
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138781469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.3138781469
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.1214071933
Short name T461
Test name
Test status
Simulation time 350066808 ps
CPU time 15.56 seconds
Started Dec 27 01:02:52 PM PST 23
Finished Dec 27 01:03:15 PM PST 23
Peak memory 218244 kb
Host smart-51e64d52-453a-4283-90f0-4b1191d167e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214071933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.1214071933
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.2789324624
Short name T711
Test name
Test status
Simulation time 391041320 ps
CPU time 3.1 seconds
Started Dec 27 01:02:34 PM PST 23
Finished Dec 27 01:02:42 PM PST 23
Peak memory 209572 kb
Host smart-63414e4a-a1ad-4ffd-9e7c-e4dfc3c55183
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789324624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_a
ccess.2789324624
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.2471256034
Short name T379
Test name
Test status
Simulation time 322460672 ps
CPU time 4.34 seconds
Started Dec 27 01:02:48 PM PST 23
Finished Dec 27 01:03:00 PM PST 23
Peak memory 218136 kb
Host smart-da8f053c-2252-4571-9d09-0040c5c39829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471256034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.2471256034
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.3870414526
Short name T524
Test name
Test status
Simulation time 1756636641 ps
CPU time 16.52 seconds
Started Dec 27 01:02:44 PM PST 23
Finished Dec 27 01:03:06 PM PST 23
Peak memory 219232 kb
Host smart-5ad0ae40-4dc6-488f-b797-3adb322f28c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870414526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.3870414526
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.1060048000
Short name T759
Test name
Test status
Simulation time 949357204 ps
CPU time 7.89 seconds
Started Dec 27 01:02:59 PM PST 23
Finished Dec 27 01:03:21 PM PST 23
Peak memory 218164 kb
Host smart-572f489a-fd30-4253-b824-a62f074591c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060048000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.1060048000
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.3137124204
Short name T448
Test name
Test status
Simulation time 1952124022 ps
CPU time 9.66 seconds
Started Dec 27 01:02:51 PM PST 23
Finished Dec 27 01:03:08 PM PST 23
Peak memory 217976 kb
Host smart-8458c912-a242-4b19-9d1c-8f7939801519
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137124204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
3137124204
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.2951980065
Short name T350
Test name
Test status
Simulation time 983952455 ps
CPU time 7.29 seconds
Started Dec 27 01:02:40 PM PST 23
Finished Dec 27 01:02:53 PM PST 23
Peak memory 218224 kb
Host smart-e06ca5d2-df2e-41d7-81a8-416ac95136f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951980065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.2951980065
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.97885281
Short name T972
Test name
Test status
Simulation time 52076496 ps
CPU time 0.98 seconds
Started Dec 27 01:02:52 PM PST 23
Finished Dec 27 01:03:05 PM PST 23
Peak memory 211656 kb
Host smart-01303658-0843-4faa-8366-143699abaea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97885281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.97885281
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.2479801253
Short name T23
Test name
Test status
Simulation time 741539918 ps
CPU time 28.83 seconds
Started Dec 27 01:02:44 PM PST 23
Finished Dec 27 01:03:18 PM PST 23
Peak memory 251104 kb
Host smart-e73a915c-cb7c-42ea-9939-8aab1e8dafbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479801253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.2479801253
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.2700412316
Short name T817
Test name
Test status
Simulation time 945253542 ps
CPU time 4.26 seconds
Started Dec 27 01:02:39 PM PST 23
Finished Dec 27 01:02:49 PM PST 23
Peak memory 222240 kb
Host smart-d6774252-3327-4db3-a346-ff7e6b3c844c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700412316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.2700412316
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.2693511348
Short name T947
Test name
Test status
Simulation time 491186110 ps
CPU time 24.86 seconds
Started Dec 27 01:02:58 PM PST 23
Finished Dec 27 01:03:36 PM PST 23
Peak memory 247988 kb
Host smart-b5154c9a-d4d9-4fbc-af92-20ed2fabd329
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693511348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.2693511348
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3226369095
Short name T769
Test name
Test status
Simulation time 45342637 ps
CPU time 0.8 seconds
Started Dec 27 01:02:37 PM PST 23
Finished Dec 27 01:02:44 PM PST 23
Peak memory 208344 kb
Host smart-3a1cfc87-69de-483a-92c9-e8d7afbb462e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226369095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.3226369095
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.205783335
Short name T895
Test name
Test status
Simulation time 19185438 ps
CPU time 0.97 seconds
Started Dec 27 01:02:41 PM PST 23
Finished Dec 27 01:02:47 PM PST 23
Peak memory 208412 kb
Host smart-9356b5d8-7ef9-4fdc-b5bc-36f40189baff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205783335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.205783335
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.1595144665
Short name T959
Test name
Test status
Simulation time 2799294317 ps
CPU time 19.06 seconds
Started Dec 27 01:02:42 PM PST 23
Finished Dec 27 01:03:06 PM PST 23
Peak memory 218284 kb
Host smart-f585369f-00a4-4b9d-a665-f842ec9e1e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595144665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.1595144665
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.3049873524
Short name T456
Test name
Test status
Simulation time 767064161 ps
CPU time 17.1 seconds
Started Dec 27 01:02:46 PM PST 23
Finished Dec 27 01:03:11 PM PST 23
Peak memory 209628 kb
Host smart-3f11d384-9c73-457c-8e37-6e0391af8b87
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049873524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_a
ccess.3049873524
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.3277439224
Short name T546
Test name
Test status
Simulation time 81707347 ps
CPU time 2.58 seconds
Started Dec 27 01:02:40 PM PST 23
Finished Dec 27 01:02:48 PM PST 23
Peak memory 218188 kb
Host smart-97bc094e-670b-4c1d-878b-919f99ba9150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277439224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3277439224
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.2961432426
Short name T853
Test name
Test status
Simulation time 633351439 ps
CPU time 18.29 seconds
Started Dec 27 01:02:51 PM PST 23
Finished Dec 27 01:03:17 PM PST 23
Peak memory 219088 kb
Host smart-418eee78-3d7c-44c8-95e4-d5bc60a87708
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961432426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.2961432426
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.2257177760
Short name T971
Test name
Test status
Simulation time 779051871 ps
CPU time 14.49 seconds
Started Dec 27 01:02:49 PM PST 23
Finished Dec 27 01:03:11 PM PST 23
Peak memory 218000 kb
Host smart-833aec05-d326-4ff1-99a3-f5d22a368379
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257177760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.2257177760
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.904713868
Short name T794
Test name
Test status
Simulation time 1226940287 ps
CPU time 6.44 seconds
Started Dec 27 01:02:51 PM PST 23
Finished Dec 27 01:03:05 PM PST 23
Peak memory 218152 kb
Host smart-599a30c7-ea80-45a2-9583-2f1777f39bf2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904713868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.904713868
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.3613102291
Short name T718
Test name
Test status
Simulation time 825646940 ps
CPU time 10.26 seconds
Started Dec 27 01:02:33 PM PST 23
Finished Dec 27 01:02:49 PM PST 23
Peak memory 218236 kb
Host smart-50f4d9dd-9589-4cb6-8a1d-3ea2631cec6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613102291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.3613102291
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.4023503972
Short name T540
Test name
Test status
Simulation time 239545729 ps
CPU time 3.02 seconds
Started Dec 27 01:02:42 PM PST 23
Finished Dec 27 01:02:50 PM PST 23
Peak memory 214436 kb
Host smart-affc1486-0556-47fc-b0f1-4bd42c9d1d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023503972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.4023503972
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.1080595846
Short name T635
Test name
Test status
Simulation time 316564470 ps
CPU time 26.94 seconds
Started Dec 27 01:02:36 PM PST 23
Finished Dec 27 01:03:09 PM PST 23
Peak memory 251072 kb
Host smart-e6023fda-5709-413b-a111-ed485c0e65b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080595846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.1080595846
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.2202355374
Short name T481
Test name
Test status
Simulation time 447895718 ps
CPU time 7.23 seconds
Started Dec 27 01:02:36 PM PST 23
Finished Dec 27 01:02:49 PM PST 23
Peak memory 246832 kb
Host smart-3f2c1ab1-0832-4085-955d-96cb126715e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202355374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2202355374
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.3575798386
Short name T777
Test name
Test status
Simulation time 10696372143 ps
CPU time 239.66 seconds
Started Dec 27 01:02:37 PM PST 23
Finished Dec 27 01:06:43 PM PST 23
Peak memory 272332 kb
Host smart-bf4c3600-da86-49c2-a424-63b286f33542
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575798386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.3575798386
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.1063848641
Short name T400
Test name
Test status
Simulation time 27749600 ps
CPU time 0.79 seconds
Started Dec 27 01:02:37 PM PST 23
Finished Dec 27 01:02:44 PM PST 23
Peak memory 208192 kb
Host smart-18a855c1-6dfa-4591-8acb-5a2bcd3dc9b4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063848641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.1063848641
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.1540277257
Short name T878
Test name
Test status
Simulation time 16872307 ps
CPU time 1.12 seconds
Started Dec 27 01:02:46 PM PST 23
Finished Dec 27 01:02:53 PM PST 23
Peak memory 208584 kb
Host smart-883b7665-c683-472e-86ee-2b3f20e2ed01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540277257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1540277257
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.3499075438
Short name T521
Test name
Test status
Simulation time 2661182280 ps
CPU time 18.38 seconds
Started Dec 27 01:02:35 PM PST 23
Finished Dec 27 01:02:59 PM PST 23
Peak memory 218244 kb
Host smart-19e93aac-7a88-4fcd-b99c-4a149cfeec36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499075438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.3499075438
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.2223098886
Short name T822
Test name
Test status
Simulation time 196592282 ps
CPU time 5.45 seconds
Started Dec 27 01:02:42 PM PST 23
Finished Dec 27 01:02:52 PM PST 23
Peak memory 209688 kb
Host smart-cc911103-bcf3-4fd7-886e-09a897f5e06f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223098886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_a
ccess.2223098886
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.2393963406
Short name T893
Test name
Test status
Simulation time 136720127 ps
CPU time 2.05 seconds
Started Dec 27 01:02:45 PM PST 23
Finished Dec 27 01:02:53 PM PST 23
Peak memory 218228 kb
Host smart-afd3372a-cce3-4d41-8d8c-22b09b380d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393963406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.2393963406
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.1425082097
Short name T700
Test name
Test status
Simulation time 8591470347 ps
CPU time 16.57 seconds
Started Dec 27 01:02:40 PM PST 23
Finished Dec 27 01:03:02 PM PST 23
Peak memory 219276 kb
Host smart-d54a2cc8-930e-4959-9db8-d90d2d68f4b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425082097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1425082097
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.1844497037
Short name T441
Test name
Test status
Simulation time 2848347260 ps
CPU time 19.55 seconds
Started Dec 27 01:02:34 PM PST 23
Finished Dec 27 01:02:59 PM PST 23
Peak memory 218196 kb
Host smart-fa43a59c-872e-4116-8ada-cf2064dd9e03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844497037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.1844497037
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.3209353897
Short name T919
Test name
Test status
Simulation time 3046455284 ps
CPU time 10.41 seconds
Started Dec 27 01:02:55 PM PST 23
Finished Dec 27 01:03:17 PM PST 23
Peak memory 218052 kb
Host smart-27747f97-b4c5-44a0-8ba7-461a7479cc9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209353897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
3209353897
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.591995348
Short name T943
Test name
Test status
Simulation time 2877775444 ps
CPU time 10.03 seconds
Started Dec 27 01:02:37 PM PST 23
Finished Dec 27 01:02:53 PM PST 23
Peak memory 218260 kb
Host smart-55a6ca21-c9c8-41f1-9e69-6d2921064464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591995348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.591995348
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.1425025082
Short name T698
Test name
Test status
Simulation time 197684200 ps
CPU time 2.97 seconds
Started Dec 27 01:02:55 PM PST 23
Finished Dec 27 01:03:10 PM PST 23
Peak memory 214124 kb
Host smart-9dfcd8ef-eb72-4278-acb9-a4f4d85edccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425025082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.1425025082
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.464766748
Short name T646
Test name
Test status
Simulation time 218689234 ps
CPU time 21.64 seconds
Started Dec 27 01:02:45 PM PST 23
Finished Dec 27 01:03:13 PM PST 23
Peak memory 251128 kb
Host smart-0c8faae0-a7d7-423b-97a4-2ce0e18ca645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464766748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.464766748
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.957731942
Short name T655
Test name
Test status
Simulation time 69528712 ps
CPU time 3.07 seconds
Started Dec 27 01:02:49 PM PST 23
Finished Dec 27 01:03:00 PM PST 23
Peak memory 222272 kb
Host smart-5dffbca8-c0b7-41bc-81f5-0a3285722696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957731942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.957731942
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.1319269498
Short name T444
Test name
Test status
Simulation time 21584206668 ps
CPU time 297.7 seconds
Started Dec 27 01:02:41 PM PST 23
Finished Dec 27 01:07:44 PM PST 23
Peak memory 316724 kb
Host smart-2e76ec74-9ede-4bf0-a82b-2248c9273c8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319269498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.1319269498
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2313506191
Short name T28
Test name
Test status
Simulation time 12381932 ps
CPU time 0.9 seconds
Started Dec 27 01:02:41 PM PST 23
Finished Dec 27 01:02:47 PM PST 23
Peak memory 208204 kb
Host smart-c17adb4e-003d-44ea-85ef-576b6a1947a4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313506191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.2313506191
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.3299704039
Short name T69
Test name
Test status
Simulation time 20511660 ps
CPU time 0.96 seconds
Started Dec 27 01:01:18 PM PST 23
Finished Dec 27 01:01:24 PM PST 23
Peak memory 209728 kb
Host smart-1d522819-e516-452f-9ca2-dc3d9d252e1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299704039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.3299704039
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.3918734715
Short name T317
Test name
Test status
Simulation time 12305144 ps
CPU time 0.84 seconds
Started Dec 27 01:01:11 PM PST 23
Finished Dec 27 01:01:15 PM PST 23
Peak memory 209456 kb
Host smart-876cf1eb-1ccc-405e-9246-957c9df750ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918734715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.3918734715
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.1635071048
Short name T707
Test name
Test status
Simulation time 897085362 ps
CPU time 12.89 seconds
Started Dec 27 01:01:07 PM PST 23
Finished Dec 27 01:01:23 PM PST 23
Peak memory 218236 kb
Host smart-f7cf2022-d5cd-4343-8d2e-5253242eea30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635071048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1635071048
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.1827982489
Short name T375
Test name
Test status
Simulation time 1851167351 ps
CPU time 9 seconds
Started Dec 27 01:01:16 PM PST 23
Finished Dec 27 01:01:30 PM PST 23
Peak memory 209708 kb
Host smart-86fc38cb-43dc-40fc-b2db-0039e18e2dde
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827982489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_ac
cess.1827982489
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.1844667416
Short name T784
Test name
Test status
Simulation time 2061247511 ps
CPU time 33.63 seconds
Started Dec 27 01:01:06 PM PST 23
Finished Dec 27 01:01:42 PM PST 23
Peak memory 218040 kb
Host smart-f4a2ffed-7f3c-47dc-89f9-e9e84bc17225
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844667416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.1844667416
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.1520084686
Short name T937
Test name
Test status
Simulation time 4391249988 ps
CPU time 21.41 seconds
Started Dec 27 01:01:13 PM PST 23
Finished Dec 27 01:01:38 PM PST 23
Peak memory 217956 kb
Host smart-622b75cc-9e0e-418b-a354-93d0270c79f6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520084686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
priority.1520084686
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.3271389553
Short name T397
Test name
Test status
Simulation time 651342531 ps
CPU time 5.6 seconds
Started Dec 27 01:01:22 PM PST 23
Finished Dec 27 01:01:34 PM PST 23
Peak memory 218092 kb
Host smart-633b0c72-db99-496e-9555-a9cc5c904359
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271389553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.3271389553
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1320272785
Short name T523
Test name
Test status
Simulation time 2683006648 ps
CPU time 20.37 seconds
Started Dec 27 01:01:17 PM PST 23
Finished Dec 27 01:01:42 PM PST 23
Peak memory 213492 kb
Host smart-a5ef986e-7c72-42e7-baf2-e428cc4ea041
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320272785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.1320272785
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.234237803
Short name T706
Test name
Test status
Simulation time 777339803 ps
CPU time 5.45 seconds
Started Dec 27 01:01:16 PM PST 23
Finished Dec 27 01:01:26 PM PST 23
Peak memory 213160 kb
Host smart-d48ea8dd-2415-48d3-b73b-12c50f98b55f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234237803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.234237803
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3594076136
Short name T856
Test name
Test status
Simulation time 13056189934 ps
CPU time 50.05 seconds
Started Dec 27 01:01:10 PM PST 23
Finished Dec 27 01:02:04 PM PST 23
Peak memory 277716 kb
Host smart-bbdeaad7-fb5d-4e84-8bef-db58c5b7a11c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594076136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.3594076136
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.1250446266
Short name T885
Test name
Test status
Simulation time 26366805288 ps
CPU time 23.57 seconds
Started Dec 27 01:01:11 PM PST 23
Finished Dec 27 01:01:38 PM PST 23
Peak memory 250536 kb
Host smart-c44ca0b3-ee0f-4fdf-b50e-06be82957eaf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250446266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.1250446266
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.2604513135
Short name T781
Test name
Test status
Simulation time 492858729 ps
CPU time 1.99 seconds
Started Dec 27 01:01:18 PM PST 23
Finished Dec 27 01:01:25 PM PST 23
Peak memory 218240 kb
Host smart-5265a88e-7d21-42d1-8d3e-389ddac85610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604513135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.2604513135
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.4138149460
Short name T79
Test name
Test status
Simulation time 1596719595 ps
CPU time 20.32 seconds
Started Dec 27 01:01:15 PM PST 23
Finished Dec 27 01:01:40 PM PST 23
Peak memory 214256 kb
Host smart-e35511c9-85b0-4c26-b908-331812270c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138149460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.4138149460
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.1468190542
Short name T732
Test name
Test status
Simulation time 1692213394 ps
CPU time 17.02 seconds
Started Dec 27 01:01:14 PM PST 23
Finished Dec 27 01:01:36 PM PST 23
Peak memory 219268 kb
Host smart-54cb03ad-8bb0-4d21-938e-29c79b19dd62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468190542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.1468190542
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.3518172790
Short name T316
Test name
Test status
Simulation time 216840352 ps
CPU time 11.1 seconds
Started Dec 27 01:01:12 PM PST 23
Finished Dec 27 01:01:27 PM PST 23
Peak memory 218156 kb
Host smart-63fc64ae-f08c-4966-b12c-4d460065ad2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518172790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.3518172790
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.2528043193
Short name T735
Test name
Test status
Simulation time 301727323 ps
CPU time 7.28 seconds
Started Dec 27 01:01:16 PM PST 23
Finished Dec 27 01:01:29 PM PST 23
Peak memory 218136 kb
Host smart-c0c83900-65a1-40a8-ba88-333bc140a97b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528043193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.2
528043193
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.68560889
Short name T490
Test name
Test status
Simulation time 1111911349 ps
CPU time 11.74 seconds
Started Dec 27 01:01:15 PM PST 23
Finished Dec 27 01:01:31 PM PST 23
Peak memory 218236 kb
Host smart-7fbcea05-ddeb-4937-afaa-e63787275275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68560889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.68560889
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.643186124
Short name T717
Test name
Test status
Simulation time 67743397 ps
CPU time 3.59 seconds
Started Dec 27 01:01:08 PM PST 23
Finished Dec 27 01:01:15 PM PST 23
Peak memory 213988 kb
Host smart-1a354048-4cc6-48e3-be0f-63fe463b7701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643186124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.643186124
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.2824870905
Short name T852
Test name
Test status
Simulation time 233472128 ps
CPU time 30.24 seconds
Started Dec 27 01:01:11 PM PST 23
Finished Dec 27 01:01:45 PM PST 23
Peak memory 251040 kb
Host smart-5f550fcc-23cd-4d8b-a887-a2a47f5e4447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824870905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.2824870905
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.24030500
Short name T518
Test name
Test status
Simulation time 241066343 ps
CPU time 6.38 seconds
Started Dec 27 01:01:13 PM PST 23
Finished Dec 27 01:01:24 PM PST 23
Peak memory 250720 kb
Host smart-59cad030-cba6-45f9-972c-ae2800c3dad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24030500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.24030500
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.107071275
Short name T780
Test name
Test status
Simulation time 65321172233 ps
CPU time 117.12 seconds
Started Dec 27 01:01:15 PM PST 23
Finished Dec 27 01:03:16 PM PST 23
Peak memory 274184 kb
Host smart-b58fd07d-db73-42f0-bcd0-f22fcc4d9ac9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107071275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.107071275
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.131913582
Short name T802
Test name
Test status
Simulation time 23743288 ps
CPU time 1.23 seconds
Started Dec 27 01:02:46 PM PST 23
Finished Dec 27 01:02:53 PM PST 23
Peak memory 208548 kb
Host smart-2f35fa37-be56-4001-9093-6235a62ef4d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131913582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.131913582
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.1624490323
Short name T302
Test name
Test status
Simulation time 727094635 ps
CPU time 7.33 seconds
Started Dec 27 01:02:37 PM PST 23
Finished Dec 27 01:02:51 PM PST 23
Peak memory 218116 kb
Host smart-a60a62b2-9578-47be-bba5-3c7564dbdafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624490323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.1624490323
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.961376919
Short name T627
Test name
Test status
Simulation time 999255242 ps
CPU time 12.69 seconds
Started Dec 27 01:02:35 PM PST 23
Finished Dec 27 01:02:53 PM PST 23
Peak memory 209616 kb
Host smart-e3c9f6e4-38bf-49d4-928a-a3527e51d153
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961376919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_ac
cess.961376919
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.666870278
Short name T509
Test name
Test status
Simulation time 242926192 ps
CPU time 3.06 seconds
Started Dec 27 01:02:41 PM PST 23
Finished Dec 27 01:02:49 PM PST 23
Peak memory 218216 kb
Host smart-9bb7a4ea-e589-4ebf-b0a7-06677d01884a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666870278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.666870278
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.588109337
Short name T372
Test name
Test status
Simulation time 254212885 ps
CPU time 11.2 seconds
Started Dec 27 01:02:39 PM PST 23
Finished Dec 27 01:02:56 PM PST 23
Peak memory 218324 kb
Host smart-660966f4-0400-4461-bd0a-2f003556aec7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588109337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.588109337
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.677984973
Short name T346
Test name
Test status
Simulation time 4477833344 ps
CPU time 22.83 seconds
Started Dec 27 01:02:54 PM PST 23
Finished Dec 27 01:03:29 PM PST 23
Peak memory 218232 kb
Host smart-e8bdd948-8013-4b81-9aed-cc2330c57cb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677984973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_di
gest.677984973
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.4154118155
Short name T628
Test name
Test status
Simulation time 701649325 ps
CPU time 7.94 seconds
Started Dec 27 01:02:40 PM PST 23
Finished Dec 27 01:02:54 PM PST 23
Peak memory 218148 kb
Host smart-df6ab847-a672-46dd-a27c-359c3c938533
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154118155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
4154118155
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.301912494
Short name T513
Test name
Test status
Simulation time 1117454546 ps
CPU time 11.35 seconds
Started Dec 27 01:02:50 PM PST 23
Finished Dec 27 01:03:09 PM PST 23
Peak memory 218160 kb
Host smart-34673422-0e4b-4044-a300-6b683e64aec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301912494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.301912494
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.1138315882
Short name T637
Test name
Test status
Simulation time 63396945 ps
CPU time 3.44 seconds
Started Dec 27 01:02:41 PM PST 23
Finished Dec 27 01:02:50 PM PST 23
Peak memory 214332 kb
Host smart-0ba28740-b763-4584-a47f-f2626bb4786f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138315882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.1138315882
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.2822567995
Short name T950
Test name
Test status
Simulation time 192447706 ps
CPU time 18.3 seconds
Started Dec 27 01:02:55 PM PST 23
Finished Dec 27 01:03:25 PM PST 23
Peak memory 251028 kb
Host smart-1854d2f0-fc0c-48d5-b07e-cd7c79401af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822567995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.2822567995
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.3128244070
Short name T912
Test name
Test status
Simulation time 69564608 ps
CPU time 6.24 seconds
Started Dec 27 01:02:41 PM PST 23
Finished Dec 27 01:02:52 PM PST 23
Peak memory 250484 kb
Host smart-ff10c873-52d3-40b3-ab1b-8357879dabbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128244070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.3128244070
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.2187412845
Short name T641
Test name
Test status
Simulation time 8201733096 ps
CPU time 299.33 seconds
Started Dec 27 01:02:46 PM PST 23
Finished Dec 27 01:07:52 PM PST 23
Peak memory 267752 kb
Host smart-6f22b679-d506-4129-865d-04333cec83e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187412845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.2187412845
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.4144765991
Short name T951
Test name
Test status
Simulation time 33411569 ps
CPU time 0.83 seconds
Started Dec 27 01:02:47 PM PST 23
Finished Dec 27 01:02:54 PM PST 23
Peak memory 208144 kb
Host smart-7b4410e6-41cd-4994-9f22-eaec9bb0f4b8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144765991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.4144765991
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.639308872
Short name T592
Test name
Test status
Simulation time 25473659 ps
CPU time 0.95 seconds
Started Dec 27 01:02:41 PM PST 23
Finished Dec 27 01:02:47 PM PST 23
Peak memory 209676 kb
Host smart-717ce46c-c570-4213-a3c2-41f5dd32f061
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639308872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.639308872
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.4017516518
Short name T33
Test name
Test status
Simulation time 378896387 ps
CPU time 12.47 seconds
Started Dec 27 01:02:55 PM PST 23
Finished Dec 27 01:03:20 PM PST 23
Peak memory 218340 kb
Host smart-3fa8d7d6-0aba-45b7-a00e-49454deb0666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017516518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.4017516518
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.3761699715
Short name T837
Test name
Test status
Simulation time 1458506919 ps
CPU time 5.06 seconds
Started Dec 27 01:02:37 PM PST 23
Finished Dec 27 01:02:48 PM PST 23
Peak memory 209628 kb
Host smart-6db9c34d-e988-4d5e-9147-71aa2bcaa703
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761699715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_a
ccess.3761699715
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.2111901772
Short name T776
Test name
Test status
Simulation time 66863580 ps
CPU time 2.92 seconds
Started Dec 27 01:02:56 PM PST 23
Finished Dec 27 01:03:11 PM PST 23
Peak memory 218132 kb
Host smart-faf24afe-6049-4565-aaa4-9306fe0669fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111901772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.2111901772
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.348573361
Short name T545
Test name
Test status
Simulation time 1725037810 ps
CPU time 14.55 seconds
Started Dec 27 01:02:49 PM PST 23
Finished Dec 27 01:03:11 PM PST 23
Peak memory 218564 kb
Host smart-5a34ee22-2a84-4859-83ef-761cbf487ef7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348573361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.348573361
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.4140911207
Short name T336
Test name
Test status
Simulation time 4054780942 ps
CPU time 19.07 seconds
Started Dec 27 01:02:56 PM PST 23
Finished Dec 27 01:03:27 PM PST 23
Peak memory 218168 kb
Host smart-d52cdae3-ca34-4be4-bf19-31f9ee8de887
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140911207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.4140911207
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.3999118479
Short name T489
Test name
Test status
Simulation time 2370563602 ps
CPU time 12.48 seconds
Started Dec 27 01:02:53 PM PST 23
Finished Dec 27 01:03:17 PM PST 23
Peak memory 218264 kb
Host smart-f22304d2-90c7-4a53-b140-4fa546ee6a05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999118479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
3999118479
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.3107953905
Short name T945
Test name
Test status
Simulation time 485186035 ps
CPU time 10.09 seconds
Started Dec 27 01:02:45 PM PST 23
Finished Dec 27 01:03:01 PM PST 23
Peak memory 218244 kb
Host smart-9d3b73a2-7f84-476f-b4fd-0e8ea33ccf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107953905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.3107953905
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.2763648983
Short name T391
Test name
Test status
Simulation time 63200640 ps
CPU time 1.57 seconds
Started Dec 27 01:02:39 PM PST 23
Finished Dec 27 01:02:46 PM PST 23
Peak memory 213540 kb
Host smart-0f47ba81-ee86-4677-99f8-6240b175b3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763648983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2763648983
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.2767315331
Short name T424
Test name
Test status
Simulation time 204173971 ps
CPU time 17.86 seconds
Started Dec 27 01:02:50 PM PST 23
Finished Dec 27 01:03:15 PM PST 23
Peak memory 250940 kb
Host smart-6b6c73c2-1d63-4e40-bd39-2e0dcfbc732d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767315331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.2767315331
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.2176743993
Short name T320
Test name
Test status
Simulation time 300162435 ps
CPU time 9.53 seconds
Started Dec 27 01:02:52 PM PST 23
Finished Dec 27 01:03:12 PM PST 23
Peak memory 251056 kb
Host smart-7c1127ad-1ab7-4632-ba4a-8648a5564a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176743993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.2176743993
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.1458552447
Short name T527
Test name
Test status
Simulation time 36283597655 ps
CPU time 536.63 seconds
Started Dec 27 01:02:51 PM PST 23
Finished Dec 27 01:11:55 PM PST 23
Peak memory 267688 kb
Host smart-4ea5951c-d071-41b7-b288-661338bac528
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458552447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.1458552447
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.917438057
Short name T595
Test name
Test status
Simulation time 38679421 ps
CPU time 0.74 seconds
Started Dec 27 01:02:37 PM PST 23
Finished Dec 27 01:02:43 PM PST 23
Peak memory 207988 kb
Host smart-4d0b4101-ed01-4530-9b58-59fb13e863fc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917438057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ct
rl_volatile_unlock_smoke.917438057
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.1824055571
Short name T558
Test name
Test status
Simulation time 44942734 ps
CPU time 1.16 seconds
Started Dec 27 01:02:50 PM PST 23
Finished Dec 27 01:02:59 PM PST 23
Peak memory 209704 kb
Host smart-736e978e-2147-474a-a357-65b9f2bde911
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824055571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1824055571
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.25928716
Short name T873
Test name
Test status
Simulation time 609697338 ps
CPU time 12.02 seconds
Started Dec 27 01:02:56 PM PST 23
Finished Dec 27 01:03:20 PM PST 23
Peak memory 218240 kb
Host smart-b8686705-8dd2-4e65-b683-2ed3c70e7ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25928716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.25928716
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.1049267782
Short name T352
Test name
Test status
Simulation time 761230327 ps
CPU time 18.1 seconds
Started Dec 27 01:02:47 PM PST 23
Finished Dec 27 01:03:12 PM PST 23
Peak memory 209676 kb
Host smart-237bab2b-8675-4d5a-ba1f-16b5e92bfc4d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049267782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_a
ccess.1049267782
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.1084548359
Short name T642
Test name
Test status
Simulation time 240649611 ps
CPU time 1.88 seconds
Started Dec 27 01:02:51 PM PST 23
Finished Dec 27 01:03:00 PM PST 23
Peak memory 218124 kb
Host smart-d1cd21b9-06f9-4130-9fb1-bec224f48ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084548359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.1084548359
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.1276436819
Short name T955
Test name
Test status
Simulation time 387112252 ps
CPU time 11.2 seconds
Started Dec 27 01:02:54 PM PST 23
Finished Dec 27 01:03:17 PM PST 23
Peak memory 218312 kb
Host smart-6b982364-1dac-4de5-972c-c63414ea9eb2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276436819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.1276436819
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.2728999511
Short name T606
Test name
Test status
Simulation time 377999221 ps
CPU time 11.61 seconds
Started Dec 27 01:02:52 PM PST 23
Finished Dec 27 01:03:14 PM PST 23
Peak memory 218184 kb
Host smart-40884afc-16c1-4239-9c36-64222d551a60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728999511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.2728999511
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.3900416854
Short name T752
Test name
Test status
Simulation time 1508742329 ps
CPU time 14.26 seconds
Started Dec 27 01:02:59 PM PST 23
Finished Dec 27 01:03:27 PM PST 23
Peak memory 218044 kb
Host smart-1af82a1b-ccfe-4a85-94be-8e3428314247
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900416854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
3900416854
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.4240835083
Short name T697
Test name
Test status
Simulation time 184229759 ps
CPU time 8.61 seconds
Started Dec 27 01:02:42 PM PST 23
Finished Dec 27 01:02:56 PM PST 23
Peak memory 218208 kb
Host smart-29034303-bbf4-49b8-8612-25d851d1c170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240835083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.4240835083
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.1971256568
Short name T80
Test name
Test status
Simulation time 16411501 ps
CPU time 1.38 seconds
Started Dec 27 01:02:44 PM PST 23
Finished Dec 27 01:02:51 PM PST 23
Peak memory 212928 kb
Host smart-437283f0-58e8-4ae8-b238-ed22e0d37034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971256568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.1971256568
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.765214027
Short name T792
Test name
Test status
Simulation time 2456121580 ps
CPU time 26.62 seconds
Started Dec 27 01:02:58 PM PST 23
Finished Dec 27 01:03:38 PM PST 23
Peak memory 250200 kb
Host smart-f6284e9c-08e8-40a9-85cc-57ad6fb8dcbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765214027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.765214027
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.729530935
Short name T731
Test name
Test status
Simulation time 258094577 ps
CPU time 7.04 seconds
Started Dec 27 01:02:44 PM PST 23
Finished Dec 27 01:02:57 PM PST 23
Peak memory 250048 kb
Host smart-29d3c542-d875-4f6b-84ca-32eaef503eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729530935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.729530935
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.1514514415
Short name T880
Test name
Test status
Simulation time 4421781051 ps
CPU time 89.67 seconds
Started Dec 27 01:02:49 PM PST 23
Finished Dec 27 01:04:26 PM PST 23
Peak memory 284008 kb
Host smart-4fa9730c-c4b0-4de9-8183-40d749be83c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514514415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.1514514415
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2041954254
Short name T31
Test name
Test status
Simulation time 21442017 ps
CPU time 0.81 seconds
Started Dec 27 01:02:55 PM PST 23
Finished Dec 27 01:03:08 PM PST 23
Peak memory 208312 kb
Host smart-ab002d85-40f9-4348-8c62-08c2cff266b9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041954254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.2041954254
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.2049158025
Short name T386
Test name
Test status
Simulation time 42896469 ps
CPU time 1.01 seconds
Started Dec 27 01:02:42 PM PST 23
Finished Dec 27 01:02:48 PM PST 23
Peak memory 208408 kb
Host smart-ae577d0f-cecb-4848-979e-a326bb945fa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049158025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2049158025
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.1771609828
Short name T315
Test name
Test status
Simulation time 535947333 ps
CPU time 13.86 seconds
Started Dec 27 01:02:49 PM PST 23
Finished Dec 27 01:03:11 PM PST 23
Peak memory 218092 kb
Host smart-b5eddeb0-bc0d-4890-a71c-460d8e730d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771609828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.1771609828
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.3097844967
Short name T573
Test name
Test status
Simulation time 608718503 ps
CPU time 4.58 seconds
Started Dec 27 01:02:53 PM PST 23
Finished Dec 27 01:03:09 PM PST 23
Peak memory 209704 kb
Host smart-4abcf286-8fb1-4239-9c04-955e2ca6b25c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097844967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_a
ccess.3097844967
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.832065944
Short name T811
Test name
Test status
Simulation time 523182684 ps
CPU time 3.66 seconds
Started Dec 27 01:02:54 PM PST 23
Finished Dec 27 01:03:10 PM PST 23
Peak memory 218196 kb
Host smart-68f9ad21-0952-4013-a3a1-a0e2c113e7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832065944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.832065944
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.3879745918
Short name T497
Test name
Test status
Simulation time 1661417873 ps
CPU time 14.27 seconds
Started Dec 27 01:02:49 PM PST 23
Finished Dec 27 01:03:11 PM PST 23
Peak memory 219260 kb
Host smart-9e732bf2-51e9-4e1c-a63b-cae067c66c92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879745918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.3879745918
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.2862137456
Short name T25
Test name
Test status
Simulation time 379092919 ps
CPU time 12.24 seconds
Started Dec 27 01:02:49 PM PST 23
Finished Dec 27 01:03:09 PM PST 23
Peak memory 218160 kb
Host smart-c6457a41-d88b-4f5b-9c48-ffbb066055e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862137456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.2862137456
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2406098860
Short name T826
Test name
Test status
Simulation time 427551991 ps
CPU time 10.57 seconds
Started Dec 27 01:02:51 PM PST 23
Finished Dec 27 01:03:09 PM PST 23
Peak memory 218064 kb
Host smart-6918d83d-5c5e-4aab-ade5-8d70e63a1cd8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406098860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
2406098860
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.1449285748
Short name T427
Test name
Test status
Simulation time 2124293039 ps
CPU time 12.57 seconds
Started Dec 27 01:03:00 PM PST 23
Finished Dec 27 01:03:26 PM PST 23
Peak memory 218176 kb
Host smart-1203882c-bf41-4f56-8650-b2284389147d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449285748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.1449285748
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.272924135
Short name T593
Test name
Test status
Simulation time 32060580 ps
CPU time 1.94 seconds
Started Dec 27 01:02:50 PM PST 23
Finished Dec 27 01:02:59 PM PST 23
Peak memory 213576 kb
Host smart-b241376a-d7f6-4ddc-bc84-fdcdcf98d3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272924135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.272924135
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.3389611978
Short name T607
Test name
Test status
Simulation time 437155024 ps
CPU time 23.69 seconds
Started Dec 27 01:02:51 PM PST 23
Finished Dec 27 01:03:22 PM PST 23
Peak memory 251200 kb
Host smart-293fe535-5744-42da-8e5d-8ca1dd6f402e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389611978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.3389611978
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.1123156747
Short name T382
Test name
Test status
Simulation time 271960502 ps
CPU time 6.05 seconds
Started Dec 27 01:02:50 PM PST 23
Finished Dec 27 01:03:04 PM PST 23
Peak memory 246292 kb
Host smart-0ee56fe8-d16d-4f04-8f0d-27f6088253ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123156747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.1123156747
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.839339815
Short name T473
Test name
Test status
Simulation time 14264925291 ps
CPU time 240.45 seconds
Started Dec 27 01:02:52 PM PST 23
Finished Dec 27 01:07:03 PM PST 23
Peak memory 221300 kb
Host smart-1600482d-b564-481a-84ad-05a5b352918d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839339815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.839339815
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.2826667280
Short name T679
Test name
Test status
Simulation time 22687521 ps
CPU time 0.79 seconds
Started Dec 27 01:02:50 PM PST 23
Finished Dec 27 01:02:58 PM PST 23
Peak memory 207992 kb
Host smart-bee05740-46aa-48f2-944e-55f9d7b85e2c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826667280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.2826667280
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.1947244422
Short name T557
Test name
Test status
Simulation time 42382255 ps
CPU time 0.82 seconds
Started Dec 27 01:03:07 PM PST 23
Finished Dec 27 01:03:19 PM PST 23
Peak memory 209548 kb
Host smart-52a54fdb-d0a7-41bb-a20a-1f7d0b00b434
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947244422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1947244422
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.2218575807
Short name T683
Test name
Test status
Simulation time 1168369665 ps
CPU time 12.53 seconds
Started Dec 27 01:02:48 PM PST 23
Finished Dec 27 01:03:08 PM PST 23
Peak memory 218180 kb
Host smart-0dc82f87-a6a2-42e4-af78-68545967ccd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218575807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2218575807
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.1537989774
Short name T409
Test name
Test status
Simulation time 68923571 ps
CPU time 1.56 seconds
Started Dec 27 01:02:56 PM PST 23
Finished Dec 27 01:03:09 PM PST 23
Peak memory 209676 kb
Host smart-ee3ab84a-8e7b-4ee4-be07-0ee72a5918e1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537989774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_a
ccess.1537989774
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.2253084589
Short name T605
Test name
Test status
Simulation time 50474808 ps
CPU time 2.9 seconds
Started Dec 27 01:02:59 PM PST 23
Finished Dec 27 01:03:16 PM PST 23
Peak memory 218192 kb
Host smart-4c955f5b-5898-4c3f-a054-18322fc735f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253084589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.2253084589
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.3154000434
Short name T324
Test name
Test status
Simulation time 1029866361 ps
CPU time 9.52 seconds
Started Dec 27 01:03:00 PM PST 23
Finished Dec 27 01:03:24 PM PST 23
Peak memory 218104 kb
Host smart-ceffb4e0-5d03-417e-8456-410964be43ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154000434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.3154000434
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.3833460628
Short name T434
Test name
Test status
Simulation time 803228632 ps
CPU time 7.25 seconds
Started Dec 27 01:02:54 PM PST 23
Finished Dec 27 01:03:14 PM PST 23
Peak memory 218248 kb
Host smart-1d1e0c07-6e61-4bee-b070-ea36ad78d4e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833460628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.3833460628
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.3246109799
Short name T747
Test name
Test status
Simulation time 270128872 ps
CPU time 11.01 seconds
Started Dec 27 01:02:57 PM PST 23
Finished Dec 27 01:03:20 PM PST 23
Peak memory 218080 kb
Host smart-5b281806-c82c-4199-bd2b-e80e2b55cdde
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246109799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
3246109799
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.1578652182
Short name T932
Test name
Test status
Simulation time 777117906 ps
CPU time 14.54 seconds
Started Dec 27 01:02:48 PM PST 23
Finished Dec 27 01:03:10 PM PST 23
Peak memory 218228 kb
Host smart-0be6d735-48da-4ffd-b995-1f36e3e95cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578652182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1578652182
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.3299953468
Short name T329
Test name
Test status
Simulation time 583071842 ps
CPU time 3.57 seconds
Started Dec 27 01:02:49 PM PST 23
Finished Dec 27 01:03:00 PM PST 23
Peak memory 213880 kb
Host smart-1e48470f-7aa9-4082-ab74-a3312f284253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299953468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.3299953468
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.1967425534
Short name T771
Test name
Test status
Simulation time 1075073064 ps
CPU time 26.35 seconds
Started Dec 27 01:03:00 PM PST 23
Finished Dec 27 01:03:40 PM PST 23
Peak memory 250932 kb
Host smart-d3bf66ce-4ceb-44be-8f2a-a24a799fef8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967425534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.1967425534
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.1241726344
Short name T353
Test name
Test status
Simulation time 89890487 ps
CPU time 8.73 seconds
Started Dec 27 01:02:57 PM PST 23
Finished Dec 27 01:03:19 PM PST 23
Peak memory 251232 kb
Host smart-308c7904-9312-43b4-b756-1f7432abe467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241726344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.1241726344
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.2554125424
Short name T583
Test name
Test status
Simulation time 8568387162 ps
CPU time 187.97 seconds
Started Dec 27 01:02:57 PM PST 23
Finished Dec 27 01:06:18 PM PST 23
Peak memory 276752 kb
Host smart-49de71d7-390c-4593-8a71-5cd3b2644b9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554125424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.2554125424
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1947388684
Short name T392
Test name
Test status
Simulation time 11748906 ps
CPU time 0.93 seconds
Started Dec 27 01:02:53 PM PST 23
Finished Dec 27 01:03:06 PM PST 23
Peak memory 208380 kb
Host smart-383e42d2-8277-40e9-9db7-dc766c7ac53d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947388684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.1947388684
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.84656574
Short name T515
Test name
Test status
Simulation time 29093243 ps
CPU time 1.1 seconds
Started Dec 27 01:02:58 PM PST 23
Finished Dec 27 01:03:13 PM PST 23
Peak memory 209780 kb
Host smart-b3f51793-ae15-437f-9097-4ed20b9f25b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84656574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.84656574
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.1013260586
Short name T924
Test name
Test status
Simulation time 1027297700 ps
CPU time 12.53 seconds
Started Dec 27 01:02:48 PM PST 23
Finished Dec 27 01:03:08 PM PST 23
Peak memory 218140 kb
Host smart-ef115703-693a-4bd8-a135-4f062d48e93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013260586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.1013260586
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.375505764
Short name T797
Test name
Test status
Simulation time 1722620740 ps
CPU time 7.13 seconds
Started Dec 27 01:02:58 PM PST 23
Finished Dec 27 01:03:19 PM PST 23
Peak memory 209648 kb
Host smart-95dca799-81fe-4bb1-99ae-9d6d7f63c426
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375505764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_ac
cess.375505764
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.2771465856
Short name T651
Test name
Test status
Simulation time 446258848 ps
CPU time 4.86 seconds
Started Dec 27 01:02:54 PM PST 23
Finished Dec 27 01:03:10 PM PST 23
Peak memory 218188 kb
Host smart-35662f8d-59a8-43eb-b436-0a7652c8e2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771465856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2771465856
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.159460363
Short name T58
Test name
Test status
Simulation time 505149199 ps
CPU time 10.44 seconds
Started Dec 27 01:02:54 PM PST 23
Finished Dec 27 01:03:16 PM PST 23
Peak memory 218196 kb
Host smart-ad37663e-3bcd-499e-8d1c-6c76cee7e4f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159460363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.159460363
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.2765510717
Short name T656
Test name
Test status
Simulation time 1330079138 ps
CPU time 11.41 seconds
Started Dec 27 01:03:02 PM PST 23
Finished Dec 27 01:03:26 PM PST 23
Peak memory 218104 kb
Host smart-70910726-d7a5-4bf8-9c36-7cbf57ba7e61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765510717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.2765510717
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.282994899
Short name T942
Test name
Test status
Simulation time 533985713 ps
CPU time 11.81 seconds
Started Dec 27 01:02:48 PM PST 23
Finished Dec 27 01:03:07 PM PST 23
Peak memory 218048 kb
Host smart-9619c3a0-15db-456d-851a-8c1c6b33cf0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282994899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.282994899
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.2683055264
Short name T471
Test name
Test status
Simulation time 1406917308 ps
CPU time 13.33 seconds
Started Dec 27 01:02:56 PM PST 23
Finished Dec 27 01:03:22 PM PST 23
Peak memory 218200 kb
Host smart-fb967315-12ba-4639-b856-9e1a7690fc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683055264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.2683055264
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.4276078628
Short name T77
Test name
Test status
Simulation time 474961328 ps
CPU time 1.84 seconds
Started Dec 27 01:02:58 PM PST 23
Finished Dec 27 01:03:13 PM PST 23
Peak memory 213364 kb
Host smart-4d1bfd6c-cd14-4bc4-bfc4-70d6898c92e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276078628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.4276078628
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.4245516882
Short name T476
Test name
Test status
Simulation time 555782825 ps
CPU time 28.98 seconds
Started Dec 27 01:02:53 PM PST 23
Finished Dec 27 01:03:34 PM PST 23
Peak memory 251080 kb
Host smart-50831489-8902-4c7f-b340-5d2fe294ce6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245516882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.4245516882
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.3771757394
Short name T857
Test name
Test status
Simulation time 260621193 ps
CPU time 8.08 seconds
Started Dec 27 01:03:01 PM PST 23
Finished Dec 27 01:03:22 PM PST 23
Peak memory 251188 kb
Host smart-379c158a-c71e-47e9-b3b2-1e91c531f0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771757394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.3771757394
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.976894172
Short name T502
Test name
Test status
Simulation time 48451769373 ps
CPU time 380.53 seconds
Started Dec 27 01:02:58 PM PST 23
Finished Dec 27 01:09:32 PM PST 23
Peak memory 267616 kb
Host smart-3ae39119-3b4a-43ff-ab02-a531294650a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976894172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.976894172
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1574807668
Short name T975
Test name
Test status
Simulation time 32725991 ps
CPU time 0.8 seconds
Started Dec 27 01:02:55 PM PST 23
Finished Dec 27 01:03:08 PM PST 23
Peak memory 208208 kb
Host smart-7618f51a-4945-423a-9c13-959db835571c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574807668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.1574807668
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.4248429031
Short name T102
Test name
Test status
Simulation time 68906234 ps
CPU time 0.84 seconds
Started Dec 27 01:02:56 PM PST 23
Finished Dec 27 01:03:10 PM PST 23
Peak memory 209688 kb
Host smart-8288f97e-42cc-4e85-9603-dd6f24bc0239
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248429031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.4248429031
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.691648577
Short name T609
Test name
Test status
Simulation time 1592781123 ps
CPU time 11.4 seconds
Started Dec 27 01:02:52 PM PST 23
Finished Dec 27 01:03:15 PM PST 23
Peak memory 218228 kb
Host smart-ba880562-378d-4d69-a3db-c135fb5a8318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691648577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.691648577
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.24248183
Short name T19
Test name
Test status
Simulation time 395759732 ps
CPU time 10.11 seconds
Started Dec 27 01:03:02 PM PST 23
Finished Dec 27 01:03:25 PM PST 23
Peak memory 209668 kb
Host smart-234951f1-f177-438a-8a44-3313e92b6e86
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24248183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jta
g_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_acc
ess.24248183
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.3599489203
Short name T569
Test name
Test status
Simulation time 56724920 ps
CPU time 3.2 seconds
Started Dec 27 01:02:50 PM PST 23
Finished Dec 27 01:03:01 PM PST 23
Peak memory 218184 kb
Host smart-905c17c1-172f-4e47-85c8-ff57017258d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599489203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.3599489203
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.1693148556
Short name T744
Test name
Test status
Simulation time 2821821731 ps
CPU time 13.63 seconds
Started Dec 27 01:03:00 PM PST 23
Finished Dec 27 01:03:28 PM PST 23
Peak memory 219636 kb
Host smart-aa90b6e0-2054-498e-8c95-1b1b80d06c95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693148556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.1693148556
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.3631464896
Short name T823
Test name
Test status
Simulation time 1053451169 ps
CPU time 19.87 seconds
Started Dec 27 01:02:49 PM PST 23
Finished Dec 27 01:03:16 PM PST 23
Peak memory 218164 kb
Host smart-6f70a432-1cf0-425f-9c57-33be52766924
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631464896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.3631464896
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.4229948284
Short name T842
Test name
Test status
Simulation time 216289313 ps
CPU time 8.76 seconds
Started Dec 27 01:02:57 PM PST 23
Finished Dec 27 01:03:18 PM PST 23
Peak memory 218136 kb
Host smart-6a3c1499-a643-4480-9254-ebadf8bfaed1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229948284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
4229948284
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.1299436058
Short name T83
Test name
Test status
Simulation time 346856496 ps
CPU time 13.17 seconds
Started Dec 27 01:02:47 PM PST 23
Finished Dec 27 01:03:07 PM PST 23
Peak memory 218188 kb
Host smart-4633d000-ebfc-4567-9bd8-555c8127f9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299436058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1299436058
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.3042844019
Short name T40
Test name
Test status
Simulation time 198115000 ps
CPU time 4.39 seconds
Started Dec 27 01:02:56 PM PST 23
Finished Dec 27 01:03:12 PM PST 23
Peak memory 214332 kb
Host smart-e1672ce5-dd0c-4595-8c3f-67c5fa82aaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042844019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.3042844019
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.827756891
Short name T519
Test name
Test status
Simulation time 1355886069 ps
CPU time 34.41 seconds
Started Dec 27 01:03:00 PM PST 23
Finished Dec 27 01:03:49 PM PST 23
Peak memory 251008 kb
Host smart-f2d8d08a-974a-41c3-99e8-76903f7d22ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827756891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.827756891
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.3026799744
Short name T665
Test name
Test status
Simulation time 128482899 ps
CPU time 7.01 seconds
Started Dec 27 01:02:48 PM PST 23
Finished Dec 27 01:03:02 PM PST 23
Peak memory 250628 kb
Host smart-6423ff16-32cf-4db2-af5d-2436d977b359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026799744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.3026799744
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.3079194386
Short name T84
Test name
Test status
Simulation time 6845888140 ps
CPU time 32.14 seconds
Started Dec 27 01:02:57 PM PST 23
Finished Dec 27 01:03:41 PM PST 23
Peak memory 226452 kb
Host smart-e19dcbb0-7e73-42d2-9a79-80ebc5221851
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079194386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.3079194386
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.1890261838
Short name T541
Test name
Test status
Simulation time 11964095 ps
CPU time 0.93 seconds
Started Dec 27 01:02:58 PM PST 23
Finished Dec 27 01:03:12 PM PST 23
Peak memory 208168 kb
Host smart-cc18bbba-6e2a-44fe-996a-6613891820c2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890261838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.1890261838
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.719675169
Short name T337
Test name
Test status
Simulation time 29563898 ps
CPU time 1.05 seconds
Started Dec 27 01:03:01 PM PST 23
Finished Dec 27 01:03:16 PM PST 23
Peak memory 209856 kb
Host smart-69af223b-642d-47bf-b9b4-8ad24ad0a511
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719675169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.719675169
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.3908694074
Short name T742
Test name
Test status
Simulation time 637403823 ps
CPU time 11.93 seconds
Started Dec 27 01:03:01 PM PST 23
Finished Dec 27 01:03:26 PM PST 23
Peak memory 218164 kb
Host smart-27f1bde6-ecfc-4874-bb92-861281449a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908694074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.3908694074
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.675724562
Short name T359
Test name
Test status
Simulation time 3003958205 ps
CPU time 6.52 seconds
Started Dec 27 01:03:03 PM PST 23
Finished Dec 27 01:03:21 PM PST 23
Peak memory 209768 kb
Host smart-6ed5180c-0593-4296-8d18-77241ed876f3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675724562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_ac
cess.675724562
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.2776311363
Short name T916
Test name
Test status
Simulation time 112877173 ps
CPU time 3.01 seconds
Started Dec 27 01:02:57 PM PST 23
Finished Dec 27 01:03:12 PM PST 23
Peak memory 218084 kb
Host smart-55ce7035-d65c-466a-93db-e581470b4214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776311363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2776311363
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.4132613499
Short name T957
Test name
Test status
Simulation time 204254221 ps
CPU time 11.62 seconds
Started Dec 27 01:02:58 PM PST 23
Finished Dec 27 01:03:23 PM PST 23
Peak memory 218228 kb
Host smart-6d763f0e-903a-48aa-9106-e3bc3b260c20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132613499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.4132613499
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.2059718997
Short name T325
Test name
Test status
Simulation time 1523909955 ps
CPU time 14.71 seconds
Started Dec 27 01:02:59 PM PST 23
Finished Dec 27 01:03:28 PM PST 23
Peak memory 218104 kb
Host smart-58e9c4fd-e45a-4e07-ab28-047a4ff164af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059718997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.2059718997
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.563473558
Short name T36
Test name
Test status
Simulation time 972403920 ps
CPU time 7.25 seconds
Started Dec 27 01:03:07 PM PST 23
Finished Dec 27 01:03:26 PM PST 23
Peak memory 218048 kb
Host smart-176dada0-5cfd-4fb1-9df1-5e1467e86b5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563473558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.563473558
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.562992160
Short name T720
Test name
Test status
Simulation time 344792276 ps
CPU time 10.94 seconds
Started Dec 27 01:02:52 PM PST 23
Finished Dec 27 01:03:14 PM PST 23
Peak memory 218216 kb
Host smart-558a869e-4a39-4ee0-bea5-aac640096e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562992160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.562992160
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2033221161
Short name T517
Test name
Test status
Simulation time 1008019921 ps
CPU time 2.64 seconds
Started Dec 27 01:02:57 PM PST 23
Finished Dec 27 01:03:12 PM PST 23
Peak memory 214088 kb
Host smart-4568b17a-5422-4d20-a98f-0b15187de61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033221161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2033221161
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.3438171606
Short name T865
Test name
Test status
Simulation time 1027004614 ps
CPU time 29.41 seconds
Started Dec 27 01:02:52 PM PST 23
Finished Dec 27 01:03:34 PM PST 23
Peak memory 251212 kb
Host smart-aabb06f2-a937-4998-88ff-fe1067d651a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438171606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3438171606
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.3864300359
Short name T420
Test name
Test status
Simulation time 49754156 ps
CPU time 6.3 seconds
Started Dec 27 01:02:55 PM PST 23
Finished Dec 27 01:03:14 PM PST 23
Peak memory 248060 kb
Host smart-3a701de1-3671-433d-a233-22bcce1b1a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864300359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.3864300359
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.705500211
Short name T677
Test name
Test status
Simulation time 14282877590 ps
CPU time 151.1 seconds
Started Dec 27 01:02:57 PM PST 23
Finished Dec 27 01:05:41 PM PST 23
Peak memory 284004 kb
Host smart-cec0ff88-64a0-4667-8edb-406cc40fecc9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705500211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.705500211
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.1525742140
Short name T306
Test name
Test status
Simulation time 31102561 ps
CPU time 0.73 seconds
Started Dec 27 01:02:49 PM PST 23
Finished Dec 27 01:02:57 PM PST 23
Peak memory 207972 kb
Host smart-1c856269-01e5-4b93-ad68-46ab52f10ee1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525742140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.1525742140
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.3969533049
Short name T688
Test name
Test status
Simulation time 37679202 ps
CPU time 0.97 seconds
Started Dec 27 01:03:03 PM PST 23
Finished Dec 27 01:03:16 PM PST 23
Peak memory 209720 kb
Host smart-0dd051cf-1637-4fbd-a37d-563e4315b43d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969533049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.3969533049
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.4015859280
Short name T49
Test name
Test status
Simulation time 2918942525 ps
CPU time 13.67 seconds
Started Dec 27 01:02:54 PM PST 23
Finished Dec 27 01:03:19 PM PST 23
Peak memory 218300 kb
Host smart-323b0391-5c0e-42dc-b4dd-9a9b74b4e419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015859280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.4015859280
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.2457356173
Short name T850
Test name
Test status
Simulation time 51534914 ps
CPU time 1.49 seconds
Started Dec 27 01:02:54 PM PST 23
Finished Dec 27 01:03:08 PM PST 23
Peak memory 209684 kb
Host smart-81263553-41d6-44b5-ae84-e9a24925ed34
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457356173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_a
ccess.2457356173
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.2908116481
Short name T466
Test name
Test status
Simulation time 141257316 ps
CPU time 2.43 seconds
Started Dec 27 01:03:03 PM PST 23
Finished Dec 27 01:03:17 PM PST 23
Peak memory 218192 kb
Host smart-8791afd7-2472-4174-8260-f79788948308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908116481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.2908116481
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.3479134841
Short name T868
Test name
Test status
Simulation time 352626287 ps
CPU time 12.91 seconds
Started Dec 27 01:03:01 PM PST 23
Finished Dec 27 01:03:28 PM PST 23
Peak memory 218220 kb
Host smart-561a57e7-82cd-480a-9445-5442590b1f01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479134841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.3479134841
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.2680119229
Short name T537
Test name
Test status
Simulation time 320787029 ps
CPU time 14.78 seconds
Started Dec 27 01:02:59 PM PST 23
Finished Dec 27 01:03:28 PM PST 23
Peak memory 218140 kb
Host smart-5f0762bf-88d0-4c2c-93d8-d0d334a6c8f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680119229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.2680119229
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.3183961035
Short name T525
Test name
Test status
Simulation time 574409121 ps
CPU time 19.01 seconds
Started Dec 27 01:03:00 PM PST 23
Finished Dec 27 01:03:34 PM PST 23
Peak memory 218176 kb
Host smart-f38dc483-4a6b-49ca-b423-e3eb09a4f01a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183961035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
3183961035
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.1881991181
Short name T407
Test name
Test status
Simulation time 753685317 ps
CPU time 14.1 seconds
Started Dec 27 01:02:56 PM PST 23
Finished Dec 27 01:03:22 PM PST 23
Peak memory 218224 kb
Host smart-cf7896d2-d3d8-4561-a02a-e33e7c26d3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881991181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.1881991181
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.778309895
Short name T74
Test name
Test status
Simulation time 16261229 ps
CPU time 1.21 seconds
Started Dec 27 01:03:00 PM PST 23
Finished Dec 27 01:03:15 PM PST 23
Peak memory 212976 kb
Host smart-23de7a26-ccd6-4425-984d-01616f639286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778309895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.778309895
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.3909005130
Short name T740
Test name
Test status
Simulation time 232450387 ps
CPU time 23.83 seconds
Started Dec 27 01:03:01 PM PST 23
Finished Dec 27 01:03:38 PM PST 23
Peak memory 251188 kb
Host smart-e7ff98ba-f986-470a-95c2-c795f84be816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909005130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3909005130
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.138518176
Short name T189
Test name
Test status
Simulation time 328498748 ps
CPU time 6.48 seconds
Started Dec 27 01:02:55 PM PST 23
Finished Dec 27 01:03:14 PM PST 23
Peak memory 251012 kb
Host smart-a2c0532d-f5c9-400f-ae32-71d6198f3a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138518176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.138518176
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.1754133917
Short name T563
Test name
Test status
Simulation time 9836785598 ps
CPU time 46.08 seconds
Started Dec 27 01:02:59 PM PST 23
Finished Dec 27 01:03:59 PM PST 23
Peak memory 251180 kb
Host smart-0dbdbfed-5c55-424b-b201-1737219fb117
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754133917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.1754133917
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.982912187
Short name T819
Test name
Test status
Simulation time 63736376 ps
CPU time 0.9 seconds
Started Dec 27 01:03:07 PM PST 23
Finished Dec 27 01:03:20 PM PST 23
Peak memory 208312 kb
Host smart-f541f724-f466-4c17-a2dd-8496701f5fa4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982912187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ct
rl_volatile_unlock_smoke.982912187
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.3223873735
Short name T969
Test name
Test status
Simulation time 41190945 ps
CPU time 0.87 seconds
Started Dec 27 01:03:01 PM PST 23
Finished Dec 27 01:03:15 PM PST 23
Peak memory 208424 kb
Host smart-13e84e8a-ee29-4ff5-bb31-8f4d8605f3ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223873735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.3223873735
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.541199245
Short name T872
Test name
Test status
Simulation time 1752910102 ps
CPU time 13.46 seconds
Started Dec 27 01:02:59 PM PST 23
Finished Dec 27 01:03:26 PM PST 23
Peak memory 218220 kb
Host smart-c4e74f6b-8615-41e5-afa7-9fae84b58f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541199245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.541199245
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.663729089
Short name T804
Test name
Test status
Simulation time 269512265 ps
CPU time 7.31 seconds
Started Dec 27 01:03:03 PM PST 23
Finished Dec 27 01:03:22 PM PST 23
Peak memory 209628 kb
Host smart-af3c72c1-4788-4d7b-a7dd-cc94318d2c9e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663729089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_ac
cess.663729089
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.1269192132
Short name T412
Test name
Test status
Simulation time 49369853 ps
CPU time 3.02 seconds
Started Dec 27 01:03:07 PM PST 23
Finished Dec 27 01:03:22 PM PST 23
Peak memory 218136 kb
Host smart-5070f3c4-5c27-418a-8dfc-7f8429dd63b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269192132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.1269192132
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.2061263618
Short name T612
Test name
Test status
Simulation time 1400963493 ps
CPU time 11.34 seconds
Started Dec 27 01:03:09 PM PST 23
Finished Dec 27 01:03:31 PM PST 23
Peak memory 218216 kb
Host smart-d19abbfb-8cef-4655-8d79-29a9dcfb5208
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061263618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.2061263618
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1817206383
Short name T907
Test name
Test status
Simulation time 187392151 ps
CPU time 6.9 seconds
Started Dec 27 01:03:06 PM PST 23
Finished Dec 27 01:03:25 PM PST 23
Peak memory 218128 kb
Host smart-1a678f74-e343-43bf-a455-b959e03cc123
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817206383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1817206383
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.580180005
Short name T964
Test name
Test status
Simulation time 1192939672 ps
CPU time 7.11 seconds
Started Dec 27 01:03:04 PM PST 23
Finished Dec 27 01:03:23 PM PST 23
Peak memory 218164 kb
Host smart-c842eb3a-5003-4fde-9c3c-56efc4819bb9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580180005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.580180005
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.3625088002
Short name T624
Test name
Test status
Simulation time 451161582 ps
CPU time 7.61 seconds
Started Dec 27 01:03:10 PM PST 23
Finished Dec 27 01:03:27 PM PST 23
Peak memory 218108 kb
Host smart-79f5e570-6ef6-4c54-b157-a2ee1cbd4fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625088002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3625088002
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.3041118017
Short name T877
Test name
Test status
Simulation time 69150796 ps
CPU time 2.3 seconds
Started Dec 27 01:03:04 PM PST 23
Finished Dec 27 01:03:19 PM PST 23
Peak memory 213752 kb
Host smart-9e478749-c244-4ddd-92b5-d2e1064931e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041118017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.3041118017
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.3883965908
Short name T387
Test name
Test status
Simulation time 1694424551 ps
CPU time 24.88 seconds
Started Dec 27 01:03:00 PM PST 23
Finished Dec 27 01:03:39 PM PST 23
Peak memory 251056 kb
Host smart-62afbb24-a559-4ae4-83f8-a234bdf645a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883965908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.3883965908
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.3827260234
Short name T966
Test name
Test status
Simulation time 215245705 ps
CPU time 7.46 seconds
Started Dec 27 01:03:11 PM PST 23
Finished Dec 27 01:03:27 PM PST 23
Peak memory 251184 kb
Host smart-202fb492-c204-4d7b-b931-eba4a6ce67a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827260234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.3827260234
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1413291981
Short name T41
Test name
Test status
Simulation time 13515080 ps
CPU time 0.93 seconds
Started Dec 27 01:03:05 PM PST 23
Finished Dec 27 01:03:18 PM PST 23
Peak memory 211484 kb
Host smart-32366fcc-1075-4e88-8297-176d870e7000
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413291981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.1413291981
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.348224282
Short name T415
Test name
Test status
Simulation time 105789239 ps
CPU time 0.92 seconds
Started Dec 27 01:01:17 PM PST 23
Finished Dec 27 01:01:23 PM PST 23
Peak memory 209700 kb
Host smart-009b0ef6-2853-4604-bebc-2574088b9886
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348224282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.348224282
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.136711303
Short name T38
Test name
Test status
Simulation time 935900039 ps
CPU time 11.77 seconds
Started Dec 27 01:01:15 PM PST 23
Finished Dec 27 01:01:31 PM PST 23
Peak memory 218188 kb
Host smart-3a0af80a-8521-4c78-91c4-870b8dd80cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136711303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.136711303
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.1198324323
Short name T380
Test name
Test status
Simulation time 872542235 ps
CPU time 6.81 seconds
Started Dec 27 01:01:18 PM PST 23
Finished Dec 27 01:01:29 PM PST 23
Peak memory 209584 kb
Host smart-eef5459b-d501-4ef8-a4fe-7342a5db40a8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198324323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_ac
cess.1198324323
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.768705664
Short name T664
Test name
Test status
Simulation time 1853119942 ps
CPU time 30.23 seconds
Started Dec 27 01:01:10 PM PST 23
Finished Dec 27 01:01:44 PM PST 23
Peak memory 218048 kb
Host smart-dd5dc8fb-9d72-4840-a9df-318fee57a8d1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768705664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_err
ors.768705664
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.148628555
Short name T59
Test name
Test status
Simulation time 4605776351 ps
CPU time 12.3 seconds
Started Dec 27 01:01:15 PM PST 23
Finished Dec 27 01:01:32 PM PST 23
Peak memory 217992 kb
Host smart-f6972737-3a4d-4b18-97d5-cfbce5b128c5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148628555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_p
riority.148628555
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.775415427
Short name T504
Test name
Test status
Simulation time 982755913 ps
CPU time 13.48 seconds
Started Dec 27 01:01:16 PM PST 23
Finished Dec 27 01:01:33 PM PST 23
Peak memory 218044 kb
Host smart-1fbcb174-bab8-42f9-b2bf-faec6ceef830
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775415427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_
prog_failure.775415427
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.467478295
Short name T454
Test name
Test status
Simulation time 4645368732 ps
CPU time 34.1 seconds
Started Dec 27 01:01:16 PM PST 23
Finished Dec 27 01:01:55 PM PST 23
Peak memory 213920 kb
Host smart-75dcc5f1-5a90-439f-909b-ce1cc1b8a507
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467478295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_regwen_during_op.467478295
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1433711040
Short name T67
Test name
Test status
Simulation time 583231233 ps
CPU time 5.43 seconds
Started Dec 27 01:01:16 PM PST 23
Finished Dec 27 01:01:27 PM PST 23
Peak memory 213044 kb
Host smart-871f3b7d-7c8b-4431-b56c-94bbbc10e580
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433711040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
1433711040
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.4062911439
Short name T621
Test name
Test status
Simulation time 1563102016 ps
CPU time 36.23 seconds
Started Dec 27 01:01:16 PM PST 23
Finished Dec 27 01:01:57 PM PST 23
Peak memory 276136 kb
Host smart-673e5f35-44b6-4a58-bacf-250469595102
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062911439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.4062911439
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.1856721613
Short name T652
Test name
Test status
Simulation time 1577592410 ps
CPU time 12.69 seconds
Started Dec 27 01:01:15 PM PST 23
Finished Dec 27 01:01:32 PM PST 23
Peak memory 251128 kb
Host smart-79175c0c-d148-4815-b103-06d2b0e9931e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856721613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.1856721613
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.654435222
Short name T935
Test name
Test status
Simulation time 166232460 ps
CPU time 2.37 seconds
Started Dec 27 01:01:17 PM PST 23
Finished Dec 27 01:01:25 PM PST 23
Peak memory 217380 kb
Host smart-b1ba03ce-f768-4b9c-9755-6b49128ceb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654435222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.654435222
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.2505173168
Short name T847
Test name
Test status
Simulation time 368611730 ps
CPU time 8.83 seconds
Started Dec 27 01:01:11 PM PST 23
Finished Dec 27 01:01:24 PM PST 23
Peak memory 214172 kb
Host smart-91ee75d2-24d4-404c-a6d7-67f61abc9e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505173168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.2505173168
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.3365701325
Short name T913
Test name
Test status
Simulation time 453713716 ps
CPU time 15.54 seconds
Started Dec 27 01:01:14 PM PST 23
Finished Dec 27 01:01:34 PM PST 23
Peak memory 219204 kb
Host smart-3db0de35-85a5-48db-81cf-78a1f07f670f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365701325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.3365701325
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.207979693
Short name T506
Test name
Test status
Simulation time 2269201249 ps
CPU time 10.41 seconds
Started Dec 27 01:01:21 PM PST 23
Finished Dec 27 01:01:38 PM PST 23
Peak memory 218204 kb
Host smart-38fca128-495d-4f21-8158-281b89e6f268
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207979693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_dig
est.207979693
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.2901258804
Short name T798
Test name
Test status
Simulation time 312902817 ps
CPU time 10.56 seconds
Started Dec 27 01:01:17 PM PST 23
Finished Dec 27 01:01:33 PM PST 23
Peak memory 218048 kb
Host smart-58a8f17d-2c46-4539-bff7-880f90f737e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901258804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.2
901258804
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.1714035755
Short name T810
Test name
Test status
Simulation time 337474164 ps
CPU time 12.28 seconds
Started Dec 27 01:01:08 PM PST 23
Finished Dec 27 01:01:24 PM PST 23
Peak memory 218220 kb
Host smart-69afb6c6-90d6-44ba-b545-77e1921b33f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714035755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1714035755
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.1646654171
Short name T597
Test name
Test status
Simulation time 31002517 ps
CPU time 2.55 seconds
Started Dec 27 01:01:11 PM PST 23
Finished Dec 27 01:01:18 PM PST 23
Peak memory 213996 kb
Host smart-405d3e7e-4b5e-4dd0-b5de-a8741d25f506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646654171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.1646654171
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.609965886
Short name T62
Test name
Test status
Simulation time 373226709 ps
CPU time 31.81 seconds
Started Dec 27 01:01:08 PM PST 23
Finished Dec 27 01:01:44 PM PST 23
Peak memory 251124 kb
Host smart-9b0180a8-f384-4417-b65d-ea5085d86cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609965886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.609965886
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.1578728076
Short name T834
Test name
Test status
Simulation time 1269425387 ps
CPU time 11.39 seconds
Started Dec 27 01:01:10 PM PST 23
Finished Dec 27 01:01:25 PM PST 23
Peak memory 251100 kb
Host smart-734d8e12-4166-4443-ae9c-b13db1cd32d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578728076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.1578728076
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.1671171747
Short name T801
Test name
Test status
Simulation time 11455722591 ps
CPU time 73.08 seconds
Started Dec 27 01:01:16 PM PST 23
Finished Dec 27 01:02:33 PM PST 23
Peak memory 267608 kb
Host smart-59b71a6e-1772-4a94-b00a-1a4f844633ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671171747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.1671171747
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.246435074
Short name T703
Test name
Test status
Simulation time 13814190 ps
CPU time 0.9 seconds
Started Dec 27 01:01:09 PM PST 23
Finished Dec 27 01:01:14 PM PST 23
Peak memory 212360 kb
Host smart-4be47b90-8682-4edb-bb66-632ae6d90a45
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246435074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctr
l_volatile_unlock_smoke.246435074
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.2578367606
Short name T103
Test name
Test status
Simulation time 60945241 ps
CPU time 1.06 seconds
Started Dec 27 01:01:11 PM PST 23
Finished Dec 27 01:01:15 PM PST 23
Peak memory 208496 kb
Host smart-d05c26b9-11d9-4692-a6c5-dede60242618
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578367606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.2578367606
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.749243796
Short name T634
Test name
Test status
Simulation time 28303815 ps
CPU time 0.79 seconds
Started Dec 27 01:01:15 PM PST 23
Finished Dec 27 01:01:20 PM PST 23
Peak memory 209416 kb
Host smart-1d987001-606e-4605-aa82-de6f702deccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749243796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.749243796
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.935332209
Short name T659
Test name
Test status
Simulation time 1142078696 ps
CPU time 17 seconds
Started Dec 27 01:01:21 PM PST 23
Finished Dec 27 01:01:44 PM PST 23
Peak memory 218172 kb
Host smart-47aeac8c-aa60-44db-a603-60d37de58787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935332209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.935332209
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.3916725094
Short name T390
Test name
Test status
Simulation time 545485922 ps
CPU time 3.27 seconds
Started Dec 27 01:01:21 PM PST 23
Finished Dec 27 01:01:31 PM PST 23
Peak memory 209720 kb
Host smart-f0b07e74-6cf9-4793-94d5-f5b957b4ec7a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916725094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_ac
cess.3916725094
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.4276633115
Short name T954
Test name
Test status
Simulation time 8532151953 ps
CPU time 107.35 seconds
Started Dec 27 01:01:11 PM PST 23
Finished Dec 27 01:03:02 PM PST 23
Peak memory 218648 kb
Host smart-18c48c2d-fcf8-425a-8d11-de7c7fba6e47
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276633115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.4276633115
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.433911820
Short name T881
Test name
Test status
Simulation time 266674526 ps
CPU time 3.9 seconds
Started Dec 27 01:01:20 PM PST 23
Finished Dec 27 01:01:31 PM PST 23
Peak memory 209720 kb
Host smart-eaeafc2d-889a-4ef4-99b4-8b80c38a732b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433911820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_p
riority.433911820
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.3940212541
Short name T555
Test name
Test status
Simulation time 175197001 ps
CPU time 4.08 seconds
Started Dec 27 01:01:17 PM PST 23
Finished Dec 27 01:01:26 PM PST 23
Peak memory 218132 kb
Host smart-0ed79e49-a1ff-4580-89e4-adcef2dcc0ba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940212541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.3940212541
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1058937565
Short name T579
Test name
Test status
Simulation time 1016706693 ps
CPU time 14.67 seconds
Started Dec 27 01:01:21 PM PST 23
Finished Dec 27 01:01:42 PM PST 23
Peak memory 213032 kb
Host smart-2a025c15-f688-4e7d-ab76-11317f5fbb0b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058937565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.1058937565
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.331111413
Short name T743
Test name
Test status
Simulation time 4039077137 ps
CPU time 5.12 seconds
Started Dec 27 01:01:16 PM PST 23
Finished Dec 27 01:01:26 PM PST 23
Peak memory 214196 kb
Host smart-137493f4-f7ef-49e1-b4ec-4f452e7d2f13
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331111413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.331111413
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.2359274369
Short name T124
Test name
Test status
Simulation time 2281142662 ps
CPU time 43.37 seconds
Started Dec 27 01:01:17 PM PST 23
Finished Dec 27 01:02:05 PM PST 23
Peak memory 276944 kb
Host smart-9daa86e4-302f-4688-aa76-c25e399309ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359274369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.2359274369
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.984118519
Short name T192
Test name
Test status
Simulation time 1008123846 ps
CPU time 17.82 seconds
Started Dec 27 01:01:21 PM PST 23
Finished Dec 27 01:01:45 PM PST 23
Peak memory 222696 kb
Host smart-d8889631-222c-4835-8bda-7b64fa6524af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984118519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_state_post_trans.984118519
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.3486931758
Short name T915
Test name
Test status
Simulation time 467568501 ps
CPU time 3.16 seconds
Started Dec 27 01:01:23 PM PST 23
Finished Dec 27 01:01:34 PM PST 23
Peak memory 218372 kb
Host smart-306c9fe8-daaf-4212-afde-d12b316e245d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486931758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.3486931758
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.707060548
Short name T619
Test name
Test status
Simulation time 981824292 ps
CPU time 15.78 seconds
Started Dec 27 01:01:11 PM PST 23
Finished Dec 27 01:01:30 PM PST 23
Peak memory 214244 kb
Host smart-82c0005d-35c9-45d7-b426-1225c6a23d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707060548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.707060548
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.823191061
Short name T358
Test name
Test status
Simulation time 2611951711 ps
CPU time 13.96 seconds
Started Dec 27 01:01:22 PM PST 23
Finished Dec 27 01:01:42 PM PST 23
Peak memory 219768 kb
Host smart-7bed6224-c70f-46f6-a637-3cff182c2ca6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823191061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.823191061
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.63103711
Short name T370
Test name
Test status
Simulation time 20455114679 ps
CPU time 20.83 seconds
Started Dec 27 01:01:16 PM PST 23
Finished Dec 27 01:01:42 PM PST 23
Peak memory 218216 kb
Host smart-ccecaa38-257b-497a-8d4d-094b08aa558b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63103711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_dige
st.63103711
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.901712660
Short name T24
Test name
Test status
Simulation time 1000443971 ps
CPU time 6.64 seconds
Started Dec 27 01:01:20 PM PST 23
Finished Dec 27 01:01:34 PM PST 23
Peak memory 218144 kb
Host smart-bf126e69-6d44-411e-8700-25a8b83f7ee7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901712660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.901712660
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.1035508779
Short name T773
Test name
Test status
Simulation time 303287732 ps
CPU time 9.27 seconds
Started Dec 27 01:01:15 PM PST 23
Finished Dec 27 01:01:29 PM PST 23
Peak memory 218176 kb
Host smart-b5042f3d-4cc0-4eee-8bf9-5558030c524f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035508779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.1035508779
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.986824756
Short name T334
Test name
Test status
Simulation time 92288746 ps
CPU time 1.55 seconds
Started Dec 27 01:01:16 PM PST 23
Finished Dec 27 01:01:22 PM PST 23
Peak memory 212672 kb
Host smart-cf968014-0f4b-4bc7-927b-f9348b88dbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986824756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.986824756
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.3897808785
Short name T682
Test name
Test status
Simulation time 300576731 ps
CPU time 23.16 seconds
Started Dec 27 01:01:15 PM PST 23
Finished Dec 27 01:01:43 PM PST 23
Peak memory 251136 kb
Host smart-b0680257-5cfb-4f27-bca0-90719aa2093f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897808785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.3897808785
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.400663463
Short name T406
Test name
Test status
Simulation time 308911389 ps
CPU time 6.41 seconds
Started Dec 27 01:01:08 PM PST 23
Finished Dec 27 01:01:18 PM PST 23
Peak memory 246664 kb
Host smart-57bfac9d-7cf1-4b5e-b8c0-0f631cc9dabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400663463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.400663463
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.2884456712
Short name T503
Test name
Test status
Simulation time 21574635907 ps
CPU time 109.27 seconds
Started Dec 27 01:01:15 PM PST 23
Finished Dec 27 01:03:09 PM PST 23
Peak memory 283944 kb
Host smart-d148e1ea-006c-4af9-a480-c855861741a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884456712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.2884456712
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1089217733
Short name T977
Test name
Test status
Simulation time 29244342 ps
CPU time 0.77 seconds
Started Dec 27 01:01:23 PM PST 23
Finished Dec 27 01:01:30 PM PST 23
Peak memory 208128 kb
Host smart-66280c22-f42c-481c-aa95-af8cbac10c22
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089217733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.1089217733
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.2845556786
Short name T578
Test name
Test status
Simulation time 38524011 ps
CPU time 0.92 seconds
Started Dec 27 01:01:17 PM PST 23
Finished Dec 27 01:01:23 PM PST 23
Peak memory 209716 kb
Host smart-b91b4664-060c-47aa-b708-eede71144a57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845556786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.2845556786
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.2345167293
Short name T449
Test name
Test status
Simulation time 26566064 ps
CPU time 0.88 seconds
Started Dec 27 01:01:11 PM PST 23
Finished Dec 27 01:01:16 PM PST 23
Peak memory 209504 kb
Host smart-1c73057c-590c-4cda-94cc-42f27cbb3006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345167293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.2345167293
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.705438399
Short name T851
Test name
Test status
Simulation time 3129978147 ps
CPU time 12.17 seconds
Started Dec 27 01:01:20 PM PST 23
Finished Dec 27 01:01:39 PM PST 23
Peak memory 218140 kb
Host smart-2d29b5a3-339d-4412-bcb7-2d609f76f01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705438399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.705438399
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.1095751137
Short name T5
Test name
Test status
Simulation time 3013848268 ps
CPU time 8.75 seconds
Started Dec 27 01:01:23 PM PST 23
Finished Dec 27 01:01:39 PM PST 23
Peak memory 209752 kb
Host smart-2a2c67b3-9408-4e20-b234-7459481f6dc7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095751137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_ac
cess.1095751137
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.961507825
Short name T457
Test name
Test status
Simulation time 2334715384 ps
CPU time 32.16 seconds
Started Dec 27 01:01:24 PM PST 23
Finished Dec 27 01:02:03 PM PST 23
Peak memory 218164 kb
Host smart-d6128830-6973-4104-a633-6ae2997f3f58
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961507825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_err
ors.961507825
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.1321335010
Short name T14
Test name
Test status
Simulation time 505304947 ps
CPU time 2.81 seconds
Started Dec 27 01:01:16 PM PST 23
Finished Dec 27 01:01:23 PM PST 23
Peak memory 209756 kb
Host smart-aef0eb13-b68b-41a1-88c0-32ae3bea9977
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321335010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
priority.1321335010
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.3030841191
Short name T512
Test name
Test status
Simulation time 2071588309 ps
CPU time 15.19 seconds
Started Dec 27 01:01:23 PM PST 23
Finished Dec 27 01:01:46 PM PST 23
Peak memory 218140 kb
Host smart-5faa2608-0d36-4983-b45b-a12cf3ff627d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030841191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.3030841191
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.514378807
Short name T366
Test name
Test status
Simulation time 5237449371 ps
CPU time 15.56 seconds
Started Dec 27 01:01:15 PM PST 23
Finished Dec 27 01:01:35 PM PST 23
Peak memory 213828 kb
Host smart-e5192350-b197-4f2e-b227-4a7b2edf7e9b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514378807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_regwen_during_op.514378807
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.2514996648
Short name T748
Test name
Test status
Simulation time 2003008400 ps
CPU time 15.93 seconds
Started Dec 27 01:01:22 PM PST 23
Finished Dec 27 01:01:45 PM PST 23
Peak memory 213644 kb
Host smart-5d064fca-789c-4f42-b9b4-9f78d081c3c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514996648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
2514996648
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.2054924585
Short name T507
Test name
Test status
Simulation time 5538753200 ps
CPU time 58.11 seconds
Started Dec 27 01:01:22 PM PST 23
Finished Dec 27 01:02:26 PM PST 23
Peak memory 251892 kb
Host smart-792135c1-9f9a-4528-a9d9-dfdc314a9eef
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054924585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.2054924585
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.3149483983
Short name T746
Test name
Test status
Simulation time 1496709463 ps
CPU time 12.55 seconds
Started Dec 27 01:01:20 PM PST 23
Finished Dec 27 01:01:40 PM PST 23
Peak memory 251136 kb
Host smart-fb858499-2cb9-4f48-be69-77c2f7bffb4d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149483983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.3149483983
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.2731080217
Short name T722
Test name
Test status
Simulation time 322031946 ps
CPU time 3.43 seconds
Started Dec 27 01:01:11 PM PST 23
Finished Dec 27 01:01:18 PM PST 23
Peak memory 218172 kb
Host smart-94625523-a620-4775-902e-1158b93827ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731080217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.2731080217
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3306584192
Short name T816
Test name
Test status
Simulation time 3142259382 ps
CPU time 26.54 seconds
Started Dec 27 01:01:14 PM PST 23
Finished Dec 27 01:01:45 PM PST 23
Peak memory 214660 kb
Host smart-c492f52c-085d-475b-8691-8425cd2805d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306584192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3306584192
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.1661082710
Short name T338
Test name
Test status
Simulation time 494430688 ps
CPU time 10.95 seconds
Started Dec 27 01:01:20 PM PST 23
Finished Dec 27 01:01:38 PM PST 23
Peak memory 218236 kb
Host smart-b2dc7758-56b2-40e0-9d2c-36fb332f3e5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661082710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.1661082710
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.2480210443
Short name T301
Test name
Test status
Simulation time 1957643992 ps
CPU time 14.38 seconds
Started Dec 27 01:01:23 PM PST 23
Finished Dec 27 01:01:44 PM PST 23
Peak memory 218120 kb
Host smart-3fb6f502-dbc8-40ca-804e-7ab8c4b59ee8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480210443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.2480210443
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.3221338243
Short name T428
Test name
Test status
Simulation time 234804731 ps
CPU time 6.71 seconds
Started Dec 27 01:01:19 PM PST 23
Finished Dec 27 01:01:33 PM PST 23
Peak memory 218080 kb
Host smart-578ddc19-cb93-4e76-8fbb-c80bdfbdc84f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221338243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.3
221338243
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.3970199345
Short name T185
Test name
Test status
Simulation time 350288980 ps
CPU time 13.21 seconds
Started Dec 27 01:01:14 PM PST 23
Finished Dec 27 01:01:31 PM PST 23
Peak memory 218120 kb
Host smart-b268b1cd-fe9f-4a73-ac86-daefef80127c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970199345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.3970199345
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.3855833703
Short name T640
Test name
Test status
Simulation time 20879671 ps
CPU time 1.16 seconds
Started Dec 27 01:01:21 PM PST 23
Finished Dec 27 01:01:28 PM PST 23
Peak memory 213004 kb
Host smart-ba787e66-de20-4908-9a42-89e90158941d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855833703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.3855833703
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.3913541869
Short name T564
Test name
Test status
Simulation time 490439328 ps
CPU time 28.79 seconds
Started Dec 27 01:01:20 PM PST 23
Finished Dec 27 01:01:56 PM PST 23
Peak memory 251132 kb
Host smart-f4d8cb90-1b4b-4525-ac06-e76d24b97476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913541869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.3913541869
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.4278804063
Short name T580
Test name
Test status
Simulation time 11780694078 ps
CPU time 116.96 seconds
Started Dec 27 01:01:21 PM PST 23
Finished Dec 27 01:03:25 PM PST 23
Peak memory 276820 kb
Host smart-d918868f-9a9d-47d8-9756-43862d755878
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278804063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.4278804063
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1000343875
Short name T29
Test name
Test status
Simulation time 35264666 ps
CPU time 0.89 seconds
Started Dec 27 01:01:11 PM PST 23
Finished Dec 27 01:01:15 PM PST 23
Peak memory 208172 kb
Host smart-587bac3f-60cd-4f77-ad4a-c9e31fea38e2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000343875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.1000343875
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.2944644963
Short name T539
Test name
Test status
Simulation time 14148689 ps
CPU time 0.84 seconds
Started Dec 27 01:01:32 PM PST 23
Finished Dec 27 01:01:36 PM PST 23
Peak memory 208376 kb
Host smart-fdf5bc35-50ec-4e21-a59d-2fae82ddaed9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944644963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.2944644963
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.664513996
Short name T833
Test name
Test status
Simulation time 98021648 ps
CPU time 0.83 seconds
Started Dec 27 01:01:18 PM PST 23
Finished Dec 27 01:01:24 PM PST 23
Peak memory 209528 kb
Host smart-bd3dfefe-2eb3-43a0-a9a5-340fbd25987d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664513996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.664513996
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.1169141894
Short name T699
Test name
Test status
Simulation time 515869394 ps
CPU time 14.44 seconds
Started Dec 27 01:01:16 PM PST 23
Finished Dec 27 01:01:35 PM PST 23
Peak memory 218224 kb
Host smart-1421aaa4-b7ff-4c5c-912c-1ed820bdec8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169141894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.1169141894
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.741501962
Short name T650
Test name
Test status
Simulation time 1111076834 ps
CPU time 6.76 seconds
Started Dec 27 01:01:30 PM PST 23
Finished Dec 27 01:01:41 PM PST 23
Peak memory 209700 kb
Host smart-15d20a24-4f4f-421a-9f7a-377eec322d56
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741501962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_acc
ess.741501962
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.3061605689
Short name T839
Test name
Test status
Simulation time 8407238211 ps
CPU time 31.83 seconds
Started Dec 27 01:01:20 PM PST 23
Finished Dec 27 01:01:58 PM PST 23
Peak memory 218408 kb
Host smart-185a0224-dfd0-4ba1-aa7e-32f29846c6a7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061605689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.3061605689
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.4235394936
Short name T536
Test name
Test status
Simulation time 369584228 ps
CPU time 2.12 seconds
Started Dec 27 01:01:23 PM PST 23
Finished Dec 27 01:01:32 PM PST 23
Peak memory 209756 kb
Host smart-72f0840c-824b-4395-9ee8-cba8d1a816dc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235394936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
priority.4235394936
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3522506066
Short name T550
Test name
Test status
Simulation time 238814965 ps
CPU time 3.79 seconds
Started Dec 27 01:01:26 PM PST 23
Finished Dec 27 01:01:36 PM PST 23
Peak memory 218108 kb
Host smart-343227ae-4c15-4d18-a9c2-cb14fa889a16
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522506066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.3522506066
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1457194404
Short name T909
Test name
Test status
Simulation time 1607172459 ps
CPU time 11.75 seconds
Started Dec 27 01:01:23 PM PST 23
Finished Dec 27 01:01:41 PM PST 23
Peak memory 212884 kb
Host smart-14eb74aa-ed43-4ff9-82e4-e1cb16c8ac8a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457194404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.1457194404
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.835412801
Short name T549
Test name
Test status
Simulation time 237155248 ps
CPU time 4.22 seconds
Started Dec 27 01:01:20 PM PST 23
Finished Dec 27 01:01:31 PM PST 23
Peak memory 213252 kb
Host smart-04527833-97a7-421b-8171-c10af8746556
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835412801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.835412801
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.75797448
Short name T633
Test name
Test status
Simulation time 7754134921 ps
CPU time 46.27 seconds
Started Dec 27 01:01:27 PM PST 23
Finished Dec 27 01:02:19 PM PST 23
Peak memory 251156 kb
Host smart-71d9239a-fe6d-43aa-b5f0-94cbde51f872
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75797448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
state_failure.75797448
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.1745212646
Short name T186
Test name
Test status
Simulation time 6142625376 ps
CPU time 13.62 seconds
Started Dec 27 01:01:24 PM PST 23
Finished Dec 27 01:01:45 PM PST 23
Peak memory 251184 kb
Host smart-3a0c849e-9549-48c9-aa6c-94abccb4e7d7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745212646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.1745212646
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.1622750025
Short name T778
Test name
Test status
Simulation time 60152296 ps
CPU time 3.09 seconds
Started Dec 27 01:01:18 PM PST 23
Finished Dec 27 01:01:27 PM PST 23
Peak memory 218180 kb
Host smart-e8f72c58-4ba8-4aa8-bac6-50557d106199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622750025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.1622750025
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.1717030906
Short name T755
Test name
Test status
Simulation time 156194524 ps
CPU time 8.94 seconds
Started Dec 27 01:01:24 PM PST 23
Finished Dec 27 01:01:40 PM PST 23
Peak memory 213924 kb
Host smart-f0264d9f-66b9-4088-b9ae-3d735b584e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717030906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.1717030906
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.2494306945
Short name T47
Test name
Test status
Simulation time 2420660979 ps
CPU time 15.3 seconds
Started Dec 27 01:01:20 PM PST 23
Finished Dec 27 01:01:42 PM PST 23
Peak memory 219264 kb
Host smart-609673ac-b759-4fa4-bb21-d84c26b10cbe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494306945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.2494306945
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.3925396898
Short name T331
Test name
Test status
Simulation time 1054167691 ps
CPU time 11.88 seconds
Started Dec 27 01:01:25 PM PST 23
Finished Dec 27 01:01:44 PM PST 23
Peak memory 218176 kb
Host smart-2258341b-ee7d-4e3a-8dcc-37690d2491a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925396898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.3925396898
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3489547808
Short name T514
Test name
Test status
Simulation time 210207841 ps
CPU time 8.59 seconds
Started Dec 27 01:01:21 PM PST 23
Finished Dec 27 01:01:36 PM PST 23
Peak memory 218164 kb
Host smart-2595d819-a9bf-451f-841b-62f9f2737fbe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489547808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.3
489547808
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.2283804098
Short name T575
Test name
Test status
Simulation time 870976044 ps
CPU time 9.59 seconds
Started Dec 27 01:01:25 PM PST 23
Finished Dec 27 01:01:42 PM PST 23
Peak memory 218212 kb
Host smart-6ef98e0b-2774-444f-900a-bd2d92ca8bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283804098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.2283804098
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.3047467296
Short name T765
Test name
Test status
Simulation time 30246355 ps
CPU time 1.11 seconds
Started Dec 27 01:01:21 PM PST 23
Finished Dec 27 01:01:28 PM PST 23
Peak memory 213064 kb
Host smart-7db3f313-14fe-46b4-a912-d6da32f76c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047467296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.3047467296
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.2377892279
Short name T552
Test name
Test status
Simulation time 1361282572 ps
CPU time 37.12 seconds
Started Dec 27 01:01:20 PM PST 23
Finished Dec 27 01:02:04 PM PST 23
Peak memory 251048 kb
Host smart-4258d2a7-e284-4299-9e40-f3a41df20f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377892279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.2377892279
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.2418680277
Short name T188
Test name
Test status
Simulation time 76181094 ps
CPU time 6.31 seconds
Started Dec 27 01:01:17 PM PST 23
Finished Dec 27 01:01:29 PM PST 23
Peak memory 246464 kb
Host smart-c2c93065-269e-4dfa-a020-fb8202057265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418680277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.2418680277
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.3880008625
Short name T902
Test name
Test status
Simulation time 16272732511 ps
CPU time 46.94 seconds
Started Dec 27 01:01:22 PM PST 23
Finished Dec 27 01:02:16 PM PST 23
Peak memory 231472 kb
Host smart-7d97f234-a546-4473-b276-b6639bb0cce0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880008625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.3880008625
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2913539200
Short name T373
Test name
Test status
Simulation time 24638412 ps
CPU time 1.03 seconds
Started Dec 27 01:01:21 PM PST 23
Finished Dec 27 01:01:28 PM PST 23
Peak memory 211568 kb
Host smart-a4f6afdd-1508-4ea2-ba43-0905ef9420e4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913539200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.2913539200
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.405282837
Short name T395
Test name
Test status
Simulation time 51913832 ps
CPU time 0.96 seconds
Started Dec 27 01:01:37 PM PST 23
Finished Dec 27 01:01:39 PM PST 23
Peak memory 209652 kb
Host smart-cd35af23-3b2b-48be-af7c-1ee598c9f47f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405282837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.405282837
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.1765189800
Short name T914
Test name
Test status
Simulation time 713985893 ps
CPU time 12.98 seconds
Started Dec 27 01:01:29 PM PST 23
Finished Dec 27 01:01:47 PM PST 23
Peak memory 218220 kb
Host smart-cb013199-6201-4da1-b0dc-024216b83bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765189800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1765189800
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.598638018
Short name T584
Test name
Test status
Simulation time 223521167 ps
CPU time 5.86 seconds
Started Dec 27 01:01:23 PM PST 23
Finished Dec 27 01:01:36 PM PST 23
Peak memory 209600 kb
Host smart-93dcaecc-317f-4ca6-9dd1-70c8f7a2e1b1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598638018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_acc
ess.598638018
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.1776805331
Short name T547
Test name
Test status
Simulation time 1701215535 ps
CPU time 32.67 seconds
Started Dec 27 01:01:25 PM PST 23
Finished Dec 27 01:02:05 PM PST 23
Peak memory 218136 kb
Host smart-09510913-7375-40fa-91a7-799579ba056a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776805331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.1776805331
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.741210350
Short name T590
Test name
Test status
Simulation time 367521711 ps
CPU time 3.03 seconds
Started Dec 27 01:01:22 PM PST 23
Finished Dec 27 01:01:31 PM PST 23
Peak memory 209748 kb
Host smart-984900ef-7ef9-4cef-8938-711a790bd082
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741210350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_p
riority.741210350
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2126345408
Short name T684
Test name
Test status
Simulation time 223027394 ps
CPU time 6.65 seconds
Started Dec 27 01:01:28 PM PST 23
Finished Dec 27 01:01:40 PM PST 23
Peak memory 218168 kb
Host smart-e749d020-9a3d-4f13-9cda-741c4af49aed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126345408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.2126345408
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.871971007
Short name T333
Test name
Test status
Simulation time 794681171 ps
CPU time 10.6 seconds
Started Dec 27 01:01:23 PM PST 23
Finished Dec 27 01:01:41 PM PST 23
Peak memory 212940 kb
Host smart-043dad92-207e-41e4-b948-74ba8e68a00e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871971007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_regwen_during_op.871971007
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2540621896
Short name T930
Test name
Test status
Simulation time 1431701543 ps
CPU time 4.7 seconds
Started Dec 27 01:01:26 PM PST 23
Finished Dec 27 01:01:37 PM PST 23
Peak memory 212968 kb
Host smart-fcd62bd0-f024-4794-87fa-57231542e41b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540621896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
2540621896
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.510363520
Short name T767
Test name
Test status
Simulation time 1356342668 ps
CPU time 58.9 seconds
Started Dec 27 01:01:26 PM PST 23
Finished Dec 27 01:02:32 PM PST 23
Peak memory 254568 kb
Host smart-a6fa9f2f-8345-41fe-8a0f-c2bb6aa0be1b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510363520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_state_failure.510363520
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.4260934278
Short name T534
Test name
Test status
Simulation time 451725910 ps
CPU time 9.11 seconds
Started Dec 27 01:01:33 PM PST 23
Finished Dec 27 01:01:44 PM PST 23
Peak memory 221824 kb
Host smart-d713c6ad-2499-41f9-9bbe-254b72084db6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260934278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.4260934278
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.4260297148
Short name T436
Test name
Test status
Simulation time 92680472 ps
CPU time 1.79 seconds
Started Dec 27 01:01:38 PM PST 23
Finished Dec 27 01:01:41 PM PST 23
Peak memory 218224 kb
Host smart-04e2cfa9-5bc8-41f5-9dbd-8df5bebd908e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260297148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.4260297148
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.3276853699
Short name T927
Test name
Test status
Simulation time 693058588 ps
CPU time 9.58 seconds
Started Dec 27 01:01:22 PM PST 23
Finished Dec 27 01:01:39 PM PST 23
Peak memory 214036 kb
Host smart-6b0ce34c-09fa-4b24-ab24-3edf330dfb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276853699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.3276853699
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.1742385975
Short name T831
Test name
Test status
Simulation time 1706556882 ps
CPU time 16.47 seconds
Started Dec 27 01:01:26 PM PST 23
Finished Dec 27 01:01:49 PM PST 23
Peak memory 219256 kb
Host smart-f687cb8c-3b3e-40a2-9064-2b84b6efc4b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742385975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1742385975
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.3893559814
Short name T565
Test name
Test status
Simulation time 22306482564 ps
CPU time 22.85 seconds
Started Dec 27 01:01:26 PM PST 23
Finished Dec 27 01:01:56 PM PST 23
Peak memory 218128 kb
Host smart-f7dd6630-9af3-4988-afe4-b2eca8d2f475
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893559814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.3893559814
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.4062295783
Short name T721
Test name
Test status
Simulation time 1819072187 ps
CPU time 15.94 seconds
Started Dec 27 01:01:31 PM PST 23
Finished Dec 27 01:01:50 PM PST 23
Peak memory 218060 kb
Host smart-9e0ac5ca-60c6-425f-bd42-95be8be1472b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062295783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.4
062295783
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.1113257442
Short name T479
Test name
Test status
Simulation time 688720870 ps
CPU time 12.5 seconds
Started Dec 27 01:01:24 PM PST 23
Finished Dec 27 01:01:44 PM PST 23
Peak memory 218112 kb
Host smart-6e02d7dc-48bf-4061-9924-6e19d8051b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113257442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.1113257442
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.1785812498
Short name T61
Test name
Test status
Simulation time 79758718 ps
CPU time 3.15 seconds
Started Dec 27 01:01:20 PM PST 23
Finished Dec 27 01:01:30 PM PST 23
Peak memory 214168 kb
Host smart-21445bfb-33a9-4c98-8aff-ccbc26915cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785812498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1785812498
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.3546119015
Short name T891
Test name
Test status
Simulation time 4908832999 ps
CPU time 26.47 seconds
Started Dec 27 01:01:28 PM PST 23
Finished Dec 27 01:02:00 PM PST 23
Peak memory 251228 kb
Host smart-3b4067aa-9068-4cfc-9913-ca37349e7a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546119015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.3546119015
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.2942916844
Short name T394
Test name
Test status
Simulation time 115794867 ps
CPU time 7.74 seconds
Started Dec 27 01:01:23 PM PST 23
Finished Dec 27 01:01:38 PM PST 23
Peak memory 251208 kb
Host smart-b9aba8e3-fd90-4d7b-97bf-bc2a0e42bcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942916844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.2942916844
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.317072536
Short name T687
Test name
Test status
Simulation time 3910525886 ps
CPU time 56.99 seconds
Started Dec 27 01:01:27 PM PST 23
Finished Dec 27 01:02:30 PM PST 23
Peak memory 248040 kb
Host smart-d8552ca3-9edb-4baa-ad83-7e1645ec969e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317072536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.317072536
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2806682400
Short name T849
Test name
Test status
Simulation time 39043340 ps
CPU time 0.78 seconds
Started Dec 27 01:01:22 PM PST 23
Finished Dec 27 01:01:29 PM PST 23
Peak memory 207944 kb
Host smart-2330af73-6050-49fb-84e1-f07ef8bd7e4c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806682400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.2806682400
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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