LC_CTRL Simulation Results

Wednesday December 27 2023 20:02:24 UTC

GitHub Revision: 0c759b93ab

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85416116840666724748485424200434981761468351851988553961117902923833034512693

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	10.430s	652.462us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	0.990s	66.543us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.060s	14.087us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.020s	178.482us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.590s	34.196us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.050s	51.833us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.060s	14.087us	20	20	100.00
		lc_ctrl_csr_aliasing	1.590s	34.196us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.390s	1.269ms	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	26.540s	3.142ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.880s	26.566us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.860s	446.259us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.580s	1.057ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	19.060s	2.799ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.580s	1.057ms	50	50	100.00
		lc_ctrl_prog_failure	4.860s	446.259us	50	50	100.00
		lc_ctrl_errors	19.060s	2.799ms	50	50	100.00
		lc_ctrl_security_escalation	14.540s	777.118us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.069m	5.705ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	15.190s	2.072ms	20	20	100.00
		lc_ctrl_jtag_errors	1.805m	6.671ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	19.000s	752.050us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	23.570s	26.367ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	15.190s	2.072ms	20	20	100.00
		lc_ctrl_jtag_errors	1.805m	6.671ms	20	20	100.00
		lc_ctrl_jtag_access	18.830s	805.563us	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	35.560s	2.614ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.860s	863.213us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.030s	119.099us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	37.070s	6.414ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	20.940s	991.169us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.880s	45.516us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	2.920s	784.470us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.270s	1.125ms	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	21.410s	4.391ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.160s	153.561us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	8.944m	36.284ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.270s	24.743us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.980s	735.728us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.980s	735.728us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	0.990s	66.543us	5	5	100.00
		lc_ctrl_csr_rw	1.060s	14.087us	20	20	100.00
		lc_ctrl_csr_aliasing	1.590s	34.196us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.800s	172.032us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	0.990s	66.543us	5	5	100.00
		lc_ctrl_csr_rw	1.060s	14.087us	20	20	100.00
		lc_ctrl_csr_aliasing	1.590s	34.196us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.800s	172.032us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	36.230s	226.470us	5	5	100.00
		lc_ctrl_tl_intg_err	5.760s	228.713us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	5.760s	228.713us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	26.540s	3.142ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.580s	1.057ms	50	50	100.00
		lc_ctrl_sec_cm	36.230s	226.470us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.580s	1.057ms	50	50	100.00
		lc_ctrl_sec_cm	36.230s	226.470us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.580s	1.057ms	50	50	100.00
		lc_ctrl_sec_cm	36.230s	226.470us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.580s	1.057ms	50	50	100.00
		lc_ctrl_sec_cm	36.230s	226.470us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.580s	1.057ms	50	50	100.00
		lc_ctrl_sec_cm	36.230s	226.470us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.580s	1.057ms	50	50	100.00
		lc_ctrl_sec_cm	36.230s	226.470us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.580s	1.057ms	50	50	100.00
		lc_ctrl_sec_cm	36.230s	226.470us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.580s	1.057ms	50	50	100.00
		lc_ctrl_sec_cm	36.230s	226.470us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	14.540s	777.118us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.390s	1.269ms	50	50	100.00
		lc_ctrl_jtag_state_post_trans	23.570s	26.367ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	25.010s	935.901us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	25.010s	935.901us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	22.860s	852.100us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	19.010s	574.409us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	19.010s	574.409us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.751h	103.443ms	4	50	8.00
V3		TOTAL			4	50	8.00
		TOTAL			983	1030	95.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.02	97.29	95.61	91.98	97.67	96.13	98.48	95.00

Failure Buckets

• Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 25 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 25 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.63163532141191109049493124778198245448680758518119015163951812219997574355447
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:a992a9a0-f4f6-485b-a62f-2802c90f0199
      

    • 1.lc_ctrl_stress_all_with_rand_reset.49088130849238766384792099852411324459026647204948566291145892552541119624419
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:e7d11e0b-95bf-4919-858f-cf91918b0dfb
      

    • ... and 23 more failures.

• Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 11 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 11 failures.

    • 21.lc_ctrl_stress_all_with_rand_reset.7055660903588601007711214399385283547107243464391872128474052509364613336425
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:fa64be7f-66b0-42d5-bd5b-19f0a06ac76e
      

    • 23.lc_ctrl_stress_all_with_rand_reset.77278394198583246055453148076486505131680452415150017795489710872679932573979
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:a9349670-8760-406b-9e91-80d86da60947
      

    • ... and 9 more failures.

• UVM_ERROR (jtag_riscv_monitor.sv:80) monitor [monitor] Bad status - DmiReserved(*) has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 13.lc_ctrl_stress_all_with_rand_reset.67266287935804482221829383095584841144294913758713333968174053657150141333714
      Line 9747, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9231111217 ps: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
        UVM_INFO @ 9231111217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 14.lc_ctrl_stress_all_with_rand_reset.106990039343019911982549995585467171848969171416733248117438122622012132983575
      Line 12409, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 50181743401 ps: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
        UVM_INFO @ 50181743401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 14.lc_ctrl_stress_all.32824396075941327889489024750246646214092794840347768568488453661103591549083
      Line 10494, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/14.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 14085736415 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 14085736415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 24.lc_ctrl_stress_all_with_rand_reset.66183633727067821663077513929691317777983534607383480750698371521994409924348
      Line 4702, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4943098243 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 4943098243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 36.lc_ctrl_stress_all_with_rand_reset.67516283185865477577510287676666907401301388608673804292847783899400598936184
      Line 31728, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/36.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 84881542832 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 84881542832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:239) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 6.lc_ctrl_stress_all_with_rand_reset.89148093277192043687350874148864186277095629187469208333563148820677044776325
      Line 8523, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10891123407 ps: (lc_ctrl_scoreboard.sv:239) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 97, LC_St DecLcStTestLocked3
        UVM_INFO @ 10891123407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.transition_token_* reset value: * has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 9.lc_ctrl_stress_all_with_rand_reset.3462303059338175726366406028263562809998358854482743997692626353100024904236
      Line 21555, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 53852663475 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 2669530944 [0x9f1dcf40]) Regname: lc_ctrl_reg_block.transition_token_1 reset value: 0x0
        UVM_INFO @ 53852663475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:519) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 39.lc_ctrl_stress_all_with_rand_reset.86365830457274649489044160162635295054472961994925181486272265590994345877732
      Line 36326, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17109401051 ps: (cip_base_vseq.sv:519) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 17109401051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (lc_ctrl_scoreboard.sv:265) scoreboard [scoreboard] Access unexpected addr * has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 43.lc_ctrl_stress_all_with_rand_reset.103516935201796012720792262015672707327398922008847408474939726569305716915333
      Line 28782, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/43.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 218300652478 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0xd847c400
        UVM_INFO @ 218300652478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:371) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: lc_ctrl_reg_block.lc_state has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 45.lc_ctrl_stress_all_with_rand_reset.17369070590827285376397465160839978441183907177902675795895048167383350225671
      Line 3367, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/45.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1874884661 ps: (lc_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (762010326 [0x2d6b5ad6] vs 796647159 [0x2f7bdef7]) reg name: lc_ctrl_reg_block.lc_state
        UVM_INFO @ 1874884661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2023.12.25_01.25.43
• 2023.12.21_00.15.46
• 2023.11.23_02.09.59
• 2023.11.02_03.38.10
• 2023.10.30_18.19.21
• 2023.10.26_03.01.18