Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

70193806

1

T1

37562

T91

10496

T92

1198

auto[1]

1227754

1

T2

792

T3

3431

T9

8614

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

70199264

1

T1

37562

T91

10496

T92

1198

auto[1]

1222296

1

T2

495

T3

2354

T9

8460

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5862795	1			T1	6206		T91	1986		T92	73
auto[IdleSt]	17515519	1			T1	2274		T91	8510		T92	1125
auto[ClkMuxSt]	29961	1			T1	67		T2	82		T9	51
auto[CntIncrSt]	29770	1			T1	67		T2	82		T9	50
auto[CntProgSt]	1251220	1			T1	6298		T2	627		T9	93
auto[TransCheckSt]	23409	1			T1	67		T2	57		T9	41
auto[TokenHashSt]	21636084	1			T1	12337		T2	4283		T9	2066
auto[FlashRmaSt]	22947	1			T2	54		T9	53		T10	7
auto[TokenCheck0St]	10241	1			T2	24		T9	21		T10	7
auto[TokenCheck1St]	7309	1			T2	14		T9	21		T10	7
auto[TransProgSt]	284297	1			T2	127		T9	35		T10	1122
auto[PostTransSt]	10404310	1			T1	10246		T2	12908		T9	16
auto[ScrapSt]	95579	1			T112	421		T111	370		T113	137
auto[EscalateSt]	5532118	1			T2	1902		T3	25183		T9	12994
auto[InvalidSt]	8714583	1			T3	77653		T13	7976		T17	1155

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1418	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	8714583	1			T3	77653		T13	7976		T17	1155
EscalateSt	5532118	1			T2	1902		T3	25183		T9	12994
ScrapSt	95579	1			T112	421		T111	370		T113	137
PostTransSt	10404310	1			T1	10246		T2	12908		T9	16
TransProgSt	284297	1			T2	127		T9	35		T10	1122
TokenCheck1St	7309	1			T2	14		T9	21		T10	7
TokenCheck0St	10241	1			T2	24		T9	21		T10	7
FlashRmaSt	22947	1			T2	54		T9	53		T10	7
TokenHashSt	21636084	1			T1	12337		T2	4283		T9	2066
TransCheckSt	23409	1			T1	67		T2	57		T9	41
CntProgSt	1251220	1			T1	6298		T2	627		T9	93
CntIncrSt	29770	1			T1	67		T2	82		T9	50
ClkMuxSt	29961	1			T1	67		T2	82		T9	51
IdleSt	17515519	1			T1	2274		T91	8510		T92	1125
ResetSt	5862795	1			T1	6206		T91	1986		T92	73
arcs[ResetSt=>IdleSt]	43937	1			T1	68		T91	21		T92	1
arcs[IdleSt=>ScrapSt]	202	1			T112	1		T111	1		T113	1
arcs[IdleSt=>ClkMuxSt]	29825	1			T1	67		T2	82		T9	51
arcs[ClkMuxSt=>CntIncrSt]	29770	1			T1	67		T2	82		T9	50
arcs[CntIncrSt=>PostTransSt]	1409	1			T2	12		T15	9		T18	23
arcs[CntIncrSt=>CntProgSt]	28287	1			T1	67		T2	70		T9	48
arcs[CntProgSt=>PostTransSt]	3778	1			T2	13		T15	10		T16	10
arcs[CntProgSt=>TransCheckSt]	23409	1			T1	67		T2	57		T9	41
arcs[TransCheckSt=>PostTransSt]	3322	1			T2	11		T11	29		T15	12
arcs[TransCheckSt=>TokenHashSt]	19985	1			T1	67		T2	46		T9	35
arcs[TokenHashSt=>PostTransSt]	8986	1			T1	67		T2	22		T11	11
arcs[TokenHashSt=>FlashRmaSt]	10339	1			T2	24		T9	21		T10	7
arcs[FlashRmaSt=>TokenCheck0St]	10241	1			T2	24		T9	21		T10	7
arcs[TokenCheck0St=>PostTransSt]	2902	1			T2	10		T11	12		T15	13
arcs[TokenCheck0St=>TokenCheck1St]	7309	1			T2	14		T9	21		T10	7
arcs[TokenCheck1St=>PostTransSt]	629	1			T2	2		T11	10		T22	2
arcs[TransProgSt=>PostTransSt]	5781	1			T2	12		T9	11		T10	7
arcs[IdleSt=>EscalateSt]	165	1			T9	5		T55	7		T58	1
arcs[ClkMuxSt=>EscalateSt]	55	1			T9	1		T55	1		T56	1
arcs[CntIncrSt=>EscalateSt]	74	1			T9	2		T55	2		T57	1
arcs[CntProgSt=>EscalateSt]	1100	1			T9	7		T55	8		T57	8
arcs[TransCheckSt=>EscalateSt]	102	1			T9	6		T55	6		T57	3
arcs[TokenHashSt=>EscalateSt]	650	1			T9	14		T55	11		T57	24
arcs[FlashRmaSt=>EscalateSt]	98	1			T55	3		T57	1		T56	4
arcs[TokenCheck0St=>EscalateSt]	30	1			T55	1		T57	2		T62	1
arcs[TokenCheck1St=>EscalateSt]	137	1			T9	1		T55	4		T57	1
arcs[TransProgSt=>EscalateSt]	762	1			T9	9		T55	8		T57	4
arcs[PostTransSt=>EscalateSt]	3984	1			T2	13		T9	11		T15	10
arcs[InvalidSt=>EscalateSt]	11654	1			T3	59		T13	51		T17	8

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5862608	1			T1	6206		T91	1986		T92	73
auto[0]	auto[IdleSt]	17515404	1			T1	2274		T91	8510		T92	1125
auto[0]	auto[ClkMuxSt]	29927	1			T1	67		T2	82		T9	50
auto[0]	auto[CntIncrSt]	29714	1			T1	67		T2	82		T9	48
auto[0]	auto[CntProgSt]	1250477	1			T1	6298		T2	627		T9	88
auto[0]	auto[TransCheckSt]	23340	1			T1	67		T2	57		T9	37
auto[0]	auto[TokenHashSt]	21635647	1			T1	12337		T2	4283		T9	2058
auto[0]	auto[FlashRmaSt]	22881	1			T2	54		T9	53		T10	7
auto[0]	auto[TokenCheck0St]	10221	1			T2	24		T9	21		T10	7
auto[0]	auto[TokenCheck1St]	7216	1			T2	14		T9	20		T10	7
auto[0]	auto[TransProgSt]	283780	1			T2	127		T9	30		T10	1122
auto[0]	auto[PostTransSt]	10402287	1			T1	10246		T2	12900		T9	8
auto[0]	auto[ScrapSt]	95541	1			T112	421		T111	370		T113	137
auto[0]	auto[EscalateSt]	4314612	1			T2	1118		T3	21787		T9	4420
auto[0]	auto[InvalidSt]	8708733	1			T3	77618		T13	7950		T17	1150
auto[1]	auto[ResetSt]	187	1			T9	3		T55	3		T57	3
auto[1]	auto[IdleSt]	115	1			T9	2		T55	6		T58	1
auto[1]	auto[ClkMuxSt]	34	1			T9	1		T184	1		T58	2
auto[1]	auto[CntIncrSt]	56	1			T9	2		T56	1		T123	1
auto[1]	auto[CntProgSt]	743	1			T9	5		T55	6		T57	7
auto[1]	auto[TransCheckSt]	69	1			T9	4		T55	3		T57	2
auto[1]	auto[TokenHashSt]	437	1			T9	8		T55	8		T57	14
auto[1]	auto[FlashRmaSt]	66	1			T55	1		T57	1		T56	2
auto[1]	auto[TokenCheck0St]	20	1			T55	1		T57	1		T62	1
auto[1]	auto[TokenCheck1St]	93	1			T9	1		T55	3		T56	4
auto[1]	auto[TransProgSt]	517	1			T9	5		T55	7		T57	2
auto[1]	auto[PostTransSt]	2023	1			T2	8		T9	8		T15	4
auto[1]	auto[ScrapSt]	38	1			T9	1		T55	2		T57	3
auto[1]	auto[EscalateSt]	1217506	1			T2	784		T3	3396		T9	8574
auto[1]	auto[InvalidSt]	5850	1			T3	35		T13	26		T17	5

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5862607	1			T1	6206		T91	1986		T92	73
auto[0]	auto[IdleSt]	17515407	1			T1	2274		T91	8510		T92	1125
auto[0]	auto[ClkMuxSt]	29918	1			T1	67		T2	82		T9	50
auto[0]	auto[CntIncrSt]	29726	1			T1	67		T2	82		T9	49
auto[0]	auto[CntProgSt]	1250483	1			T1	6298		T2	627		T9	89
auto[0]	auto[TransCheckSt]	23341	1			T1	67		T2	57		T9	39
auto[0]	auto[TokenHashSt]	21635622	1			T1	12337		T2	4283		T9	2057
auto[0]	auto[FlashRmaSt]	22881	1			T2	54		T9	53		T10	7
auto[0]	auto[TokenCheck0St]	10220	1			T2	24		T9	21		T10	7
auto[0]	auto[TokenCheck1St]	7225	1			T2	14		T9	21		T10	7
auto[0]	auto[TransProgSt]	283788	1			T2	127		T9	28		T10	1122
auto[0]	auto[PostTransSt]	10402294	1			T1	10246		T2	12903		T9	9
auto[0]	auto[ScrapSt]	95546	1			T112	421		T111	370		T113	137
auto[0]	auto[EscalateSt]	4320009	1			T2	1412		T3	22853		T9	4573
auto[0]	auto[InvalidSt]	8708779	1			T3	77629		T13	7951		T17	1152
auto[1]	auto[ResetSt]	188	1			T9	3		T55	3		T57	4
auto[1]	auto[IdleSt]	112	1			T9	4		T55	5		T62	10
auto[1]	auto[ClkMuxSt]	43	1			T9	1		T55	1		T56	1
auto[1]	auto[CntIncrSt]	44	1			T9	1		T55	2		T57	1
auto[1]	auto[CntProgSt]	737	1			T9	4		T55	7		T57	4
auto[1]	auto[TransCheckSt]	68	1			T9	2		T55	4		T57	3
auto[1]	auto[TokenHashSt]	462	1			T9	9		T55	6		T57	19
auto[1]	auto[FlashRmaSt]	66	1			T55	3		T56	2		T62	3
auto[1]	auto[TokenCheck0St]	21	1			T57	2		T185	1		T186	1
auto[1]	auto[TokenCheck1St]	84	1			T55	3		T57	1		T56	4
auto[1]	auto[TransProgSt]	509	1			T9	7		T55	4		T57	3
auto[1]	auto[PostTransSt]	2016	1			T2	5		T9	7		T15	6
auto[1]	auto[ScrapSt]	33	1			T9	1		T55	2		T57	3
auto[1]	auto[EscalateSt]	1212109	1			T2	490		T3	2330		T9	8421
auto[1]	auto[InvalidSt]	5804	1			T3	24		T13	25		T17	3