Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	978091	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1167625

1

T1

1860

T91

633

T92

57

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1851578	1			T1	2765		T91	84		T92	6
values[0x0]	146542	1			T1	278		T91	328		T92	33
values[0x1]	147596	1			T1	258		T91	338		T92	32

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	775298	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1370418

1

T1

2156

T91

673

T92

60

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8748	1			T1	11		T93	1		T98	1
valid_sources[0x01]	7725	1			T1	21		T92	36		T97	1
valid_sources[0x02]	7442	1			T1	11		T129	4		T103	6
valid_sources[0x03]	8985	1			T1	16		T97	1		T99	1
valid_sources[0x04]	8402	1			T1	14		T98	2		T99	1
valid_sources[0x05]	8088	1			T1	18		T93	2		T97	1
valid_sources[0x06]	7558	1			T1	5		T129	1		T103	1
valid_sources[0x07]	8258	1			T1	15		T95	1		T99	1
valid_sources[0x08]	7411	1			T1	12		T103	5		T125	1
valid_sources[0x09]	8153	1			T1	15		T98	1		T129	1
valid_sources[0x0a]	7598	1			T1	10		T96	3		T103	6
valid_sources[0x0b]	7396	1			T1	8		T129	2		T165	5
valid_sources[0x0c]	7715	1			T1	11		T103	5		T124	1
valid_sources[0x0d]	7323	1			T1	22		T97	1		T98	2
valid_sources[0x0e]	9292	1			T1	10		T103	3		T125	1
valid_sources[0x0f]	7533	1			T1	18		T98	1		T129	2
valid_sources[0x10]	7448	1			T1	14		T125	1		T178	2
valid_sources[0x11]	7639	1			T1	19		T103	7		T125	2
valid_sources[0x12]	7942	1			T1	14		T96	2		T97	1
valid_sources[0x13]	8817	1			T1	13		T96	1		T98	2
valid_sources[0x14]	7647	1			T1	13		T98	1		T99	1
valid_sources[0x15]	10449	1			T1	12		T93	1		T96	4
valid_sources[0x16]	7899	1			T1	9		T97	2		T98	1
valid_sources[0x17]	7971	1			T1	8		T97	1		T129	6
valid_sources[0x18]	8113	1			T1	9		T94	22		T97	3
valid_sources[0x19]	7505	1			T1	14		T96	1		T98	2
valid_sources[0x1a]	7467	1			T1	7		T98	1		T129	1
valid_sources[0x1b]	8776	1			T1	14		T98	1		T129	2
valid_sources[0x1c]	9078	1			T1	11		T97	2		T98	2
valid_sources[0x1d]	8031	1			T1	8		T98	1		T129	1
valid_sources[0x1e]	7433	1			T1	6		T95	1		T97	1
valid_sources[0x1f]	10200	1			T1	5		T91	18		T129	2
valid_sources[0x20]	7235	1			T1	8		T97	1		T103	3
valid_sources[0x21]	7716	1			T1	26		T97	2		T129	3
valid_sources[0x22]	8989	1			T1	18		T93	2		T103	3
valid_sources[0x23]	7530	1			T1	14		T97	1		T98	1
valid_sources[0x24]	7420	1			T1	12		T97	2		T98	3
valid_sources[0x25]	7803	1			T1	20		T97	1		T98	2
valid_sources[0x26]	8928	1			T1	21		T91	17		T96	3
valid_sources[0x27]	7825	1			T1	20		T93	2		T98	2
valid_sources[0x28]	7191	1			T1	16		T97	2		T99	1
valid_sources[0x29]	7594	1			T1	22		T93	3		T94	8
valid_sources[0x2a]	7896	1			T1	19		T97	2		T98	2
valid_sources[0x2b]	8836	1			T1	32		T98	2		T178	5
valid_sources[0x2c]	7828	1			T1	14		T125	3		T112	3
valid_sources[0x2d]	7922	1			T1	10		T94	11		T96	1
valid_sources[0x2e]	7573	1			T1	7		T93	1		T94	1
valid_sources[0x2f]	9356	1			T1	11		T93	1		T95	2
valid_sources[0x30]	7728	1			T1	23		T95	1		T97	1
valid_sources[0x31]	7809	1			T1	20		T91	46		T98	2
valid_sources[0x32]	8142	1			T1	6		T103	1		T125	2
valid_sources[0x33]	7624	1			T1	9		T103	1		T125	1
valid_sources[0x34]	8674	1			T1	5		T97	1		T178	4
valid_sources[0x35]	7451	1			T1	18		T95	2		T96	5
valid_sources[0x36]	7930	1			T1	15		T97	1		T98	3
valid_sources[0x37]	7451	1			T1	5		T97	2		T124	16
valid_sources[0x38]	7611	1			T1	18		T93	1		T124	5
valid_sources[0x39]	7655	1			T1	11		T95	1		T97	1
valid_sources[0x3a]	7829	1			T1	15		T95	1		T98	2
valid_sources[0x3b]	7732	1			T1	7		T129	1		T178	3
valid_sources[0x3c]	8430	1			T1	23		T93	1		T94	2
valid_sources[0x3d]	7693	1			T1	24		T97	2		T98	1
valid_sources[0x3e]	11211	1			T1	21		T98	3		T178	2
valid_sources[0x3f]	7610	1			T1	18		T98	1		T125	1
valid_sources[0x40]	8411	1			T1	7		T95	1		T129	6
valid_sources[0x41]	10517	1			T1	9		T129	1		T103	7
valid_sources[0x42]	7422	1			T1	7		T98	1		T125	2
valid_sources[0x43]	7787	1			T1	12		T91	19		T93	1
valid_sources[0x44]	7027	1			T1	19		T93	2		T97	4
valid_sources[0x45]	7380	1			T1	36		T98	1		T129	1
valid_sources[0x46]	7403	1			T1	18		T91	18		T97	1
valid_sources[0x47]	7480	1			T1	16		T96	1		T97	1
valid_sources[0x48]	7832	1			T1	23		T98	1		T99	1
valid_sources[0x49]	8574	1			T1	8		T97	1		T98	1
valid_sources[0x4a]	9214	1			T1	17		T97	2		T98	1
valid_sources[0x4b]	7644	1			T1	12		T95	1		T97	1
valid_sources[0x4c]	7345	1			T1	4		T98	1		T103	9
valid_sources[0x4d]	7709	1			T1	22		T91	19		T98	3
valid_sources[0x4e]	7614	1			T1	6		T97	1		T98	3
valid_sources[0x4f]	9775	1			T1	20		T129	4		T125	2
valid_sources[0x50]	7553	1			T97	3		T99	1		T125	2
valid_sources[0x51]	7399	1			T1	19		T98	2		T103	4
valid_sources[0x52]	9226	1			T1	4		T97	1		T98	2
valid_sources[0x53]	10817	1			T1	15		T91	18		T129	4
valid_sources[0x54]	7408	1			T1	14		T93	1		T98	1
valid_sources[0x55]	7374	1			T1	24		T97	1		T98	1
valid_sources[0x56]	7546	1			T1	13		T96	2		T99	1
valid_sources[0x57]	7461	1			T1	7		T95	1		T129	5
valid_sources[0x58]	11924	1			T1	14		T95	1		T129	3
valid_sources[0x59]	9310	1			T1	15		T93	1		T97	2
valid_sources[0x5a]	11238	1			T1	22		T97	2		T99	2
valid_sources[0x5b]	7619	1			T1	14		T96	3		T99	1
valid_sources[0x5c]	7694	1			T1	13		T97	2		T98	2
valid_sources[0x5d]	7334	1			T1	22		T97	1		T103	2
valid_sources[0x5e]	9406	1			T1	19		T91	18		T99	1
valid_sources[0x5f]	11023	1			T1	9		T91	17		T97	1
valid_sources[0x60]	8828	1			T1	10		T97	2		T98	1
valid_sources[0x61]	10730	1			T1	7		T93	1		T97	1
valid_sources[0x62]	7436	1			T1	13		T96	1		T97	2
valid_sources[0x63]	10024	1			T1	11		T129	1		T125	1
valid_sources[0x64]	7725	1			T1	10		T93	1		T97	1
valid_sources[0x65]	7459	1			T1	13		T93	1		T96	1
valid_sources[0x66]	7689	1			T1	24		T93	1		T98	2
valid_sources[0x67]	7546	1			T1	10		T94	1		T96	2
valid_sources[0x68]	8084	1			T1	8		T93	2		T97	1
valid_sources[0x69]	8654	1			T1	9		T91	37		T97	1
valid_sources[0x6a]	7567	1			T1	9		T98	1		T124	8
valid_sources[0x6b]	9163	1			T1	9		T95	1		T96	1
valid_sources[0x6c]	7133	1			T1	2		T98	1		T99	1
valid_sources[0x6d]	8892	1			T1	9		T91	19		T97	3
valid_sources[0x6e]	7794	1			T1	18		T97	1		T98	1
valid_sources[0x6f]	9517	1			T1	12		T97	2		T98	1
valid_sources[0x70]	7745	1			T1	6		T94	13		T97	3
valid_sources[0x71]	7162	1			T1	8		T98	1		T129	9
valid_sources[0x72]	7684	1			T1	10		T95	2		T98	2
valid_sources[0x73]	7650	1			T1	4		T98	1		T99	2
valid_sources[0x74]	7541	1			T1	6		T96	2		T97	1
valid_sources[0x75]	7575	1			T1	10		T93	1		T94	8
valid_sources[0x76]	7564	1			T1	7		T96	2		T97	1
valid_sources[0x77]	7150	1			T1	21		T97	1		T98	1
valid_sources[0x78]	7285	1			T1	15		T93	1		T97	2
valid_sources[0x79]	7617	1			T1	9		T93	1		T97	1
valid_sources[0x7a]	36375	1			T1	14		T93	1		T129	5
valid_sources[0x7b]	9787	1			T1	13		T95	1		T129	8
valid_sources[0x7c]	7458	1			T1	22		T97	1		T103	3
valid_sources[0x7d]	7884	1			T1	16		T92	2		T125	1
valid_sources[0x7e]	7470	1			T1	13		T96	8		T98	4
valid_sources[0x7f]	7489	1			T1	28		T125	2		T178	2
valid_sources[0x80]	8611	1			T1	12		T93	1		T99	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

914321

1

T1

1389

T91

22

T92

2

values[0x0]

all_enables

biggest_size

126932

1

T1

247

T91

305

T92

28

values[0x1]

all_enables

biggest_size

126372

1

T1

224

T91

306

T92

27