Unified Coverage Report :: Module :: prim_secded_inv_64_57_dec

Module : prim_secded_inv_64_57_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tap_tlul_host.u_rsp_chk.u_chk	6.90			6.90
tb.dut.u_reg_tap.u_chk.u_chk	17.24			17.24
tb.dut.u_reg.u_chk.u_chk	100.00			100.00

---

Module Instance : tb.dut.u_tap_tlul_host.u_rsp_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
6.90			6.90

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
6.90			6.90

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_rsp_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
17.24			17.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
17.24			17.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_64_57_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	232	232	100.00
Total Bits 0->1	116	116	100.00
Total Bits 1->0	116	116	100.00

Ports	4	4	100.00
Port Bits	232	232	100.00
Port Bits 0->1	116	116	100.00
Port Bits 1->0	116	116	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T1,*T91,*T92	Yes	T1,T91,T92	INPUT
data_i[56:43]	Unreachable	Unreachable		Unreachable		INPUT
data_i[63:57]	Yes	Yes	T1,T91,T92	Yes	T1,T91,T92	INPUT
data_o[56:0]	Yes	Yes	T1,T91,T92	Yes	T1,T91,T92	OUTPUT
syndrome_o[6:0]	Yes	Yes	T91,T93,T97	Yes	T91,T93,T97	OUTPUT
err_o[1:0]	Yes	Yes	T91,T93,T97	Yes	T91,T93,T97	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_tap_tlul_host.u_rsp_chk.u_chk

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	232	16	6.90
Total Bits 0->1	116	8	6.90
Total Bits 1->0	116	8	6.90

Ports	4	0	0.00
Port Bits	232	16	6.90
Port Bits 0->1	116	8	6.90
Port Bits 1->0	116	8	6.90

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[1:0]	No	No		No		INPUT
data_i[3:2]	Yes	Yes	T114,*T149,T150	Yes	T104,T105,T106	INPUT
data_i[42:4]	No	No		No		INPUT
data_i[56:43]	Unreachable	Unreachable		Unreachable		INPUT
data_i[58:57]	Yes	Yes	T104,T105,T106	Yes	T104,T105,T106	INPUT
data_i[60:59]	No	No		No		INPUT
data_i[62:61]	Yes	Yes	T114,T149,T150	Yes	T104,T105,T106	INPUT
data_i[63]	No	No		No		INPUT
data_o[1:0]	No	No		No		OUTPUT
data_o[3:2]	Yes	Yes	T114,*T149,T150	Yes	T104,T105,T106	OUTPUT
data_o[56:4]	No	No		No		OUTPUT
syndrome_o[6:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_reg_tap.u_chk.u_chk

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	232	40	17.24
Total Bits 0->1	116	20	17.24
Total Bits 1->0	116	20	17.24

Ports	4	0	0.00
Port Bits	232	40	17.24
Port Bits 0->1	116	20	17.24
Port Bits 1->0	116	20	17.24

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[5:0]	No	No		No		INPUT
data_i[6]	Yes	Yes	*T105,*T106,*T146	Yes	T104,T105,T106	INPUT
data_i[8:7]	No	No		No		INPUT
data_i[14:9]	Yes	Yes	T104,*T105,T106	Yes	T104,T105,T106	INPUT
data_i[42:15]	No	No		No		INPUT
data_i[56:43]	Unreachable	Unreachable		Unreachable		INPUT
data_i[57]	Yes	Yes	*T104,*T105,*T106	Yes	T104,T105,T106	INPUT
data_i[58]	No	No		No		INPUT
data_i[63:59]	Yes	Yes	T104,T105,T106	Yes	T105,T106,T146	INPUT
data_o[5:0]	No	No		No		OUTPUT
data_o[6]	Yes	Yes	*T105,*T106,*T146	Yes	T104,T105,T106	OUTPUT
data_o[8:7]	No	No		No		OUTPUT
data_o[14:9]	Yes	Yes	T104,*T105,T106	Yes	T104,T105,T106	OUTPUT
data_o[56:15]	No	No		No		OUTPUT
syndrome_o[6:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_reg.u_chk.u_chk

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	232	232	100.00
Total Bits 0->1	116	116	100.00
Total Bits 1->0	116	116	100.00

Ports	4	4	100.00
Port Bits	232	232	100.00
Port Bits 0->1	116	116	100.00
Port Bits 1->0	116	116	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T1,*T91,*T92	Yes	T1,T91,T92	INPUT
data_i[56:43]	Unreachable	Unreachable		Unreachable		INPUT
data_i[63:57]	Yes	Yes	T1,T91,T92	Yes	T1,T91,T92	INPUT
data_o[56:0]	Yes	Yes	T1,T91,T92	Yes	T1,T91,T92	OUTPUT
syndrome_o[6:0]	Yes	Yes	T91,T93,T97	Yes	T91,T93,T97	OUTPUT
err_o[1:0]	Yes	Yes	T91,T93,T97	Yes	T91,T93,T97	OUTPUT

*Tests covering at least one bit in the range