Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.13	100.00	83.10	98.16		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	71421315	14321	0	0
claim_transition_if_regwen_rd_A	71421315	1937	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71421315	14321	0	0
T91	10496	9	0	0
T94	2452	51	0	0
T103	5849	3	0	0
T111	10250	11	0	0
T112	11033	8	0	0
T114	0	87	0	0
T124	3914	735	0	0
T125	2750	531	0	0
T126	10234	827	0	0
T130	0	795	0	0
T146	29886	0	0	0
T154	2085	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71421315	1937	0	0
T93	1098	2	0	0
T96	1799	11	0	0
T111	10250	0	0	0
T112	11033	67	0	0
T114	5345	0	0	0
T129	4491	5	0	0
T130	10188	0	0	0
T133	0	55	0	0
T146	29886	0	0	0
T147	8286	0	0	0
T155	4672	60	0	0
T156	0	209	0	0
T157	0	3	0	0
T158	0	18	0	0
T159	0	7	0	0