Unified Coverage Report :: Module :: lc_ctrl_signal_decode

Module : lc_ctrl_signal_decode

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.69	98.41				91.67	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_signal_decode.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode	96.69	98.41				91.67	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.69	98.41				91.67	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.86	99.21				97.37	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.54	97.73	94.32		100.00	97.33	93.33	u_lc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_flop_keymgr_div	100.00	100.00				100.00
u_prim_lc_sender_cpu_en	100.00	100.00				100.00
u_prim_lc_sender_creator_seed_sw_rw_en	100.00	100.00				100.00
u_prim_lc_sender_dft_en	100.00	100.00				100.00
u_prim_lc_sender_escalate_en	100.00	100.00				100.00
u_prim_lc_sender_hw_debug_en	100.00	100.00				100.00
u_prim_lc_sender_iso_part_sw_rd_en	100.00	100.00				100.00
u_prim_lc_sender_iso_part_sw_wr_en	100.00	100.00				100.00
u_prim_lc_sender_keymgr_en	100.00	100.00				100.00
u_prim_lc_sender_nvm_debug_en	100.00	100.00				100.00
u_prim_lc_sender_owner_seed_sw_rw_en	100.00	100.00				100.00
u_prim_lc_sender_raw_test_rma	100.00	100.00				100.00
u_prim_lc_sender_seed_hw_rd_en	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : lc_ctrl_signal_decode

	Line No.	Total	Covered	Percent
TOTAL		63	62	98.41
ALWAYS	56	62	61	98.39
CONT_ASSIGN	292	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_signal_decode.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_signal_decode.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
66	1	1
68	1	1
70	1	1
72	1	1
75	1	1
88	1	1
89	1	1
100	1	1
112	1	1
113	1	1
114	1	1
115	1	1
116	1	1
117	1	1
118	1	1
125	1	1
126	1	1
127	1	1
128	1	1
129	1	1
130	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
145	1	1
148	1	1
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	1	1
164	1	1
167	1	1
172	1	1
173	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
193	0	1
200	1	1
207	1	1
292	1	1

---

Branch Coverage for Module : lc_ctrl_signal_decode

	Line No.	Total	Covered	Percent
Branches		12	11	91.67
CASE	72	12	11	91.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_signal_decode.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_signal_decode.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	72	case (fsm_state_i)
-2-:	88	if (lc_state_valid_i)
-3-:	89	case (lc_state_i)

Branches:

-1-	-2-	-3-	Status	Tests
ResetSt	-	-	Covered	T1,T2,T3
CASEITEM-2: IdleSt ClkMuxSt CntIncrSt CntProgSt TransCheckSt FlashRmaSt TokenHashSt TokenCheck0St TokenCheck1St TransProgSt	1	CASEITEM-1: LcStRaw LcStTestLocked0 LcStTestLocked1 LcStTestLocked2 LcStTestLocked3 LcStTestLocked4 LcStTestLocked5 LcStTestLocked6	Covered	T1,T2,T3
CASEITEM-2: IdleSt ClkMuxSt CntIncrSt CntProgSt TransCheckSt FlashRmaSt TokenHashSt TokenCheck0St TokenCheck1St TransProgSt	1	CASEITEM-2: LcStTestUnlocked0 LcStTestUnlocked1 LcStTestUnlocked2 LcStTestUnlocked3 LcStTestUnlocked4 LcStTestUnlocked5 LcStTestUnlocked6	Covered	T1,T2,T3
CASEITEM-2: IdleSt ClkMuxSt CntIncrSt CntProgSt TransCheckSt FlashRmaSt TokenHashSt TokenCheck0St TokenCheck1St TransProgSt	1	LcStTestUnlocked7	Covered	T1,T2,T3
CASEITEM-2: IdleSt ClkMuxSt CntIncrSt CntProgSt TransCheckSt FlashRmaSt TokenHashSt TokenCheck0St TokenCheck1St TransProgSt	1	LcStProd LcStProdEnd	Covered	T1,T2,T3
CASEITEM-2: IdleSt ClkMuxSt CntIncrSt CntProgSt TransCheckSt FlashRmaSt TokenHashSt TokenCheck0St TokenCheck1St TransProgSt	1	LcStDev	Covered	T1,T2,T3
CASEITEM-2: IdleSt ClkMuxSt CntIncrSt CntProgSt TransCheckSt FlashRmaSt TokenHashSt TokenCheck0St TokenCheck1St TransProgSt	1	LcStRma	Covered	T1,T2,T3
CASEITEM-2: IdleSt ClkMuxSt CntIncrSt CntProgSt TransCheckSt FlashRmaSt TokenHashSt TokenCheck0St TokenCheck1St TransProgSt	1	default	Covered	T3,T9,T13
CASEITEM-2: IdleSt ClkMuxSt CntIncrSt CntProgSt TransCheckSt FlashRmaSt TokenHashSt TokenCheck0St TokenCheck1St TransProgSt	0	-	Not Covered
PostTransSt	-	-	Covered	T1,T2,T9
ScrapSt EscalateSt InvalidSt	-	-	Covered	T2,T3,T9
default	-	-	Covered	T3,T13,T32

---

Assert Coverage for Module : lc_ctrl_signal_decode

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FsmInScrap_A	69433519	14275750	0	0
LcKeymgrDivUnique0_A	801	801	0	0
LcKeymgrDivUnique1_A	801	801	0	0
SignalsAreOffWhenNotEnabled_A	69433519	1375089	0	0
StateInScrap_A	69433519	4425	0	0

FsmInScrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69433519	14275750	0	0
T2	35565	1889	0	0
T3	121834	102784	0	0
T4	12354	0	0	0
T8	1143	0	0	0
T9	27973	12936	0	0
T10	5215	0	0	0
T11	58420	0	0	0
T12	1305	0	0	0
T13	22612	15202	0	0
T14	3555	0	0	0
T15	0	1251	0	0
T16	0	8142	0	0
T17	0	3175	0	0
T18	0	5793	0	0
T32	0	2151	0	0
T33	0	2174	0	0

LcKeymgrDivUnique0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	801	801	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

LcKeymgrDivUnique1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	801	801	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

SignalsAreOffWhenNotEnabled_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69433519	1375089	0	0
T1	37562	68	0	0
T2	35565	83	0	0
T3	121834	9857	0	0
T8	1143	1	0	0
T9	27973	62	0	0
T10	5215	7	0	0
T11	58420	63	0	0
T12	1305	1	0	0
T13	22612	1023	0	0
T14	3555	1	0	0

StateInScrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69433519	4425	0	0
T3	121834	23	0	0
T4	12354	0	0	0
T8	1143	0	0	0
T9	27973	1	0	0
T10	5215	0	0	0
T11	58420	0	0	0
T12	1305	0	0	0
T13	22612	22	0	0
T14	3555	0	0	0
T15	31445	0	0	0
T17	0	2	0	0
T20	0	37	0	0
T22	0	78	0	0
T32	0	3	0	0
T88	0	25	0	0
T89	0	34	0	0
T90	0	19	0	0