Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.38 97.29 95.97 91.98 100.00 96.13 98.48 94.82


Total test records in report: 986
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T757 /workspace/coverage/default/47.lc_ctrl_prog_failure.2589432664 Dec 31 12:36:59 PM PST 23 Dec 31 12:37:17 PM PST 23 431233433 ps
T758 /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1716655422 Dec 31 12:36:34 PM PST 23 Dec 31 12:36:51 PM PST 23 11123186 ps
T759 /workspace/coverage/default/14.lc_ctrl_sec_token_mux.3713431987 Dec 31 12:36:16 PM PST 23 Dec 31 12:36:48 PM PST 23 2065836704 ps
T760 /workspace/coverage/default/19.lc_ctrl_stress_all.2692130005 Dec 31 12:36:43 PM PST 23 Dec 31 12:39:25 PM PST 23 20029430558 ps
T761 /workspace/coverage/default/46.lc_ctrl_state_failure.2622580558 Dec 31 12:36:35 PM PST 23 Dec 31 12:37:13 PM PST 23 1274068424 ps
T762 /workspace/coverage/default/48.lc_ctrl_state_failure.3342793539 Dec 31 12:37:32 PM PST 23 Dec 31 12:38:03 PM PST 23 768752488 ps
T763 /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.342931522 Dec 31 12:36:46 PM PST 23 Dec 31 12:37:03 PM PST 23 15964872 ps
T764 /workspace/coverage/default/23.lc_ctrl_smoke.2208272637 Dec 31 12:36:31 PM PST 23 Dec 31 12:36:48 PM PST 23 215159650 ps
T765 /workspace/coverage/default/21.lc_ctrl_alert_test.784640351 Dec 31 12:36:24 PM PST 23 Dec 31 12:36:42 PM PST 23 20569443 ps
T766 /workspace/coverage/default/7.lc_ctrl_jtag_smoke.753621571 Dec 31 12:36:02 PM PST 23 Dec 31 12:36:24 PM PST 23 330855566 ps
T767 /workspace/coverage/default/5.lc_ctrl_jtag_priority.1424589249 Dec 31 12:35:42 PM PST 23 Dec 31 12:35:56 PM PST 23 2277753296 ps
T180 /workspace/coverage/default/0.lc_ctrl_claim_transition_if.572954313 Dec 31 12:35:41 PM PST 23 Dec 31 12:35:45 PM PST 23 10616573 ps
T768 /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.4142640839 Dec 31 12:36:11 PM PST 23 Dec 31 12:36:38 PM PST 23 278851004 ps
T769 /workspace/coverage/default/47.lc_ctrl_sec_token_digest.4261694104 Dec 31 12:37:16 PM PST 23 Dec 31 12:37:39 PM PST 23 2663322822 ps
T770 /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.1285138385 Dec 31 12:36:16 PM PST 23 Dec 31 12:36:48 PM PST 23 3294204582 ps
T771 /workspace/coverage/default/17.lc_ctrl_jtag_errors.350699556 Dec 31 12:36:08 PM PST 23 Dec 31 12:37:25 PM PST 23 8605846706 ps
T772 /workspace/coverage/default/6.lc_ctrl_jtag_access.107011377 Dec 31 12:35:46 PM PST 23 Dec 31 12:36:06 PM PST 23 3262674991 ps
T773 /workspace/coverage/default/34.lc_ctrl_state_post_trans.2002442317 Dec 31 12:36:46 PM PST 23 Dec 31 12:37:11 PM PST 23 294625200 ps
T774 /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.2402226642 Dec 31 12:36:11 PM PST 23 Dec 31 12:36:47 PM PST 23 914091732 ps
T775 /workspace/coverage/default/30.lc_ctrl_sec_token_mux.2620908176 Dec 31 12:36:34 PM PST 23 Dec 31 12:37:03 PM PST 23 1310589357 ps
T776 /workspace/coverage/default/13.lc_ctrl_sec_token_mux.2029766936 Dec 31 12:35:59 PM PST 23 Dec 31 12:36:25 PM PST 23 1205818564 ps
T777 /workspace/coverage/default/3.lc_ctrl_prog_failure.3635099323 Dec 31 12:36:04 PM PST 23 Dec 31 12:36:23 PM PST 23 631727064 ps
T778 /workspace/coverage/default/15.lc_ctrl_jtag_access.478341971 Dec 31 12:36:27 PM PST 23 Dec 31 12:36:47 PM PST 23 334154311 ps
T779 /workspace/coverage/default/36.lc_ctrl_prog_failure.2057081261 Dec 31 12:36:36 PM PST 23 Dec 31 12:36:55 PM PST 23 51014919 ps
T780 /workspace/coverage/default/11.lc_ctrl_jtag_access.1076618821 Dec 31 12:35:59 PM PST 23 Dec 31 12:36:26 PM PST 23 874766973 ps
T781 /workspace/coverage/default/46.lc_ctrl_state_post_trans.1870892731 Dec 31 12:37:17 PM PST 23 Dec 31 12:37:35 PM PST 23 282921114 ps
T782 /workspace/coverage/default/39.lc_ctrl_alert_test.955376161 Dec 31 12:37:03 PM PST 23 Dec 31 12:37:19 PM PST 23 39506614 ps
T783 /workspace/coverage/default/7.lc_ctrl_state_post_trans.97117254 Dec 31 12:36:18 PM PST 23 Dec 31 12:36:42 PM PST 23 323978704 ps
T784 /workspace/coverage/default/44.lc_ctrl_security_escalation.1151655043 Dec 31 12:36:58 PM PST 23 Dec 31 12:37:22 PM PST 23 452075184 ps
T785 /workspace/coverage/default/0.lc_ctrl_state_failure.2311826899 Dec 31 12:35:50 PM PST 23 Dec 31 12:36:29 PM PST 23 883108102 ps
T786 /workspace/coverage/default/20.lc_ctrl_errors.3670656216 Dec 31 12:36:58 PM PST 23 Dec 31 12:37:25 PM PST 23 1671194769 ps
T787 /workspace/coverage/default/18.lc_ctrl_jtag_smoke.1601818888 Dec 31 12:36:26 PM PST 23 Dec 31 12:36:58 PM PST 23 2507434187 ps
T788 /workspace/coverage/default/47.lc_ctrl_sec_token_mux.2387299619 Dec 31 12:37:23 PM PST 23 Dec 31 12:37:44 PM PST 23 390196345 ps
T789 /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.93727046 Dec 31 12:36:02 PM PST 23 Dec 31 12:36:20 PM PST 23 14190141 ps
T790 /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.2533293529 Dec 31 12:36:34 PM PST 23 Dec 31 12:37:04 PM PST 23 921185549 ps
T791 /workspace/coverage/default/31.lc_ctrl_prog_failure.725677567 Dec 31 12:36:32 PM PST 23 Dec 31 12:36:48 PM PST 23 16056043 ps
T792 /workspace/coverage/default/6.lc_ctrl_regwen_during_op.162743009 Dec 31 12:35:54 PM PST 23 Dec 31 12:36:18 PM PST 23 374600265 ps
T793 /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.2680553746 Dec 31 12:36:25 PM PST 23 Dec 31 12:36:56 PM PST 23 524737180 ps
T794 /workspace/coverage/default/18.lc_ctrl_sec_token_digest.628900675 Dec 31 12:36:18 PM PST 23 Dec 31 12:36:47 PM PST 23 484173079 ps
T795 /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.3613155022 Dec 31 12:35:46 PM PST 23 Dec 31 12:36:05 PM PST 23 389903822 ps
T796 /workspace/coverage/default/45.lc_ctrl_state_failure.1568717836 Dec 31 12:37:03 PM PST 23 Dec 31 12:37:39 PM PST 23 259156993 ps
T797 /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2425979801 Dec 31 12:36:08 PM PST 23 Dec 31 12:36:43 PM PST 23 1258469520 ps
T798 /workspace/coverage/default/21.lc_ctrl_sec_token_digest.4057827998 Dec 31 12:36:14 PM PST 23 Dec 31 12:36:44 PM PST 23 233247576 ps
T799 /workspace/coverage/default/13.lc_ctrl_state_failure.1495661354 Dec 31 12:36:06 PM PST 23 Dec 31 12:36:50 PM PST 23 324486819 ps
T800 /workspace/coverage/default/17.lc_ctrl_alert_test.2391710108 Dec 31 12:36:27 PM PST 23 Dec 31 12:36:44 PM PST 23 17163198 ps
T801 /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.4071984798 Dec 31 12:37:07 PM PST 23 Dec 31 12:38:27 PM PST 23 74007118936 ps
T802 /workspace/coverage/default/19.lc_ctrl_prog_failure.824044937 Dec 31 12:36:27 PM PST 23 Dec 31 12:36:46 PM PST 23 381782506 ps
T803 /workspace/coverage/default/16.lc_ctrl_sec_token_digest.1285482554 Dec 31 12:36:25 PM PST 23 Dec 31 12:36:57 PM PST 23 349826687 ps
T804 /workspace/coverage/default/0.lc_ctrl_regwen_during_op.555079094 Dec 31 12:35:41 PM PST 23 Dec 31 12:35:54 PM PST 23 250757543 ps
T805 /workspace/coverage/default/38.lc_ctrl_prog_failure.3612581528 Dec 31 12:36:55 PM PST 23 Dec 31 12:37:12 PM PST 23 186720496 ps
T806 /workspace/coverage/default/24.lc_ctrl_stress_all.3545217766 Dec 31 12:36:47 PM PST 23 Dec 31 12:39:12 PM PST 23 9664464809 ps
T807 /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.1780877219 Dec 31 12:36:01 PM PST 23 Dec 31 12:37:22 PM PST 23 7453334952 ps
T808 /workspace/coverage/default/22.lc_ctrl_errors.3408608060 Dec 31 12:36:38 PM PST 23 Dec 31 12:37:08 PM PST 23 1770065695 ps
T809 /workspace/coverage/default/29.lc_ctrl_sec_mubi.3359650808 Dec 31 12:36:55 PM PST 23 Dec 31 12:37:22 PM PST 23 282849553 ps
T810 /workspace/coverage/default/27.lc_ctrl_stress_all.3632430475 Dec 31 12:36:42 PM PST 23 Dec 31 12:41:13 PM PST 23 18398615861 ps
T85 /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1372622794 Dec 31 12:35:49 PM PST 23 Dec 31 12:36:13 PM PST 23 478814087 ps
T811 /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1916833677 Dec 31 12:36:48 PM PST 23 Dec 31 12:37:05 PM PST 23 33863432 ps
T812 /workspace/coverage/default/43.lc_ctrl_jtag_access.2127587909 Dec 31 12:37:17 PM PST 23 Dec 31 12:37:31 PM PST 23 143880411 ps
T813 /workspace/coverage/default/13.lc_ctrl_stress_all.2562934514 Dec 31 12:36:17 PM PST 23 Dec 31 12:40:13 PM PST 23 19030515227 ps
T814 /workspace/coverage/default/1.lc_ctrl_jtag_priority.2790119234 Dec 31 12:35:45 PM PST 23 Dec 31 12:36:01 PM PST 23 808028601 ps
T815 /workspace/coverage/default/36.lc_ctrl_alert_test.3596669217 Dec 31 12:36:59 PM PST 23 Dec 31 12:37:15 PM PST 23 122706818 ps
T816 /workspace/coverage/default/33.lc_ctrl_errors.401658936 Dec 31 12:36:42 PM PST 23 Dec 31 12:37:13 PM PST 23 216447318 ps
T817 /workspace/coverage/default/25.lc_ctrl_stress_all.99233220 Dec 31 12:36:44 PM PST 23 Dec 31 12:41:42 PM PST 23 18620548148 ps
T818 /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2721041426 Dec 31 12:36:42 PM PST 23 Dec 31 12:37:00 PM PST 23 27624514 ps
T819 /workspace/coverage/default/22.lc_ctrl_smoke.1852852521 Dec 31 12:36:12 PM PST 23 Dec 31 12:36:33 PM PST 23 15942858 ps
T820 /workspace/coverage/default/9.lc_ctrl_stress_all.3718767996 Dec 31 12:35:59 PM PST 23 Dec 31 12:36:32 PM PST 23 4758717325 ps
T821 /workspace/coverage/default/6.lc_ctrl_sec_token_mux.4210888245 Dec 31 12:35:49 PM PST 23 Dec 31 12:36:15 PM PST 23 2660216007 ps
T822 /workspace/coverage/default/10.lc_ctrl_security_escalation.855358233 Dec 31 12:36:01 PM PST 23 Dec 31 12:36:28 PM PST 23 482948573 ps
T823 /workspace/coverage/default/37.lc_ctrl_state_post_trans.697690886 Dec 31 12:36:54 PM PST 23 Dec 31 12:37:12 PM PST 23 117353126 ps
T824 /workspace/coverage/default/20.lc_ctrl_state_post_trans.1294702161 Dec 31 12:36:26 PM PST 23 Dec 31 12:36:49 PM PST 23 608856018 ps
T825 /workspace/coverage/default/26.lc_ctrl_state_failure.1645032429 Dec 31 12:36:41 PM PST 23 Dec 31 12:37:29 PM PST 23 685301652 ps
T826 /workspace/coverage/default/2.lc_ctrl_state_post_trans.2314832291 Dec 31 12:36:01 PM PST 23 Dec 31 12:36:24 PM PST 23 71163615 ps
T827 /workspace/coverage/default/35.lc_ctrl_jtag_access.2945145605 Dec 31 12:36:41 PM PST 23 Dec 31 12:37:08 PM PST 23 1152962781 ps
T828 /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3138931282 Dec 31 12:36:40 PM PST 23 Dec 31 12:37:12 PM PST 23 1584149812 ps
T829 /workspace/coverage/default/3.lc_ctrl_security_escalation.3825150794 Dec 31 12:35:57 PM PST 23 Dec 31 12:36:25 PM PST 23 3300023487 ps
T830 /workspace/coverage/default/49.lc_ctrl_smoke.3709105525 Dec 31 12:37:16 PM PST 23 Dec 31 12:37:33 PM PST 23 85080554 ps
T831 /workspace/coverage/default/2.lc_ctrl_jtag_errors.3033660191 Dec 31 12:35:40 PM PST 23 Dec 31 12:36:09 PM PST 23 1940094238 ps
T832 /workspace/coverage/default/28.lc_ctrl_stress_all.2361611909 Dec 31 12:36:34 PM PST 23 Dec 31 12:38:48 PM PST 23 2858696731 ps
T833 /workspace/coverage/default/2.lc_ctrl_jtag_priority.2649813886 Dec 31 12:35:42 PM PST 23 Dec 31 12:36:46 PM PST 23 2843521773 ps
T834 /workspace/coverage/default/10.lc_ctrl_jtag_smoke.49586651 Dec 31 12:35:58 PM PST 23 Dec 31 12:36:21 PM PST 23 289793609 ps
T835 /workspace/coverage/default/29.lc_ctrl_security_escalation.4198051305 Dec 31 12:37:11 PM PST 23 Dec 31 12:37:31 PM PST 23 993821386 ps
T836 /workspace/coverage/default/44.lc_ctrl_sec_token_mux.3145725492 Dec 31 12:37:09 PM PST 23 Dec 31 12:37:30 PM PST 23 488704659 ps
T837 /workspace/coverage/default/45.lc_ctrl_stress_all.3510898180 Dec 31 12:37:31 PM PST 23 Dec 31 12:39:45 PM PST 23 37630228836 ps
T838 /workspace/coverage/default/8.lc_ctrl_sec_token_mux.202824085 Dec 31 12:36:10 PM PST 23 Dec 31 12:36:35 PM PST 23 329162573 ps
T839 /workspace/coverage/default/15.lc_ctrl_smoke.1885914213 Dec 31 12:36:03 PM PST 23 Dec 31 12:36:22 PM PST 23 120937696 ps
T840 /workspace/coverage/default/4.lc_ctrl_jtag_errors.2879587350 Dec 31 12:36:01 PM PST 23 Dec 31 12:36:44 PM PST 23 3081790989 ps
T841 /workspace/coverage/default/9.lc_ctrl_security_escalation.4289482712 Dec 31 12:35:51 PM PST 23 Dec 31 12:36:09 PM PST 23 3583018422 ps
T842 /workspace/coverage/default/5.lc_ctrl_sec_mubi.1771100149 Dec 31 12:36:08 PM PST 23 Dec 31 12:36:44 PM PST 23 2907429228 ps
T843 /workspace/coverage/default/34.lc_ctrl_jtag_access.1400880186 Dec 31 12:37:08 PM PST 23 Dec 31 12:37:23 PM PST 23 109152246 ps
T844 /workspace/coverage/default/1.lc_ctrl_errors.1216460824 Dec 31 12:35:54 PM PST 23 Dec 31 12:36:21 PM PST 23 494050068 ps
T845 /workspace/coverage/default/46.lc_ctrl_sec_token_digest.2289149217 Dec 31 12:37:21 PM PST 23 Dec 31 12:37:45 PM PST 23 422891854 ps
T846 /workspace/coverage/default/7.lc_ctrl_state_failure.2108929383 Dec 31 12:36:12 PM PST 23 Dec 31 12:36:55 PM PST 23 926839803 ps
T847 /workspace/coverage/default/44.lc_ctrl_state_post_trans.1746484739 Dec 31 12:37:13 PM PST 23 Dec 31 12:37:33 PM PST 23 329805636 ps
T848 /workspace/coverage/default/8.lc_ctrl_smoke.1517479806 Dec 31 12:35:58 PM PST 23 Dec 31 12:36:18 PM PST 23 34633430 ps
T849 /workspace/coverage/default/35.lc_ctrl_prog_failure.1771044939 Dec 31 12:36:45 PM PST 23 Dec 31 12:37:04 PM PST 23 239646250 ps
T850 /workspace/coverage/default/27.lc_ctrl_sec_token_digest.3905460736 Dec 31 12:36:39 PM PST 23 Dec 31 12:37:05 PM PST 23 289725065 ps
T851 /workspace/coverage/default/42.lc_ctrl_stress_all.2604320057 Dec 31 12:36:41 PM PST 23 Dec 31 12:38:20 PM PST 23 20088727562 ps
T852 /workspace/coverage/default/24.lc_ctrl_sec_token_digest.2522926879 Dec 31 12:36:52 PM PST 23 Dec 31 12:37:24 PM PST 23 477772547 ps
T853 /workspace/coverage/default/41.lc_ctrl_errors.1141860481 Dec 31 12:37:09 PM PST 23 Dec 31 12:37:32 PM PST 23 1426778047 ps
T77 /workspace/coverage/default/5.lc_ctrl_alert_test.3464899592 Dec 31 12:36:06 PM PST 23 Dec 31 12:36:23 PM PST 23 60096112 ps
T854 /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1286592759 Dec 31 12:36:36 PM PST 23 Dec 31 12:37:10 PM PST 23 5344717308 ps
T855 /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.1080700668 Dec 31 12:36:00 PM PST 23 Dec 31 12:36:32 PM PST 23 2699877554 ps
T856 /workspace/coverage/default/42.lc_ctrl_errors.3026577699 Dec 31 12:36:48 PM PST 23 Dec 31 12:37:13 PM PST 23 1157896692 ps
T857 /workspace/coverage/default/19.lc_ctrl_sec_token_digest.926111272 Dec 31 12:36:09 PM PST 23 Dec 31 12:36:44 PM PST 23 7682880720 ps
T858 /workspace/coverage/default/35.lc_ctrl_sec_mubi.61375236 Dec 31 12:36:39 PM PST 23 Dec 31 12:37:11 PM PST 23 422330442 ps
T859 /workspace/coverage/default/42.lc_ctrl_state_post_trans.3478626213 Dec 31 12:36:47 PM PST 23 Dec 31 12:37:06 PM PST 23 383671309 ps
T860 /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.955127720 Dec 31 12:36:40 PM PST 23 Dec 31 12:37:36 PM PST 23 1215617015 ps
T861 /workspace/coverage/default/22.lc_ctrl_security_escalation.2426346676 Dec 31 12:36:30 PM PST 23 Dec 31 12:37:00 PM PST 23 423384211 ps
T862 /workspace/coverage/default/4.lc_ctrl_state_failure.556364822 Dec 31 12:35:44 PM PST 23 Dec 31 12:36:17 PM PST 23 237685267 ps
T863 /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3277870570 Dec 31 12:36:02 PM PST 23 Dec 31 12:36:28 PM PST 23 884073284 ps
T864 /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.3618812831 Dec 31 12:36:08 PM PST 23 Dec 31 12:36:36 PM PST 23 1380490886 ps
T865 /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.552698792 Dec 31 12:36:00 PM PST 23 Dec 31 12:36:27 PM PST 23 12881921 ps
T866 /workspace/coverage/default/20.lc_ctrl_state_failure.466165073 Dec 31 12:36:26 PM PST 23 Dec 31 12:37:11 PM PST 23 1406712975 ps
T867 /workspace/coverage/default/27.lc_ctrl_errors.195259153 Dec 31 12:36:39 PM PST 23 Dec 31 12:37:07 PM PST 23 1344070445 ps
T868 /workspace/coverage/default/3.lc_ctrl_smoke.1558366177 Dec 31 12:36:11 PM PST 23 Dec 31 12:36:36 PM PST 23 88708288 ps
T869 /workspace/coverage/default/46.lc_ctrl_sec_mubi.1454311946 Dec 31 12:37:01 PM PST 23 Dec 31 12:37:25 PM PST 23 292235642 ps
T870 /workspace/coverage/default/12.lc_ctrl_jtag_errors.4166284235 Dec 31 12:36:11 PM PST 23 Dec 31 12:36:55 PM PST 23 884608689 ps
T871 /workspace/coverage/default/4.lc_ctrl_sec_token_digest.3006387766 Dec 31 12:35:46 PM PST 23 Dec 31 12:36:05 PM PST 23 1867476910 ps
T872 /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.1765487839 Dec 31 12:36:39 PM PST 23 Dec 31 12:36:58 PM PST 23 12783302 ps
T873 /workspace/coverage/default/1.lc_ctrl_jtag_access.2300668306 Dec 31 12:35:45 PM PST 23 Dec 31 12:35:54 PM PST 23 34309744 ps
T874 /workspace/coverage/default/3.lc_ctrl_jtag_errors.865240634 Dec 31 12:35:57 PM PST 23 Dec 31 12:37:55 PM PST 23 15731632922 ps
T875 /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.192741285 Dec 31 12:36:12 PM PST 23 Dec 31 12:36:37 PM PST 23 173437172 ps
T876 /workspace/coverage/default/11.lc_ctrl_sec_mubi.920362257 Dec 31 12:35:58 PM PST 23 Dec 31 12:36:33 PM PST 23 1690614102 ps
T877 /workspace/coverage/default/11.lc_ctrl_sec_token_digest.880274550 Dec 31 12:36:02 PM PST 23 Dec 31 12:36:44 PM PST 23 2281991833 ps
T878 /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.2172041698 Dec 31 12:35:51 PM PST 23 Dec 31 12:36:09 PM PST 23 6518191398 ps
T879 /workspace/coverage/default/17.lc_ctrl_jtag_smoke.722858386 Dec 31 12:36:33 PM PST 23 Dec 31 12:36:54 PM PST 23 139850710 ps
T880 /workspace/coverage/default/43.lc_ctrl_sec_mubi.3141777941 Dec 31 12:37:03 PM PST 23 Dec 31 12:37:30 PM PST 23 320398146 ps
T881 /workspace/coverage/default/19.lc_ctrl_state_failure.3993252394 Dec 31 12:36:08 PM PST 23 Dec 31 12:36:42 PM PST 23 1216941304 ps
T882 /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.262872839 Dec 31 12:35:58 PM PST 23 Dec 31 12:36:17 PM PST 23 94353571 ps
T883 /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.2468204246 Dec 31 12:36:48 PM PST 23 Dec 31 12:37:14 PM PST 23 1553243699 ps
T884 /workspace/coverage/default/5.lc_ctrl_jtag_smoke.410166255 Dec 31 12:35:58 PM PST 23 Dec 31 12:36:21 PM PST 23 342518581 ps
T885 /workspace/coverage/default/42.lc_ctrl_alert_test.2662812716 Dec 31 12:37:04 PM PST 23 Dec 31 12:37:19 PM PST 23 62060839 ps
T886 /workspace/coverage/default/14.lc_ctrl_state_post_trans.127086428 Dec 31 12:36:22 PM PST 23 Dec 31 12:36:47 PM PST 23 83895561 ps
T887 /workspace/coverage/default/1.lc_ctrl_sec_mubi.283466418 Dec 31 12:35:31 PM PST 23 Dec 31 12:35:43 PM PST 23 296008652 ps
T888 /workspace/coverage/default/45.lc_ctrl_security_escalation.1890062999 Dec 31 12:36:46 PM PST 23 Dec 31 12:37:08 PM PST 23 815807136 ps
T889 /workspace/coverage/default/6.lc_ctrl_smoke.1329627567 Dec 31 12:36:01 PM PST 23 Dec 31 12:36:22 PM PST 23 126759728 ps
T890 /workspace/coverage/default/13.lc_ctrl_jtag_errors.3456363798 Dec 31 12:35:58 PM PST 23 Dec 31 12:36:51 PM PST 23 1182463560 ps
T891 /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2390005564 Dec 31 12:36:19 PM PST 23 Dec 31 12:36:40 PM PST 23 13820502 ps
T892 /workspace/coverage/default/22.lc_ctrl_alert_test.151813652 Dec 31 12:36:27 PM PST 23 Dec 31 12:36:44 PM PST 23 46077932 ps
T893 /workspace/coverage/default/10.lc_ctrl_sec_token_mux.2975609426 Dec 31 12:36:02 PM PST 23 Dec 31 12:36:30 PM PST 23 283228403 ps
T894 /workspace/coverage/default/40.lc_ctrl_jtag_access.1246288668 Dec 31 12:37:04 PM PST 23 Dec 31 12:37:23 PM PST 23 424598632 ps
T895 /workspace/coverage/default/3.lc_ctrl_jtag_smoke.967166627 Dec 31 12:36:10 PM PST 23 Dec 31 12:36:32 PM PST 23 3019594091 ps
T896 /workspace/coverage/default/3.lc_ctrl_errors.2812904316 Dec 31 12:35:58 PM PST 23 Dec 31 12:36:29 PM PST 23 1616158007 ps
T897 /workspace/coverage/default/43.lc_ctrl_prog_failure.3703936997 Dec 31 12:36:52 PM PST 23 Dec 31 12:37:10 PM PST 23 480493342 ps
T898 /workspace/coverage/default/37.lc_ctrl_stress_all.3460755576 Dec 31 12:37:19 PM PST 23 Dec 31 12:42:48 PM PST 23 20183098454 ps
T86 /workspace/coverage/default/28.lc_ctrl_smoke.3279881713 Dec 31 12:36:53 PM PST 23 Dec 31 12:37:10 PM PST 23 32163678 ps
T899 /workspace/coverage/default/49.lc_ctrl_alert_test.4119970694 Dec 31 12:37:07 PM PST 23 Dec 31 12:37:21 PM PST 23 26103314 ps
T900 /workspace/coverage/default/18.lc_ctrl_stress_all.495794412 Dec 31 12:36:16 PM PST 23 Dec 31 12:38:27 PM PST 23 9138609339 ps
T901 /workspace/coverage/default/20.lc_ctrl_sec_token_digest.46306000 Dec 31 12:36:27 PM PST 23 Dec 31 12:36:53 PM PST 23 1230837850 ps
T902 /workspace/coverage/default/20.lc_ctrl_smoke.553591893 Dec 31 12:36:44 PM PST 23 Dec 31 12:37:06 PM PST 23 346930234 ps
T903 /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.2326055416 Dec 31 12:36:16 PM PST 23 Dec 31 12:36:44 PM PST 23 2402163490 ps
T904 /workspace/coverage/default/2.lc_ctrl_sec_token_digest.2008567447 Dec 31 12:35:59 PM PST 23 Dec 31 12:36:40 PM PST 23 554033013 ps
T905 /workspace/coverage/default/29.lc_ctrl_sec_token_digest.632296964 Dec 31 12:36:25 PM PST 23 Dec 31 12:36:52 PM PST 23 253056010 ps
T906 /workspace/coverage/default/14.lc_ctrl_stress_all.3809580597 Dec 31 12:36:14 PM PST 23 Dec 31 12:39:53 PM PST 23 37895542802 ps
T907 /workspace/coverage/default/31.lc_ctrl_errors.486939883 Dec 31 12:36:32 PM PST 23 Dec 31 12:37:04 PM PST 23 806660580 ps
T908 /workspace/coverage/default/35.lc_ctrl_sec_token_digest.3346406999 Dec 31 12:37:02 PM PST 23 Dec 31 12:37:25 PM PST 23 233097755 ps
T909 /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3989697448 Dec 31 12:36:53 PM PST 23 Dec 31 12:37:08 PM PST 23 11868036 ps
T910 /workspace/coverage/default/24.lc_ctrl_sec_token_mux.2548547253 Dec 31 12:36:29 PM PST 23 Dec 31 12:36:52 PM PST 23 1904850060 ps
T911 /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2492344363 Dec 31 12:36:32 PM PST 23 Dec 31 12:36:48 PM PST 23 25276014 ps
T912 /workspace/coverage/default/10.lc_ctrl_prog_failure.211876054 Dec 31 12:36:04 PM PST 23 Dec 31 12:36:22 PM PST 23 66909788 ps
T913 /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1851852770 Dec 31 12:36:58 PM PST 23 Dec 31 12:37:14 PM PST 23 11600351 ps
T914 /workspace/coverage/default/41.lc_ctrl_sec_token_digest.2703502177 Dec 31 12:36:53 PM PST 23 Dec 31 12:37:19 PM PST 23 270476227 ps
T915 /workspace/coverage/default/3.lc_ctrl_stress_all.766675420 Dec 31 12:35:36 PM PST 23 Dec 31 12:36:47 PM PST 23 2906828197 ps
T916 /workspace/coverage/default/5.lc_ctrl_stress_all.2703285981 Dec 31 12:36:01 PM PST 23 Dec 31 12:38:57 PM PST 23 9230688716 ps
T917 /workspace/coverage/default/27.lc_ctrl_jtag_access.1041284589 Dec 31 12:36:34 PM PST 23 Dec 31 12:37:07 PM PST 23 762886364 ps
T183 /workspace/coverage/default/9.lc_ctrl_claim_transition_if.65102576 Dec 31 12:35:55 PM PST 23 Dec 31 12:36:11 PM PST 23 12923221 ps
T918 /workspace/coverage/default/28.lc_ctrl_errors.2805496353 Dec 31 12:36:58 PM PST 23 Dec 31 12:37:27 PM PST 23 916405451 ps
T919 /workspace/coverage/default/33.lc_ctrl_alert_test.2798831376 Dec 31 12:36:34 PM PST 23 Dec 31 12:36:51 PM PST 23 24594914 ps
T920 /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.2745286628 Dec 31 12:36:11 PM PST 23 Dec 31 12:36:33 PM PST 23 633243590 ps
T921 /workspace/coverage/default/24.lc_ctrl_state_failure.3089345160 Dec 31 12:36:49 PM PST 23 Dec 31 12:37:43 PM PST 23 336985692 ps
T922 /workspace/coverage/default/29.lc_ctrl_smoke.3468265830 Dec 31 12:36:37 PM PST 23 Dec 31 12:36:56 PM PST 23 126282374 ps
T923 /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.1261685006 Dec 31 12:37:18 PM PST 23 Dec 31 12:37:30 PM PST 23 12039230 ps
T924 /workspace/coverage/default/32.lc_ctrl_stress_all.3119439798 Dec 31 12:36:59 PM PST 23 Dec 31 12:43:22 PM PST 23 15118557336 ps
T925 /workspace/coverage/default/46.lc_ctrl_alert_test.3394864863 Dec 31 12:37:11 PM PST 23 Dec 31 12:37:25 PM PST 23 23874414 ps
T926 /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.1083380860 Dec 31 12:35:54 PM PST 23 Dec 31 12:36:16 PM PST 23 1073229961 ps
T927 /workspace/coverage/default/31.lc_ctrl_smoke.684686788 Dec 31 12:36:49 PM PST 23 Dec 31 12:37:07 PM PST 23 155597885 ps
T928 /workspace/coverage/default/34.lc_ctrl_state_failure.1813337440 Dec 31 12:36:42 PM PST 23 Dec 31 12:37:27 PM PST 23 571785856 ps
T929 /workspace/coverage/default/9.lc_ctrl_jtag_errors.886652730 Dec 31 12:35:49 PM PST 23 Dec 31 12:36:31 PM PST 23 2781875124 ps
T930 /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1599428205 Dec 31 12:37:08 PM PST 23 Dec 31 12:37:22 PM PST 23 10825703 ps
T931 /workspace/coverage/default/7.lc_ctrl_sec_mubi.2337250512 Dec 31 12:35:57 PM PST 23 Dec 31 12:36:28 PM PST 23 1822661824 ps
T54 /workspace/coverage/default/36.lc_ctrl_errors.1525414463 Dec 31 12:36:54 PM PST 23 Dec 31 12:37:22 PM PST 23 1035906747 ps
T932 /workspace/coverage/default/12.lc_ctrl_sec_token_digest.2346384232 Dec 31 12:36:20 PM PST 23 Dec 31 12:36:47 PM PST 23 1594635435 ps
T933 /workspace/coverage/default/24.lc_ctrl_smoke.2136361278 Dec 31 12:36:36 PM PST 23 Dec 31 12:36:55 PM PST 23 298508529 ps
T934 /workspace/coverage/default/0.lc_ctrl_jtag_priority.2411435820 Dec 31 12:35:30 PM PST 23 Dec 31 12:35:34 PM PST 23 291893274 ps
T935 /workspace/coverage/default/24.lc_ctrl_alert_test.1085524846 Dec 31 12:36:36 PM PST 23 Dec 31 12:36:53 PM PST 23 28764091 ps
T936 /workspace/coverage/default/2.lc_ctrl_sec_mubi.3075579572 Dec 31 12:36:00 PM PST 23 Dec 31 12:36:33 PM PST 23 3112261883 ps
T937 /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.3237285989 Dec 31 12:36:09 PM PST 23 Dec 31 12:36:46 PM PST 23 2091763768 ps
T938 /workspace/coverage/default/6.lc_ctrl_security_escalation.1342364251 Dec 31 12:36:01 PM PST 23 Dec 31 12:36:29 PM PST 23 225962547 ps
T939 /workspace/coverage/default/11.lc_ctrl_errors.3071015943 Dec 31 12:36:06 PM PST 23 Dec 31 12:36:40 PM PST 23 349758435 ps
T940 /workspace/coverage/default/35.lc_ctrl_security_escalation.2419185998 Dec 31 12:36:30 PM PST 23 Dec 31 12:36:54 PM PST 23 357214234 ps
T941 /workspace/coverage/default/45.lc_ctrl_jtag_access.4037068404 Dec 31 12:36:46 PM PST 23 Dec 31 12:37:06 PM PST 23 1538985537 ps
T942 /workspace/coverage/default/43.lc_ctrl_errors.2745966037 Dec 31 12:37:06 PM PST 23 Dec 31 12:37:26 PM PST 23 216862723 ps
T943 /workspace/coverage/default/38.lc_ctrl_stress_all.1571792622 Dec 31 12:36:58 PM PST 23 Dec 31 12:38:27 PM PST 23 1849517703 ps
T944 /workspace/coverage/default/26.lc_ctrl_security_escalation.213678023 Dec 31 12:36:39 PM PST 23 Dec 31 12:37:06 PM PST 23 433878641 ps
T945 /workspace/coverage/default/21.lc_ctrl_errors.3685093113 Dec 31 12:36:25 PM PST 23 Dec 31 12:36:53 PM PST 23 1361048603 ps
T946 /workspace/coverage/default/39.lc_ctrl_prog_failure.1349938276 Dec 31 12:36:53 PM PST 23 Dec 31 12:37:12 PM PST 23 341089368 ps
T947 /workspace/coverage/default/43.lc_ctrl_alert_test.452610405 Dec 31 12:37:00 PM PST 23 Dec 31 12:37:16 PM PST 23 32164870 ps
T948 /workspace/coverage/default/47.lc_ctrl_errors.3668332788 Dec 31 12:37:35 PM PST 23 Dec 31 12:37:47 PM PST 23 288798558 ps
T949 /workspace/coverage/default/5.lc_ctrl_security_escalation.3978225719 Dec 31 12:35:42 PM PST 23 Dec 31 12:35:58 PM PST 23 2391359031 ps
T950 /workspace/coverage/default/9.lc_ctrl_jtag_priority.2158954740 Dec 31 12:35:56 PM PST 23 Dec 31 12:36:15 PM PST 23 161529270 ps
T951 /workspace/coverage/default/9.lc_ctrl_state_post_trans.2763140925 Dec 31 12:35:57 PM PST 23 Dec 31 12:36:24 PM PST 23 266038958 ps
T952 /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2759095689 Dec 31 12:36:05 PM PST 23 Dec 31 12:36:22 PM PST 23 92958316 ps
T953 /workspace/coverage/default/32.lc_ctrl_smoke.750111289 Dec 31 12:36:54 PM PST 23 Dec 31 12:37:10 PM PST 23 29595236 ps
T954 /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.776445234 Dec 31 12:36:48 PM PST 23 Dec 31 12:37:21 PM PST 23 13085448746 ps
T955 /workspace/coverage/default/3.lc_ctrl_alert_test.3937365118 Dec 31 12:35:39 PM PST 23 Dec 31 12:35:43 PM PST 23 31915709 ps
T956 /workspace/coverage/default/27.lc_ctrl_sec_token_mux.4261568745 Dec 31 12:36:57 PM PST 23 Dec 31 12:37:20 PM PST 23 469885992 ps
T957 /workspace/coverage/default/6.lc_ctrl_sec_token_digest.1164191530 Dec 31 12:36:08 PM PST 23 Dec 31 12:36:39 PM PST 23 345146364 ps
T958 /workspace/coverage/default/44.lc_ctrl_jtag_access.1742452969 Dec 31 12:37:04 PM PST 23 Dec 31 12:37:20 PM PST 23 286679939 ps
T959 /workspace/coverage/default/13.lc_ctrl_sec_token_digest.4062954005 Dec 31 12:36:16 PM PST 23 Dec 31 12:36:51 PM PST 23 694816754 ps
T960 /workspace/coverage/default/11.lc_ctrl_security_escalation.1075684558 Dec 31 12:36:00 PM PST 23 Dec 31 12:36:37 PM PST 23 240274776 ps
T961 /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2330956601 Dec 31 12:37:14 PM PST 23 Dec 31 12:37:36 PM PST 23 1551262731 ps
T962 /workspace/coverage/default/0.lc_ctrl_jtag_errors.3071814925 Dec 31 12:35:46 PM PST 23 Dec 31 12:36:47 PM PST 23 1982663335 ps
T963 /workspace/coverage/default/3.lc_ctrl_sec_token_digest.3282144113 Dec 31 12:35:36 PM PST 23 Dec 31 12:35:47 PM PST 23 1106639369 ps
T964 /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.4237083237 Dec 31 12:35:49 PM PST 23 Dec 31 12:36:52 PM PST 23 9060238323 ps
T965 /workspace/coverage/default/19.lc_ctrl_jtag_smoke.2090558164 Dec 31 12:36:05 PM PST 23 Dec 31 12:36:24 PM PST 23 184865490 ps
T966 /workspace/coverage/default/10.lc_ctrl_errors.2162270619 Dec 31 12:37:20 PM PST 23 Dec 31 12:37:47 PM PST 23 835057420 ps
T967 /workspace/coverage/default/45.lc_ctrl_errors.2814993024 Dec 31 12:37:05 PM PST 23 Dec 31 12:37:29 PM PST 23 651026895 ps
T968 /workspace/coverage/default/33.lc_ctrl_state_failure.294068708 Dec 31 12:36:56 PM PST 23 Dec 31 12:37:30 PM PST 23 226249180 ps
T969 /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.518746796 Dec 31 12:35:55 PM PST 23 Dec 31 12:36:20 PM PST 23 928119978 ps
T970 /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.1953895030 Dec 31 12:37:10 PM PST 23 Dec 31 12:37:24 PM PST 23 11223134 ps
T971 /workspace/coverage/default/42.lc_ctrl_sec_token_mux.4186250703 Dec 31 12:37:21 PM PST 23 Dec 31 12:37:41 PM PST 23 1274445835 ps
T972 /workspace/coverage/default/22.lc_ctrl_state_failure.1561717733 Dec 31 12:36:28 PM PST 23 Dec 31 12:36:59 PM PST 23 3646776279 ps
T973 /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.964361974 Dec 31 12:35:46 PM PST 23 Dec 31 12:36:42 PM PST 23 2462804309 ps
T974 /workspace/coverage/default/9.lc_ctrl_jtag_smoke.3917026456 Dec 31 12:35:52 PM PST 23 Dec 31 12:36:06 PM PST 23 204841592 ps
T975 /workspace/coverage/default/38.lc_ctrl_jtag_access.3304790793 Dec 31 12:36:43 PM PST 23 Dec 31 12:37:07 PM PST 23 1361065067 ps
T976 /workspace/coverage/default/31.lc_ctrl_sec_token_digest.2919892331 Dec 31 12:36:31 PM PST 23 Dec 31 12:37:09 PM PST 23 3446171669 ps
T977 /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.1030773724 Dec 31 12:36:14 PM PST 23 Dec 31 12:38:33 PM PST 23 4844908307 ps
T978 /workspace/coverage/default/44.lc_ctrl_sec_token_digest.1574114468 Dec 31 12:37:09 PM PST 23 Dec 31 12:37:32 PM PST 23 959728449 ps
T979 /workspace/coverage/default/1.lc_ctrl_regwen_during_op.2438576425 Dec 31 12:36:02 PM PST 23 Dec 31 12:36:28 PM PST 23 1654453690 ps
T980 /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2001956286 Dec 31 12:36:55 PM PST 23 Dec 31 12:37:11 PM PST 23 27799980 ps
T981 /workspace/coverage/default/40.lc_ctrl_alert_test.118119100 Dec 31 12:37:03 PM PST 23 Dec 31 12:37:19 PM PST 23 22213132 ps
T982 /workspace/coverage/default/3.lc_ctrl_sec_mubi.1859701112 Dec 31 12:35:53 PM PST 23 Dec 31 12:36:18 PM PST 23 2615610805 ps
T983 /workspace/coverage/default/6.lc_ctrl_jtag_errors.984952634 Dec 31 12:36:01 PM PST 23 Dec 31 12:36:38 PM PST 23 1327614757 ps
T984 /workspace/coverage/default/30.lc_ctrl_alert_test.1639450545 Dec 31 12:36:51 PM PST 23 Dec 31 12:37:07 PM PST 23 19300250 ps
T985 /workspace/coverage/default/0.lc_ctrl_smoke.1457161994 Dec 31 12:35:46 PM PST 23 Dec 31 12:35:59 PM PST 23 55386145 ps
T986 /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.2031081747 Dec 31 12:36:06 PM PST 23 Dec 31 12:36:42 PM PST 23 780914367 ps

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1179023483
Short name T1
Test name
Test status
Simulation time 782538968 ps
CPU time 10.86 seconds
Started Dec 31 12:36:44 PM PST 23
Finished Dec 31 12:37:12 PM PST 23
Peak memory 217952 kb
Host smart-5e4a9ea7-87fb-40e3-a570-378544762141
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179023483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.1179023483
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.3989271415
Short name T22
Test name
Test status
Simulation time 93794648128 ps
CPU time 422.51 seconds
Started Dec 31 12:35:51 PM PST 23
Finished Dec 31 12:43:04 PM PST 23
Peak memory 283796 kb
Host smart-b79fc51d-4f11-47ed-b1d4-a594d7d2cf2e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989271415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.3989271415
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.1172615755
Short name T9
Test name
Test status
Simulation time 4662347335 ps
CPU time 6.89 seconds
Started Dec 31 12:35:57 PM PST 23
Finished Dec 31 12:36:21 PM PST 23
Peak memory 218128 kb
Host smart-3d7c0e77-a0fd-4ead-a566-e59eb72d8a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172615755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.1172615755
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2835500654
Short name T114
Test name
Test status
Simulation time 109091262 ps
CPU time 2.33 seconds
Started Dec 31 12:44:35 PM PST 23
Finished Dec 31 12:44:43 PM PST 23
Peak memory 217688 kb
Host smart-68eb7367-42c2-448b-a60e-6dd044604fa0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283550
0654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2835500654
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1398247785
Short name T129
Test name
Test status
Simulation time 45847127 ps
CPU time 1.85 seconds
Started Dec 31 12:45:50 PM PST 23
Finished Dec 31 12:45:53 PM PST 23
Peak memory 209028 kb
Host smart-f5f43470-9e8f-41b8-9786-c27afa02185e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398247785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.1398247785
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.2484497853
Short name T50
Test name
Test status
Simulation time 766839602 ps
CPU time 9.73 seconds
Started Dec 31 12:36:05 PM PST 23
Finished Dec 31 12:36:31 PM PST 23
Peak memory 218084 kb
Host smart-a204e205-e236-4021-912a-023c66d5d754
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484497853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.2484497853
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.231045366
Short name T35
Test name
Test status
Simulation time 12668121 ps
CPU time 0.79 seconds
Started Dec 31 12:36:57 PM PST 23
Finished Dec 31 12:37:12 PM PST 23
Peak memory 208264 kb
Host smart-be95cc0a-7158-4260-8880-52fbe2ee22ea
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231045366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ct
rl_volatile_unlock_smoke.231045366
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.120370280
Short name T55
Test name
Test status
Simulation time 247501425 ps
CPU time 9.79 seconds
Started Dec 31 12:35:51 PM PST 23
Finished Dec 31 12:36:11 PM PST 23
Peak memory 218064 kb
Host smart-9cf09fe6-1a08-4ac5-b09a-aaf1cdcb630e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120370280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.120370280
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.1253848167
Short name T52
Test name
Test status
Simulation time 45285323461 ps
CPU time 2238.57 seconds
Started Dec 31 12:36:35 PM PST 23
Finished Dec 31 01:14:10 PM PST 23
Peak memory 1511468 kb
Host smart-e7ab7bb8-99df-4b72-a5dd-a4f62c41dcfb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1253848167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.1253848167
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1374805746
Short name T152
Test name
Test status
Simulation time 208322384 ps
CPU time 2.78 seconds
Started Dec 31 12:44:51 PM PST 23
Finished Dec 31 12:44:59 PM PST 23
Peak memory 210764 kb
Host smart-6ff30e2a-8175-4a66-9de4-8ee505f5b524
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374805746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1374805746
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.2766632509
Short name T59
Test name
Test status
Simulation time 234919996 ps
CPU time 35.84 seconds
Started Dec 31 12:35:51 PM PST 23
Finished Dec 31 12:36:38 PM PST 23
Peak memory 269308 kb
Host smart-253f06a7-5d29-4290-b058-5e09579b3fec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766632509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.2766632509
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.505782143
Short name T112
Test name
Test status
Simulation time 113760997 ps
CPU time 3.11 seconds
Started Dec 31 12:45:10 PM PST 23
Finished Dec 31 12:45:15 PM PST 23
Peak memory 222192 kb
Host smart-4a3ff988-ca0a-47e9-8c27-1973e7b312c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505782143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg_
err.505782143
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.2691243014
Short name T11
Test name
Test status
Simulation time 1168443303 ps
CPU time 11.56 seconds
Started Dec 31 12:36:50 PM PST 23
Finished Dec 31 12:37:17 PM PST 23
Peak memory 218012 kb
Host smart-8d54cd0a-f515-4b09-8e76-58a4e83129e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691243014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
2691243014
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.3591294628
Short name T160
Test name
Test status
Simulation time 475492682 ps
CPU time 11.42 seconds
Started Dec 31 12:37:22 PM PST 23
Finished Dec 31 12:37:43 PM PST 23
Peak memory 218176 kb
Host smart-75e69aa2-26fb-43ce-9331-68691669b91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591294628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3591294628
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3102651049
Short name T93
Test name
Test status
Simulation time 91504357 ps
CPU time 0.98 seconds
Started Dec 31 12:44:55 PM PST 23
Finished Dec 31 12:44:59 PM PST 23
Peak memory 209088 kb
Host smart-14280bba-1c54-4d69-a83c-77f951475565
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102651049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3102651049
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.346265534
Short name T206
Test name
Test status
Simulation time 91050003 ps
CPU time 2.01 seconds
Started Dec 31 12:44:46 PM PST 23
Finished Dec 31 12:44:52 PM PST 23
Peak memory 217776 kb
Host smart-fa6a5d22-1031-4c94-946b-c10093b9bd6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346265534 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.346265534
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.3009467220
Short name T110
Test name
Test status
Simulation time 12665330140 ps
CPU time 95.08 seconds
Started Dec 31 12:36:59 PM PST 23
Finished Dec 31 12:38:49 PM PST 23
Peak memory 283892 kb
Host smart-b170541d-0dcb-4311-9949-46a042de8418
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009467220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.3009467220
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.34653025
Short name T91
Test name
Test status
Simulation time 456382552 ps
CPU time 2.95 seconds
Started Dec 31 12:44:52 PM PST 23
Finished Dec 31 12:44:59 PM PST 23
Peak memory 221572 kb
Host smart-2a2a1418-4635-46fb-99ec-c3180f91cb74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34653025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg_e
rr.34653025
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.2893234352
Short name T332
Test name
Test status
Simulation time 11514166 ps
CPU time 0.8 seconds
Started Dec 31 12:35:59 PM PST 23
Finished Dec 31 12:36:17 PM PST 23
Peak memory 209364 kb
Host smart-bf3637b4-23c9-47b7-bc19-72abf50191aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893234352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.2893234352
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.4098596390
Short name T6
Test name
Test status
Simulation time 2034258530 ps
CPU time 9.02 seconds
Started Dec 31 12:36:36 PM PST 23
Finished Dec 31 12:37:02 PM PST 23
Peak memory 209464 kb
Host smart-946571c0-f42f-481d-b4ea-03e681cb4d20
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098596390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_a
ccess.4098596390
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.2615820930
Short name T70
Test name
Test status
Simulation time 275159894 ps
CPU time 11.5 seconds
Started Dec 31 12:36:42 PM PST 23
Finished Dec 31 12:37:12 PM PST 23
Peak memory 219108 kb
Host smart-768fb3fb-6815-4fc0-88c5-2d80be98fa27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615820930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.2615820930
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.4119409536
Short name T143
Test name
Test status
Simulation time 2031609335 ps
CPU time 2.88 seconds
Started Dec 31 12:44:57 PM PST 23
Finished Dec 31 12:45:02 PM PST 23
Peak memory 221492 kb
Host smart-397bd12e-644b-4ff0-b6a8-e6bc2b9e72f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119409536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.4119409536
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1087049034
Short name T133
Test name
Test status
Simulation time 235664424 ps
CPU time 2.69 seconds
Started Dec 31 12:45:10 PM PST 23
Finished Dec 31 12:45:14 PM PST 23
Peak memory 217708 kb
Host smart-0ded7743-ff85-4a57-a2e4-13da99cc46b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087049034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.1087049034
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.352025907
Short name T21
Test name
Test status
Simulation time 7739553402 ps
CPU time 55.08 seconds
Started Dec 31 12:35:45 PM PST 23
Finished Dec 31 12:36:49 PM PST 23
Peak memory 218796 kb
Host smart-35e7353e-6045-42bb-8d31-4df5039cf45c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352025907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_err
ors.352025907
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.422076939
Short name T39
Test name
Test status
Simulation time 12159430 ps
CPU time 0.89 seconds
Started Dec 31 12:35:49 PM PST 23
Finished Dec 31 12:36:01 PM PST 23
Peak memory 208216 kb
Host smart-59252ba4-f791-4fcb-bafe-8963fb95daa9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422076939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctr
l_volatile_unlock_smoke.422076939
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3232487291
Short name T103
Test name
Test status
Simulation time 58516557 ps
CPU time 2.54 seconds
Started Dec 31 12:45:07 PM PST 23
Finished Dec 31 12:45:12 PM PST 23
Peak memory 217692 kb
Host smart-48f4b33a-8699-4cc5-bf11-45afcb342b6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232487291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.3232487291
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2268850119
Short name T30
Test name
Test status
Simulation time 12192511 ps
CPU time 0.8 seconds
Started Dec 31 12:35:58 PM PST 23
Finished Dec 31 12:36:17 PM PST 23
Peak memory 207972 kb
Host smart-837c0d7f-698d-4baa-8cb4-8c3915b30c81
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268850119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.2268850119
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3510109255
Short name T124
Test name
Test status
Simulation time 279634003 ps
CPU time 2.46 seconds
Started Dec 31 12:45:14 PM PST 23
Finished Dec 31 12:45:22 PM PST 23
Peak memory 218724 kb
Host smart-568f08da-7d2d-46da-b429-3ce7b959accc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510109255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.3510109255
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.737988686
Short name T111
Test name
Test status
Simulation time 107908868 ps
CPU time 2.77 seconds
Started Dec 31 12:44:54 PM PST 23
Finished Dec 31 12:45:00 PM PST 23
Peak memory 222140 kb
Host smart-15282d39-a719-4eec-819d-389a4bbd380a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737988686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_e
rr.737988686
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2241418615
Short name T138
Test name
Test status
Simulation time 43036054 ps
CPU time 1.67 seconds
Started Dec 31 12:44:40 PM PST 23
Finished Dec 31 12:44:51 PM PST 23
Peak memory 221120 kb
Host smart-00c58f10-2562-4311-a8a8-884781b23aed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241418615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2241418615
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2187235434
Short name T137
Test name
Test status
Simulation time 58330110 ps
CPU time 1.86 seconds
Started Dec 31 12:44:48 PM PST 23
Finished Dec 31 12:44:53 PM PST 23
Peak memory 221728 kb
Host smart-e3c5db30-585d-4170-ae3c-65c5e1d3137c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187235434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.2187235434
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.572954313
Short name T180
Test name
Test status
Simulation time 10616573 ps
CPU time 0.92 seconds
Started Dec 31 12:35:41 PM PST 23
Finished Dec 31 12:35:45 PM PST 23
Peak memory 209504 kb
Host smart-4dd02898-4cb5-4bf6-8f30-a541465fa92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572954313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.572954313
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.965536225
Short name T557
Test name
Test status
Simulation time 1339170900 ps
CPU time 9.62 seconds
Started Dec 31 12:36:10 PM PST 23
Finished Dec 31 12:36:38 PM PST 23
Peak memory 218076 kb
Host smart-d81f32d8-bfdd-423a-b833-887982dc8ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965536225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.965536225
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.2625654850
Short name T182
Test name
Test status
Simulation time 13924153 ps
CPU time 0.96 seconds
Started Dec 31 12:35:47 PM PST 23
Finished Dec 31 12:36:00 PM PST 23
Peak memory 209472 kb
Host smart-51d9d230-a6d4-48d0-a2ea-e4a06656e6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625654850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.2625654850
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.65102576
Short name T183
Test name
Test status
Simulation time 12923221 ps
CPU time 0.94 seconds
Started Dec 31 12:35:55 PM PST 23
Finished Dec 31 12:36:11 PM PST 23
Peak memory 209512 kb
Host smart-6de83a8b-9e3a-4641-9212-ceb4922336f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65102576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.65102576
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.156034167
Short name T40
Test name
Test status
Simulation time 11656845520 ps
CPU time 176.14 seconds
Started Dec 31 12:35:47 PM PST 23
Finished Dec 31 12:38:55 PM PST 23
Peak memory 271812 kb
Host smart-15ed8d67-0696-4e4c-8b73-70a13a8a3dff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156034167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.156034167
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.464222275
Short name T131
Test name
Test status
Simulation time 504296081 ps
CPU time 2.99 seconds
Started Dec 31 12:44:48 PM PST 23
Finished Dec 31 12:44:54 PM PST 23
Peak memory 221620 kb
Host smart-483a2820-0a80-4258-8d43-59a51a1e4667
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464222275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg_
err.464222275
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3168407407
Short name T134
Test name
Test status
Simulation time 80641296 ps
CPU time 2.1 seconds
Started Dec 31 12:45:04 PM PST 23
Finished Dec 31 12:45:08 PM PST 23
Peak memory 221456 kb
Host smart-9e32698d-69f7-4af1-b8d4-4b90571e01e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168407407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.3168407407
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2256869023
Short name T128
Test name
Test status
Simulation time 298335646 ps
CPU time 1.77 seconds
Started Dec 31 12:44:29 PM PST 23
Finished Dec 31 12:44:36 PM PST 23
Peak memory 221500 kb
Host smart-1b89f25b-4cec-4123-a415-b9e0806b519f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256869023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.2256869023
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1524028903
Short name T139
Test name
Test status
Simulation time 225633829 ps
CPU time 2.52 seconds
Started Dec 31 12:44:59 PM PST 23
Finished Dec 31 12:45:04 PM PST 23
Peak memory 221448 kb
Host smart-27468811-0be9-43d6-98a7-f635ce1a276f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524028903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.1524028903
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.297431643
Short name T53
Test name
Test status
Simulation time 65942446348 ps
CPU time 682.55 seconds
Started Dec 31 12:35:49 PM PST 23
Finished Dec 31 12:47:23 PM PST 23
Peak memory 562552 kb
Host smart-a41a5145-41a5-4250-ba51-5704b6aa4a94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=297431643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.297431643
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.1525414463
Short name T54
Test name
Test status
Simulation time 1035906747 ps
CPU time 13.81 seconds
Started Dec 31 12:36:54 PM PST 23
Finished Dec 31 12:37:22 PM PST 23
Peak memory 218076 kb
Host smart-4cdc843a-a4ab-43fc-91d6-61d4b12a26e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525414463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.1525414463
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2255100283
Short name T96
Test name
Test status
Simulation time 19157854 ps
CPU time 0.98 seconds
Started Dec 31 12:44:55 PM PST 23
Finished Dec 31 12:44:59 PM PST 23
Peak memory 209472 kb
Host smart-7adb1d61-5f93-41ab-89e5-ad54830471b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255100283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.2255100283
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2765669988
Short name T153
Test name
Test status
Simulation time 13673367 ps
CPU time 1.22 seconds
Started Dec 31 12:45:10 PM PST 23
Finished Dec 31 12:45:13 PM PST 23
Peak memory 219040 kb
Host smart-0dfacd15-0a73-48ae-8d9e-8612c98445a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765669988 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.2765669988
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1437557593
Short name T156
Test name
Test status
Simulation time 53668655 ps
CPU time 1.66 seconds
Started Dec 31 12:44:18 PM PST 23
Finished Dec 31 12:44:24 PM PST 23
Peak memory 209464 kb
Host smart-dbda7970-2926-47f4-a01e-1b82a806300d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437557593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.1437557593
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.242839471
Short name T279
Test name
Test status
Simulation time 94062911 ps
CPU time 3.07 seconds
Started Dec 31 12:44:32 PM PST 23
Finished Dec 31 12:44:40 PM PST 23
Peak memory 209500 kb
Host smart-9274aa98-f0bc-47c6-8027-bb12dac54be3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242839471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bash
.242839471
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1868203930
Short name T169
Test name
Test status
Simulation time 22008317 ps
CPU time 1.03 seconds
Started Dec 31 12:44:20 PM PST 23
Finished Dec 31 12:44:24 PM PST 23
Peak memory 211300 kb
Host smart-9ed6769f-f602-466f-acfa-94a1c295fcea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868203930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.1868203930
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1893375808
Short name T170
Test name
Test status
Simulation time 22145362 ps
CPU time 0.8 seconds
Started Dec 31 12:44:31 PM PST 23
Finished Dec 31 12:44:37 PM PST 23
Peak memory 209296 kb
Host smart-d7e3d422-4ba2-41d9-a88f-3dce746e8f0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893375808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.1893375808
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.404261831
Short name T195
Test name
Test status
Simulation time 156143495 ps
CPU time 1.48 seconds
Started Dec 31 12:44:32 PM PST 23
Finished Dec 31 12:44:39 PM PST 23
Peak memory 209352 kb
Host smart-72090779-7be7-4960-961d-d41f19a37b55
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404261831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.lc_ctrl_jtag_alert_test.404261831
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.4128154988
Short name T232
Test name
Test status
Simulation time 1570940183 ps
CPU time 5.98 seconds
Started Dec 31 12:44:39 PM PST 23
Finished Dec 31 12:44:50 PM PST 23
Peak memory 209356 kb
Host smart-1e199066-a49d-4adb-a5fb-361eaf31c86a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128154988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.4128154988
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2023985446
Short name T285
Test name
Test status
Simulation time 1751428936 ps
CPU time 33.79 seconds
Started Dec 31 12:44:29 PM PST 23
Finished Dec 31 12:45:08 PM PST 23
Peak memory 209404 kb
Host smart-37965bdf-4a97-46b1-a7f5-727aa926fe38
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023985446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.2023985446
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.489018994
Short name T273
Test name
Test status
Simulation time 448173481 ps
CPU time 2.77 seconds
Started Dec 31 12:44:24 PM PST 23
Finished Dec 31 12:44:30 PM PST 23
Peak memory 210844 kb
Host smart-1608f5f1-bb06-40b4-8fb7-2111453163bf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489018994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.489018994
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1724200834
Short name T106
Test name
Test status
Simulation time 572292954 ps
CPU time 1.44 seconds
Started Dec 31 12:44:49 PM PST 23
Finished Dec 31 12:44:54 PM PST 23
Peak memory 209368 kb
Host smart-0deb1079-6324-422b-8f75-7b9d8ad19e8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724200834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.1724200834
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1346522705
Short name T238
Test name
Test status
Simulation time 71586575 ps
CPU time 1.15 seconds
Started Dec 31 12:44:18 PM PST 23
Finished Dec 31 12:44:23 PM PST 23
Peak memory 209100 kb
Host smart-3a34ebc9-7ba6-443d-bb56-96558236e15a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346522705 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.1346522705
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3890687204
Short name T193
Test name
Test status
Simulation time 26669791 ps
CPU time 1.34 seconds
Started Dec 31 12:45:02 PM PST 23
Finished Dec 31 12:45:06 PM PST 23
Peak memory 209464 kb
Host smart-0414c162-3599-4b4b-af4a-d0d18502af78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890687204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.3890687204
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3831992815
Short name T281
Test name
Test status
Simulation time 82015571 ps
CPU time 2.14 seconds
Started Dec 31 12:44:43 PM PST 23
Finished Dec 31 12:44:49 PM PST 23
Peak memory 217668 kb
Host smart-b0b0a1ed-6b85-402c-b424-5aa58933e37e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831992815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.3831992815
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3453851890
Short name T144
Test name
Test status
Simulation time 86847968 ps
CPU time 2.57 seconds
Started Dec 31 12:44:23 PM PST 23
Finished Dec 31 12:44:30 PM PST 23
Peak memory 217724 kb
Host smart-080e4334-faf7-489f-8312-df5a1bccfc3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453851890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.3453851890
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3524683913
Short name T174
Test name
Test status
Simulation time 139283650 ps
CPU time 1.64 seconds
Started Dec 31 12:45:05 PM PST 23
Finished Dec 31 12:45:09 PM PST 23
Peak memory 209512 kb
Host smart-a6698441-63d2-49c5-a4f7-c36940f796d4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524683913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.3524683913
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.789425144
Short name T251
Test name
Test status
Simulation time 196787439 ps
CPU time 1.87 seconds
Started Dec 31 12:44:32 PM PST 23
Finished Dec 31 12:44:39 PM PST 23
Peak memory 209448 kb
Host smart-08d3573c-31b9-4017-b66a-6044bfe071d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789425144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bash
.789425144
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.26464387
Short name T292
Test name
Test status
Simulation time 34811741 ps
CPU time 1.25 seconds
Started Dec 31 12:44:21 PM PST 23
Finished Dec 31 12:44:25 PM PST 23
Peak memory 219480 kb
Host smart-1526f61b-9abe-4af1-ba3c-73a7687a65a9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26464387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_reset.26464387
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1605402059
Short name T266
Test name
Test status
Simulation time 133643116 ps
CPU time 1.39 seconds
Started Dec 31 12:45:03 PM PST 23
Finished Dec 31 12:45:06 PM PST 23
Peak memory 217712 kb
Host smart-ca54c580-79a8-47ec-9245-494c43e3a8a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605402059 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.1605402059
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1397514524
Short name T302
Test name
Test status
Simulation time 34779731 ps
CPU time 0.93 seconds
Started Dec 31 12:44:33 PM PST 23
Finished Dec 31 12:44:40 PM PST 23
Peak memory 209296 kb
Host smart-6491f5f0-6285-48bd-8c0e-6cd022b63506
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397514524 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1397514524
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1248959077
Short name T210
Test name
Test status
Simulation time 498649388 ps
CPU time 7.04 seconds
Started Dec 31 12:44:24 PM PST 23
Finished Dec 31 12:44:35 PM PST 23
Peak memory 209452 kb
Host smart-fba97c48-2e88-428f-a9f6-d44c49319bc3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248959077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.1248959077
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.376121677
Short name T105
Test name
Test status
Simulation time 540480866 ps
CPU time 12.41 seconds
Started Dec 31 12:44:49 PM PST 23
Finished Dec 31 12:45:05 PM PST 23
Peak memory 207912 kb
Host smart-d461262f-541f-43ab-9b04-1a1c6e011760
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376121677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.376121677
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1706715652
Short name T255
Test name
Test status
Simulation time 157422578 ps
CPU time 1.72 seconds
Started Dec 31 12:44:52 PM PST 23
Finished Dec 31 12:44:58 PM PST 23
Peak memory 218276 kb
Host smart-b2a43104-fee7-4f60-86f8-b9119b1bd671
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170671
5652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1706715652
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3993089839
Short name T250
Test name
Test status
Simulation time 65384000 ps
CPU time 1.25 seconds
Started Dec 31 12:44:41 PM PST 23
Finished Dec 31 12:44:47 PM PST 23
Peak memory 209216 kb
Host smart-3866b738-099d-4c20-b4bd-ad123cabfb26
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993089839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.3993089839
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3730944301
Short name T288
Test name
Test status
Simulation time 220998004 ps
CPU time 1.4 seconds
Started Dec 31 12:44:44 PM PST 23
Finished Dec 31 12:44:49 PM PST 23
Peak memory 211348 kb
Host smart-796be57b-7eed-4571-b79f-abeea57f89ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730944301 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.3730944301
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2998884117
Short name T246
Test name
Test status
Simulation time 47004566 ps
CPU time 1.11 seconds
Started Dec 31 12:44:45 PM PST 23
Finished Dec 31 12:44:50 PM PST 23
Peak memory 209000 kb
Host smart-98ee03fc-952b-4648-acae-63594a10c3f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998884117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.2998884117
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1971173033
Short name T245
Test name
Test status
Simulation time 62364436 ps
CPU time 2.93 seconds
Started Dec 31 12:45:00 PM PST 23
Finished Dec 31 12:45:09 PM PST 23
Peak memory 217676 kb
Host smart-d1311b81-02dd-4431-bdcb-215d87a11e63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971173033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1971173033
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1868533275
Short name T207
Test name
Test status
Simulation time 46779159 ps
CPU time 0.86 seconds
Started Dec 31 12:44:42 PM PST 23
Finished Dec 31 12:44:47 PM PST 23
Peak memory 209492 kb
Host smart-2d1d1b5b-d762-459e-bbb0-fc77149d7744
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868533275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1868533275
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3601062334
Short name T154
Test name
Test status
Simulation time 21292901 ps
CPU time 1.49 seconds
Started Dec 31 12:44:43 PM PST 23
Finished Dec 31 12:44:48 PM PST 23
Peak memory 209568 kb
Host smart-5c1d6f83-aba2-49c8-87cb-9cbce5eaa315
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601062334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.3601062334
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2518303129
Short name T264
Test name
Test status
Simulation time 144264201 ps
CPU time 3.14 seconds
Started Dec 31 12:44:42 PM PST 23
Finished Dec 31 12:44:49 PM PST 23
Peak memory 217700 kb
Host smart-2feffee9-258a-46ba-b2ae-c1339ce9cf1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518303129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.2518303129
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2748338564
Short name T132
Test name
Test status
Simulation time 397449068 ps
CPU time 2.71 seconds
Started Dec 31 12:45:02 PM PST 23
Finished Dec 31 12:45:07 PM PST 23
Peak memory 222320 kb
Host smart-2f10cdf5-754a-451c-8a33-a278c504c87c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748338564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.2748338564
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3899694882
Short name T258
Test name
Test status
Simulation time 14963423 ps
CPU time 0.93 seconds
Started Dec 31 12:44:55 PM PST 23
Finished Dec 31 12:44:59 PM PST 23
Peak memory 217812 kb
Host smart-aa50ac66-9f72-40bb-a16d-d4c76c472d63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899694882 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.3899694882
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.444816127
Short name T225
Test name
Test status
Simulation time 71914809 ps
CPU time 1.7 seconds
Started Dec 31 12:44:41 PM PST 23
Finished Dec 31 12:44:47 PM PST 23
Peak memory 209540 kb
Host smart-013871d9-dc85-4d6d-8d03-0d5f0db550a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444816127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_same_csr_outstanding.444816127
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.632739999
Short name T140
Test name
Test status
Simulation time 307538614 ps
CPU time 3.61 seconds
Started Dec 31 12:44:49 PM PST 23
Finished Dec 31 12:44:56 PM PST 23
Peak memory 217620 kb
Host smart-44809d7b-4b44-40dd-975e-f6980c582ef6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632739999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.632739999
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.361822404
Short name T141
Test name
Test status
Simulation time 232062806 ps
CPU time 2.48 seconds
Started Dec 31 12:44:41 PM PST 23
Finished Dec 31 12:44:47 PM PST 23
Peak memory 217716 kb
Host smart-00b68392-bdd5-42ec-9b4a-1ee12853daeb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361822404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg_
err.361822404
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3341787519
Short name T127
Test name
Test status
Simulation time 17862507 ps
CPU time 1.23 seconds
Started Dec 31 12:45:07 PM PST 23
Finished Dec 31 12:45:10 PM PST 23
Peak memory 218620 kb
Host smart-434b4348-ae98-42e2-8bbd-fae075ffe3a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341787519 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.3341787519
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2329126283
Short name T289
Test name
Test status
Simulation time 52857237 ps
CPU time 0.78 seconds
Started Dec 31 12:45:12 PM PST 23
Finished Dec 31 12:45:15 PM PST 23
Peak memory 208644 kb
Host smart-df7abc61-ca4b-4621-b41b-b2134f1400fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329126283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.2329126283
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3948655897
Short name T165
Test name
Test status
Simulation time 20509580 ps
CPU time 1.17 seconds
Started Dec 31 12:44:31 PM PST 23
Finished Dec 31 12:44:38 PM PST 23
Peak memory 211152 kb
Host smart-107baa46-6a9e-4cdf-8b55-c22f3ef5f0fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948655897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.3948655897
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3034633357
Short name T236
Test name
Test status
Simulation time 32867292 ps
CPU time 1.96 seconds
Started Dec 31 12:44:54 PM PST 23
Finished Dec 31 12:44:59 PM PST 23
Peak memory 217688 kb
Host smart-c80d4ebb-70fb-4377-8c9d-b551764e538a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034633357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.3034633357
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.941036077
Short name T243
Test name
Test status
Simulation time 26206452 ps
CPU time 1.79 seconds
Started Dec 31 12:45:07 PM PST 23
Finished Dec 31 12:45:11 PM PST 23
Peak memory 219724 kb
Host smart-35dd7de9-3d0c-430c-bce7-08ad618bb1cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941036077 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.941036077
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.987120173
Short name T257
Test name
Test status
Simulation time 31638888 ps
CPU time 0.9 seconds
Started Dec 31 12:44:45 PM PST 23
Finished Dec 31 12:44:50 PM PST 23
Peak memory 208928 kb
Host smart-be818426-0c27-484e-b8c1-0c9b8d6ce9ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987120173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.987120173
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2906174414
Short name T241
Test name
Test status
Simulation time 294657541 ps
CPU time 1.22 seconds
Started Dec 31 12:44:35 PM PST 23
Finished Dec 31 12:44:41 PM PST 23
Peak memory 208744 kb
Host smart-01e02c28-ce64-4eda-85a6-585ee79e5cbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906174414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.2906174414
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1316400152
Short name T262
Test name
Test status
Simulation time 22082560 ps
CPU time 1.7 seconds
Started Dec 31 12:45:08 PM PST 23
Finished Dec 31 12:45:13 PM PST 23
Peak memory 218444 kb
Host smart-84ccbf8c-1df9-4413-ac12-33558c2a3437
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316400152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.1316400152
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2176147348
Short name T191
Test name
Test status
Simulation time 14393232 ps
CPU time 1.24 seconds
Started Dec 31 12:45:10 PM PST 23
Finished Dec 31 12:45:13 PM PST 23
Peak memory 218904 kb
Host smart-07993e95-809f-41ce-a46b-f7d2a153a12c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176147348 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.2176147348
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.4287482761
Short name T166
Test name
Test status
Simulation time 33645530 ps
CPU time 0.89 seconds
Started Dec 31 12:45:11 PM PST 23
Finished Dec 31 12:45:13 PM PST 23
Peak memory 209356 kb
Host smart-94770fa0-a245-4ab7-9455-0102ff769e68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287482761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.4287482761
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1509724444
Short name T256
Test name
Test status
Simulation time 30354315 ps
CPU time 1.46 seconds
Started Dec 31 12:44:36 PM PST 23
Finished Dec 31 12:44:44 PM PST 23
Peak memory 209496 kb
Host smart-b59d7d79-ec0a-40b7-a68f-318c44e7ee7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509724444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.1509724444
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.679892112
Short name T231
Test name
Test status
Simulation time 19182753 ps
CPU time 1.11 seconds
Started Dec 31 12:45:02 PM PST 23
Finished Dec 31 12:45:06 PM PST 23
Peak memory 217812 kb
Host smart-9e5eb022-8fda-4cb9-898c-00f593b73af7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679892112 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.679892112
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.574339470
Short name T252
Test name
Test status
Simulation time 11127976 ps
CPU time 0.96 seconds
Started Dec 31 12:44:59 PM PST 23
Finished Dec 31 12:45:02 PM PST 23
Peak memory 209456 kb
Host smart-49c51ac3-6f32-4022-a23b-233cedf1f70a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574339470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.574339470
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.46985287
Short name T203
Test name
Test status
Simulation time 57585940 ps
CPU time 1.35 seconds
Started Dec 31 12:44:58 PM PST 23
Finished Dec 31 12:45:04 PM PST 23
Peak memory 209052 kb
Host smart-8c27c8b6-2f1f-4169-a118-5478b8a06905
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46985287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_
same_csr_outstanding.46985287
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3770583650
Short name T234
Test name
Test status
Simulation time 168154087 ps
CPU time 2.83 seconds
Started Dec 31 12:45:11 PM PST 23
Finished Dec 31 12:45:16 PM PST 23
Peak memory 217760 kb
Host smart-4123a708-f8ec-4856-804e-2cbd01a87fa4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770583650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.3770583650
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3459176216
Short name T267
Test name
Test status
Simulation time 77542071 ps
CPU time 1.35 seconds
Started Dec 31 12:45:36 PM PST 23
Finished Dec 31 12:45:38 PM PST 23
Peak memory 219652 kb
Host smart-30cd257d-7a6a-4529-8654-98434e442178
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459176216 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.3459176216
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.4142898851
Short name T99
Test name
Test status
Simulation time 52406993 ps
CPU time 0.86 seconds
Started Dec 31 12:45:11 PM PST 23
Finished Dec 31 12:45:13 PM PST 23
Peak memory 209000 kb
Host smart-52420f90-fa5a-49bf-bc30-45b4420b032c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142898851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.4142898851
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1039778504
Short name T228
Test name
Test status
Simulation time 76152137 ps
CPU time 1.87 seconds
Started Dec 31 12:45:24 PM PST 23
Finished Dec 31 12:45:27 PM PST 23
Peak memory 211256 kb
Host smart-743ff20d-913b-48b9-b8ca-c9e1ade5b7b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039778504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.1039778504
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1566198013
Short name T204
Test name
Test status
Simulation time 81076620 ps
CPU time 1.57 seconds
Started Dec 31 12:45:04 PM PST 23
Finished Dec 31 12:45:09 PM PST 23
Peak memory 218608 kb
Host smart-89e18604-976c-472a-9f21-262b4e12d988
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566198013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.1566198013
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.343283263
Short name T94
Test name
Test status
Simulation time 24546188 ps
CPU time 1.49 seconds
Started Dec 31 12:45:17 PM PST 23
Finished Dec 31 12:45:22 PM PST 23
Peak memory 219148 kb
Host smart-1203a8f4-5f2c-44b9-a0f5-b97c5431ebd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343283263 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.343283263
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3693380987
Short name T92
Test name
Test status
Simulation time 23987059 ps
CPU time 1 seconds
Started Dec 31 12:45:04 PM PST 23
Finished Dec 31 12:45:08 PM PST 23
Peak memory 209444 kb
Host smart-aa3b13b4-c27e-4e7b-9b24-509088f17521
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693380987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.3693380987
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2510158446
Short name T126
Test name
Test status
Simulation time 409418232 ps
CPU time 3.06 seconds
Started Dec 31 12:44:45 PM PST 23
Finished Dec 31 12:44:52 PM PST 23
Peak memory 217624 kb
Host smart-a8a74713-1d12-4c91-81a5-fe38f9eb03eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510158446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.2510158446
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3348174950
Short name T113
Test name
Test status
Simulation time 292718397 ps
CPU time 3.2 seconds
Started Dec 31 12:44:36 PM PST 23
Finished Dec 31 12:44:45 PM PST 23
Peak memory 221828 kb
Host smart-015a21d2-cb44-42d5-9273-879b139d56fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348174950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.3348174950
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2594223758
Short name T268
Test name
Test status
Simulation time 224039412 ps
CPU time 1.14 seconds
Started Dec 31 12:44:52 PM PST 23
Finished Dec 31 12:44:57 PM PST 23
Peak memory 218900 kb
Host smart-8a5c3239-6cdc-43a3-a49a-6e4a06c73ff6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594223758 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.2594223758
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2182337280
Short name T162
Test name
Test status
Simulation time 163530015 ps
CPU time 0.84 seconds
Started Dec 31 12:45:23 PM PST 23
Finished Dec 31 12:45:25 PM PST 23
Peak memory 209468 kb
Host smart-7b6215ae-6925-4003-8415-d995b6649db6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182337280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.2182337280
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1435327378
Short name T201
Test name
Test status
Simulation time 79089201 ps
CPU time 1.73 seconds
Started Dec 31 12:45:03 PM PST 23
Finished Dec 31 12:45:07 PM PST 23
Peak memory 209404 kb
Host smart-ae22be3c-b6ff-4a8f-bc5e-9bf6ae91af35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435327378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.1435327378
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1452731704
Short name T263
Test name
Test status
Simulation time 215805114 ps
CPU time 2.36 seconds
Started Dec 31 12:45:03 PM PST 23
Finished Dec 31 12:45:07 PM PST 23
Peak memory 217652 kb
Host smart-e3d3e906-c936-4813-8d0a-d22f95d1f7f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452731704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.1452731704
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3693596592
Short name T135
Test name
Test status
Simulation time 155645644 ps
CPU time 3.32 seconds
Started Dec 31 12:45:22 PM PST 23
Finished Dec 31 12:45:27 PM PST 23
Peak memory 221844 kb
Host smart-9a2755da-e0b6-41d4-8228-0dff4ea3d2a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693596592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.3693596592
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1787489051
Short name T208
Test name
Test status
Simulation time 21834367 ps
CPU time 1.09 seconds
Started Dec 31 12:45:12 PM PST 23
Finished Dec 31 12:45:15 PM PST 23
Peak memory 217752 kb
Host smart-89640307-4d46-4618-9785-f1c30a4359ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787489051 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.1787489051
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3752028110
Short name T176
Test name
Test status
Simulation time 15228387 ps
CPU time 0.83 seconds
Started Dec 31 12:45:18 PM PST 23
Finished Dec 31 12:45:21 PM PST 23
Peak memory 209320 kb
Host smart-d38f9fd4-2eca-40dc-beb2-17d17784d778
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752028110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.3752028110
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.455359400
Short name T209
Test name
Test status
Simulation time 130918574 ps
CPU time 1.33 seconds
Started Dec 31 12:45:15 PM PST 23
Finished Dec 31 12:45:21 PM PST 23
Peak memory 211148 kb
Host smart-dd831781-02e6-491b-8f5f-3118a4ffd7d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455359400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_same_csr_outstanding.455359400
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3813548769
Short name T205
Test name
Test status
Simulation time 319496259 ps
CPU time 2.17 seconds
Started Dec 31 12:45:00 PM PST 23
Finished Dec 31 12:45:04 PM PST 23
Peak memory 217628 kb
Host smart-e40dbb92-98a4-4d66-af6c-54e492a35578
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813548769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.3813548769
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.4216336302
Short name T247
Test name
Test status
Simulation time 15434567 ps
CPU time 1.12 seconds
Started Dec 31 12:44:42 PM PST 23
Finished Dec 31 12:44:47 PM PST 23
Peak memory 209448 kb
Host smart-f90be036-8570-4411-9a3d-5c9e2938e7a7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216336302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.4216336302
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1773541860
Short name T178
Test name
Test status
Simulation time 64226909 ps
CPU time 1.8 seconds
Started Dec 31 12:44:48 PM PST 23
Finished Dec 31 12:44:53 PM PST 23
Peak memory 209500 kb
Host smart-bc0fea56-07e0-494e-b1a2-91c1c316945b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773541860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.1773541860
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2729585304
Short name T107
Test name
Test status
Simulation time 56741174 ps
CPU time 0.95 seconds
Started Dec 31 12:44:42 PM PST 23
Finished Dec 31 12:44:47 PM PST 23
Peak memory 210184 kb
Host smart-e83b534a-88bf-49f0-9add-ce29c81595b9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729585304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.2729585304
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.694371541
Short name T157
Test name
Test status
Simulation time 37664815 ps
CPU time 1.04 seconds
Started Dec 31 12:44:30 PM PST 23
Finished Dec 31 12:44:36 PM PST 23
Peak memory 218860 kb
Host smart-e69d0d37-b8d0-4bfe-9b77-9ed0258b406a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694371541 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.694371541
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3319155063
Short name T95
Test name
Test status
Simulation time 12358413 ps
CPU time 0.82 seconds
Started Dec 31 12:44:37 PM PST 23
Finished Dec 31 12:44:43 PM PST 23
Peak memory 209256 kb
Host smart-04a3017c-fbca-4143-b533-eb4c6218f77d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319155063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.3319155063
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.526874116
Short name T270
Test name
Test status
Simulation time 18045544 ps
CPU time 1.05 seconds
Started Dec 31 12:44:38 PM PST 23
Finished Dec 31 12:44:45 PM PST 23
Peak memory 207816 kb
Host smart-def034d2-942f-4229-baba-84b24a57026b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526874116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.lc_ctrl_jtag_alert_test.526874116
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1389653406
Short name T227
Test name
Test status
Simulation time 576349157 ps
CPU time 5.17 seconds
Started Dec 31 12:44:21 PM PST 23
Finished Dec 31 12:44:29 PM PST 23
Peak memory 208316 kb
Host smart-e36597be-6eca-46aa-9626-bc7454539dd2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389653406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.1389653406
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3703921647
Short name T294
Test name
Test status
Simulation time 3978035761 ps
CPU time 40.17 seconds
Started Dec 31 12:44:37 PM PST 23
Finished Dec 31 12:45:24 PM PST 23
Peak memory 209476 kb
Host smart-9a94b532-f7ef-4d39-b810-6b42ca6b1333
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703921647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.3703921647
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2799419228
Short name T150
Test name
Test status
Simulation time 211478348 ps
CPU time 3.12 seconds
Started Dec 31 12:44:57 PM PST 23
Finished Dec 31 12:45:02 PM PST 23
Peak memory 210948 kb
Host smart-0e909f17-1dc9-4969-972a-73de5907e796
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799419228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.2799419228
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3640817132
Short name T199
Test name
Test status
Simulation time 209799595 ps
CPU time 1.72 seconds
Started Dec 31 12:44:23 PM PST 23
Finished Dec 31 12:44:29 PM PST 23
Peak memory 218756 kb
Host smart-8198f761-423c-448b-849a-845e064913d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364081
7132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3640817132
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2962983146
Short name T295
Test name
Test status
Simulation time 86277223 ps
CPU time 1.16 seconds
Started Dec 31 12:44:35 PM PST 23
Finished Dec 31 12:44:42 PM PST 23
Peak memory 209360 kb
Host smart-ac265f9f-61c8-405b-a834-07fc667b782e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962983146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.2962983146
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3288936523
Short name T155
Test name
Test status
Simulation time 97358784 ps
CPU time 1.43 seconds
Started Dec 31 12:44:39 PM PST 23
Finished Dec 31 12:44:46 PM PST 23
Peak memory 209560 kb
Host smart-5f9924d7-c7b2-4215-971e-bfdd7cc48718
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288936523 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.3288936523
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3242340738
Short name T287
Test name
Test status
Simulation time 33594208 ps
CPU time 1.19 seconds
Started Dec 31 12:44:34 PM PST 23
Finished Dec 31 12:44:41 PM PST 23
Peak memory 209496 kb
Host smart-297505d9-eb67-4cf6-bf63-8d470697740b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242340738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.3242340738
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1347894321
Short name T164
Test name
Test status
Simulation time 208525730 ps
CPU time 3.02 seconds
Started Dec 31 12:44:34 PM PST 23
Finished Dec 31 12:44:43 PM PST 23
Peak memory 218772 kb
Host smart-860138bb-3909-45c2-ac8c-ee4817bf23f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347894321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.1347894321
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3724853680
Short name T142
Test name
Test status
Simulation time 64686610 ps
CPU time 2.68 seconds
Started Dec 31 12:44:46 PM PST 23
Finished Dec 31 12:44:53 PM PST 23
Peak memory 217800 kb
Host smart-d6d4c4a3-a1fc-4f25-9fd5-9e121874edd3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724853680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.3724853680
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.4282107804
Short name T275
Test name
Test status
Simulation time 44702939 ps
CPU time 1.26 seconds
Started Dec 31 12:44:51 PM PST 23
Finished Dec 31 12:44:56 PM PST 23
Peak memory 209420 kb
Host smart-dc882b38-cc03-4cc2-9a8f-ac466bd60808
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282107804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.4282107804
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3171725529
Short name T172
Test name
Test status
Simulation time 26661902 ps
CPU time 1.8 seconds
Started Dec 31 12:44:29 PM PST 23
Finished Dec 31 12:44:36 PM PST 23
Peak memory 208352 kb
Host smart-e698e263-995a-4305-b71c-9874ad3f29bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171725529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.3171725529
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2763329526
Short name T248
Test name
Test status
Simulation time 47548354 ps
CPU time 1.05 seconds
Started Dec 31 12:44:42 PM PST 23
Finished Dec 31 12:44:47 PM PST 23
Peak memory 211420 kb
Host smart-07dad04b-f3d2-411a-9954-267852c8f9d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763329526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.2763329526
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3558597864
Short name T269
Test name
Test status
Simulation time 258545713 ps
CPU time 1.47 seconds
Started Dec 31 12:44:55 PM PST 23
Finished Dec 31 12:44:59 PM PST 23
Peak memory 217712 kb
Host smart-e1e5d115-4798-4de0-aa37-7cbf8a801a17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558597864 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.3558597864
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3427122324
Short name T272
Test name
Test status
Simulation time 82913347 ps
CPU time 0.97 seconds
Started Dec 31 12:44:57 PM PST 23
Finished Dec 31 12:45:01 PM PST 23
Peak memory 209408 kb
Host smart-843c4c1e-e190-477f-bd7f-74c39a6e4819
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427122324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.3427122324
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.86567429
Short name T151
Test name
Test status
Simulation time 58581741 ps
CPU time 1.92 seconds
Started Dec 31 12:44:42 PM PST 23
Finished Dec 31 12:44:48 PM PST 23
Peak memory 209360 kb
Host smart-7b56abc2-890a-4ee8-8d86-6b9951bcaa6e
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86567429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_alert_test.86567429
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2517633618
Short name T237
Test name
Test status
Simulation time 224996282 ps
CPU time 5.43 seconds
Started Dec 31 12:44:39 PM PST 23
Finished Dec 31 12:44:50 PM PST 23
Peak memory 209408 kb
Host smart-fa294b08-aa2c-4459-91bb-6b3ddb411c0d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517633618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.2517633618
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2196154656
Short name T221
Test name
Test status
Simulation time 1002713571 ps
CPU time 5.31 seconds
Started Dec 31 12:44:47 PM PST 23
Finished Dec 31 12:44:56 PM PST 23
Peak memory 208476 kb
Host smart-d017bb30-f4dc-4c96-b794-417cc3df38d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196154656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.2196154656
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.701963978
Short name T149
Test name
Test status
Simulation time 221061982 ps
CPU time 1.69 seconds
Started Dec 31 12:44:21 PM PST 23
Finished Dec 31 12:44:27 PM PST 23
Peak memory 210496 kb
Host smart-911c9cab-8644-4faa-91e1-a02b8a4ed1eb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701963978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.701963978
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.67211895
Short name T265
Test name
Test status
Simulation time 83646982 ps
CPU time 2.01 seconds
Started Dec 31 12:44:32 PM PST 23
Finished Dec 31 12:44:40 PM PST 23
Peak memory 218704 kb
Host smart-d35c92cb-088b-4a62-91c1-935bd6ebeeed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672118
95 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.67211895
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.4003096276
Short name T291
Test name
Test status
Simulation time 46497499 ps
CPU time 1.29 seconds
Started Dec 31 12:44:50 PM PST 23
Finished Dec 31 12:44:55 PM PST 23
Peak memory 209288 kb
Host smart-6fc305f8-b3b1-4fac-bc76-03a9ad14c598
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003096276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.4003096276
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3147733966
Short name T298
Test name
Test status
Simulation time 26642859 ps
CPU time 1.38 seconds
Started Dec 31 12:44:46 PM PST 23
Finished Dec 31 12:44:53 PM PST 23
Peak memory 209496 kb
Host smart-36d631e0-9b62-43f7-8d58-e4dd9eff50fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147733966 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3147733966
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3604324236
Short name T216
Test name
Test status
Simulation time 46370169 ps
CPU time 0.94 seconds
Started Dec 31 12:44:24 PM PST 23
Finished Dec 31 12:44:28 PM PST 23
Peak memory 217108 kb
Host smart-f8a5bdea-9825-4741-9610-273b9203b054
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604324236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.3604324236
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.4160852954
Short name T220
Test name
Test status
Simulation time 106865883 ps
CPU time 2.97 seconds
Started Dec 31 12:44:49 PM PST 23
Finished Dec 31 12:44:56 PM PST 23
Peak memory 217664 kb
Host smart-df2d96ec-28cd-421c-9ae9-827e329c0931
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160852954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.4160852954
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2427255732
Short name T173
Test name
Test status
Simulation time 24592523 ps
CPU time 0.94 seconds
Started Dec 31 12:44:46 PM PST 23
Finished Dec 31 12:44:51 PM PST 23
Peak memory 209444 kb
Host smart-68a0d1c3-466b-477f-8c3b-3db0a2f79c6e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427255732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.2427255732
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1915957972
Short name T239
Test name
Test status
Simulation time 68674602 ps
CPU time 1.34 seconds
Started Dec 31 12:45:05 PM PST 23
Finished Dec 31 12:45:09 PM PST 23
Peak memory 209508 kb
Host smart-c1272c67-9fcb-4a5a-be5a-8ac777b815be
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915957972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.1915957972
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3789697757
Short name T175
Test name
Test status
Simulation time 62855125 ps
CPU time 1.02 seconds
Started Dec 31 12:44:31 PM PST 23
Finished Dec 31 12:44:38 PM PST 23
Peak memory 217944 kb
Host smart-e5932cc7-8ecd-437d-ad76-1b7d3accc142
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789697757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.3789697757
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3643681960
Short name T219
Test name
Test status
Simulation time 39915572 ps
CPU time 1.14 seconds
Started Dec 31 12:44:46 PM PST 23
Finished Dec 31 12:44:51 PM PST 23
Peak memory 218828 kb
Host smart-9ad32883-d78f-4d75-9811-c707f9fe2f64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643681960 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3643681960
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2900106979
Short name T168
Test name
Test status
Simulation time 27311276 ps
CPU time 0.96 seconds
Started Dec 31 12:45:13 PM PST 23
Finished Dec 31 12:45:20 PM PST 23
Peak memory 209448 kb
Host smart-a48035a3-a4ff-44c9-a61b-01ebec2d8e66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900106979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.2900106979
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.114916124
Short name T194
Test name
Test status
Simulation time 171390966 ps
CPU time 1.57 seconds
Started Dec 31 12:44:29 PM PST 23
Finished Dec 31 12:44:36 PM PST 23
Peak memory 207920 kb
Host smart-9ef268c4-8952-4c31-932d-be016488ff97
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114916124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.lc_ctrl_jtag_alert_test.114916124
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3058474159
Short name T278
Test name
Test status
Simulation time 402295702 ps
CPU time 2.87 seconds
Started Dec 31 12:44:53 PM PST 23
Finished Dec 31 12:45:00 PM PST 23
Peak memory 209380 kb
Host smart-a2637320-8f6a-4122-8b6f-431bfe70615b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058474159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.3058474159
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3474853151
Short name T148
Test name
Test status
Simulation time 4021650321 ps
CPU time 8.55 seconds
Started Dec 31 12:44:26 PM PST 23
Finished Dec 31 12:44:38 PM PST 23
Peak memory 209456 kb
Host smart-8e5d5778-ce72-4a2e-942f-6d4b36fe0b3d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474853151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3474853151
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1571434446
Short name T283
Test name
Test status
Simulation time 567289720 ps
CPU time 2.37 seconds
Started Dec 31 12:44:30 PM PST 23
Finished Dec 31 12:44:38 PM PST 23
Peak memory 210796 kb
Host smart-51b2bc9e-23e6-4dca-b51f-362a096c6083
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571434446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.1571434446
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1532245690
Short name T261
Test name
Test status
Simulation time 225924621 ps
CPU time 2.18 seconds
Started Dec 31 12:44:32 PM PST 23
Finished Dec 31 12:44:40 PM PST 23
Peak memory 218796 kb
Host smart-ff22fba3-c6cd-43f7-a241-0d8714445ae4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153224
5690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1532245690
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3043673370
Short name T104
Test name
Test status
Simulation time 155337644 ps
CPU time 1.05 seconds
Started Dec 31 12:44:44 PM PST 23
Finished Dec 31 12:44:49 PM PST 23
Peak memory 209244 kb
Host smart-506f023a-6f99-4a39-947c-aa4bea40c8bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043673370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.3043673370
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.461583421
Short name T158
Test name
Test status
Simulation time 86325714 ps
CPU time 1.39 seconds
Started Dec 31 12:44:31 PM PST 23
Finished Dec 31 12:44:38 PM PST 23
Peak memory 209112 kb
Host smart-79d9160a-ea41-403f-9e5b-0e3e9617f123
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461583421 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.461583421
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2242228016
Short name T97
Test name
Test status
Simulation time 30846582 ps
CPU time 1.14 seconds
Started Dec 31 12:44:59 PM PST 23
Finished Dec 31 12:45:03 PM PST 23
Peak memory 208632 kb
Host smart-0d03737c-a0f4-4c9c-9c7a-18058225838d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242228016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.2242228016
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1029513362
Short name T125
Test name
Test status
Simulation time 105832839 ps
CPU time 1.86 seconds
Started Dec 31 12:44:37 PM PST 23
Finished Dec 31 12:44:44 PM PST 23
Peak memory 218728 kb
Host smart-7baf7102-9ade-4f11-a6e2-eacb4f431da2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029513362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1029513362
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.433962236
Short name T276
Test name
Test status
Simulation time 139745862 ps
CPU time 0.95 seconds
Started Dec 31 12:44:59 PM PST 23
Finished Dec 31 12:45:02 PM PST 23
Peak memory 217788 kb
Host smart-37da7de1-0c69-45ab-b1ce-95abca873067
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433962236 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.433962236
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2269337903
Short name T192
Test name
Test status
Simulation time 22987899 ps
CPU time 0.97 seconds
Started Dec 31 12:44:35 PM PST 23
Finished Dec 31 12:44:41 PM PST 23
Peak memory 209476 kb
Host smart-0c135442-88ea-4491-8750-9e47ade73d66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269337903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.2269337903
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2420013689
Short name T211
Test name
Test status
Simulation time 664993556 ps
CPU time 2.37 seconds
Started Dec 31 12:44:42 PM PST 23
Finished Dec 31 12:44:48 PM PST 23
Peak memory 209372 kb
Host smart-9f06776e-bfe9-4b2c-a3a6-c929fe265248
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420013689 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.2420013689
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3365078282
Short name T198
Test name
Test status
Simulation time 1572354485 ps
CPU time 9.26 seconds
Started Dec 31 12:44:50 PM PST 23
Finished Dec 31 12:45:03 PM PST 23
Peak memory 209424 kb
Host smart-81533fbc-7bfa-4bfc-8a24-5af1e083dcb1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365078282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.3365078282
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.776692556
Short name T223
Test name
Test status
Simulation time 1493946874 ps
CPU time 7.48 seconds
Started Dec 31 12:44:49 PM PST 23
Finished Dec 31 12:45:00 PM PST 23
Peak memory 209384 kb
Host smart-1669207e-321f-4f70-b540-17b0c36cd63a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776692556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.776692556
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.413334493
Short name T233
Test name
Test status
Simulation time 1373949999 ps
CPU time 3.23 seconds
Started Dec 31 12:44:50 PM PST 23
Finished Dec 31 12:44:56 PM PST 23
Peak memory 210912 kb
Host smart-f215cec1-37df-4393-a4de-d7c64bd35ef2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413334493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.413334493
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3349610025
Short name T249
Test name
Test status
Simulation time 40167588 ps
CPU time 2.05 seconds
Started Dec 31 12:45:12 PM PST 23
Finished Dec 31 12:45:16 PM PST 23
Peak memory 217824 kb
Host smart-39109f0b-9934-4ff4-894e-2e2483378268
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334961
0025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3349610025
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3396109851
Short name T254
Test name
Test status
Simulation time 180459336 ps
CPU time 2.59 seconds
Started Dec 31 12:44:52 PM PST 23
Finished Dec 31 12:44:59 PM PST 23
Peak memory 209384 kb
Host smart-d43fd194-9557-40c6-aa6a-a325266f62b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396109851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.3396109851
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3432847254
Short name T280
Test name
Test status
Simulation time 65640199 ps
CPU time 1.18 seconds
Started Dec 31 12:44:44 PM PST 23
Finished Dec 31 12:44:49 PM PST 23
Peak memory 209532 kb
Host smart-9b1af318-d2e3-4a48-b37b-a2288ffbc39f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432847254 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3432847254
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3979005180
Short name T230
Test name
Test status
Simulation time 41193911 ps
CPU time 1.33 seconds
Started Dec 31 12:44:48 PM PST 23
Finished Dec 31 12:44:53 PM PST 23
Peak memory 209448 kb
Host smart-0f610469-b6a8-42f8-9a60-2969c9cee7bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979005180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.3979005180
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3759436421
Short name T229
Test name
Test status
Simulation time 67902869 ps
CPU time 2.12 seconds
Started Dec 31 12:44:45 PM PST 23
Finished Dec 31 12:44:51 PM PST 23
Peak memory 217616 kb
Host smart-2e6247b7-ad29-4d48-9165-9ce09e1a8e0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759436421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.3759436421
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1890686137
Short name T136
Test name
Test status
Simulation time 171896390 ps
CPU time 2.02 seconds
Started Dec 31 12:44:57 PM PST 23
Finished Dec 31 12:45:07 PM PST 23
Peak memory 221760 kb
Host smart-62b65026-66ee-4ba3-ba9c-328adfe7a0de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890686137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.1890686137
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.4291285690
Short name T271
Test name
Test status
Simulation time 65567740 ps
CPU time 1.13 seconds
Started Dec 31 12:45:02 PM PST 23
Finished Dec 31 12:45:05 PM PST 23
Peak memory 218756 kb
Host smart-633265fb-f010-4cac-afa6-5fc9ccd99f53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291285690 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.4291285690
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1255352583
Short name T200
Test name
Test status
Simulation time 14086788 ps
CPU time 1.03 seconds
Started Dec 31 12:44:43 PM PST 23
Finished Dec 31 12:44:48 PM PST 23
Peak memory 209448 kb
Host smart-cf6a6649-1a60-4ece-bc1f-30991d218b6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255352583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1255352583
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1154820174
Short name T222
Test name
Test status
Simulation time 1159555324 ps
CPU time 3.42 seconds
Started Dec 31 12:44:46 PM PST 23
Finished Dec 31 12:44:58 PM PST 23
Peak memory 209292 kb
Host smart-e34f9555-7209-43f6-8a17-0c451f7b9a48
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154820174 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.1154820174
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2633978584
Short name T197
Test name
Test status
Simulation time 1280614464 ps
CPU time 8.05 seconds
Started Dec 31 12:44:36 PM PST 23
Finished Dec 31 12:44:50 PM PST 23
Peak memory 209372 kb
Host smart-8e6c3374-abc5-4de8-b5d9-7bab00cf0cee
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633978584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.2633978584
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3149554707
Short name T146
Test name
Test status
Simulation time 347540776 ps
CPU time 4.37 seconds
Started Dec 31 12:44:43 PM PST 23
Finished Dec 31 12:44:52 PM PST 23
Peak memory 207832 kb
Host smart-b040d6ad-de4a-4f4b-b06b-7d38daa036ad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149554707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.3149554707
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.4135212267
Short name T290
Test name
Test status
Simulation time 59350374 ps
CPU time 2.05 seconds
Started Dec 31 12:44:34 PM PST 23
Finished Dec 31 12:44:42 PM PST 23
Peak memory 210384 kb
Host smart-91b23545-91f1-4a60-8221-129611a9eea7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135212267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.4135212267
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2176501561
Short name T163
Test name
Test status
Simulation time 247471750 ps
CPU time 2.38 seconds
Started Dec 31 12:45:08 PM PST 23
Finished Dec 31 12:45:12 PM PST 23
Peak memory 217828 kb
Host smart-ddb40209-0506-47eb-b550-03df81bb4c5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217650
1561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2176501561
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.787978156
Short name T217
Test name
Test status
Simulation time 117871940 ps
CPU time 2 seconds
Started Dec 31 12:44:43 PM PST 23
Finished Dec 31 12:44:49 PM PST 23
Peak memory 209348 kb
Host smart-868c3cef-3b0e-4761-8132-e448898219db
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787978156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.787978156
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.4098212924
Short name T98
Test name
Test status
Simulation time 73239396 ps
CPU time 1.26 seconds
Started Dec 31 12:44:55 PM PST 23
Finished Dec 31 12:44:59 PM PST 23
Peak memory 209076 kb
Host smart-50d68b39-1b31-4805-ad68-fea3601e0de6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098212924 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.4098212924
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.485300371
Short name T296
Test name
Test status
Simulation time 22436680 ps
CPU time 0.98 seconds
Started Dec 31 12:45:07 PM PST 23
Finished Dec 31 12:45:10 PM PST 23
Peak memory 209400 kb
Host smart-f1306da2-f58b-4a55-8ee2-b09498f301df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485300371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
same_csr_outstanding.485300371
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.4219247690
Short name T282
Test name
Test status
Simulation time 318376951 ps
CPU time 2.33 seconds
Started Dec 31 12:44:31 PM PST 23
Finished Dec 31 12:44:39 PM PST 23
Peak memory 217572 kb
Host smart-63922ba3-1659-4024-a3ad-fd23a6a70922
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219247690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.4219247690
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3881353477
Short name T159
Test name
Test status
Simulation time 19342718 ps
CPU time 1.05 seconds
Started Dec 31 12:44:42 PM PST 23
Finished Dec 31 12:44:52 PM PST 23
Peak memory 217820 kb
Host smart-485cfe1c-3258-4ff6-9b74-a3fd3813dfd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881353477 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.3881353477
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.212971509
Short name T303
Test name
Test status
Simulation time 26373977 ps
CPU time 1.01 seconds
Started Dec 31 12:44:48 PM PST 23
Finished Dec 31 12:44:52 PM PST 23
Peak memory 209524 kb
Host smart-c612033f-553e-4d92-b742-c94c20e78934
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212971509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.212971509
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1778884860
Short name T301
Test name
Test status
Simulation time 263774763 ps
CPU time 2.16 seconds
Started Dec 31 12:44:51 PM PST 23
Finished Dec 31 12:44:58 PM PST 23
Peak memory 207816 kb
Host smart-9d44f3c0-967e-43c8-be5b-b7730f779ab7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778884860 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.1778884860
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.834097051
Short name T218
Test name
Test status
Simulation time 851734999 ps
CPU time 14.08 seconds
Started Dec 31 12:44:56 PM PST 23
Finished Dec 31 12:45:12 PM PST 23
Peak memory 207976 kb
Host smart-4a9d2c4f-6c45-4f23-9a39-4e88f8b9a433
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834097051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.834097051
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3801804659
Short name T299
Test name
Test status
Simulation time 343607080 ps
CPU time 4.27 seconds
Started Dec 31 12:45:01 PM PST 23
Finished Dec 31 12:45:08 PM PST 23
Peak memory 209472 kb
Host smart-4b628410-d993-4d83-8972-49b46f9df5c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801804659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.3801804659
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3823085252
Short name T242
Test name
Test status
Simulation time 226943138 ps
CPU time 5.04 seconds
Started Dec 31 12:44:33 PM PST 23
Finished Dec 31 12:44:43 PM PST 23
Peak memory 210856 kb
Host smart-a7005085-fcf0-4df2-8205-8187f9e315d0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823085252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.3823085252
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.457120327
Short name T202
Test name
Test status
Simulation time 148580273 ps
CPU time 1.26 seconds
Started Dec 31 12:45:04 PM PST 23
Finished Dec 31 12:45:08 PM PST 23
Peak memory 218664 kb
Host smart-249b73df-d97d-4e49-a2c3-9d87688d3e3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457120
327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.457120327
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1490219920
Short name T274
Test name
Test status
Simulation time 551988420 ps
CPU time 3.63 seconds
Started Dec 31 12:44:29 PM PST 23
Finished Dec 31 12:44:38 PM PST 23
Peak memory 209412 kb
Host smart-c5a2d97a-aeb3-4f57-927c-5f9c4f29b2de
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490219920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.1490219920
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1822231121
Short name T226
Test name
Test status
Simulation time 66522220 ps
CPU time 1.14 seconds
Started Dec 31 12:44:49 PM PST 23
Finished Dec 31 12:44:53 PM PST 23
Peak memory 209552 kb
Host smart-f737fb10-6ccf-49ed-9b2b-cad555c0d047
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822231121 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1822231121
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3785059414
Short name T260
Test name
Test status
Simulation time 107807157 ps
CPU time 1.05 seconds
Started Dec 31 12:44:50 PM PST 23
Finished Dec 31 12:44:55 PM PST 23
Peak memory 209448 kb
Host smart-e210a9ac-b72e-4545-880e-07cf1bf93da6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785059414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.3785059414
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.4195424974
Short name T215
Test name
Test status
Simulation time 149380168 ps
CPU time 2.72 seconds
Started Dec 31 12:44:49 PM PST 23
Finished Dec 31 12:44:55 PM PST 23
Peak memory 217576 kb
Host smart-92ea38d7-9e71-41dd-ac9c-29bd4ba64272
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195424974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.4195424974
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.524048080
Short name T286
Test name
Test status
Simulation time 24738267 ps
CPU time 1.36 seconds
Started Dec 31 12:44:53 PM PST 23
Finished Dec 31 12:45:03 PM PST 23
Peak memory 218588 kb
Host smart-08a6dd87-69a9-4de0-8e0e-e5839f58d83c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524048080 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.524048080
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.285801683
Short name T167
Test name
Test status
Simulation time 23590762 ps
CPU time 1 seconds
Started Dec 31 12:44:57 PM PST 23
Finished Dec 31 12:45:00 PM PST 23
Peak memory 209460 kb
Host smart-b48f29f9-1e8d-46f1-b758-5275068e6e95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285801683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.285801683
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2002934476
Short name T300
Test name
Test status
Simulation time 116823434 ps
CPU time 1.29 seconds
Started Dec 31 12:44:53 PM PST 23
Finished Dec 31 12:44:58 PM PST 23
Peak memory 207820 kb
Host smart-b37541a8-f87f-4d60-990c-77a04f1b39a5
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002934476 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.2002934476
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.4243480588
Short name T108
Test name
Test status
Simulation time 2764756933 ps
CPU time 9.38 seconds
Started Dec 31 12:44:49 PM PST 23
Finished Dec 31 12:45:02 PM PST 23
Peak memory 209448 kb
Host smart-fc21c3f5-155f-4b06-a929-47f39d471db2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243480588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.4243480588
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1156043914
Short name T297
Test name
Test status
Simulation time 3219612179 ps
CPU time 18.2 seconds
Started Dec 31 12:44:57 PM PST 23
Finished Dec 31 12:45:18 PM PST 23
Peak memory 209528 kb
Host smart-71c01eeb-14a7-4b0d-9ae0-3dac79189fb8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156043914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.1156043914
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1758560379
Short name T213
Test name
Test status
Simulation time 194997379 ps
CPU time 1.23 seconds
Started Dec 31 12:44:41 PM PST 23
Finished Dec 31 12:44:46 PM PST 23
Peak memory 210556 kb
Host smart-f23bbbec-15c9-4647-afde-ecb4babcdbcb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758560379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.1758560379
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1919437138
Short name T284
Test name
Test status
Simulation time 199866760 ps
CPU time 1.41 seconds
Started Dec 31 12:44:48 PM PST 23
Finished Dec 31 12:44:53 PM PST 23
Peak memory 217984 kb
Host smart-5f575a7e-21af-4329-b10e-08d338028e57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191943
7138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1919437138
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1614600225
Short name T147
Test name
Test status
Simulation time 360329225 ps
CPU time 1.38 seconds
Started Dec 31 12:45:06 PM PST 23
Finished Dec 31 12:45:10 PM PST 23
Peak memory 209380 kb
Host smart-ea491d11-8f77-4def-88a5-df1fce9dcba9
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614600225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.1614600225
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3437242897
Short name T240
Test name
Test status
Simulation time 500496502 ps
CPU time 1.33 seconds
Started Dec 31 12:44:37 PM PST 23
Finished Dec 31 12:44:45 PM PST 23
Peak memory 209476 kb
Host smart-e3911d29-cdc3-46b4-a7da-914d77fffc23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437242897 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.3437242897
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3482435425
Short name T212
Test name
Test status
Simulation time 189813268 ps
CPU time 1.98 seconds
Started Dec 31 12:44:50 PM PST 23
Finished Dec 31 12:44:56 PM PST 23
Peak memory 211276 kb
Host smart-f36d861d-5149-4d13-8d1c-345df5ebc348
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482435425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.3482435425
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.4274087120
Short name T177
Test name
Test status
Simulation time 100887362 ps
CPU time 4.19 seconds
Started Dec 31 12:44:51 PM PST 23
Finished Dec 31 12:44:59 PM PST 23
Peak memory 217700 kb
Host smart-81097d6b-65e6-4656-9480-427a45d55580
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274087120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.4274087120
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2458315845
Short name T145
Test name
Test status
Simulation time 52032285 ps
CPU time 1.93 seconds
Started Dec 31 12:44:48 PM PST 23
Finished Dec 31 12:44:53 PM PST 23
Peak memory 221616 kb
Host smart-0d235e99-14c0-45a5-96ee-d9e6ca9b5242
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458315845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.2458315845
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.118777326
Short name T224
Test name
Test status
Simulation time 292386953 ps
CPU time 1.5 seconds
Started Dec 31 12:44:53 PM PST 23
Finished Dec 31 12:44:58 PM PST 23
Peak memory 218840 kb
Host smart-0a9ceac8-26b7-48b8-8117-c91dbbabf0ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118777326 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.118777326
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1922640406
Short name T259
Test name
Test status
Simulation time 51929250 ps
CPU time 0.88 seconds
Started Dec 31 12:44:44 PM PST 23
Finished Dec 31 12:44:48 PM PST 23
Peak memory 209464 kb
Host smart-65df3f04-177e-45ad-ad80-2f5fc7046f2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922640406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.1922640406
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.203956450
Short name T244
Test name
Test status
Simulation time 238579551 ps
CPU time 1.39 seconds
Started Dec 31 12:44:32 PM PST 23
Finished Dec 31 12:44:39 PM PST 23
Peak memory 209276 kb
Host smart-0e5eeaf0-30ed-4fec-aeb2-95b670fc397f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203956450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.lc_ctrl_jtag_alert_test.203956450
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3027354795
Short name T293
Test name
Test status
Simulation time 188853674 ps
CPU time 5.1 seconds
Started Dec 31 12:44:42 PM PST 23
Finished Dec 31 12:44:56 PM PST 23
Peak memory 209384 kb
Host smart-e3a2f544-0583-43f9-8e93-334448955f51
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027354795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.3027354795
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3741286028
Short name T214
Test name
Test status
Simulation time 3764493629 ps
CPU time 20.01 seconds
Started Dec 31 12:45:07 PM PST 23
Finished Dec 31 12:45:29 PM PST 23
Peak memory 209540 kb
Host smart-88c5e85b-76f1-4db4-938d-28ef908994df
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741286028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.3741286028
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2057110223
Short name T196
Test name
Test status
Simulation time 141361312 ps
CPU time 2.05 seconds
Started Dec 31 12:44:50 PM PST 23
Finished Dec 31 12:44:56 PM PST 23
Peak memory 210784 kb
Host smart-b1732432-9201-4e8c-a30f-8e46c90ad6d6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057110223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.2057110223
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3698297260
Short name T277
Test name
Test status
Simulation time 182380791 ps
CPU time 1.41 seconds
Started Dec 31 12:44:44 PM PST 23
Finished Dec 31 12:44:49 PM PST 23
Peak memory 217776 kb
Host smart-2825a5d0-a9c3-44b8-9014-6920ba46107c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369829
7260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3698297260
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.893464283
Short name T235
Test name
Test status
Simulation time 186986071 ps
CPU time 1.08 seconds
Started Dec 31 12:45:17 PM PST 23
Finished Dec 31 12:45:21 PM PST 23
Peak memory 209380 kb
Host smart-7e3a2cee-b500-4ecc-9267-451f751a0618
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893464283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.893464283
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.59545483
Short name T253
Test name
Test status
Simulation time 40347978 ps
CPU time 1.38 seconds
Started Dec 31 12:44:42 PM PST 23
Finished Dec 31 12:44:48 PM PST 23
Peak memory 211236 kb
Host smart-877cc589-bbdb-4c7a-a398-4410c9d163d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59545483 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.59545483
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2945631884
Short name T171
Test name
Test status
Simulation time 135962573 ps
CPU time 1.31 seconds
Started Dec 31 12:44:48 PM PST 23
Finished Dec 31 12:44:58 PM PST 23
Peak memory 209464 kb
Host smart-b33bdb7a-0ac4-4927-b8b3-2b166513753d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945631884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.2945631884
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.647049764
Short name T130
Test name
Test status
Simulation time 207943683 ps
CPU time 3.99 seconds
Started Dec 31 12:44:42 PM PST 23
Finished Dec 31 12:44:50 PM PST 23
Peak memory 217588 kb
Host smart-9f4408a6-2ece-4c5f-9d6f-482b5a165d70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647049764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.647049764
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.3895795508
Short name T334
Test name
Test status
Simulation time 1824387303 ps
CPU time 10.88 seconds
Started Dec 31 12:35:46 PM PST 23
Finished Dec 31 12:36:08 PM PST 23
Peak memory 218060 kb
Host smart-5d51779c-55ba-4c4b-a1a4-c100f6d54e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895795508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.3895795508
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.2542390366
Short name T400
Test name
Test status
Simulation time 2262937103 ps
CPU time 3.64 seconds
Started Dec 31 12:35:56 PM PST 23
Finished Dec 31 12:36:16 PM PST 23
Peak memory 209580 kb
Host smart-bec40576-53e5-4a7b-aeac-ff1566d236c1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542390366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_ac
cess.2542390366
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.3071814925
Short name T962
Test name
Test status
Simulation time 1982663335 ps
CPU time 50.62 seconds
Started Dec 31 12:35:46 PM PST 23
Finished Dec 31 12:36:47 PM PST 23
Peak memory 217984 kb
Host smart-030caada-6c6b-44f0-bb1a-978ceace1522
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071814925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.3071814925
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.2411435820
Short name T934
Test name
Test status
Simulation time 291893274 ps
CPU time 2.45 seconds
Started Dec 31 12:35:30 PM PST 23
Finished Dec 31 12:35:34 PM PST 23
Peak memory 209576 kb
Host smart-b34f5696-4147-4280-9341-196c43d2c258
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411435820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
priority.2411435820
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.2498619199
Short name T460
Test name
Test status
Simulation time 347222409 ps
CPU time 6.94 seconds
Started Dec 31 12:35:39 PM PST 23
Finished Dec 31 12:35:50 PM PST 23
Peak memory 217980 kb
Host smart-3cb01335-53f2-40a0-9a1a-8f5102270de3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498619199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.2498619199
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1317090064
Short name T580
Test name
Test status
Simulation time 961342909 ps
CPU time 14.28 seconds
Started Dec 31 12:35:42 PM PST 23
Finished Dec 31 12:35:59 PM PST 23
Peak memory 212920 kb
Host smart-15347326-e8f6-458e-a537-c81bcaa4a94a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317090064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.1317090064
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.2900761622
Short name T657
Test name
Test status
Simulation time 360579424 ps
CPU time 3.56 seconds
Started Dec 31 12:35:49 PM PST 23
Finished Dec 31 12:36:04 PM PST 23
Peak memory 213212 kb
Host smart-c8f14753-ee24-4442-940c-6209303e2a16
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900761622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
2900761622
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.4237083237
Short name T964
Test name
Test status
Simulation time 9060238323 ps
CPU time 52.01 seconds
Started Dec 31 12:35:49 PM PST 23
Finished Dec 31 12:36:52 PM PST 23
Peak memory 267384 kb
Host smart-a6fee52c-071d-488b-b401-bd9d498e88d0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237083237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.4237083237
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.3613155022
Short name T795
Test name
Test status
Simulation time 389903822 ps
CPU time 8.71 seconds
Started Dec 31 12:35:46 PM PST 23
Finished Dec 31 12:36:05 PM PST 23
Peak memory 221696 kb
Host smart-c84e156e-4ed1-4165-8e6b-2548bd0465c6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613155022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.3613155022
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.642923076
Short name T117
Test name
Test status
Simulation time 90093042 ps
CPU time 2.47 seconds
Started Dec 31 12:35:47 PM PST 23
Finished Dec 31 12:36:03 PM PST 23
Peak memory 218056 kb
Host smart-06248c44-8c68-475c-8dd8-fd22e9c387d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642923076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.642923076
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.555079094
Short name T804
Test name
Test status
Simulation time 250757543 ps
CPU time 9.35 seconds
Started Dec 31 12:35:41 PM PST 23
Finished Dec 31 12:35:54 PM PST 23
Peak memory 213508 kb
Host smart-4b69e79a-57a1-49ba-bc4d-2841aa6a7992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555079094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.555079094
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.3048491473
Short name T61
Test name
Test status
Simulation time 1145635278 ps
CPU time 23.8 seconds
Started Dec 31 12:35:59 PM PST 23
Finished Dec 31 12:36:41 PM PST 23
Peak memory 281500 kb
Host smart-68200986-8f40-4612-ae35-99146f37f5cc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048491473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.3048491473
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.1043863251
Short name T393
Test name
Test status
Simulation time 3325012842 ps
CPU time 7.25 seconds
Started Dec 31 12:36:06 PM PST 23
Finished Dec 31 12:36:29 PM PST 23
Peak memory 218120 kb
Host smart-2f18ba6e-550c-4362-8f73-30ccc51d0183
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043863251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.1043863251
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.2109031633
Short name T716
Test name
Test status
Simulation time 387315343 ps
CPU time 13.83 seconds
Started Dec 31 12:36:00 PM PST 23
Finished Dec 31 12:36:31 PM PST 23
Peak memory 218092 kb
Host smart-312db8ff-463c-44bc-b522-773b0e22ae9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109031633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.2109031633
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.754270690
Short name T456
Test name
Test status
Simulation time 337371546 ps
CPU time 11.58 seconds
Started Dec 31 12:35:55 PM PST 23
Finished Dec 31 12:36:23 PM PST 23
Peak memory 218004 kb
Host smart-758d2bdb-cda3-4b11-9017-20296ba3e7f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754270690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.754270690
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.312681957
Short name T584
Test name
Test status
Simulation time 570792833 ps
CPU time 6.22 seconds
Started Dec 31 12:35:48 PM PST 23
Finished Dec 31 12:36:07 PM PST 23
Peak memory 218016 kb
Host smart-8f898961-4161-4abd-b068-67447e3c9af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312681957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.312681957
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.1457161994
Short name T985
Test name
Test status
Simulation time 55386145 ps
CPU time 1.8 seconds
Started Dec 31 12:35:46 PM PST 23
Finished Dec 31 12:35:59 PM PST 23
Peak memory 213356 kb
Host smart-0faee4d5-4892-4c6b-b221-7ffe3772eca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457161994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1457161994
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.2311826899
Short name T785
Test name
Test status
Simulation time 883108102 ps
CPU time 28.75 seconds
Started Dec 31 12:35:50 PM PST 23
Finished Dec 31 12:36:29 PM PST 23
Peak memory 250936 kb
Host smart-a37941d8-cff6-40ef-af95-86cbf5e6c9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311826899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.2311826899
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.3293336686
Short name T396
Test name
Test status
Simulation time 298110520 ps
CPU time 8.62 seconds
Started Dec 31 12:36:07 PM PST 23
Finished Dec 31 12:36:32 PM PST 23
Peak memory 251024 kb
Host smart-d30ec80f-9572-4517-a3dd-8df411e98139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293336686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.3293336686
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.3046386288
Short name T512
Test name
Test status
Simulation time 32121992 ps
CPU time 0.84 seconds
Started Dec 31 12:35:39 PM PST 23
Finished Dec 31 12:35:44 PM PST 23
Peak memory 208196 kb
Host smart-bfc07063-7e3b-42fd-9909-8e7ac75d15dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046386288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.3046386288
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.4218403665
Short name T179
Test name
Test status
Simulation time 22916920 ps
CPU time 0.78 seconds
Started Dec 31 12:35:53 PM PST 23
Finished Dec 31 12:36:08 PM PST 23
Peak memory 208016 kb
Host smart-ca3c891b-b62f-4000-8cf0-fbe8009d8ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218403665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.4218403665
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1216460824
Short name T844
Test name
Test status
Simulation time 494050068 ps
CPU time 11.73 seconds
Started Dec 31 12:35:54 PM PST 23
Finished Dec 31 12:36:21 PM PST 23
Peak memory 218036 kb
Host smart-90d46fe9-30ad-4c22-b47d-13f566bc6402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216460824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1216460824
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.2300668306
Short name T873
Test name
Test status
Simulation time 34309744 ps
CPU time 1.07 seconds
Started Dec 31 12:35:45 PM PST 23
Finished Dec 31 12:35:54 PM PST 23
Peak memory 209536 kb
Host smart-b0ccf2fb-59ef-4ae5-81c1-1411b4920658
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300668306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_ac
cess.2300668306
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2790119234
Short name T814
Test name
Test status
Simulation time 808028601 ps
CPU time 5.83 seconds
Started Dec 31 12:35:45 PM PST 23
Finished Dec 31 12:36:01 PM PST 23
Peak memory 217900 kb
Host smart-b83ada8e-b496-4499-940e-390280ee4918
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790119234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_
priority.2790119234
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.4142640839
Short name T768
Test name
Test status
Simulation time 278851004 ps
CPU time 8.47 seconds
Started Dec 31 12:36:11 PM PST 23
Finished Dec 31 12:36:38 PM PST 23
Peak memory 217996 kb
Host smart-fe3bc235-3249-4583-9abb-0a1b969d2fe7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142640839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.4142640839
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1579563741
Short name T353
Test name
Test status
Simulation time 1541672481 ps
CPU time 20.47 seconds
Started Dec 31 12:35:49 PM PST 23
Finished Dec 31 12:36:21 PM PST 23
Peak memory 212932 kb
Host smart-2f1c4f36-d2c7-40b4-99a2-7f8f4e5f02ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579563741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.1579563741
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3685976252
Short name T598
Test name
Test status
Simulation time 1987445451 ps
CPU time 7.53 seconds
Started Dec 31 12:35:53 PM PST 23
Finished Dec 31 12:36:15 PM PST 23
Peak memory 213244 kb
Host smart-937755e8-6574-4a1d-9d93-3a6d2ed4ec42
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685976252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
3685976252
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.275423503
Short name T738
Test name
Test status
Simulation time 2190536809 ps
CPU time 58.85 seconds
Started Dec 31 12:35:55 PM PST 23
Finished Dec 31 12:37:10 PM PST 23
Peak memory 275796 kb
Host smart-fd2eb04b-30a7-4dff-9bc4-81e58cc08172
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275423503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_state_failure.275423503
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.2402226642
Short name T774
Test name
Test status
Simulation time 914091732 ps
CPU time 18.4 seconds
Started Dec 31 12:36:11 PM PST 23
Finished Dec 31 12:36:47 PM PST 23
Peak memory 250296 kb
Host smart-ead833c1-7d8b-4ac9-b1b6-7f4ef402de64
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402226642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.2402226642
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.1400122118
Short name T599
Test name
Test status
Simulation time 25810366 ps
CPU time 1.64 seconds
Started Dec 31 12:36:02 PM PST 23
Finished Dec 31 12:36:20 PM PST 23
Peak memory 218032 kb
Host smart-016431ff-ff1e-4897-b0b5-1e76130513cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400122118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.1400122118
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.2438576425
Short name T979
Test name
Test status
Simulation time 1654453690 ps
CPU time 9.36 seconds
Started Dec 31 12:36:02 PM PST 23
Finished Dec 31 12:36:28 PM PST 23
Peak memory 218144 kb
Host smart-6959007f-f6bf-4d46-8836-82e75842bf72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438576425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.2438576425
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.2052108672
Short name T101
Test name
Test status
Simulation time 110921902 ps
CPU time 23.01 seconds
Started Dec 31 12:35:53 PM PST 23
Finished Dec 31 12:36:29 PM PST 23
Peak memory 272928 kb
Host smart-63e9478f-fff3-4012-9ead-fe1b8c3c1f62
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052108672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.2052108672
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.283466418
Short name T887
Test name
Test status
Simulation time 296008652 ps
CPU time 11.08 seconds
Started Dec 31 12:35:31 PM PST 23
Finished Dec 31 12:35:43 PM PST 23
Peak memory 218064 kb
Host smart-946aadcb-55ed-4c50-914d-eb3d93b2a809
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283466418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.283466418
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.3612866537
Short name T658
Test name
Test status
Simulation time 302093599 ps
CPU time 12.3 seconds
Started Dec 31 12:36:07 PM PST 23
Finished Dec 31 12:36:38 PM PST 23
Peak memory 217932 kb
Host smart-50dc4cd7-ec1c-4a13-898f-347c9bd918de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612866537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.3612866537
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.780106237
Short name T642
Test name
Test status
Simulation time 641850720 ps
CPU time 8.24 seconds
Started Dec 31 12:35:40 PM PST 23
Finished Dec 31 12:35:52 PM PST 23
Peak memory 218004 kb
Host smart-75796a99-e257-441f-b398-10194ce3a1f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780106237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.780106237
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.1953350987
Short name T431
Test name
Test status
Simulation time 699009936 ps
CPU time 7 seconds
Started Dec 31 12:36:01 PM PST 23
Finished Dec 31 12:36:29 PM PST 23
Peak memory 218076 kb
Host smart-49bbf362-2468-465c-9f69-87fec6c51861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953350987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.1953350987
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.1657335835
Short name T76
Test name
Test status
Simulation time 188557384 ps
CPU time 2.39 seconds
Started Dec 31 12:36:21 PM PST 23
Finished Dec 31 12:36:42 PM PST 23
Peak memory 213704 kb
Host smart-9aa138b1-05f3-4081-8d1a-6cb726938f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657335835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.1657335835
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.2656882689
Short name T612
Test name
Test status
Simulation time 224899573 ps
CPU time 20.34 seconds
Started Dec 31 12:36:05 PM PST 23
Finished Dec 31 12:36:42 PM PST 23
Peak memory 250964 kb
Host smart-1a7375f6-74d4-482b-aef9-07d94672b043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656882689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.2656882689
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.3175990231
Short name T532
Test name
Test status
Simulation time 65336545 ps
CPU time 7.08 seconds
Started Dec 31 12:36:03 PM PST 23
Finished Dec 31 12:36:27 PM PST 23
Peak memory 250912 kb
Host smart-89dfa648-d2c4-4835-922a-739b4f8b5c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175990231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.3175990231
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.2588716158
Short name T323
Test name
Test status
Simulation time 39906845750 ps
CPU time 344.6 seconds
Started Dec 31 12:36:02 PM PST 23
Finished Dec 31 12:42:03 PM PST 23
Peak memory 267964 kb
Host smart-abd73de2-995a-484b-8c08-1e9f930e7178
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588716158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.2588716158
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.1893879971
Short name T538
Test name
Test status
Simulation time 19857669 ps
CPU time 1.15 seconds
Started Dec 31 12:35:56 PM PST 23
Finished Dec 31 12:36:13 PM PST 23
Peak memory 208460 kb
Host smart-d1c57b1d-dd81-4500-90b4-1191a20c743a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893879971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.1893879971
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.2162270619
Short name T966
Test name
Test status
Simulation time 835057420 ps
CPU time 16.2 seconds
Started Dec 31 12:37:20 PM PST 23
Finished Dec 31 12:37:47 PM PST 23
Peak memory 217988 kb
Host smart-a3805f78-76cc-4a97-9599-a3a03d1ec1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162270619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.2162270619
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.3538392031
Short name T27
Test name
Test status
Simulation time 471926118 ps
CPU time 5.83 seconds
Started Dec 31 12:36:10 PM PST 23
Finished Dec 31 12:36:34 PM PST 23
Peak memory 209504 kb
Host smart-a39291e9-54a1-49dc-bc16-9567b6c110b6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538392031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_a
ccess.3538392031
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1077091512
Short name T48
Test name
Test status
Simulation time 34769643838 ps
CPU time 105.74 seconds
Started Dec 31 12:36:09 PM PST 23
Finished Dec 31 12:38:12 PM PST 23
Peak memory 218524 kb
Host smart-26594f29-9d9c-4771-86a5-84950b4ccfee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077091512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1077091512
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.820579430
Short name T682
Test name
Test status
Simulation time 294835826 ps
CPU time 9.37 seconds
Started Dec 31 12:35:58 PM PST 23
Finished Dec 31 12:36:25 PM PST 23
Peak memory 217920 kb
Host smart-3c2a0f52-61bc-4aa1-9203-22d97e4ff501
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820579430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag
_prog_failure.820579430
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.49586651
Short name T834
Test name
Test status
Simulation time 289793609 ps
CPU time 5.44 seconds
Started Dec 31 12:35:58 PM PST 23
Finished Dec 31 12:36:21 PM PST 23
Peak memory 213064 kb
Host smart-b56fcaae-b84f-4dda-a19f-50632ff2648f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49586651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke.49586651
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.3802506139
Short name T591
Test name
Test status
Simulation time 3312481859 ps
CPU time 65.05 seconds
Started Dec 31 12:36:19 PM PST 23
Finished Dec 31 12:37:43 PM PST 23
Peak memory 276624 kb
Host smart-8384fc6c-3128-4e87-ba6b-8bbad29e5521
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802506139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.3802506139
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.518746796
Short name T969
Test name
Test status
Simulation time 928119978 ps
CPU time 9.06 seconds
Started Dec 31 12:35:55 PM PST 23
Finished Dec 31 12:36:20 PM PST 23
Peak memory 222752 kb
Host smart-839a6883-5a36-4231-9857-5c7dd3b610d8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518746796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_
jtag_state_post_trans.518746796
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.211876054
Short name T912
Test name
Test status
Simulation time 66909788 ps
CPU time 1.44 seconds
Started Dec 31 12:36:04 PM PST 23
Finished Dec 31 12:36:22 PM PST 23
Peak memory 218072 kb
Host smart-ddc6ce70-cf66-4bb9-9618-4772970cdedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211876054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.211876054
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.3075394342
Short name T718
Test name
Test status
Simulation time 386016897 ps
CPU time 7.66 seconds
Started Dec 31 12:36:01 PM PST 23
Finished Dec 31 12:36:25 PM PST 23
Peak memory 218092 kb
Host smart-c57c8a0f-c7af-477c-be0b-8b65fa7ac192
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075394342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.3075394342
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.4016147578
Short name T694
Test name
Test status
Simulation time 2102090342 ps
CPU time 8.89 seconds
Started Dec 31 12:36:06 PM PST 23
Finished Dec 31 12:36:31 PM PST 23
Peak memory 218112 kb
Host smart-b4edb8b4-ed09-4f46-8161-442a77f5fc5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016147578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.4016147578
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.2975609426
Short name T893
Test name
Test status
Simulation time 283228403 ps
CPU time 11.75 seconds
Started Dec 31 12:36:02 PM PST 23
Finished Dec 31 12:36:30 PM PST 23
Peak memory 218100 kb
Host smart-1db959fb-e297-45b3-99f4-10f7dbf64f84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975609426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
2975609426
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.855358233
Short name T822
Test name
Test status
Simulation time 482948573 ps
CPU time 10.58 seconds
Started Dec 31 12:36:01 PM PST 23
Finished Dec 31 12:36:28 PM PST 23
Peak memory 218076 kb
Host smart-5b514adc-7ae4-47ef-a9f6-eb35506f5547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855358233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.855358233
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.1650124091
Short name T636
Test name
Test status
Simulation time 115191595 ps
CPU time 5.04 seconds
Started Dec 31 12:35:58 PM PST 23
Finished Dec 31 12:36:20 PM PST 23
Peak memory 214628 kb
Host smart-cbfb174b-b29a-43cc-b671-a075c497bf7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650124091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.1650124091
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.228627363
Short name T709
Test name
Test status
Simulation time 586130155 ps
CPU time 26.78 seconds
Started Dec 31 12:35:54 PM PST 23
Finished Dec 31 12:36:35 PM PST 23
Peak memory 250864 kb
Host smart-c4ef1f4b-f4d5-4b74-9088-583e2e5c8d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228627363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.228627363
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.4038399909
Short name T392
Test name
Test status
Simulation time 164622080 ps
CPU time 6.3 seconds
Started Dec 31 12:36:09 PM PST 23
Finished Dec 31 12:36:34 PM PST 23
Peak memory 248296 kb
Host smart-df22fe19-56eb-4b50-b3a0-2901b8757402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038399909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.4038399909
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.2409867744
Short name T401
Test name
Test status
Simulation time 688023123 ps
CPU time 28.26 seconds
Started Dec 31 12:36:21 PM PST 23
Finished Dec 31 12:37:08 PM PST 23
Peak memory 251012 kb
Host smart-8a19f163-df68-4da2-9b03-270dc2c8318e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409867744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.2409867744
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.262872839
Short name T882
Test name
Test status
Simulation time 94353571 ps
CPU time 0.93 seconds
Started Dec 31 12:35:58 PM PST 23
Finished Dec 31 12:36:17 PM PST 23
Peak memory 212428 kb
Host smart-04d798b9-eeed-455d-8018-686e165ef3b7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262872839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ct
rl_volatile_unlock_smoke.262872839
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.470998336
Short name T488
Test name
Test status
Simulation time 28554845 ps
CPU time 0.83 seconds
Started Dec 31 12:37:13 PM PST 23
Finished Dec 31 12:37:26 PM PST 23
Peak memory 208036 kb
Host smart-9c88ba72-e9b0-4997-bcdf-9f4e34a2a639
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470998336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.470998336
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.3071015943
Short name T939
Test name
Test status
Simulation time 349758435 ps
CPU time 17.8 seconds
Started Dec 31 12:36:06 PM PST 23
Finished Dec 31 12:36:40 PM PST 23
Peak memory 218036 kb
Host smart-20ffa67c-3715-4473-bd6c-b2bfa2b7d54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071015943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.3071015943
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.1076618821
Short name T780
Test name
Test status
Simulation time 874766973 ps
CPU time 9.52 seconds
Started Dec 31 12:35:59 PM PST 23
Finished Dec 31 12:36:26 PM PST 23
Peak memory 217736 kb
Host smart-a589e4cf-d299-4ef6-a009-91f42dbb3031
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076618821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_a
ccess.1076618821
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.599126226
Short name T619
Test name
Test status
Simulation time 1954416738 ps
CPU time 27.05 seconds
Started Dec 31 12:35:59 PM PST 23
Finished Dec 31 12:36:44 PM PST 23
Peak memory 218136 kb
Host smart-82467d1d-8aa6-4e5f-a9f5-62bd136303aa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599126226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_er
rors.599126226
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.2172041698
Short name T878
Test name
Test status
Simulation time 6518191398 ps
CPU time 7.01 seconds
Started Dec 31 12:35:51 PM PST 23
Finished Dec 31 12:36:09 PM PST 23
Peak memory 218040 kb
Host smart-c09114c0-7da9-4563-82d5-34ee00f8cbcc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172041698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.2172041698
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.1191833093
Short name T385
Test name
Test status
Simulation time 174995162 ps
CPU time 4.95 seconds
Started Dec 31 12:36:11 PM PST 23
Finished Dec 31 12:36:35 PM PST 23
Peak memory 212980 kb
Host smart-39c3299f-01b6-4933-a1e8-8aa1d716b1d0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191833093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.1191833093
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.3362041596
Short name T20
Test name
Test status
Simulation time 1472642773 ps
CPU time 45.92 seconds
Started Dec 31 12:35:56 PM PST 23
Finished Dec 31 12:36:59 PM PST 23
Peak memory 267356 kb
Host smart-20430162-760f-4fda-b597-19931bf6850d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362041596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.3362041596
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.1080700668
Short name T855
Test name
Test status
Simulation time 2699877554 ps
CPU time 15.2 seconds
Started Dec 31 12:36:00 PM PST 23
Finished Dec 31 12:36:32 PM PST 23
Peak memory 250788 kb
Host smart-86dba9f6-e820-4ce5-99c5-7d709079fd4d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080700668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.1080700668
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.3301115358
Short name T399
Test name
Test status
Simulation time 25677029 ps
CPU time 1.89 seconds
Started Dec 31 12:36:02 PM PST 23
Finished Dec 31 12:36:21 PM PST 23
Peak memory 218052 kb
Host smart-c16d4544-632f-4707-aba5-e5bb5ca1eb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301115358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.3301115358
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.920362257
Short name T876
Test name
Test status
Simulation time 1690614102 ps
CPU time 17.4 seconds
Started Dec 31 12:35:58 PM PST 23
Finished Dec 31 12:36:33 PM PST 23
Peak memory 219060 kb
Host smart-d0ade2e1-597e-4370-81a5-60b1e1d0eaa3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920362257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.920362257
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.880274550
Short name T877
Test name
Test status
Simulation time 2281991833 ps
CPU time 25.93 seconds
Started Dec 31 12:36:02 PM PST 23
Finished Dec 31 12:36:44 PM PST 23
Peak memory 218180 kb
Host smart-71eec001-afe3-404f-a500-78da484bd1f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880274550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_di
gest.880274550
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.4124125927
Short name T622
Test name
Test status
Simulation time 1319098107 ps
CPU time 10.87 seconds
Started Dec 31 12:36:04 PM PST 23
Finished Dec 31 12:36:31 PM PST 23
Peak memory 218028 kb
Host smart-69806118-385e-46f7-85aa-7fd4a06b8bc6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124125927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
4124125927
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.1075684558
Short name T960
Test name
Test status
Simulation time 240274776 ps
CPU time 10.5 seconds
Started Dec 31 12:36:00 PM PST 23
Finished Dec 31 12:36:37 PM PST 23
Peak memory 218044 kb
Host smart-334d1bf9-cb69-4eb3-aed1-9f4acd420d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075684558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.1075684558
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.325933933
Short name T74
Test name
Test status
Simulation time 20389059 ps
CPU time 0.97 seconds
Started Dec 31 12:36:04 PM PST 23
Finished Dec 31 12:36:21 PM PST 23
Peak memory 209592 kb
Host smart-f381b00d-6447-480a-9586-02f85eedcc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325933933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.325933933
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.378003892
Short name T752
Test name
Test status
Simulation time 267256194 ps
CPU time 29.83 seconds
Started Dec 31 12:35:59 PM PST 23
Finished Dec 31 12:36:46 PM PST 23
Peak memory 250988 kb
Host smart-734542b5-172d-4c0f-95d8-7374bfb28f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378003892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.378003892
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.3196852380
Short name T620
Test name
Test status
Simulation time 390523025 ps
CPU time 6.27 seconds
Started Dec 31 12:36:07 PM PST 23
Finished Dec 31 12:36:29 PM PST 23
Peak memory 250648 kb
Host smart-4c883e2b-8b2f-4188-8efe-e18cb265708b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196852380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.3196852380
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.3458322496
Short name T109
Test name
Test status
Simulation time 8986953095 ps
CPU time 199.32 seconds
Started Dec 31 12:36:01 PM PST 23
Finished Dec 31 12:39:37 PM PST 23
Peak memory 251220 kb
Host smart-37f7d3aa-1a10-4ffd-837f-a6cd73feb2c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458322496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.3458322496
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3381091595
Short name T565
Test name
Test status
Simulation time 14936071 ps
CPU time 0.97 seconds
Started Dec 31 12:35:58 PM PST 23
Finished Dec 31 12:36:17 PM PST 23
Peak memory 208288 kb
Host smart-e1c9b166-1c67-4b07-9183-60166d90a98b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381091595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.3381091595
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.2976776771
Short name T320
Test name
Test status
Simulation time 48707762 ps
CPU time 0.95 seconds
Started Dec 31 12:36:11 PM PST 23
Finished Dec 31 12:36:30 PM PST 23
Peak memory 209552 kb
Host smart-8d790676-ba97-43a3-b0db-100ace79b07d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976776771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.2976776771
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.2155690336
Short name T463
Test name
Test status
Simulation time 258144543 ps
CPU time 8.22 seconds
Started Dec 31 12:36:15 PM PST 23
Finished Dec 31 12:36:44 PM PST 23
Peak memory 218092 kb
Host smart-74722d82-f896-4310-8daf-d21339f3bffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155690336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.2155690336
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.543904779
Short name T402
Test name
Test status
Simulation time 4623790896 ps
CPU time 6.22 seconds
Started Dec 31 12:36:03 PM PST 23
Finished Dec 31 12:36:25 PM PST 23
Peak memory 209556 kb
Host smart-096bd2e7-964d-4fe5-8767-65701ca2828a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543904779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_ac
cess.543904779
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.4166284235
Short name T870
Test name
Test status
Simulation time 884608689 ps
CPU time 25.48 seconds
Started Dec 31 12:36:11 PM PST 23
Finished Dec 31 12:36:55 PM PST 23
Peak memory 217968 kb
Host smart-d76e10c6-a897-4328-8239-7375a4687ee3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166284235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.4166284235
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.2745286628
Short name T920
Test name
Test status
Simulation time 633243590 ps
CPU time 3.89 seconds
Started Dec 31 12:36:11 PM PST 23
Finished Dec 31 12:36:33 PM PST 23
Peak memory 218008 kb
Host smart-1bde0ba8-2563-410e-9340-396547b71c50
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745286628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.2745286628
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.131129596
Short name T354
Test name
Test status
Simulation time 246840685 ps
CPU time 6.66 seconds
Started Dec 31 12:36:07 PM PST 23
Finished Dec 31 12:36:29 PM PST 23
Peak memory 213008 kb
Host smart-177f609a-8c7d-4516-adf0-c85b658a1dc9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131129596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke.
131129596
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.4116420735
Short name T408
Test name
Test status
Simulation time 2676369480 ps
CPU time 87.42 seconds
Started Dec 31 12:36:00 PM PST 23
Finished Dec 31 12:37:44 PM PST 23
Peak memory 283192 kb
Host smart-0fa0cda4-15c6-43d9-82fd-491010e041fc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116420735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.4116420735
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.2700338388
Short name T678
Test name
Test status
Simulation time 454631463 ps
CPU time 13.09 seconds
Started Dec 31 12:36:14 PM PST 23
Finished Dec 31 12:36:47 PM PST 23
Peak memory 251028 kb
Host smart-3b58ca48-83e5-4f4d-927f-f03a146cd576
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700338388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.2700338388
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.3748447754
Short name T503
Test name
Test status
Simulation time 36563551 ps
CPU time 1.72 seconds
Started Dec 31 12:37:12 PM PST 23
Finished Dec 31 12:37:26 PM PST 23
Peak memory 217852 kb
Host smart-89fdaeeb-18a9-47d2-ba52-e9946569c870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748447754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.3748447754
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.1128478136
Short name T377
Test name
Test status
Simulation time 256780572 ps
CPU time 11.13 seconds
Started Dec 31 12:36:13 PM PST 23
Finished Dec 31 12:36:44 PM PST 23
Peak memory 219100 kb
Host smart-db64c521-8188-4d01-afbd-031e0a3f4ac4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128478136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.1128478136
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.2346384232
Short name T932
Test name
Test status
Simulation time 1594635435 ps
CPU time 7.3 seconds
Started Dec 31 12:36:20 PM PST 23
Finished Dec 31 12:36:47 PM PST 23
Peak memory 217960 kb
Host smart-d019425d-ea56-48f5-a7dc-e284f43e97f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346384232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.2346384232
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.66058356
Short name T751
Test name
Test status
Simulation time 540414283 ps
CPU time 9.6 seconds
Started Dec 31 12:35:57 PM PST 23
Finished Dec 31 12:36:25 PM PST 23
Peak memory 217984 kb
Host smart-6c2332c8-cced-4fd8-92ca-4467af05a0e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66058356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.66058356
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.4177429053
Short name T696
Test name
Test status
Simulation time 1082032151 ps
CPU time 10.5 seconds
Started Dec 31 12:37:07 PM PST 23
Finished Dec 31 12:37:31 PM PST 23
Peak memory 217832 kb
Host smart-464d1eb7-6a51-4954-8a36-6e231cdd39e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177429053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.4177429053
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.740328312
Short name T655
Test name
Test status
Simulation time 89506145 ps
CPU time 2.56 seconds
Started Dec 31 12:36:25 PM PST 23
Finished Dec 31 12:36:44 PM PST 23
Peak memory 214008 kb
Host smart-11895f0d-2dae-46e8-b4b8-796f497b7b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740328312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.740328312
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.1582579346
Short name T753
Test name
Test status
Simulation time 4952435088 ps
CPU time 25.91 seconds
Started Dec 31 12:36:02 PM PST 23
Finished Dec 31 12:36:45 PM PST 23
Peak memory 251056 kb
Host smart-4256038c-8478-41f6-b788-288ba9e55c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582579346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.1582579346
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.972560368
Short name T380
Test name
Test status
Simulation time 429497893 ps
CPU time 8.25 seconds
Started Dec 31 12:35:54 PM PST 23
Finished Dec 31 12:36:18 PM PST 23
Peak memory 246332 kb
Host smart-773fa74c-e54a-41ef-a49d-84829fd8fec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972560368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.972560368
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.2345785340
Short name T398
Test name
Test status
Simulation time 13827968527 ps
CPU time 90.32 seconds
Started Dec 31 12:35:54 PM PST 23
Finished Dec 31 12:37:39 PM PST 23
Peak memory 278880 kb
Host smart-ddec337a-9fce-4f20-9d73-21c6625daf8d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345785340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.2345785340
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3632862367
Short name T605
Test name
Test status
Simulation time 35257697 ps
CPU time 0.86 seconds
Started Dec 31 12:36:17 PM PST 23
Finished Dec 31 12:36:38 PM PST 23
Peak memory 208216 kb
Host smart-29085736-4d36-4e32-804e-c01073c98627
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632862367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3632862367
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.2783497602
Short name T493
Test name
Test status
Simulation time 20410698 ps
CPU time 1.14 seconds
Started Dec 31 12:36:06 PM PST 23
Finished Dec 31 12:36:25 PM PST 23
Peak memory 209596 kb
Host smart-c6d246a4-8263-4790-ad33-8d56af3f8a56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783497602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.2783497602
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.498444609
Short name T566
Test name
Test status
Simulation time 243358624 ps
CPU time 10.46 seconds
Started Dec 31 12:36:12 PM PST 23
Finished Dec 31 12:36:41 PM PST 23
Peak memory 218080 kb
Host smart-0d771e0d-29de-41ba-9246-decfe0414a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498444609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.498444609
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.651184802
Short name T733
Test name
Test status
Simulation time 205308312 ps
CPU time 3.11 seconds
Started Dec 31 12:36:17 PM PST 23
Finished Dec 31 12:36:41 PM PST 23
Peak memory 209492 kb
Host smart-7791c98d-6dca-4cc3-b79b-2e9add47beaa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651184802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_ac
cess.651184802
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.3456363798
Short name T890
Test name
Test status
Simulation time 1182463560 ps
CPU time 36.08 seconds
Started Dec 31 12:35:58 PM PST 23
Finished Dec 31 12:36:51 PM PST 23
Peak memory 218004 kb
Host smart-cee5f1e8-cb9c-4f9e-97dc-57248a10cabc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456363798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.3456363798
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.4161217893
Short name T454
Test name
Test status
Simulation time 1240741974 ps
CPU time 4.54 seconds
Started Dec 31 12:36:06 PM PST 23
Finished Dec 31 12:36:27 PM PST 23
Peak memory 218000 kb
Host smart-a4143afe-49e6-4be5-959e-bebf937cf2ad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161217893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.4161217893
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.1017081715
Short name T318
Test name
Test status
Simulation time 201175745 ps
CPU time 1.97 seconds
Started Dec 31 12:36:10 PM PST 23
Finished Dec 31 12:36:30 PM PST 23
Peak memory 212660 kb
Host smart-4de1e389-acf2-42f5-91d5-a6fa49934b29
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017081715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.1017081715
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.955127720
Short name T860
Test name
Test status
Simulation time 1215617015 ps
CPU time 37.84 seconds
Started Dec 31 12:36:40 PM PST 23
Finished Dec 31 12:37:36 PM PST 23
Peak memory 283760 kb
Host smart-382c1a74-b737-4c5d-b5c1-d0b8ff346c0f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955127720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_state_failure.955127720
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.3059852539
Short name T369
Test name
Test status
Simulation time 361791943 ps
CPU time 14.83 seconds
Started Dec 31 12:35:50 PM PST 23
Finished Dec 31 12:36:15 PM PST 23
Peak memory 247116 kb
Host smart-3f8182f1-ae68-4230-9652-ed397697a4fd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059852539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.3059852539
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.515175072
Short name T381
Test name
Test status
Simulation time 19243670 ps
CPU time 1.46 seconds
Started Dec 31 12:36:30 PM PST 23
Finished Dec 31 12:36:47 PM PST 23
Peak memory 218008 kb
Host smart-a7c5fd04-4dc2-414a-aed6-3a96f89e4274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515175072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.515175072
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.2010838899
Short name T592
Test name
Test status
Simulation time 431228450 ps
CPU time 15.85 seconds
Started Dec 31 12:36:14 PM PST 23
Finished Dec 31 12:36:50 PM PST 23
Peak memory 219104 kb
Host smart-358e488d-d9c6-4b94-88c2-9e3c457693ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010838899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.2010838899
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.4062954005
Short name T959
Test name
Test status
Simulation time 694816754 ps
CPU time 13.56 seconds
Started Dec 31 12:36:16 PM PST 23
Finished Dec 31 12:36:51 PM PST 23
Peak memory 218008 kb
Host smart-eefd0b24-6d04-4c61-962b-f56d1144d7aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062954005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.4062954005
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.2029766936
Short name T776
Test name
Test status
Simulation time 1205818564 ps
CPU time 8.85 seconds
Started Dec 31 12:35:59 PM PST 23
Finished Dec 31 12:36:25 PM PST 23
Peak memory 218008 kb
Host smart-58eaf088-ba02-4f66-ba39-377a1e01caef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029766936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
2029766936
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.1543866518
Short name T717
Test name
Test status
Simulation time 141440750 ps
CPU time 2.57 seconds
Started Dec 31 12:36:13 PM PST 23
Finished Dec 31 12:36:36 PM PST 23
Peak memory 214372 kb
Host smart-45300d8b-b31f-48bc-90a3-dbdb939a6721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543866518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.1543866518
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.1495661354
Short name T799
Test name
Test status
Simulation time 324486819 ps
CPU time 27.9 seconds
Started Dec 31 12:36:06 PM PST 23
Finished Dec 31 12:36:50 PM PST 23
Peak memory 250900 kb
Host smart-dfee2ab3-4b44-4f01-b086-3dc9583cefd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495661354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.1495661354
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.454788519
Short name T365
Test name
Test status
Simulation time 86422162 ps
CPU time 3.05 seconds
Started Dec 31 12:36:00 PM PST 23
Finished Dec 31 12:36:21 PM PST 23
Peak memory 222132 kb
Host smart-77ff1aec-b4e8-423c-a39c-3285c88e0ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454788519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.454788519
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.2562934514
Short name T813
Test name
Test status
Simulation time 19030515227 ps
CPU time 215.16 seconds
Started Dec 31 12:36:17 PM PST 23
Finished Dec 31 12:40:13 PM PST 23
Peak memory 283872 kb
Host smart-15f5c43e-2f54-41d0-bbae-9e7ae763cdc0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562934514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.2562934514
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2759095689
Short name T952
Test name
Test status
Simulation time 92958316 ps
CPU time 0.81 seconds
Started Dec 31 12:36:05 PM PST 23
Finished Dec 31 12:36:22 PM PST 23
Peak memory 208004 kb
Host smart-8f1cfdd2-a457-4613-a74a-3a0faf231e2a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759095689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.2759095689
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.2486597237
Short name T371
Test name
Test status
Simulation time 255021743 ps
CPU time 1.08 seconds
Started Dec 31 12:36:09 PM PST 23
Finished Dec 31 12:36:28 PM PST 23
Peak memory 209572 kb
Host smart-79d39eb1-4b2d-4a7b-9265-17e8149860b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486597237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.2486597237
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.1759261814
Short name T479
Test name
Test status
Simulation time 1212225445 ps
CPU time 12.47 seconds
Started Dec 31 12:35:59 PM PST 23
Finished Dec 31 12:36:29 PM PST 23
Peak memory 218076 kb
Host smart-2c416f84-0edc-4918-a7cc-66fa9458bd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759261814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.1759261814
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.2058524041
Short name T558
Test name
Test status
Simulation time 2546507905 ps
CPU time 5.5 seconds
Started Dec 31 12:36:18 PM PST 23
Finished Dec 31 12:36:44 PM PST 23
Peak memory 209688 kb
Host smart-81074dcd-b924-4586-aa38-3db601aaefe1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058524041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_a
ccess.2058524041
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.4170765254
Short name T309
Test name
Test status
Simulation time 3303390805 ps
CPU time 47.02 seconds
Started Dec 31 12:36:13 PM PST 23
Finished Dec 31 12:37:20 PM PST 23
Peak memory 218040 kb
Host smart-2b8a9078-56f6-446d-8749-5909c85df2a8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170765254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.4170765254
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.192741285
Short name T875
Test name
Test status
Simulation time 173437172 ps
CPU time 6.03 seconds
Started Dec 31 12:36:12 PM PST 23
Finished Dec 31 12:36:37 PM PST 23
Peak memory 217996 kb
Host smart-0b7a8ac2-766f-4f88-8912-a4c4e26fe603
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192741285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag
_prog_failure.192741285
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.566717035
Short name T44
Test name
Test status
Simulation time 45059797 ps
CPU time 1.32 seconds
Started Dec 31 12:36:09 PM PST 23
Finished Dec 31 12:36:28 PM PST 23
Peak memory 212376 kb
Host smart-27cdf79f-c3db-4fe1-acd5-c305c474ae00
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566717035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke.
566717035
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.1470007504
Short name T480
Test name
Test status
Simulation time 2016781345 ps
CPU time 44.68 seconds
Started Dec 31 12:36:18 PM PST 23
Finished Dec 31 12:37:23 PM PST 23
Peak memory 268276 kb
Host smart-73693fbe-cb40-4239-b67c-b5b5356bf323
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470007504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.1470007504
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.1507207012
Short name T742
Test name
Test status
Simulation time 280848263 ps
CPU time 7.99 seconds
Started Dec 31 12:36:02 PM PST 23
Finished Dec 31 12:36:27 PM PST 23
Peak memory 221360 kb
Host smart-3d67bbf9-a3c3-4dca-8b83-de9d2dae92cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507207012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.1507207012
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.431985717
Short name T482
Test name
Test status
Simulation time 68145549 ps
CPU time 3.45 seconds
Started Dec 31 12:36:15 PM PST 23
Finished Dec 31 12:36:39 PM PST 23
Peak memory 217996 kb
Host smart-d1cfe7ee-405d-415e-8b6e-1a4915f6aca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431985717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.431985717
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.1763168372
Short name T667
Test name
Test status
Simulation time 2266984780 ps
CPU time 15.02 seconds
Started Dec 31 12:36:19 PM PST 23
Finished Dec 31 12:36:54 PM PST 23
Peak memory 219172 kb
Host smart-05f5b141-d2dc-4a3c-aae1-ef539d01eb61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763168372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.1763168372
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.2497935728
Short name T345
Test name
Test status
Simulation time 785081672 ps
CPU time 8.26 seconds
Started Dec 31 12:36:23 PM PST 23
Finished Dec 31 12:36:49 PM PST 23
Peak memory 217992 kb
Host smart-1aac3df6-7178-4429-97db-2367efccc7bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497935728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.2497935728
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.3713431987
Short name T759
Test name
Test status
Simulation time 2065836704 ps
CPU time 10.63 seconds
Started Dec 31 12:36:16 PM PST 23
Finished Dec 31 12:36:48 PM PST 23
Peak memory 218104 kb
Host smart-057b2e01-79dc-49a7-a960-ba5f5b11db6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713431987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
3713431987
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.4010336181
Short name T62
Test name
Test status
Simulation time 743415411 ps
CPU time 13.8 seconds
Started Dec 31 12:36:18 PM PST 23
Finished Dec 31 12:36:52 PM PST 23
Peak memory 218032 kb
Host smart-e78830ca-411c-4e1e-a2ca-8581e36a7d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010336181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.4010336181
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.196652037
Short name T660
Test name
Test status
Simulation time 83368207 ps
CPU time 2.87 seconds
Started Dec 31 12:36:06 PM PST 23
Finished Dec 31 12:36:24 PM PST 23
Peak memory 213936 kb
Host smart-78195597-1ac5-48f3-bffa-de56b5f84bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196652037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.196652037
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.1908882373
Short name T90
Test name
Test status
Simulation time 141610203 ps
CPU time 14.56 seconds
Started Dec 31 12:36:02 PM PST 23
Finished Dec 31 12:36:33 PM PST 23
Peak memory 250968 kb
Host smart-a0ffca52-116c-4b04-9a74-bf15315f5489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908882373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.1908882373
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.127086428
Short name T886
Test name
Test status
Simulation time 83895561 ps
CPU time 6.41 seconds
Started Dec 31 12:36:22 PM PST 23
Finished Dec 31 12:36:47 PM PST 23
Peak memory 250260 kb
Host smart-ad5d6aff-f0ad-4b7f-b4ef-ab46cb497fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127086428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.127086428
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.3809580597
Short name T906
Test name
Test status
Simulation time 37895542802 ps
CPU time 198.74 seconds
Started Dec 31 12:36:14 PM PST 23
Finished Dec 31 12:39:53 PM PST 23
Peak memory 315596 kb
Host smart-699a91c8-32dd-4fef-a630-5135101eef0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809580597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.3809580597
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3344780120
Short name T462
Test name
Test status
Simulation time 16927567 ps
CPU time 0.84 seconds
Started Dec 31 12:36:25 PM PST 23
Finished Dec 31 12:36:43 PM PST 23
Peak memory 208036 kb
Host smart-94c696e0-c64b-41bf-ab23-448a690b93f2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344780120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.3344780120
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.1139863698
Short name T601
Test name
Test status
Simulation time 17104973 ps
CPU time 0.83 seconds
Started Dec 31 12:36:16 PM PST 23
Finished Dec 31 12:36:38 PM PST 23
Peak memory 209560 kb
Host smart-ed3f4c56-4afc-40dc-89e6-79b5caa1d279
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139863698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.1139863698
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.1027184985
Short name T700
Test name
Test status
Simulation time 3092611497 ps
CPU time 15.54 seconds
Started Dec 31 12:36:37 PM PST 23
Finished Dec 31 12:37:09 PM PST 23
Peak memory 218132 kb
Host smart-8cc61781-57e1-4f58-8c8d-476e9da99d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027184985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.1027184985
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.478341971
Short name T778
Test name
Test status
Simulation time 334154311 ps
CPU time 4.09 seconds
Started Dec 31 12:36:27 PM PST 23
Finished Dec 31 12:36:47 PM PST 23
Peak memory 209536 kb
Host smart-69d396a4-1e55-4f8f-bce4-bccb15c77bd0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478341971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_ac
cess.478341971
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.1034484269
Short name T472
Test name
Test status
Simulation time 5715025552 ps
CPU time 36.99 seconds
Started Dec 31 12:36:44 PM PST 23
Finished Dec 31 12:37:38 PM PST 23
Peak memory 219044 kb
Host smart-31326dc6-0629-470f-a807-c36d93b83934
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034484269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.1034484269
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.3823540956
Short name T19
Test name
Test status
Simulation time 943323712 ps
CPU time 10.86 seconds
Started Dec 31 12:35:58 PM PST 23
Finished Dec 31 12:36:27 PM PST 23
Peak memory 217972 kb
Host smart-760261e2-7cb0-443a-ab53-10c770e14e75
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823540956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.3823540956
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1942989298
Short name T729
Test name
Test status
Simulation time 522766438 ps
CPU time 12.56 seconds
Started Dec 31 12:36:14 PM PST 23
Finished Dec 31 12:36:47 PM PST 23
Peak memory 213152 kb
Host smart-fcdf9dba-6f40-4448-8379-64ad02887fb6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942989298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.1942989298
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3187937243
Short name T329
Test name
Test status
Simulation time 16472251892 ps
CPU time 98.99 seconds
Started Dec 31 12:36:11 PM PST 23
Finished Dec 31 12:38:09 PM PST 23
Peak memory 283864 kb
Host smart-d04687b2-7f3c-48f5-8562-77992b054d2d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187937243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.3187937243
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.1285138385
Short name T770
Test name
Test status
Simulation time 3294204582 ps
CPU time 10.5 seconds
Started Dec 31 12:36:16 PM PST 23
Finished Dec 31 12:36:48 PM PST 23
Peak memory 247264 kb
Host smart-8c216080-accd-4d1f-a04f-2f8a84e0d564
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285138385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.1285138385
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.748963396
Short name T651
Test name
Test status
Simulation time 145291373 ps
CPU time 2.81 seconds
Started Dec 31 12:36:17 PM PST 23
Finished Dec 31 12:36:40 PM PST 23
Peak memory 218056 kb
Host smart-d1c0a3d1-cae0-4b5a-b2f4-975e4ce35b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748963396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.748963396
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.609684123
Short name T513
Test name
Test status
Simulation time 295415858 ps
CPU time 13.37 seconds
Started Dec 31 12:36:27 PM PST 23
Finished Dec 31 12:36:56 PM PST 23
Peak memory 219072 kb
Host smart-159c0e0c-1fd3-4799-8404-8be86fd229de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609684123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.609684123
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.1144331910
Short name T351
Test name
Test status
Simulation time 317277978 ps
CPU time 12.85 seconds
Started Dec 31 12:35:59 PM PST 23
Finished Dec 31 12:36:29 PM PST 23
Peak memory 218000 kb
Host smart-f0838bcb-eff4-4abf-a508-dc23300adfb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144331910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.1144331910
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.628824963
Short name T68
Test name
Test status
Simulation time 1455555731 ps
CPU time 9.7 seconds
Started Dec 31 12:36:24 PM PST 23
Finished Dec 31 12:36:51 PM PST 23
Peak memory 218080 kb
Host smart-226c1efd-daa3-41b1-be6e-f92b20530da2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628824963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.628824963
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.3720526554
Short name T417
Test name
Test status
Simulation time 524762243 ps
CPU time 9.72 seconds
Started Dec 31 12:36:27 PM PST 23
Finished Dec 31 12:36:53 PM PST 23
Peak memory 218064 kb
Host smart-e446bd48-26f0-4eba-9033-c4583dda055b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720526554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3720526554
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.1885914213
Short name T839
Test name
Test status
Simulation time 120937696 ps
CPU time 1.98 seconds
Started Dec 31 12:36:03 PM PST 23
Finished Dec 31 12:36:22 PM PST 23
Peak memory 213440 kb
Host smart-8aa93bad-1325-4391-b3d7-c6c178d7a977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885914213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1885914213
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.3143744494
Short name T115
Test name
Test status
Simulation time 262014049 ps
CPU time 27.26 seconds
Started Dec 31 12:36:36 PM PST 23
Finished Dec 31 12:37:20 PM PST 23
Peak memory 251000 kb
Host smart-3c929b34-db1d-4268-a9ae-4aac5e44b81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143744494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.3143744494
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.2730519016
Short name T754
Test name
Test status
Simulation time 63876781 ps
CPU time 5.8 seconds
Started Dec 31 12:36:01 PM PST 23
Finished Dec 31 12:36:24 PM PST 23
Peak memory 246380 kb
Host smart-8feab205-c59b-4e43-bc43-48aab0bac952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730519016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.2730519016
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.1462923170
Short name T420
Test name
Test status
Simulation time 1224972920 ps
CPU time 23.44 seconds
Started Dec 31 12:35:58 PM PST 23
Finished Dec 31 12:36:40 PM PST 23
Peak memory 251000 kb
Host smart-de0b427b-8d2c-421f-8c21-dc3d51454044
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462923170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.1462923170
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.1717093604
Short name T441
Test name
Test status
Simulation time 21727883 ps
CPU time 0.86 seconds
Started Dec 31 12:36:14 PM PST 23
Finished Dec 31 12:36:35 PM PST 23
Peak memory 208020 kb
Host smart-20c86c0f-376d-4346-834d-86aac420152e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717093604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.1717093604
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.920496306
Short name T475
Test name
Test status
Simulation time 105981183 ps
CPU time 0.82 seconds
Started Dec 31 12:36:33 PM PST 23
Finished Dec 31 12:36:49 PM PST 23
Peak memory 208180 kb
Host smart-a8c5844e-06d4-4d75-9057-de95338a8db9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920496306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.920496306
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.1834156104
Short name T672
Test name
Test status
Simulation time 278925618 ps
CPU time 8.36 seconds
Started Dec 31 12:36:03 PM PST 23
Finished Dec 31 12:36:28 PM PST 23
Peak memory 218020 kb
Host smart-e4ecd934-b913-496e-bf63-7d0550222158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834156104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1834156104
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.2954556570
Short name T28
Test name
Test status
Simulation time 97550630 ps
CPU time 1.65 seconds
Started Dec 31 12:36:33 PM PST 23
Finished Dec 31 12:36:50 PM PST 23
Peak memory 209620 kb
Host smart-a128c755-fbe7-4535-8aab-82b7ef398563
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954556570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_a
ccess.2954556570
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.2806017723
Short name T469
Test name
Test status
Simulation time 15388845973 ps
CPU time 64.55 seconds
Started Dec 31 12:36:10 PM PST 23
Finished Dec 31 12:37:33 PM PST 23
Peak memory 219288 kb
Host smart-fe1588c5-2dfc-4b29-9105-6e7f51fed85b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806017723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.2806017723
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1625468655
Short name T560
Test name
Test status
Simulation time 905812876 ps
CPU time 6.39 seconds
Started Dec 31 12:36:09 PM PST 23
Finished Dec 31 12:36:43 PM PST 23
Peak memory 218008 kb
Host smart-56673f4a-dc4b-4198-9aa9-265fe47fccc5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625468655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1625468655
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.56432748
Short name T610
Test name
Test status
Simulation time 233862504 ps
CPU time 3.69 seconds
Started Dec 31 12:36:01 PM PST 23
Finished Dec 31 12:36:22 PM PST 23
Peak memory 212992 kb
Host smart-85c55fea-06e5-4d87-93f5-5a543d91d9d5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56432748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke.56432748
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.1051755332
Short name T542
Test name
Test status
Simulation time 1757738717 ps
CPU time 69 seconds
Started Dec 31 12:36:13 PM PST 23
Finished Dec 31 12:37:42 PM PST 23
Peak memory 269604 kb
Host smart-16942505-b3bd-461c-8a51-1799b32cc28f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051755332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.1051755332
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.2519636025
Short name T705
Test name
Test status
Simulation time 680128933 ps
CPU time 7.79 seconds
Started Dec 31 12:36:21 PM PST 23
Finished Dec 31 12:36:48 PM PST 23
Peak memory 222748 kb
Host smart-b9246138-41c7-4130-bebe-072ea6e9a621
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519636025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.2519636025
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.31803615
Short name T582
Test name
Test status
Simulation time 35989603 ps
CPU time 2.09 seconds
Started Dec 31 12:36:11 PM PST 23
Finished Dec 31 12:36:32 PM PST 23
Peak memory 218084 kb
Host smart-983b0463-694b-41ac-b41c-c2388f7433c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31803615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.31803615
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.1708294785
Short name T445
Test name
Test status
Simulation time 194463964 ps
CPU time 7.11 seconds
Started Dec 31 12:36:28 PM PST 23
Finished Dec 31 12:36:51 PM PST 23
Peak memory 218052 kb
Host smart-3e41585b-cb67-4bf8-a77b-e7cde2fc2a16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708294785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1708294785
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.1285482554
Short name T803
Test name
Test status
Simulation time 349826687 ps
CPU time 14.83 seconds
Started Dec 31 12:36:25 PM PST 23
Finished Dec 31 12:36:57 PM PST 23
Peak memory 217992 kb
Host smart-b6386d3b-44b5-45c6-8f5c-2230965b3eeb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285482554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.1285482554
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.1067169873
Short name T743
Test name
Test status
Simulation time 373871788 ps
CPU time 13.69 seconds
Started Dec 31 12:36:13 PM PST 23
Finished Dec 31 12:36:47 PM PST 23
Peak memory 218040 kb
Host smart-70a78798-a605-47c6-9329-4995ff5abc1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067169873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
1067169873
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.787980061
Short name T81
Test name
Test status
Simulation time 325183977 ps
CPU time 2.39 seconds
Started Dec 31 12:36:10 PM PST 23
Finished Dec 31 12:36:30 PM PST 23
Peak memory 213932 kb
Host smart-5c631785-966a-4c33-85cb-172c810157c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787980061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.787980061
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.1397535690
Short name T484
Test name
Test status
Simulation time 1788198671 ps
CPU time 30.55 seconds
Started Dec 31 12:36:20 PM PST 23
Finished Dec 31 12:37:10 PM PST 23
Peak memory 251012 kb
Host smart-d56bdfe2-c6ad-4ad7-856e-12b9bcaf780f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397535690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.1397535690
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.2062142754
Short name T367
Test name
Test status
Simulation time 267814151 ps
CPU time 7.86 seconds
Started Dec 31 12:36:02 PM PST 23
Finished Dec 31 12:36:27 PM PST 23
Peak memory 250592 kb
Host smart-374a9302-cc61-45e9-b57d-b2a8df98a278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062142754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.2062142754
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.41898367
Short name T563
Test name
Test status
Simulation time 7818112355 ps
CPU time 142.89 seconds
Started Dec 31 12:36:22 PM PST 23
Finished Dec 31 12:39:03 PM PST 23
Peak memory 283944 kb
Host smart-f5247f7f-f412-4d39-8fd1-adf752e4ef74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41898367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.lc_ctrl_stress_all.41898367
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3938317903
Short name T47
Test name
Test status
Simulation time 30658884 ps
CPU time 0.74 seconds
Started Dec 31 12:35:59 PM PST 23
Finished Dec 31 12:36:17 PM PST 23
Peak memory 208064 kb
Host smart-dafa9abd-250a-47cc-8e09-883630850f3a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938317903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.3938317903
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.2391710108
Short name T800
Test name
Test status
Simulation time 17163198 ps
CPU time 1.09 seconds
Started Dec 31 12:36:27 PM PST 23
Finished Dec 31 12:36:44 PM PST 23
Peak memory 209556 kb
Host smart-db288d65-a8b8-498b-887f-0152c5d23ec8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391710108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.2391710108
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.2605839143
Short name T749
Test name
Test status
Simulation time 636519080 ps
CPU time 10.79 seconds
Started Dec 31 12:36:03 PM PST 23
Finished Dec 31 12:36:31 PM PST 23
Peak memory 218080 kb
Host smart-406e56cf-f259-45d1-96dc-5a1319149540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605839143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.2605839143
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.3957112305
Short name T496
Test name
Test status
Simulation time 150873943 ps
CPU time 2.56 seconds
Started Dec 31 12:36:04 PM PST 23
Finished Dec 31 12:36:23 PM PST 23
Peak memory 209592 kb
Host smart-1f6b5891-222d-4dd5-b8f2-bf62303ef88d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957112305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_a
ccess.3957112305
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.350699556
Short name T771
Test name
Test status
Simulation time 8605846706 ps
CPU time 60.55 seconds
Started Dec 31 12:36:08 PM PST 23
Finished Dec 31 12:37:25 PM PST 23
Peak memory 219060 kb
Host smart-8116d097-bfec-4bcb-8e32-ae01ce1d6cca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350699556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_er
rors.350699556
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.2326055416
Short name T903
Test name
Test status
Simulation time 2402163490 ps
CPU time 6.85 seconds
Started Dec 31 12:36:16 PM PST 23
Finished Dec 31 12:36:44 PM PST 23
Peak memory 218064 kb
Host smart-62d75519-8668-4783-8683-ddbe8821d7a7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326055416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.2326055416
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.722858386
Short name T879
Test name
Test status
Simulation time 139850710 ps
CPU time 4.29 seconds
Started Dec 31 12:36:33 PM PST 23
Finished Dec 31 12:36:54 PM PST 23
Peak memory 212948 kb
Host smart-f617963b-7034-4a90-879d-c779446c9207
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722858386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.
722858386
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.215807288
Short name T590
Test name
Test status
Simulation time 6067966333 ps
CPU time 58.16 seconds
Started Dec 31 12:36:16 PM PST 23
Finished Dec 31 12:37:35 PM PST 23
Peak memory 252028 kb
Host smart-fce8f4f1-bb4d-4233-949a-e3e1bcd65562
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215807288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_state_failure.215807288
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.2533293529
Short name T790
Test name
Test status
Simulation time 921185549 ps
CPU time 13.25 seconds
Started Dec 31 12:36:34 PM PST 23
Finished Dec 31 12:37:04 PM PST 23
Peak memory 225368 kb
Host smart-83c4e330-bb72-4ddf-a694-9b9a8b2200c8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533293529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.2533293529
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.1709065449
Short name T616
Test name
Test status
Simulation time 313769252 ps
CPU time 2.11 seconds
Started Dec 31 12:36:20 PM PST 23
Finished Dec 31 12:36:41 PM PST 23
Peak memory 218412 kb
Host smart-fb21a8a0-d46e-4e3f-b615-cb31e53aa96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709065449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1709065449
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.4235025103
Short name T644
Test name
Test status
Simulation time 1191993822 ps
CPU time 7.54 seconds
Started Dec 31 12:36:44 PM PST 23
Finished Dec 31 12:37:09 PM PST 23
Peak memory 218092 kb
Host smart-892c6f09-9f4b-492f-a5c1-7a67aff7746a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235025103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.4235025103
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2561456827
Short name T416
Test name
Test status
Simulation time 507722411 ps
CPU time 11.01 seconds
Started Dec 31 12:36:33 PM PST 23
Finished Dec 31 12:37:01 PM PST 23
Peak memory 218016 kb
Host smart-c73e06d7-8d9d-46dd-adae-4723c563135d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561456827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2561456827
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.3207343836
Short name T515
Test name
Test status
Simulation time 344014518 ps
CPU time 9.17 seconds
Started Dec 31 12:36:16 PM PST 23
Finished Dec 31 12:36:46 PM PST 23
Peak memory 218136 kb
Host smart-229bdbc0-d2ad-4f8c-995c-a29cab401f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207343836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3207343836
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.2210205509
Short name T65
Test name
Test status
Simulation time 32245161 ps
CPU time 2.18 seconds
Started Dec 31 12:36:12 PM PST 23
Finished Dec 31 12:36:34 PM PST 23
Peak memory 213920 kb
Host smart-6d37779d-ca2f-4634-8e06-e8b8ded99f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210205509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2210205509
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.2813572538
Short name T527
Test name
Test status
Simulation time 884780320 ps
CPU time 27.59 seconds
Started Dec 31 12:36:35 PM PST 23
Finished Dec 31 12:37:19 PM PST 23
Peak memory 250988 kb
Host smart-60c91a05-2c3d-42f0-8d23-b0c63359d0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813572538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.2813572538
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.1679022018
Short name T476
Test name
Test status
Simulation time 339233171 ps
CPU time 6.96 seconds
Started Dec 31 12:36:22 PM PST 23
Finished Dec 31 12:36:48 PM PST 23
Peak memory 246088 kb
Host smart-7aa83570-95e4-4ea2-8409-a0923bf1cc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679022018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.1679022018
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.2639401627
Short name T581
Test name
Test status
Simulation time 2382137039 ps
CPU time 81.09 seconds
Started Dec 31 12:36:16 PM PST 23
Finished Dec 31 12:37:58 PM PST 23
Peak memory 251496 kb
Host smart-897525e3-e35f-4948-9758-a6d67c7be6a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639401627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.2639401627
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3587639206
Short name T707
Test name
Test status
Simulation time 12356269 ps
CPU time 0.89 seconds
Started Dec 31 12:36:24 PM PST 23
Finished Dec 31 12:36:42 PM PST 23
Peak memory 208276 kb
Host smart-07b8bf72-9ec5-46bd-8e7d-d42ba45d636d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587639206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.3587639206
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.2786816694
Short name T745
Test name
Test status
Simulation time 57555152 ps
CPU time 1.01 seconds
Started Dec 31 12:36:12 PM PST 23
Finished Dec 31 12:36:32 PM PST 23
Peak memory 208376 kb
Host smart-61cb5453-7c5a-42a8-a1ea-96970c1769c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786816694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.2786816694
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.262190195
Short name T587
Test name
Test status
Simulation time 211448740 ps
CPU time 7.8 seconds
Started Dec 31 12:36:36 PM PST 23
Finished Dec 31 12:37:01 PM PST 23
Peak memory 218044 kb
Host smart-9292e235-927c-440e-9348-0a5bfb5d0992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262190195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.262190195
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.2842276256
Short name T449
Test name
Test status
Simulation time 294916136 ps
CPU time 3.05 seconds
Started Dec 31 12:36:23 PM PST 23
Finished Dec 31 12:36:44 PM PST 23
Peak memory 209528 kb
Host smart-0c5dd794-60fe-47e4-be9b-f830135040b7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842276256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_a
ccess.2842276256
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.2453407393
Short name T429
Test name
Test status
Simulation time 8616883844 ps
CPU time 30.07 seconds
Started Dec 31 12:36:12 PM PST 23
Finished Dec 31 12:37:01 PM PST 23
Peak memory 218180 kb
Host smart-fc0a6324-7ba4-41f4-af6e-524ec17b27f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453407393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.2453407393
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3517857915
Short name T665
Test name
Test status
Simulation time 1778589917 ps
CPU time 8.58 seconds
Started Dec 31 12:36:24 PM PST 23
Finished Dec 31 12:36:50 PM PST 23
Peak memory 218020 kb
Host smart-0c502629-ce07-4f4c-af31-32d0e4744429
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517857915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.3517857915
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.1601818888
Short name T787
Test name
Test status
Simulation time 2507434187 ps
CPU time 15.53 seconds
Started Dec 31 12:36:26 PM PST 23
Finished Dec 31 12:36:58 PM PST 23
Peak memory 213636 kb
Host smart-755b9414-044c-4fb4-b822-16d0eb332e24
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601818888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.1601818888
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.3228554266
Short name T338
Test name
Test status
Simulation time 12628320182 ps
CPU time 130.97 seconds
Started Dec 31 12:36:14 PM PST 23
Finished Dec 31 12:38:47 PM PST 23
Peak memory 283784 kb
Host smart-dcdf2491-c9e8-43b2-a0fb-ea8b20f54c9a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228554266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.3228554266
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.3237285989
Short name T937
Test name
Test status
Simulation time 2091763768 ps
CPU time 20.53 seconds
Started Dec 31 12:36:09 PM PST 23
Finished Dec 31 12:36:46 PM PST 23
Peak memory 250968 kb
Host smart-53c34d88-4813-46c2-8f5e-b960c969eb0d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237285989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.3237285989
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.2801962406
Short name T691
Test name
Test status
Simulation time 58139400 ps
CPU time 1.57 seconds
Started Dec 31 12:36:16 PM PST 23
Finished Dec 31 12:36:39 PM PST 23
Peak memory 218096 kb
Host smart-134f4cc0-c700-4d43-b21e-34760273fa5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801962406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.2801962406
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.36504625
Short name T688
Test name
Test status
Simulation time 1547676064 ps
CPU time 10.67 seconds
Started Dec 31 12:36:29 PM PST 23
Finished Dec 31 12:36:55 PM PST 23
Peak memory 219092 kb
Host smart-9f897ae0-86a7-4aef-ad74-92fe15568e1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36504625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.36504625
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.628900675
Short name T794
Test name
Test status
Simulation time 484173079 ps
CPU time 8.74 seconds
Started Dec 31 12:36:18 PM PST 23
Finished Dec 31 12:36:47 PM PST 23
Peak memory 217920 kb
Host smart-d9eab5c8-d233-4932-8b7f-006af55dfa99
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628900675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_di
gest.628900675
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.2662276342
Short name T389
Test name
Test status
Simulation time 2136429665 ps
CPU time 15.89 seconds
Started Dec 31 12:36:00 PM PST 23
Finished Dec 31 12:36:33 PM PST 23
Peak memory 218116 kb
Host smart-430d5d91-fc05-42ea-9176-83b7d0b9cc26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662276342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
2662276342
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.2463614207
Short name T185
Test name
Test status
Simulation time 615691043 ps
CPU time 15.61 seconds
Started Dec 31 12:36:33 PM PST 23
Finished Dec 31 12:37:05 PM PST 23
Peak memory 218052 kb
Host smart-214f519d-16bf-4d9b-b2ae-ead330508541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463614207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2463614207
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.2891648632
Short name T78
Test name
Test status
Simulation time 56101289 ps
CPU time 1.9 seconds
Started Dec 31 12:36:24 PM PST 23
Finished Dec 31 12:36:43 PM PST 23
Peak memory 213704 kb
Host smart-91ebc663-e43b-4698-8725-b346841e31cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891648632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.2891648632
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.4067241315
Short name T577
Test name
Test status
Simulation time 2357057663 ps
CPU time 29.24 seconds
Started Dec 31 12:36:53 PM PST 23
Finished Dec 31 12:37:37 PM PST 23
Peak memory 251172 kb
Host smart-b3766c62-00e2-430e-bd81-26958973593f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067241315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.4067241315
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.3188117564
Short name T744
Test name
Test status
Simulation time 225162746 ps
CPU time 8.04 seconds
Started Dec 31 12:36:17 PM PST 23
Finished Dec 31 12:36:45 PM PST 23
Peak memory 251068 kb
Host smart-9d52afe1-b84e-4906-88d7-0df0da2b4fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188117564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.3188117564
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.495794412
Short name T900
Test name
Test status
Simulation time 9138609339 ps
CPU time 109.99 seconds
Started Dec 31 12:36:16 PM PST 23
Finished Dec 31 12:38:27 PM PST 23
Peak memory 283748 kb
Host smart-853fc843-a4a8-42c5-a914-55a8833abed1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495794412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.495794412
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.1030773724
Short name T977
Test name
Test status
Simulation time 4844908307 ps
CPU time 118.7 seconds
Started Dec 31 12:36:14 PM PST 23
Finished Dec 31 12:38:33 PM PST 23
Peak memory 279184 kb
Host smart-ad63ed7d-6815-4c26-9cbe-afe3a46cb78d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1030773724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.1030773724
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.1383798558
Short name T597
Test name
Test status
Simulation time 15693105 ps
CPU time 0.76 seconds
Started Dec 31 12:36:31 PM PST 23
Finished Dec 31 12:36:47 PM PST 23
Peak memory 208380 kb
Host smart-7ebe72e1-7997-492e-a29c-b651ce54e298
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383798558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.1383798558
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.1310741507
Short name T490
Test name
Test status
Simulation time 45449955 ps
CPU time 1.11 seconds
Started Dec 31 12:36:13 PM PST 23
Finished Dec 31 12:36:34 PM PST 23
Peak memory 209652 kb
Host smart-f74bf5cc-2128-4873-9e73-4f5292ed496e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310741507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.1310741507
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.3767013277
Short name T49
Test name
Test status
Simulation time 1160248714 ps
CPU time 11.15 seconds
Started Dec 31 12:36:10 PM PST 23
Finished Dec 31 12:36:39 PM PST 23
Peak memory 218044 kb
Host smart-c870366a-5a5a-4c66-a1bc-fcfd2ea4f015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767013277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.3767013277
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.944353213
Short name T485
Test name
Test status
Simulation time 829124880 ps
CPU time 19.13 seconds
Started Dec 31 12:36:34 PM PST 23
Finished Dec 31 12:37:09 PM PST 23
Peak memory 209468 kb
Host smart-9237317a-ae66-4f90-8c2f-4d17098f4699
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944353213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_ac
cess.944353213
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.372506767
Short name T715
Test name
Test status
Simulation time 4812072241 ps
CPU time 28.5 seconds
Started Dec 31 12:36:09 PM PST 23
Finished Dec 31 12:36:54 PM PST 23
Peak memory 218272 kb
Host smart-cf631cbf-5bff-4003-af4c-b78c5f405053
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372506767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_er
rors.372506767
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.2680553746
Short name T793
Test name
Test status
Simulation time 524737180 ps
CPU time 14.27 seconds
Started Dec 31 12:36:25 PM PST 23
Finished Dec 31 12:36:56 PM PST 23
Peak memory 218024 kb
Host smart-e938af4d-6f5f-45df-bc1d-9ea39a867363
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680553746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.2680553746
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.2090558164
Short name T965
Test name
Test status
Simulation time 184865490 ps
CPU time 2.7 seconds
Started Dec 31 12:36:05 PM PST 23
Finished Dec 31 12:36:24 PM PST 23
Peak memory 212868 kb
Host smart-0594472d-0388-40d9-8849-10e3de30a952
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090558164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.2090558164
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.2773051929
Short name T564
Test name
Test status
Simulation time 4821744238 ps
CPU time 32.61 seconds
Started Dec 31 12:36:10 PM PST 23
Finished Dec 31 12:37:00 PM PST 23
Peak memory 251092 kb
Host smart-8b557737-adf7-4e44-b7f1-351bdf8c0fec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773051929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.2773051929
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.2031081747
Short name T986
Test name
Test status
Simulation time 780914367 ps
CPU time 19.53 seconds
Started Dec 31 12:36:06 PM PST 23
Finished Dec 31 12:36:42 PM PST 23
Peak memory 222672 kb
Host smart-63035ad9-3cb6-4b2d-8b37-35b743197670
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031081747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.2031081747
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.824044937
Short name T802
Test name
Test status
Simulation time 381782506 ps
CPU time 3.18 seconds
Started Dec 31 12:36:27 PM PST 23
Finished Dec 31 12:36:46 PM PST 23
Peak memory 218056 kb
Host smart-5fcd8624-4f4b-4d06-a54b-a0e939930d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824044937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.824044937
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.926111272
Short name T857
Test name
Test status
Simulation time 7682880720 ps
CPU time 16.87 seconds
Started Dec 31 12:36:09 PM PST 23
Finished Dec 31 12:36:44 PM PST 23
Peak memory 218096 kb
Host smart-11669866-2c08-4f7f-aad7-027ebc4ee0d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926111272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_di
gest.926111272
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.1057963833
Short name T600
Test name
Test status
Simulation time 729628688 ps
CPU time 7.64 seconds
Started Dec 31 12:36:46 PM PST 23
Finished Dec 31 12:37:10 PM PST 23
Peak memory 218012 kb
Host smart-51481708-b71b-4ca5-a388-1a7264eb0172
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057963833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
1057963833
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.1661949708
Short name T356
Test name
Test status
Simulation time 251522513 ps
CPU time 8.57 seconds
Started Dec 31 12:36:18 PM PST 23
Finished Dec 31 12:36:47 PM PST 23
Peak memory 218068 kb
Host smart-234e19d8-e9c0-437e-a808-6477d93874b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661949708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.1661949708
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.2509337412
Short name T368
Test name
Test status
Simulation time 104694284 ps
CPU time 1.94 seconds
Started Dec 31 12:36:29 PM PST 23
Finished Dec 31 12:36:46 PM PST 23
Peak memory 213540 kb
Host smart-36198e24-5212-4102-bdc0-77d006960759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509337412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.2509337412
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.3993252394
Short name T881
Test name
Test status
Simulation time 1216941304 ps
CPU time 17.78 seconds
Started Dec 31 12:36:08 PM PST 23
Finished Dec 31 12:36:42 PM PST 23
Peak memory 250940 kb
Host smart-d18d1077-9c1d-45a3-88b7-176f31c18b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993252394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.3993252394
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.2275331668
Short name T730
Test name
Test status
Simulation time 84688600 ps
CPU time 8.02 seconds
Started Dec 31 12:36:18 PM PST 23
Finished Dec 31 12:36:46 PM PST 23
Peak memory 251068 kb
Host smart-99e08d8a-6bba-4d3f-b1a2-adba5a068c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275331668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.2275331668
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.2692130005
Short name T760
Test name
Test status
Simulation time 20029430558 ps
CPU time 145.02 seconds
Started Dec 31 12:36:43 PM PST 23
Finished Dec 31 12:39:25 PM PST 23
Peak memory 250504 kb
Host smart-a7d090fc-40ad-4285-8222-80adcc8aef5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692130005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.2692130005
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3353295434
Short name T555
Test name
Test status
Simulation time 163178746 ps
CPU time 0.89 seconds
Started Dec 31 12:36:13 PM PST 23
Finished Dec 31 12:36:34 PM PST 23
Peak memory 208476 kb
Host smart-6990e71e-3f9b-456d-aa61-13a24e8bbd84
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353295434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.3353295434
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.3553929658
Short name T444
Test name
Test status
Simulation time 50911535 ps
CPU time 0.93 seconds
Started Dec 31 12:35:58 PM PST 23
Finished Dec 31 12:36:16 PM PST 23
Peak memory 209572 kb
Host smart-62a2a519-5f14-4b50-8b94-7548207ab87e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553929658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.3553929658
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.3544406240
Short name T571
Test name
Test status
Simulation time 19960103 ps
CPU time 0.76 seconds
Started Dec 31 12:35:45 PM PST 23
Finished Dec 31 12:35:54 PM PST 23
Peak memory 209288 kb
Host smart-101dd611-bbdf-4591-9cac-b253616b20bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544406240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.3544406240
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.4151399429
Short name T550
Test name
Test status
Simulation time 245944247 ps
CPU time 11.91 seconds
Started Dec 31 12:36:05 PM PST 23
Finished Dec 31 12:36:34 PM PST 23
Peak memory 218056 kb
Host smart-d21f663b-4b17-4e61-8aec-407c6fc0187a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151399429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.4151399429
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.1607986267
Short name T325
Test name
Test status
Simulation time 80879500 ps
CPU time 1.35 seconds
Started Dec 31 12:35:53 PM PST 23
Finished Dec 31 12:36:08 PM PST 23
Peak memory 209504 kb
Host smart-2a66f62f-1e33-4cf9-91d6-bf569bac6bc6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607986267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_ac
cess.1607986267
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.3033660191
Short name T831
Test name
Test status
Simulation time 1940094238 ps
CPU time 25.57 seconds
Started Dec 31 12:35:40 PM PST 23
Finished Dec 31 12:36:09 PM PST 23
Peak memory 218000 kb
Host smart-72108947-fc4d-4de9-89ad-9657059adc6c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033660191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.3033660191
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.2649813886
Short name T833
Test name
Test status
Simulation time 2843521773 ps
CPU time 60.65 seconds
Started Dec 31 12:35:42 PM PST 23
Finished Dec 31 12:36:46 PM PST 23
Peak memory 217776 kb
Host smart-2147008f-7f04-4473-a004-53458610a290
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649813886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_
priority.2649813886
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.4026790614
Short name T16
Test name
Test status
Simulation time 506122258 ps
CPU time 6.9 seconds
Started Dec 31 12:35:56 PM PST 23
Finished Dec 31 12:36:20 PM PST 23
Peak memory 218108 kb
Host smart-e2fa814a-4d87-45c7-8a99-492be730f5e3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026790614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.4026790614
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1372622794
Short name T85
Test name
Test status
Simulation time 478814087 ps
CPU time 12.87 seconds
Started Dec 31 12:35:49 PM PST 23
Finished Dec 31 12:36:13 PM PST 23
Peak memory 212824 kb
Host smart-99faee84-7414-48f7-89e2-fd429c26994e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372622794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.1372622794
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.3938879277
Short name T604
Test name
Test status
Simulation time 1585547899 ps
CPU time 9.98 seconds
Started Dec 31 12:36:15 PM PST 23
Finished Dec 31 12:36:46 PM PST 23
Peak memory 213132 kb
Host smart-b0347ff3-25e4-4a2f-8fdb-c46ff63e5e03
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938879277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
3938879277
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.964361974
Short name T973
Test name
Test status
Simulation time 2462804309 ps
CPU time 45.18 seconds
Started Dec 31 12:35:46 PM PST 23
Finished Dec 31 12:36:42 PM PST 23
Peak memory 267368 kb
Host smart-e89882bb-bce0-4111-9094-5743a97c8176
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964361974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_state_failure.964361974
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.720471509
Short name T361
Test name
Test status
Simulation time 431990352 ps
CPU time 13.2 seconds
Started Dec 31 12:35:47 PM PST 23
Finished Dec 31 12:36:11 PM PST 23
Peak memory 221708 kb
Host smart-f729905c-30c7-4f87-a537-39a290f70199
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720471509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_state_post_trans.720471509
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.1410014871
Short name T681
Test name
Test status
Simulation time 291050989 ps
CPU time 1.86 seconds
Started Dec 31 12:35:56 PM PST 23
Finished Dec 31 12:36:15 PM PST 23
Peak memory 218068 kb
Host smart-ec87e5f2-ba51-4e38-b258-ce34e4803940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410014871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.1410014871
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.973218768
Short name T73
Test name
Test status
Simulation time 580187221 ps
CPU time 7.42 seconds
Started Dec 31 12:35:25 PM PST 23
Finished Dec 31 12:35:33 PM PST 23
Peak memory 213992 kb
Host smart-e90cde8a-3c4e-4949-96c9-6056b1a6baf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973218768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.973218768
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.3075579572
Short name T936
Test name
Test status
Simulation time 3112261883 ps
CPU time 16.66 seconds
Started Dec 31 12:36:00 PM PST 23
Finished Dec 31 12:36:33 PM PST 23
Peak memory 219144 kb
Host smart-82df1fbe-4fdb-49bd-8eef-b5319d61506b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075579572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.3075579572
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.2008567447
Short name T904
Test name
Test status
Simulation time 554033013 ps
CPU time 23.19 seconds
Started Dec 31 12:35:59 PM PST 23
Finished Dec 31 12:36:40 PM PST 23
Peak memory 218004 kb
Host smart-b079c295-3a5c-415f-9921-c7e640f956b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008567447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.2008567447
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.2637093657
Short name T349
Test name
Test status
Simulation time 534496433 ps
CPU time 10.34 seconds
Started Dec 31 12:35:56 PM PST 23
Finished Dec 31 12:36:23 PM PST 23
Peak memory 217976 kb
Host smart-cd0877d3-d29c-49be-925e-d2c672f21644
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637093657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.2
637093657
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.2137840184
Short name T435
Test name
Test status
Simulation time 988005907 ps
CPU time 7.94 seconds
Started Dec 31 12:35:37 PM PST 23
Finished Dec 31 12:35:46 PM PST 23
Peak memory 218076 kb
Host smart-2066ab46-a588-4b23-84d1-247a501c2c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137840184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.2137840184
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.2743672200
Short name T698
Test name
Test status
Simulation time 280054141 ps
CPU time 2.8 seconds
Started Dec 31 12:35:53 PM PST 23
Finished Dec 31 12:36:19 PM PST 23
Peak memory 213884 kb
Host smart-ef8176c7-b933-4b98-bff9-ae21fcaf8ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743672200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.2743672200
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.3051985349
Short name T680
Test name
Test status
Simulation time 693630466 ps
CPU time 22.15 seconds
Started Dec 31 12:36:07 PM PST 23
Finished Dec 31 12:36:45 PM PST 23
Peak memory 250992 kb
Host smart-891d4a76-682e-452f-9bae-c5c8c557cab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051985349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.3051985349
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.2314832291
Short name T826
Test name
Test status
Simulation time 71163615 ps
CPU time 6.4 seconds
Started Dec 31 12:36:01 PM PST 23
Finished Dec 31 12:36:24 PM PST 23
Peak memory 246292 kb
Host smart-5c86dca3-1cff-47be-b5a0-727f246e14d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314832291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.2314832291
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.93727046
Short name T789
Test name
Test status
Simulation time 14190141 ps
CPU time 0.77 seconds
Started Dec 31 12:36:02 PM PST 23
Finished Dec 31 12:36:20 PM PST 23
Peak memory 208224 kb
Host smart-28cff72a-80b7-44ea-ae31-c80aa5b5d55c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93727046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_volatile_unlock_smoke.93727046
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.1175506917
Short name T593
Test name
Test status
Simulation time 116743732 ps
CPU time 0.97 seconds
Started Dec 31 12:36:29 PM PST 23
Finished Dec 31 12:36:45 PM PST 23
Peak memory 209632 kb
Host smart-5dd03bad-605b-4049-af98-deb21a5fc7e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175506917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.1175506917
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.3670656216
Short name T786
Test name
Test status
Simulation time 1671194769 ps
CPU time 11.82 seconds
Started Dec 31 12:36:58 PM PST 23
Finished Dec 31 12:37:25 PM PST 23
Peak memory 218028 kb
Host smart-8c218bcb-45ec-4676-96f8-a87961451647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670656216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.3670656216
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.2971639372
Short name T453
Test name
Test status
Simulation time 1196342526 ps
CPU time 10.11 seconds
Started Dec 31 12:36:30 PM PST 23
Finished Dec 31 12:36:55 PM PST 23
Peak memory 209472 kb
Host smart-1e0be4f8-394b-4e88-bb4e-6bfbce840bb6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971639372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_a
ccess.2971639372
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2699431782
Short name T465
Test name
Test status
Simulation time 246976155 ps
CPU time 2.95 seconds
Started Dec 31 12:36:37 PM PST 23
Finished Dec 31 12:36:56 PM PST 23
Peak memory 218080 kb
Host smart-ef2c72ee-535b-4ef8-af66-b96bfdd9c786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699431782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2699431782
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.4228426512
Short name T116
Test name
Test status
Simulation time 1054638606 ps
CPU time 12.02 seconds
Started Dec 31 12:36:36 PM PST 23
Finished Dec 31 12:37:05 PM PST 23
Peak memory 218184 kb
Host smart-a4b4842a-64c8-49dc-8602-6b4b88cee23f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228426512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.4228426512
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.46306000
Short name T901
Test name
Test status
Simulation time 1230837850 ps
CPU time 10.36 seconds
Started Dec 31 12:36:27 PM PST 23
Finished Dec 31 12:36:53 PM PST 23
Peak memory 217960 kb
Host smart-e492851a-d06a-4586-bc08-4e1ef8906105
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46306000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_dig
est.46306000
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.1246631237
Short name T736
Test name
Test status
Simulation time 1527080080 ps
CPU time 9.77 seconds
Started Dec 31 12:36:32 PM PST 23
Finished Dec 31 12:36:57 PM PST 23
Peak memory 218000 kb
Host smart-b0ba2ee4-cc2a-41f4-add9-3a3cb78d7de0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246631237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
1246631237
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.1391360809
Short name T442
Test name
Test status
Simulation time 207224129 ps
CPU time 8.51 seconds
Started Dec 31 12:36:16 PM PST 23
Finished Dec 31 12:36:45 PM PST 23
Peak memory 218076 kb
Host smart-b976a840-86f0-4764-9a77-deb80008216d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391360809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.1391360809
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.553591893
Short name T902
Test name
Test status
Simulation time 346930234 ps
CPU time 4.24 seconds
Started Dec 31 12:36:44 PM PST 23
Finished Dec 31 12:37:06 PM PST 23
Peak memory 214452 kb
Host smart-0478a80a-f60e-4f1f-a33f-07521dc73213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553591893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.553591893
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.466165073
Short name T866
Test name
Test status
Simulation time 1406712975 ps
CPU time 28.19 seconds
Started Dec 31 12:36:26 PM PST 23
Finished Dec 31 12:37:11 PM PST 23
Peak memory 250984 kb
Host smart-d79ec387-a438-47e9-936e-8cf987e50b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466165073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.466165073
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.1294702161
Short name T824
Test name
Test status
Simulation time 608856018 ps
CPU time 6.53 seconds
Started Dec 31 12:36:26 PM PST 23
Finished Dec 31 12:36:49 PM PST 23
Peak memory 246616 kb
Host smart-cdffdb8e-c533-4b45-bc79-0d54279804bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294702161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.1294702161
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.1408998905
Short name T410
Test name
Test status
Simulation time 4118555302 ps
CPU time 65.62 seconds
Started Dec 31 12:36:35 PM PST 23
Finished Dec 31 12:37:57 PM PST 23
Peak memory 249024 kb
Host smart-ab7578b8-8eea-4438-9023-819c3e4e6add
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408998905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.1408998905
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.342931522
Short name T763
Test name
Test status
Simulation time 15964872 ps
CPU time 0.7 seconds
Started Dec 31 12:36:46 PM PST 23
Finished Dec 31 12:37:03 PM PST 23
Peak memory 207820 kb
Host smart-63a9d32d-df62-4074-9033-065b5b2c29f4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342931522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ct
rl_volatile_unlock_smoke.342931522
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.784640351
Short name T765
Test name
Test status
Simulation time 20569443 ps
CPU time 0.93 seconds
Started Dec 31 12:36:24 PM PST 23
Finished Dec 31 12:36:42 PM PST 23
Peak memory 209596 kb
Host smart-1cb065c8-f602-4368-8bd7-c06eb2bc6bde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784640351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.784640351
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.3685093113
Short name T945
Test name
Test status
Simulation time 1361048603 ps
CPU time 11.67 seconds
Started Dec 31 12:36:25 PM PST 23
Finished Dec 31 12:36:53 PM PST 23
Peak memory 218064 kb
Host smart-67ad47c3-d34a-4822-b2a7-3e06b284229e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685093113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.3685093113
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.3056675765
Short name T23
Test name
Test status
Simulation time 595672316 ps
CPU time 3.96 seconds
Started Dec 31 12:36:29 PM PST 23
Finished Dec 31 12:36:48 PM PST 23
Peak memory 209544 kb
Host smart-d8d79e9f-3dca-4b66-9968-0e07e6a09601
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056675765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_a
ccess.3056675765
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.253817396
Short name T448
Test name
Test status
Simulation time 74067943 ps
CPU time 2.86 seconds
Started Dec 31 12:36:13 PM PST 23
Finished Dec 31 12:36:36 PM PST 23
Peak memory 218020 kb
Host smart-5a498ef8-5aae-4056-8959-aba89bfac9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253817396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.253817396
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.4057827998
Short name T798
Test name
Test status
Simulation time 233247576 ps
CPU time 10.16 seconds
Started Dec 31 12:36:14 PM PST 23
Finished Dec 31 12:36:44 PM PST 23
Peak memory 218088 kb
Host smart-5c4d34b8-d265-4784-870c-e66e5f6f1f7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057827998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.4057827998
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3138931282
Short name T828
Test name
Test status
Simulation time 1584149812 ps
CPU time 14.34 seconds
Started Dec 31 12:36:40 PM PST 23
Finished Dec 31 12:37:12 PM PST 23
Peak memory 218020 kb
Host smart-8070174e-9851-4ace-bb22-f52bcd488639
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138931282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
3138931282
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.1632636447
Short name T728
Test name
Test status
Simulation time 577399526 ps
CPU time 11.16 seconds
Started Dec 31 12:37:06 PM PST 23
Finished Dec 31 12:37:30 PM PST 23
Peak memory 218040 kb
Host smart-994dfff1-0e88-4894-9434-ec78b674055f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632636447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.1632636447
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.3297383643
Short name T317
Test name
Test status
Simulation time 60946561 ps
CPU time 3.37 seconds
Started Dec 31 12:36:19 PM PST 23
Finished Dec 31 12:36:42 PM PST 23
Peak memory 214152 kb
Host smart-13012966-11bb-4c6b-a073-97a19e370f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297383643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.3297383643
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.90502650
Short name T474
Test name
Test status
Simulation time 364990349 ps
CPU time 25.42 seconds
Started Dec 31 12:36:27 PM PST 23
Finished Dec 31 12:37:09 PM PST 23
Peak memory 251048 kb
Host smart-50c66261-b196-48c3-b1b5-f1deb4fffe47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90502650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.90502650
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.2954769846
Short name T394
Test name
Test status
Simulation time 99757786 ps
CPU time 8.92 seconds
Started Dec 31 12:36:33 PM PST 23
Finished Dec 31 12:36:58 PM PST 23
Peak memory 251128 kb
Host smart-d52f26ad-5d32-4178-92ad-47237b55f16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954769846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.2954769846
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.1486731963
Short name T421
Test name
Test status
Simulation time 24709274347 ps
CPU time 71.34 seconds
Started Dec 31 12:36:13 PM PST 23
Finished Dec 31 12:37:45 PM PST 23
Peak memory 264524 kb
Host smart-8e4a41d9-fdac-4775-b6b6-111e515c8d1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486731963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.1486731963
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1961289646
Short name T38
Test name
Test status
Simulation time 13530129 ps
CPU time 0.92 seconds
Started Dec 31 12:36:32 PM PST 23
Finished Dec 31 12:36:48 PM PST 23
Peak memory 208572 kb
Host smart-4bf10131-dd1f-4d8f-b3b4-8347c6f9dd18
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961289646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.1961289646
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.151813652
Short name T892
Test name
Test status
Simulation time 46077932 ps
CPU time 0.95 seconds
Started Dec 31 12:36:27 PM PST 23
Finished Dec 31 12:36:44 PM PST 23
Peak memory 209656 kb
Host smart-e6259c9a-62e2-4c31-9813-1692078e4443
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151813652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.151813652
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.3408608060
Short name T808
Test name
Test status
Simulation time 1770065695 ps
CPU time 13.36 seconds
Started Dec 31 12:36:38 PM PST 23
Finished Dec 31 12:37:08 PM PST 23
Peak memory 218176 kb
Host smart-cde718ee-b8f5-49d3-bc8d-c8a30daff6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408608060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.3408608060
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.621959406
Short name T25
Test name
Test status
Simulation time 383293684 ps
CPU time 10.37 seconds
Started Dec 31 12:36:17 PM PST 23
Finished Dec 31 12:36:48 PM PST 23
Peak memory 209652 kb
Host smart-8682b908-6244-47c3-a5ef-2c3ee110fc61
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621959406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_ac
cess.621959406
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.1772237500
Short name T675
Test name
Test status
Simulation time 136669627 ps
CPU time 5.44 seconds
Started Dec 31 12:36:31 PM PST 23
Finished Dec 31 12:36:52 PM PST 23
Peak memory 218016 kb
Host smart-27dc6a34-3abd-4601-b5b6-b4479d23d028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772237500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.1772237500
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.754656168
Short name T606
Test name
Test status
Simulation time 358462785 ps
CPU time 16.12 seconds
Started Dec 31 12:36:36 PM PST 23
Finished Dec 31 12:37:09 PM PST 23
Peak memory 218272 kb
Host smart-95bf2a94-937d-41ef-b61d-d9329ec71c78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754656168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.754656168
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.3827187499
Short name T343
Test name
Test status
Simulation time 1987255753 ps
CPU time 11.68 seconds
Started Dec 31 12:36:28 PM PST 23
Finished Dec 31 12:36:55 PM PST 23
Peak memory 218012 kb
Host smart-d6cde5b2-4131-4059-b8c4-38716b118236
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827187499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.3827187499
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.4205069389
Short name T548
Test name
Test status
Simulation time 930701619 ps
CPU time 9.47 seconds
Started Dec 31 12:36:26 PM PST 23
Finished Dec 31 12:36:52 PM PST 23
Peak memory 218012 kb
Host smart-4d00986e-3c51-467d-b8d5-af840dd8d7e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205069389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
4205069389
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.2426346676
Short name T861
Test name
Test status
Simulation time 423384211 ps
CPU time 14.71 seconds
Started Dec 31 12:36:30 PM PST 23
Finished Dec 31 12:37:00 PM PST 23
Peak memory 218172 kb
Host smart-937689c7-06da-4fdd-9cb9-1502cfaf8d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426346676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.2426346676
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.1852852521
Short name T819
Test name
Test status
Simulation time 15942858 ps
CPU time 1.27 seconds
Started Dec 31 12:36:12 PM PST 23
Finished Dec 31 12:36:33 PM PST 23
Peak memory 213232 kb
Host smart-27befae7-9e60-4a94-b1a1-95dc5b0cdc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852852521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.1852852521
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.1561717733
Short name T972
Test name
Test status
Simulation time 3646776279 ps
CPU time 15.06 seconds
Started Dec 31 12:36:28 PM PST 23
Finished Dec 31 12:36:59 PM PST 23
Peak memory 251136 kb
Host smart-b3b2abe1-c27d-416f-a775-e4cb307f773c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561717733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.1561717733
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.1921459566
Short name T734
Test name
Test status
Simulation time 431668374 ps
CPU time 8.23 seconds
Started Dec 31 12:36:39 PM PST 23
Finished Dec 31 12:37:04 PM PST 23
Peak memory 251076 kb
Host smart-43db01f1-965a-43dc-aac6-628222db7dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921459566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1921459566
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.4112149051
Short name T87
Test name
Test status
Simulation time 4260915147 ps
CPU time 73.06 seconds
Started Dec 31 12:36:22 PM PST 23
Finished Dec 31 12:37:54 PM PST 23
Peak memory 220116 kb
Host smart-cf69486f-7467-4b89-ac53-c8a497af7a5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112149051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.4112149051
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.1159091580
Short name T478
Test name
Test status
Simulation time 13278629 ps
CPU time 1.05 seconds
Started Dec 31 12:36:27 PM PST 23
Finished Dec 31 12:36:52 PM PST 23
Peak memory 211360 kb
Host smart-2fb22368-ea88-4a66-bb28-7ef9e152e2a7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159091580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.1159091580
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.3654966502
Short name T404
Test name
Test status
Simulation time 22233701 ps
CPU time 0.88 seconds
Started Dec 31 12:36:52 PM PST 23
Finished Dec 31 12:37:08 PM PST 23
Peak memory 209572 kb
Host smart-3d8b20ed-60e3-4be1-af26-03ae63c0751f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654966502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.3654966502
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.3706185891
Short name T567
Test name
Test status
Simulation time 363806197 ps
CPU time 14.86 seconds
Started Dec 31 12:36:46 PM PST 23
Finished Dec 31 12:37:17 PM PST 23
Peak memory 218080 kb
Host smart-62de8477-b763-4841-8e1d-8bca5108648f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706185891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3706185891
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.1758548423
Short name T645
Test name
Test status
Simulation time 358227438 ps
CPU time 7.7 seconds
Started Dec 31 12:36:46 PM PST 23
Finished Dec 31 12:37:10 PM PST 23
Peak memory 209484 kb
Host smart-31be391b-e66b-41db-9aba-c6e7bc9c3e22
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758548423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_a
ccess.1758548423
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.191769743
Short name T406
Test name
Test status
Simulation time 71944195 ps
CPU time 3.77 seconds
Started Dec 31 12:36:30 PM PST 23
Finished Dec 31 12:36:49 PM PST 23
Peak memory 218088 kb
Host smart-19202ca4-9db4-4b9d-baab-9994fc33cb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191769743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.191769743
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.1564829474
Short name T543
Test name
Test status
Simulation time 409627419 ps
CPU time 13.78 seconds
Started Dec 31 12:36:49 PM PST 23
Finished Dec 31 12:37:18 PM PST 23
Peak memory 218572 kb
Host smart-89c70784-af1b-4a33-9c43-931fea3fe21a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564829474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.1564829474
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.3878221049
Short name T461
Test name
Test status
Simulation time 576715568 ps
CPU time 12.9 seconds
Started Dec 31 12:36:37 PM PST 23
Finished Dec 31 12:37:06 PM PST 23
Peak memory 218016 kb
Host smart-9704aee1-c6c6-4084-86dd-79935fda26f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878221049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.3878221049
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.3814346149
Short name T504
Test name
Test status
Simulation time 216533934 ps
CPU time 8.48 seconds
Started Dec 31 12:37:03 PM PST 23
Finished Dec 31 12:37:27 PM PST 23
Peak memory 218044 kb
Host smart-9ec45cd3-ec2d-45a9-9d45-48c29ed07c48
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814346149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
3814346149
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.2126355578
Short name T419
Test name
Test status
Simulation time 178774860 ps
CPU time 7.46 seconds
Started Dec 31 12:36:51 PM PST 23
Finished Dec 31 12:37:13 PM PST 23
Peak memory 218128 kb
Host smart-cb5a9333-cfcb-4b07-8cd1-bf8becd4c206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126355578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.2126355578
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.2208272637
Short name T764
Test name
Test status
Simulation time 215159650 ps
CPU time 2.41 seconds
Started Dec 31 12:36:31 PM PST 23
Finished Dec 31 12:36:48 PM PST 23
Peak memory 214248 kb
Host smart-264a873e-bdc8-4b73-b134-e315ec22b3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208272637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.2208272637
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.4201155369
Short name T88
Test name
Test status
Simulation time 954171218 ps
CPU time 30.06 seconds
Started Dec 31 12:36:47 PM PST 23
Finished Dec 31 12:37:33 PM PST 23
Peak memory 250988 kb
Host smart-2cbb051f-61c4-43b5-a389-a8352c67ba52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201155369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.4201155369
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.2991555619
Short name T628
Test name
Test status
Simulation time 509861211 ps
CPU time 3.75 seconds
Started Dec 31 12:36:13 PM PST 23
Finished Dec 31 12:36:36 PM PST 23
Peak memory 222280 kb
Host smart-ddeb1c9e-bf9b-455d-9eb8-c7f868810e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991555619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2991555619
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.1394860825
Short name T677
Test name
Test status
Simulation time 922446560 ps
CPU time 61.06 seconds
Started Dec 31 12:36:42 PM PST 23
Finished Dec 31 12:38:00 PM PST 23
Peak memory 250604 kb
Host smart-db19cbc3-0f30-460a-b13b-117fafa8f169
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394860825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.1394860825
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.2105042570
Short name T630
Test name
Test status
Simulation time 14850208 ps
CPU time 0.73 seconds
Started Dec 31 12:36:46 PM PST 23
Finished Dec 31 12:37:03 PM PST 23
Peak memory 207980 kb
Host smart-7bf9d676-a370-4f0e-a374-5bb44f8f105c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105042570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.2105042570
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.1085524846
Short name T935
Test name
Test status
Simulation time 28764091 ps
CPU time 0.99 seconds
Started Dec 31 12:36:36 PM PST 23
Finished Dec 31 12:36:53 PM PST 23
Peak memory 209608 kb
Host smart-86d296f1-d560-49e3-9e34-4613d6987186
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085524846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.1085524846
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.1687582600
Short name T446
Test name
Test status
Simulation time 462808475 ps
CPU time 13.09 seconds
Started Dec 31 12:37:01 PM PST 23
Finished Dec 31 12:37:29 PM PST 23
Peak memory 218048 kb
Host smart-670f4810-50fa-49c7-8ed7-584e4f5ea322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687582600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.1687582600
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.148721503
Short name T440
Test name
Test status
Simulation time 1957683642 ps
CPU time 10.91 seconds
Started Dec 31 12:36:32 PM PST 23
Finished Dec 31 12:36:58 PM PST 23
Peak memory 209564 kb
Host smart-f9800665-7199-4296-8f49-b28a3134f893
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148721503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_ac
cess.148721503
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.3198484665
Short name T188
Test name
Test status
Simulation time 397449991 ps
CPU time 4.05 seconds
Started Dec 31 12:36:49 PM PST 23
Finished Dec 31 12:37:09 PM PST 23
Peak memory 218052 kb
Host smart-c2c2d788-dafe-47e1-97d7-c408db408730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198484665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.3198484665
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.139807719
Short name T470
Test name
Test status
Simulation time 504385300 ps
CPU time 16.06 seconds
Started Dec 31 12:36:17 PM PST 23
Finished Dec 31 12:36:54 PM PST 23
Peak memory 218196 kb
Host smart-a67499c8-fef1-40ed-a2f7-906439261c31
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139807719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.139807719
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.2522926879
Short name T852
Test name
Test status
Simulation time 477772547 ps
CPU time 17.41 seconds
Started Dec 31 12:36:52 PM PST 23
Finished Dec 31 12:37:24 PM PST 23
Peak memory 218028 kb
Host smart-b7435ee0-7014-425c-92e4-187e4d4fc06d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522926879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.2522926879
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.2548547253
Short name T910
Test name
Test status
Simulation time 1904850060 ps
CPU time 7.69 seconds
Started Dec 31 12:36:29 PM PST 23
Finished Dec 31 12:36:52 PM PST 23
Peak memory 217988 kb
Host smart-6a3369c5-b350-4688-ae37-9ecad1acf234
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548547253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
2548547253
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.588617328
Short name T559
Test name
Test status
Simulation time 1453060492 ps
CPU time 9.49 seconds
Started Dec 31 12:36:45 PM PST 23
Finished Dec 31 12:37:11 PM PST 23
Peak memory 218060 kb
Host smart-78653ea7-3b05-463e-b8bd-6363f1c9e622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588617328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.588617328
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.2136361278
Short name T933
Test name
Test status
Simulation time 298508529 ps
CPU time 2.7 seconds
Started Dec 31 12:36:36 PM PST 23
Finished Dec 31 12:36:55 PM PST 23
Peak memory 214076 kb
Host smart-2b3fd49a-b5c9-4658-bf79-c8102152a7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136361278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.2136361278
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.3089345160
Short name T921
Test name
Test status
Simulation time 336985692 ps
CPU time 37.28 seconds
Started Dec 31 12:36:49 PM PST 23
Finished Dec 31 12:37:43 PM PST 23
Peak memory 250988 kb
Host smart-87b1553f-bc75-4337-bce0-aadd761cc4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089345160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.3089345160
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.3029271437
Short name T755
Test name
Test status
Simulation time 54779154 ps
CPU time 8.8 seconds
Started Dec 31 12:36:25 PM PST 23
Finished Dec 31 12:36:51 PM PST 23
Peak memory 251096 kb
Host smart-f4ec639a-89ad-4113-b565-952425f9292b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029271437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.3029271437
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.3545217766
Short name T806
Test name
Test status
Simulation time 9664464809 ps
CPU time 129.04 seconds
Started Dec 31 12:36:47 PM PST 23
Finished Dec 31 12:39:12 PM PST 23
Peak memory 277696 kb
Host smart-fc635ce2-d929-486f-b8f2-85aa4b4b14f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545217766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.3545217766
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1052811973
Short name T737
Test name
Test status
Simulation time 31892166 ps
CPU time 0.75 seconds
Started Dec 31 12:36:17 PM PST 23
Finished Dec 31 12:36:38 PM PST 23
Peak memory 208080 kb
Host smart-071c6ea5-3f23-49c2-8a75-711699815260
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052811973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.1052811973
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.121321701
Short name T443
Test name
Test status
Simulation time 36904860 ps
CPU time 0.9 seconds
Started Dec 31 12:36:34 PM PST 23
Finished Dec 31 12:36:51 PM PST 23
Peak memory 208304 kb
Host smart-c9d03539-4414-468f-aa40-0d2ec99cb7ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121321701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.121321701
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.3015514084
Short name T517
Test name
Test status
Simulation time 682248576 ps
CPU time 11.84 seconds
Started Dec 31 12:36:38 PM PST 23
Finished Dec 31 12:37:06 PM PST 23
Peak memory 218076 kb
Host smart-b6669dc4-5041-45b4-8248-fc40b95d0f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015514084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.3015514084
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.234803918
Short name T447
Test name
Test status
Simulation time 1692018374 ps
CPU time 5.06 seconds
Started Dec 31 12:36:35 PM PST 23
Finished Dec 31 12:36:57 PM PST 23
Peak memory 209544 kb
Host smart-33a11316-6c08-453c-8237-69fd3ff3b2f2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234803918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_ac
cess.234803918
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.210321963
Short name T424
Test name
Test status
Simulation time 242601183 ps
CPU time 2.95 seconds
Started Dec 31 12:36:53 PM PST 23
Finished Dec 31 12:37:10 PM PST 23
Peak memory 218064 kb
Host smart-fa6b30ec-f4fa-4278-9cf7-6ae6330222d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210321963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.210321963
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.701879975
Short name T712
Test name
Test status
Simulation time 2880681033 ps
CPU time 16.12 seconds
Started Dec 31 12:36:39 PM PST 23
Finished Dec 31 12:37:12 PM PST 23
Peak memory 219180 kb
Host smart-69068482-29c8-4177-8334-32ee7fe86fd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701879975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.701879975
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.2084560165
Short name T344
Test name
Test status
Simulation time 451798532 ps
CPU time 10.48 seconds
Started Dec 31 12:36:43 PM PST 23
Finished Dec 31 12:37:11 PM PST 23
Peak memory 217984 kb
Host smart-7b28dbb7-c94e-45f1-bf8a-91185d14b5c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084560165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.2084560165
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.4090611820
Short name T756
Test name
Test status
Simulation time 468632204 ps
CPU time 7.27 seconds
Started Dec 31 12:36:41 PM PST 23
Finished Dec 31 12:37:06 PM PST 23
Peak memory 218084 kb
Host smart-6abe6970-cd53-4bf3-8346-033ee01e5997
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090611820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
4090611820
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.1973512290
Short name T583
Test name
Test status
Simulation time 3434744323 ps
CPU time 5.43 seconds
Started Dec 31 12:36:30 PM PST 23
Finished Dec 31 12:36:50 PM PST 23
Peak memory 218144 kb
Host smart-7a1f1aec-e454-42cb-a78d-90a9d2b47232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973512290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.1973512290
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.2486466661
Short name T10
Test name
Test status
Simulation time 52175935 ps
CPU time 3.21 seconds
Started Dec 31 12:36:34 PM PST 23
Finished Dec 31 12:36:53 PM PST 23
Peak memory 213920 kb
Host smart-8de9663f-5e25-48b9-8a41-dbf5a3e3784d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486466661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.2486466661
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.1764666191
Short name T331
Test name
Test status
Simulation time 1441196778 ps
CPU time 23.68 seconds
Started Dec 31 12:37:12 PM PST 23
Finished Dec 31 12:37:48 PM PST 23
Peak memory 250652 kb
Host smart-6a49576d-1282-4592-b7c8-896bbaee8781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764666191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.1764666191
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.3739725488
Short name T355
Test name
Test status
Simulation time 133203935 ps
CPU time 10.33 seconds
Started Dec 31 12:36:22 PM PST 23
Finished Dec 31 12:36:51 PM PST 23
Peak memory 250944 kb
Host smart-2b933d8c-dbda-41ef-80c4-2d60047153e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739725488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.3739725488
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.99233220
Short name T817
Test name
Test status
Simulation time 18620548148 ps
CPU time 280.77 seconds
Started Dec 31 12:36:44 PM PST 23
Finished Dec 31 12:41:42 PM PST 23
Peak memory 251240 kb
Host smart-9d16e510-a8f5-4ba6-9715-5dd7cb1c6407
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99233220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.lc_ctrl_stress_all.99233220
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2721041426
Short name T818
Test name
Test status
Simulation time 27624514 ps
CPU time 0.82 seconds
Started Dec 31 12:36:42 PM PST 23
Finished Dec 31 12:37:00 PM PST 23
Peak memory 208196 kb
Host smart-92ba08a2-8896-4724-b842-5281fe0a8152
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721041426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.2721041426
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.574530475
Short name T307
Test name
Test status
Simulation time 31594800 ps
CPU time 1.06 seconds
Started Dec 31 12:36:34 PM PST 23
Finished Dec 31 12:36:52 PM PST 23
Peak memory 209568 kb
Host smart-5c5958e9-4598-4ef0-ade3-cb6af49c22c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574530475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.574530475
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.419830981
Short name T574
Test name
Test status
Simulation time 422742877 ps
CPU time 13.23 seconds
Started Dec 31 12:36:46 PM PST 23
Finished Dec 31 12:37:16 PM PST 23
Peak memory 218188 kb
Host smart-b733990a-b852-42ad-9ca3-79434465785b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419830981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.419830981
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1230517907
Short name T26
Test name
Test status
Simulation time 981673455 ps
CPU time 4.05 seconds
Started Dec 31 12:36:45 PM PST 23
Finished Dec 31 12:37:06 PM PST 23
Peak memory 209524 kb
Host smart-eb3bfc14-c2f6-4eb3-9e4f-427ee5d9e7c3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230517907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_a
ccess.1230517907
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.384296424
Short name T33
Test name
Test status
Simulation time 100211655 ps
CPU time 3.45 seconds
Started Dec 31 12:36:55 PM PST 23
Finished Dec 31 12:37:13 PM PST 23
Peak memory 218080 kb
Host smart-a2ac01be-f20f-4868-a126-9c918c9aaae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384296424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.384296424
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.1026708464
Short name T69
Test name
Test status
Simulation time 1860124998 ps
CPU time 14.42 seconds
Started Dec 31 12:36:17 PM PST 23
Finished Dec 31 12:36:55 PM PST 23
Peak memory 219104 kb
Host smart-f0f48039-4bdc-4c12-a045-614a6753b3ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026708464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.1026708464
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.2283440648
Short name T459
Test name
Test status
Simulation time 1827473556 ps
CPU time 9.11 seconds
Started Dec 31 12:36:39 PM PST 23
Finished Dec 31 12:37:05 PM PST 23
Peak memory 218008 kb
Host smart-c3c03ddd-65ac-4111-a2c3-8434dd58bf49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283440648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.2283440648
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.237229046
Short name T67
Test name
Test status
Simulation time 1421073177 ps
CPU time 7.37 seconds
Started Dec 31 12:36:36 PM PST 23
Finished Dec 31 12:37:00 PM PST 23
Peak memory 218284 kb
Host smart-379cb7b1-4c81-48e7-9dc8-a26f1cda6876
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237229046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.237229046
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.213678023
Short name T944
Test name
Test status
Simulation time 433878641 ps
CPU time 10.38 seconds
Started Dec 31 12:36:39 PM PST 23
Finished Dec 31 12:37:06 PM PST 23
Peak memory 218072 kb
Host smart-8f703919-ca7a-45ae-bc84-4e89ea094bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213678023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.213678023
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.3022554287
Short name T422
Test name
Test status
Simulation time 22536278 ps
CPU time 1.07 seconds
Started Dec 31 12:36:43 PM PST 23
Finished Dec 31 12:37:01 PM PST 23
Peak memory 212584 kb
Host smart-f236a9a1-d824-45de-b719-94c6f627ae94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022554287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.3022554287
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.1645032429
Short name T825
Test name
Test status
Simulation time 685301652 ps
CPU time 31.27 seconds
Started Dec 31 12:36:41 PM PST 23
Finished Dec 31 12:37:29 PM PST 23
Peak memory 250928 kb
Host smart-b6de4484-d4bc-4f15-9961-ce33151e16f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645032429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.1645032429
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.1282276005
Short name T525
Test name
Test status
Simulation time 341988628 ps
CPU time 3.72 seconds
Started Dec 31 12:37:05 PM PST 23
Finished Dec 31 12:37:22 PM PST 23
Peak memory 222124 kb
Host smart-da2e5018-81f0-4881-9fe9-357f35c5d152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282276005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.1282276005
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.3442876421
Short name T82
Test name
Test status
Simulation time 30993770906 ps
CPU time 231.57 seconds
Started Dec 31 12:36:33 PM PST 23
Finished Dec 31 12:40:41 PM PST 23
Peak memory 283892 kb
Host smart-6d618ebd-f34e-413b-8efc-e4298ba88641
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442876421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.3442876421
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1916833677
Short name T811
Test name
Test status
Simulation time 33863432 ps
CPU time 0.81 seconds
Started Dec 31 12:36:48 PM PST 23
Finished Dec 31 12:37:05 PM PST 23
Peak memory 207948 kb
Host smart-eadeaef6-d80b-4e95-94a8-3d088dda8a79
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916833677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1916833677
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.2416430911
Short name T668
Test name
Test status
Simulation time 67928179 ps
CPU time 0.82 seconds
Started Dec 31 12:36:40 PM PST 23
Finished Dec 31 12:36:58 PM PST 23
Peak memory 209420 kb
Host smart-37a9e750-d173-41f3-a532-412b28739d6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416430911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.2416430911
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.195259153
Short name T867
Test name
Test status
Simulation time 1344070445 ps
CPU time 10.28 seconds
Started Dec 31 12:36:39 PM PST 23
Finished Dec 31 12:37:07 PM PST 23
Peak memory 218076 kb
Host smart-fa8776e8-6d5c-47ce-a54e-b3798861f6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195259153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.195259153
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.1041284589
Short name T917
Test name
Test status
Simulation time 762886364 ps
CPU time 17.23 seconds
Started Dec 31 12:36:34 PM PST 23
Finished Dec 31 12:37:07 PM PST 23
Peak memory 209484 kb
Host smart-06dd4ed8-e236-4434-a985-f26888a5a0fd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041284589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_a
ccess.1041284589
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.1741555971
Short name T346
Test name
Test status
Simulation time 139300172 ps
CPU time 2.05 seconds
Started Dec 31 12:37:04 PM PST 23
Finished Dec 31 12:37:21 PM PST 23
Peak memory 218056 kb
Host smart-14954b2a-e09e-4872-88e6-62f9fb7cb812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741555971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.1741555971
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.3078713954
Short name T614
Test name
Test status
Simulation time 374146385 ps
CPU time 12.96 seconds
Started Dec 31 12:36:28 PM PST 23
Finished Dec 31 12:36:57 PM PST 23
Peak memory 218104 kb
Host smart-3852b52d-c19b-4a2e-aa05-ceba8a231148
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078713954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.3078713954
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.3905460736
Short name T850
Test name
Test status
Simulation time 289725065 ps
CPU time 9.05 seconds
Started Dec 31 12:36:39 PM PST 23
Finished Dec 31 12:37:05 PM PST 23
Peak memory 218004 kb
Host smart-cd1a7346-5350-4408-aa58-5a427c96b024
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905460736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.3905460736
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.4261568745
Short name T956
Test name
Test status
Simulation time 469885992 ps
CPU time 8.35 seconds
Started Dec 31 12:36:57 PM PST 23
Finished Dec 31 12:37:20 PM PST 23
Peak memory 217988 kb
Host smart-7b244749-22cd-4170-bca6-cb14a34c8bb3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261568745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
4261568745
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.2571309658
Short name T407
Test name
Test status
Simulation time 301798462 ps
CPU time 8.66 seconds
Started Dec 31 12:36:52 PM PST 23
Finished Dec 31 12:37:22 PM PST 23
Peak memory 218064 kb
Host smart-880f040b-98b9-4df8-b3d7-dff58def11d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571309658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.2571309658
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.48508009
Short name T450
Test name
Test status
Simulation time 191863872 ps
CPU time 3.54 seconds
Started Dec 31 12:36:22 PM PST 23
Finished Dec 31 12:36:44 PM PST 23
Peak memory 214212 kb
Host smart-4fc02dff-b717-4559-99b2-499c919f31f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48508009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.48508009
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.2237211715
Short name T631
Test name
Test status
Simulation time 870551732 ps
CPU time 30.14 seconds
Started Dec 31 12:36:37 PM PST 23
Finished Dec 31 12:37:24 PM PST 23
Peak memory 250972 kb
Host smart-b016a737-d8b7-4e91-9de2-d116067f7c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237211715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.2237211715
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.3751050383
Short name T697
Test name
Test status
Simulation time 431912018 ps
CPU time 7.64 seconds
Started Dec 31 12:37:01 PM PST 23
Finished Dec 31 12:37:24 PM PST 23
Peak memory 250972 kb
Host smart-4743df93-d333-4891-9eb5-4a753ff2843d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751050383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.3751050383
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.3632430475
Short name T810
Test name
Test status
Simulation time 18398615861 ps
CPU time 253.17 seconds
Started Dec 31 12:36:42 PM PST 23
Finished Dec 31 12:41:13 PM PST 23
Peak memory 277500 kb
Host smart-6cd66f3a-1711-4296-8d37-73a0e1f8556f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632430475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.3632430475
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2824702339
Short name T489
Test name
Test status
Simulation time 93047214 ps
CPU time 0.97 seconds
Started Dec 31 12:36:39 PM PST 23
Finished Dec 31 12:36:57 PM PST 23
Peak memory 211408 kb
Host smart-ddb293ed-3d44-4494-b976-3fde5d50f19c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824702339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.2824702339
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.4185984862
Short name T670
Test name
Test status
Simulation time 44552275 ps
CPU time 0.92 seconds
Started Dec 31 12:36:45 PM PST 23
Finished Dec 31 12:37:03 PM PST 23
Peak memory 209488 kb
Host smart-a977c882-5bea-45ff-9054-cb2fc4a5a29b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185984862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.4185984862
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.2805496353
Short name T918
Test name
Test status
Simulation time 916405451 ps
CPU time 9.32 seconds
Started Dec 31 12:36:58 PM PST 23
Finished Dec 31 12:37:27 PM PST 23
Peak memory 218076 kb
Host smart-71aefdc2-161e-4675-9d9b-18b2c348823c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805496353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.2805496353
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.2800752942
Short name T641
Test name
Test status
Simulation time 260071093 ps
CPU time 3.48 seconds
Started Dec 31 12:36:31 PM PST 23
Finished Dec 31 12:36:50 PM PST 23
Peak memory 209620 kb
Host smart-9af3100f-12e9-483d-b4ee-a85367622f9d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800752942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_a
ccess.2800752942
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.3206593971
Short name T594
Test name
Test status
Simulation time 336002908 ps
CPU time 2.18 seconds
Started Dec 31 12:36:37 PM PST 23
Finished Dec 31 12:36:56 PM PST 23
Peak memory 218076 kb
Host smart-f7ecd314-e564-4890-a082-027384e87cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206593971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.3206593971
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.998719002
Short name T687
Test name
Test status
Simulation time 870731398 ps
CPU time 8.33 seconds
Started Dec 31 12:36:53 PM PST 23
Finished Dec 31 12:37:16 PM PST 23
Peak memory 218152 kb
Host smart-efc1c9c7-6363-409f-bb99-89e85843f81c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998719002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.998719002
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.782820020
Short name T502
Test name
Test status
Simulation time 1434514271 ps
CPU time 13.43 seconds
Started Dec 31 12:36:39 PM PST 23
Finished Dec 31 12:37:10 PM PST 23
Peak memory 218024 kb
Host smart-94d8bcae-e417-419a-a43e-8a691126d377
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782820020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_di
gest.782820020
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.778742105
Short name T617
Test name
Test status
Simulation time 2765136692 ps
CPU time 10.69 seconds
Started Dec 31 12:36:43 PM PST 23
Finished Dec 31 12:37:11 PM PST 23
Peak memory 218072 kb
Host smart-a18c3f33-eaf3-49dd-873d-2770b6ba5673
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778742105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.778742105
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.2048576925
Short name T509
Test name
Test status
Simulation time 1091509331 ps
CPU time 6.82 seconds
Started Dec 31 12:36:27 PM PST 23
Finished Dec 31 12:36:50 PM PST 23
Peak memory 218104 kb
Host smart-5fb7399c-dd6c-4ea6-95e3-377806a30f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048576925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.2048576925
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.3279881713
Short name T86
Test name
Test status
Simulation time 32163678 ps
CPU time 2.43 seconds
Started Dec 31 12:36:53 PM PST 23
Finished Dec 31 12:37:10 PM PST 23
Peak memory 213700 kb
Host smart-edbe0c35-245c-4961-857f-e08f345fee62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279881713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.3279881713
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.2939838311
Short name T305
Test name
Test status
Simulation time 319772277 ps
CPU time 28.51 seconds
Started Dec 31 12:36:35 PM PST 23
Finished Dec 31 12:37:20 PM PST 23
Peak memory 250968 kb
Host smart-272e0fbd-ba4e-4659-9c0d-6d46a7749e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939838311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.2939838311
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.2334930120
Short name T17
Test name
Test status
Simulation time 94813925 ps
CPU time 4.15 seconds
Started Dec 31 12:36:48 PM PST 23
Finished Dec 31 12:37:08 PM PST 23
Peak memory 221960 kb
Host smart-d043fa4b-30fe-48cd-918d-0fc661c58b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334930120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.2334930120
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.2361611909
Short name T832
Test name
Test status
Simulation time 2858696731 ps
CPU time 116.96 seconds
Started Dec 31 12:36:34 PM PST 23
Finished Dec 31 12:38:48 PM PST 23
Peak memory 249212 kb
Host smart-be4a25e2-1130-4600-bf5e-b17cdfea90f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361611909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.2361611909
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1345494067
Short name T374
Test name
Test status
Simulation time 27643073 ps
CPU time 0.98 seconds
Started Dec 31 12:36:36 PM PST 23
Finished Dec 31 12:36:54 PM PST 23
Peak memory 211392 kb
Host smart-2f355611-b0e8-4460-a3d7-48307c95b55a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345494067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.1345494067
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.719134932
Short name T121
Test name
Test status
Simulation time 15487065 ps
CPU time 0.82 seconds
Started Dec 31 12:36:30 PM PST 23
Finished Dec 31 12:36:46 PM PST 23
Peak memory 209416 kb
Host smart-175c9cc1-2b3b-42a0-80a3-899b536443ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719134932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.719134932
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.531693042
Short name T511
Test name
Test status
Simulation time 796847901 ps
CPU time 11.58 seconds
Started Dec 31 12:36:51 PM PST 23
Finished Dec 31 12:37:17 PM PST 23
Peak memory 218128 kb
Host smart-67d2ee5a-b5f8-4aed-a19f-b1b69a930c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531693042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.531693042
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.650976566
Short name T378
Test name
Test status
Simulation time 65028213 ps
CPU time 2.26 seconds
Started Dec 31 12:36:35 PM PST 23
Finished Dec 31 12:36:53 PM PST 23
Peak memory 218020 kb
Host smart-6be33e0e-9bab-44fc-b7da-48e892943740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650976566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.650976566
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.3359650808
Short name T809
Test name
Test status
Simulation time 282849553 ps
CPU time 12.23 seconds
Started Dec 31 12:36:55 PM PST 23
Finished Dec 31 12:37:22 PM PST 23
Peak memory 218260 kb
Host smart-cbf4fe92-303a-4292-b297-24425ea0f4c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359650808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.3359650808
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.632296964
Short name T905
Test name
Test status
Simulation time 253056010 ps
CPU time 9.93 seconds
Started Dec 31 12:36:25 PM PST 23
Finished Dec 31 12:36:52 PM PST 23
Peak memory 217996 kb
Host smart-a257b2fe-95f4-4652-bd9e-c8dcda372004
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632296964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_di
gest.632296964
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.3442515015
Short name T501
Test name
Test status
Simulation time 1369127516 ps
CPU time 11.44 seconds
Started Dec 31 12:36:39 PM PST 23
Finished Dec 31 12:37:08 PM PST 23
Peak memory 218012 kb
Host smart-da529982-33c4-47fa-8647-89d638e9ea1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442515015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
3442515015
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.4198051305
Short name T835
Test name
Test status
Simulation time 993821386 ps
CPU time 7.61 seconds
Started Dec 31 12:37:11 PM PST 23
Finished Dec 31 12:37:31 PM PST 23
Peak memory 218068 kb
Host smart-36ca5a7f-4e7c-4157-b1bb-c560ef85bb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198051305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.4198051305
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.3468265830
Short name T922
Test name
Test status
Simulation time 126282374 ps
CPU time 2.62 seconds
Started Dec 31 12:36:37 PM PST 23
Finished Dec 31 12:36:56 PM PST 23
Peak memory 213932 kb
Host smart-e4a6c16d-b4c2-4b82-9a26-bc1b5de3c928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468265830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.3468265830
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.3530455580
Short name T710
Test name
Test status
Simulation time 585184930 ps
CPU time 17.3 seconds
Started Dec 31 12:36:49 PM PST 23
Finished Dec 31 12:37:22 PM PST 23
Peak memory 251064 kb
Host smart-f430448b-65e8-4fae-b60c-f32f5d9988e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530455580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.3530455580
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.409524910
Short name T679
Test name
Test status
Simulation time 375711473 ps
CPU time 3.44 seconds
Started Dec 31 12:36:52 PM PST 23
Finished Dec 31 12:37:10 PM PST 23
Peak memory 226576 kb
Host smart-1f6b121c-4505-456e-a620-46150d4b685a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409524910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.409524910
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.1307418806
Short name T576
Test name
Test status
Simulation time 18580693063 ps
CPU time 120.78 seconds
Started Dec 31 12:36:44 PM PST 23
Finished Dec 31 12:39:02 PM PST 23
Peak memory 283900 kb
Host smart-b468b97c-45bf-46f4-b802-866a2c755d44
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307418806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.1307418806
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3989697448
Short name T909
Test name
Test status
Simulation time 11868036 ps
CPU time 0.74 seconds
Started Dec 31 12:36:53 PM PST 23
Finished Dec 31 12:37:08 PM PST 23
Peak memory 207568 kb
Host smart-8bb9f1a3-5b95-4479-94d7-d18dc460cd0b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989697448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.3989697448
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.3937365118
Short name T955
Test name
Test status
Simulation time 31915709 ps
CPU time 1.05 seconds
Started Dec 31 12:35:39 PM PST 23
Finished Dec 31 12:35:43 PM PST 23
Peak memory 209640 kb
Host smart-097b4739-cce4-403e-991c-61b2fed435c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937365118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.3937365118
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.683902333
Short name T428
Test name
Test status
Simulation time 14163449 ps
CPU time 0.79 seconds
Started Dec 31 12:35:58 PM PST 23
Finished Dec 31 12:36:17 PM PST 23
Peak memory 209288 kb
Host smart-a63de61a-9bd0-4abf-a267-83930741faa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683902333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.683902333
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.2812904316
Short name T896
Test name
Test status
Simulation time 1616158007 ps
CPU time 12.98 seconds
Started Dec 31 12:35:58 PM PST 23
Finished Dec 31 12:36:29 PM PST 23
Peak memory 218056 kb
Host smart-718b0017-616c-450b-a50c-4a0f0b604f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812904316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.2812904316
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.2338355732
Short name T632
Test name
Test status
Simulation time 3070437891 ps
CPU time 17.72 seconds
Started Dec 31 12:35:58 PM PST 23
Finished Dec 31 12:36:34 PM PST 23
Peak memory 209584 kb
Host smart-c825bea0-6266-4a9b-ac99-9980f8c59d94
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338355732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_ac
cess.2338355732
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.865240634
Short name T874
Test name
Test status
Simulation time 15731632922 ps
CPU time 102.37 seconds
Started Dec 31 12:35:57 PM PST 23
Finished Dec 31 12:37:55 PM PST 23
Peak memory 220120 kb
Host smart-6316e2f4-8c8a-4762-8b26-ed2be4291122
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865240634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_err
ors.865240634
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.1051656991
Short name T676
Test name
Test status
Simulation time 286982416 ps
CPU time 2.05 seconds
Started Dec 31 12:35:39 PM PST 23
Finished Dec 31 12:35:45 PM PST 23
Peak memory 209604 kb
Host smart-549edc70-df2e-4e05-af3d-964083442dc4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051656991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_
priority.1051656991
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.3236207173
Short name T699
Test name
Test status
Simulation time 448091109 ps
CPU time 12.16 seconds
Started Dec 31 12:35:46 PM PST 23
Finished Dec 31 12:36:09 PM PST 23
Peak memory 217956 kb
Host smart-32b2dbd1-94dd-46af-aef2-547b313d7b8d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236207173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.3236207173
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.558675019
Short name T523
Test name
Test status
Simulation time 1347297329 ps
CPU time 18.76 seconds
Started Dec 31 12:35:39 PM PST 23
Finished Dec 31 12:36:01 PM PST 23
Peak memory 212908 kb
Host smart-feb47314-d6e6-47d3-a9a9-936964b0167c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558675019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_regwen_during_op.558675019
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.967166627
Short name T895
Test name
Test status
Simulation time 3019594091 ps
CPU time 4.05 seconds
Started Dec 31 12:36:10 PM PST 23
Finished Dec 31 12:36:32 PM PST 23
Peak memory 213900 kb
Host smart-2cf1e54a-0b6b-4bff-8f78-782dbe09513b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967166627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.967166627
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.4071984798
Short name T801
Test name
Test status
Simulation time 74007118936 ps
CPU time 66.83 seconds
Started Dec 31 12:37:07 PM PST 23
Finished Dec 31 12:38:27 PM PST 23
Peak memory 267184 kb
Host smart-7cd4efbd-85b4-4de6-a8fc-da7227b958d3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071984798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.4071984798
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.776445234
Short name T954
Test name
Test status
Simulation time 13085448746 ps
CPU time 16.11 seconds
Started Dec 31 12:36:48 PM PST 23
Finished Dec 31 12:37:21 PM PST 23
Peak memory 223864 kb
Host smart-30233f4c-b030-405f-a705-113c4f79b0e5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776445234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_state_post_trans.776445234
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.3635099323
Short name T777
Test name
Test status
Simulation time 631727064 ps
CPU time 2.14 seconds
Started Dec 31 12:36:04 PM PST 23
Finished Dec 31 12:36:23 PM PST 23
Peak memory 218056 kb
Host smart-f312c206-a12f-4ab7-b790-c7441782d8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635099323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.3635099323
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.2409118758
Short name T79
Test name
Test status
Simulation time 124660411 ps
CPU time 5.42 seconds
Started Dec 31 12:36:06 PM PST 23
Finished Dec 31 12:36:28 PM PST 23
Peak memory 213920 kb
Host smart-59c8e51e-52fe-4a98-8af4-2e384cd2b6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409118758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.2409118758
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.3851660661
Short name T100
Test name
Test status
Simulation time 963599784 ps
CPU time 34.82 seconds
Started Dec 31 12:35:48 PM PST 23
Finished Dec 31 12:36:35 PM PST 23
Peak memory 273104 kb
Host smart-06c26960-6958-4eb7-96d4-1e65f9d2d8f5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851660661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.3851660661
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.1859701112
Short name T982
Test name
Test status
Simulation time 2615610805 ps
CPU time 11.6 seconds
Started Dec 31 12:35:53 PM PST 23
Finished Dec 31 12:36:18 PM PST 23
Peak memory 219116 kb
Host smart-2b578bc7-8340-448e-b956-32392e80ec2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859701112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.1859701112
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.3282144113
Short name T963
Test name
Test status
Simulation time 1106639369 ps
CPU time 9.07 seconds
Started Dec 31 12:35:36 PM PST 23
Finished Dec 31 12:35:47 PM PST 23
Peak memory 218016 kb
Host smart-2438ef54-3088-4645-8591-aac4646e0ab5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282144113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.3282144113
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.4167171085
Short name T491
Test name
Test status
Simulation time 1211043582 ps
CPU time 9.09 seconds
Started Dec 31 12:35:48 PM PST 23
Finished Dec 31 12:36:09 PM PST 23
Peak memory 218012 kb
Host smart-92c29d44-1169-485e-8335-4dcba90f01c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167171085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.4
167171085
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.3825150794
Short name T829
Test name
Test status
Simulation time 3300023487 ps
CPU time 11.61 seconds
Started Dec 31 12:35:57 PM PST 23
Finished Dec 31 12:36:25 PM PST 23
Peak memory 218132 kb
Host smart-b901b446-c1f5-4dbe-bcad-f3b46e36044b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825150794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.3825150794
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.1558366177
Short name T868
Test name
Test status
Simulation time 88708288 ps
CPU time 5.94 seconds
Started Dec 31 12:36:11 PM PST 23
Finished Dec 31 12:36:36 PM PST 23
Peak memory 214040 kb
Host smart-b8451bcc-232d-4be7-9670-ead15a74e053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558366177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.1558366177
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.894462551
Short name T430
Test name
Test status
Simulation time 717541496 ps
CPU time 35.36 seconds
Started Dec 31 12:36:03 PM PST 23
Finished Dec 31 12:36:55 PM PST 23
Peak memory 251004 kb
Host smart-30bc253a-719c-47db-aa33-534474b7c2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894462551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.894462551
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.4214352579
Short name T32
Test name
Test status
Simulation time 293460600 ps
CPU time 7.01 seconds
Started Dec 31 12:35:52 PM PST 23
Finished Dec 31 12:36:09 PM PST 23
Peak memory 246736 kb
Host smart-763fc33e-31ac-44c8-ac73-a8dc1effbf56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214352579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.4214352579
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.766675420
Short name T915
Test name
Test status
Simulation time 2906828197 ps
CPU time 69.05 seconds
Started Dec 31 12:35:36 PM PST 23
Finished Dec 31 12:36:47 PM PST 23
Peak memory 269772 kb
Host smart-9baaab17-05ea-4ef4-b420-e8a2d30b5417
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766675420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.766675420
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2294472342
Short name T37
Test name
Test status
Simulation time 12003691 ps
CPU time 0.89 seconds
Started Dec 31 12:35:55 PM PST 23
Finished Dec 31 12:36:13 PM PST 23
Peak memory 208016 kb
Host smart-5cb7e2c2-0d55-4346-a032-f94841dbe96f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294472342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.2294472342
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.1639450545
Short name T984
Test name
Test status
Simulation time 19300250 ps
CPU time 1.08 seconds
Started Dec 31 12:36:51 PM PST 23
Finished Dec 31 12:37:07 PM PST 23
Peak memory 209576 kb
Host smart-eef24d7b-c67d-4ef5-a5c4-30ab60af2b42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639450545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.1639450545
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.3613619912
Short name T2
Test name
Test status
Simulation time 1975996692 ps
CPU time 10.69 seconds
Started Dec 31 12:36:53 PM PST 23
Finished Dec 31 12:37:18 PM PST 23
Peak memory 218084 kb
Host smart-0b460d66-2056-448e-a5f1-83b928f6169b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613619912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.3613619912
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.976911163
Short name T29
Test name
Test status
Simulation time 765221426 ps
CPU time 8.21 seconds
Started Dec 31 12:36:53 PM PST 23
Finished Dec 31 12:37:16 PM PST 23
Peak memory 209540 kb
Host smart-54782e67-75d1-41bc-b7e4-303d2f7f73de
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976911163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_ac
cess.976911163
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.3637899812
Short name T540
Test name
Test status
Simulation time 69782109 ps
CPU time 2.89 seconds
Started Dec 31 12:36:37 PM PST 23
Finished Dec 31 12:36:56 PM PST 23
Peak memory 218084 kb
Host smart-cd264e4d-acc8-4af6-bb72-13c2b1bd6d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637899812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.3637899812
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.3233226426
Short name T575
Test name
Test status
Simulation time 340769715 ps
CPU time 8.65 seconds
Started Dec 31 12:37:00 PM PST 23
Finished Dec 31 12:37:24 PM PST 23
Peak memory 218140 kb
Host smart-0be4e984-68fe-40a1-8236-b7d87f3c0431
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233226426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.3233226426
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.2714163395
Short name T519
Test name
Test status
Simulation time 1191395014 ps
CPU time 11.83 seconds
Started Dec 31 12:36:46 PM PST 23
Finished Dec 31 12:37:14 PM PST 23
Peak memory 217976 kb
Host smart-3e89fe47-bb3c-4799-b28b-3e2367dfc175
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714163395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.2714163395
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.2620908176
Short name T775
Test name
Test status
Simulation time 1310589357 ps
CPU time 12.04 seconds
Started Dec 31 12:36:34 PM PST 23
Finished Dec 31 12:37:03 PM PST 23
Peak memory 217984 kb
Host smart-1589c5de-3cce-4af9-b9dd-361f732378ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620908176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
2620908176
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.567473792
Short name T578
Test name
Test status
Simulation time 588888643 ps
CPU time 8.03 seconds
Started Dec 31 12:36:50 PM PST 23
Finished Dec 31 12:37:13 PM PST 23
Peak memory 218076 kb
Host smart-0f517837-89eb-4e7e-8566-ed6054362504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567473792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.567473792
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.3395683067
Short name T609
Test name
Test status
Simulation time 120454308 ps
CPU time 1.76 seconds
Started Dec 31 12:36:33 PM PST 23
Finished Dec 31 12:36:51 PM PST 23
Peak memory 213700 kb
Host smart-85ccc392-03cd-4418-ac5e-0aa3b1f812eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395683067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.3395683067
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.852953204
Short name T423
Test name
Test status
Simulation time 370149800 ps
CPU time 20.56 seconds
Started Dec 31 12:36:35 PM PST 23
Finished Dec 31 12:37:12 PM PST 23
Peak memory 250948 kb
Host smart-271b9416-e34a-44e4-8625-59d52c166c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852953204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.852953204
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.985763505
Short name T372
Test name
Test status
Simulation time 102448774 ps
CPU time 2.85 seconds
Started Dec 31 12:36:49 PM PST 23
Finished Dec 31 12:37:07 PM PST 23
Peak memory 220712 kb
Host smart-8841bb70-e28f-4c8d-a088-f2406317824d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985763505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.985763505
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.262098481
Short name T695
Test name
Test status
Simulation time 44222127345 ps
CPU time 318.7 seconds
Started Dec 31 12:36:58 PM PST 23
Finished Dec 31 12:42:32 PM PST 23
Peak memory 251116 kb
Host smart-f216ccdf-d025-4b6f-812c-08b9ca3051c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262098481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.262098481
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.1953895030
Short name T970
Test name
Test status
Simulation time 11223134 ps
CPU time 0.74 seconds
Started Dec 31 12:37:10 PM PST 23
Finished Dec 31 12:37:24 PM PST 23
Peak memory 208000 kb
Host smart-238445c6-72c7-418a-85e4-0bd8ff02371a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953895030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.1953895030
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.2225338450
Short name T534
Test name
Test status
Simulation time 82606088 ps
CPU time 0.89 seconds
Started Dec 31 12:36:43 PM PST 23
Finished Dec 31 12:37:01 PM PST 23
Peak memory 209584 kb
Host smart-ea777035-d2de-42e4-9448-052b217ca552
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225338450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.2225338450
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.486939883
Short name T907
Test name
Test status
Simulation time 806660580 ps
CPU time 17.3 seconds
Started Dec 31 12:36:32 PM PST 23
Finished Dec 31 12:37:04 PM PST 23
Peak memory 218060 kb
Host smart-2188bd65-4c24-4ed6-a855-c24acdd41267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486939883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.486939883
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.860045280
Short name T7
Test name
Test status
Simulation time 2082259855 ps
CPU time 12.99 seconds
Started Dec 31 12:36:52 PM PST 23
Finished Dec 31 12:37:19 PM PST 23
Peak memory 209672 kb
Host smart-3bcb1541-d76b-43e9-8455-a012386f94a0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860045280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_ac
cess.860045280
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.725677567
Short name T791
Test name
Test status
Simulation time 16056043 ps
CPU time 1.4 seconds
Started Dec 31 12:36:32 PM PST 23
Finished Dec 31 12:36:48 PM PST 23
Peak memory 218180 kb
Host smart-71f2a438-19c5-40cb-b732-54c4ea6c954e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725677567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.725677567
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.713309101
Short name T477
Test name
Test status
Simulation time 691979607 ps
CPU time 26.87 seconds
Started Dec 31 12:36:41 PM PST 23
Finished Dec 31 12:37:26 PM PST 23
Peak memory 219080 kb
Host smart-46352018-c9d7-46a3-acd8-7a88e7a7f676
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713309101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.713309101
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.2919892331
Short name T976
Test name
Test status
Simulation time 3446171669 ps
CPU time 22.88 seconds
Started Dec 31 12:36:31 PM PST 23
Finished Dec 31 12:37:09 PM PST 23
Peak memory 218188 kb
Host smart-733fb390-17dc-488a-b66b-02b6793965a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919892331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.2919892331
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.2812799816
Short name T119
Test name
Test status
Simulation time 1245523713 ps
CPU time 13.31 seconds
Started Dec 31 12:36:36 PM PST 23
Finished Dec 31 12:37:06 PM PST 23
Peak memory 218360 kb
Host smart-721306d4-d5c1-400b-8687-39d5ec924683
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812799816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
2812799816
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.988239345
Short name T549
Test name
Test status
Simulation time 664161649 ps
CPU time 7.16 seconds
Started Dec 31 12:36:37 PM PST 23
Finished Dec 31 12:37:00 PM PST 23
Peak memory 218080 kb
Host smart-14ca07ee-ae3e-4146-81eb-9557dae0fc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988239345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.988239345
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.684686788
Short name T927
Test name
Test status
Simulation time 155597885 ps
CPU time 2.39 seconds
Started Dec 31 12:36:49 PM PST 23
Finished Dec 31 12:37:07 PM PST 23
Peak memory 214040 kb
Host smart-f9b932c7-4ad8-4016-8bb8-169f2560a34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684686788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.684686788
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.4068662911
Short name T452
Test name
Test status
Simulation time 226084397 ps
CPU time 23.67 seconds
Started Dec 31 12:36:35 PM PST 23
Finished Dec 31 12:37:15 PM PST 23
Peak memory 251012 kb
Host smart-1cde30af-f611-448d-8b04-98114f6b0fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068662911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.4068662911
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.1441249589
Short name T505
Test name
Test status
Simulation time 275585754 ps
CPU time 9.11 seconds
Started Dec 31 12:36:50 PM PST 23
Finished Dec 31 12:37:14 PM PST 23
Peak memory 250996 kb
Host smart-88cef880-a5db-4471-962b-b96a8a5534e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441249589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1441249589
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.3288298115
Short name T588
Test name
Test status
Simulation time 32303384484 ps
CPU time 121.83 seconds
Started Dec 31 12:37:03 PM PST 23
Finished Dec 31 12:39:20 PM PST 23
Peak memory 226188 kb
Host smart-5e2e560e-0950-45ef-a824-f648e728d2b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288298115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.3288298115
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.1765487839
Short name T872
Test name
Test status
Simulation time 12783302 ps
CPU time 1.1 seconds
Started Dec 31 12:36:39 PM PST 23
Finished Dec 31 12:36:58 PM PST 23
Peak memory 211628 kb
Host smart-b31af9a2-ef0b-4f62-8ef9-9861171b57c5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765487839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.1765487839
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.1230184284
Short name T14
Test name
Test status
Simulation time 69740185 ps
CPU time 1.46 seconds
Started Dec 31 12:36:40 PM PST 23
Finished Dec 31 12:36:58 PM PST 23
Peak memory 209556 kb
Host smart-df8a8761-d6e1-435e-835e-8cced8add264
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230184284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.1230184284
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.966600470
Short name T41
Test name
Test status
Simulation time 273577431 ps
CPU time 11.14 seconds
Started Dec 31 12:36:42 PM PST 23
Finished Dec 31 12:37:10 PM PST 23
Peak memory 218012 kb
Host smart-37fbb08d-4741-46de-9f6e-6bc8b312425e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966600470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.966600470
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.96374173
Short name T24
Test name
Test status
Simulation time 381922441 ps
CPU time 10.43 seconds
Started Dec 31 12:36:37 PM PST 23
Finished Dec 31 12:37:04 PM PST 23
Peak memory 209536 kb
Host smart-086c18e8-3086-43f4-9653-530679b2c1f9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96374173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jta
g_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_acc
ess.96374173
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.1345756741
Short name T316
Test name
Test status
Simulation time 73120228 ps
CPU time 3.14 seconds
Started Dec 31 12:37:01 PM PST 23
Finished Dec 31 12:37:20 PM PST 23
Peak memory 218028 kb
Host smart-f43a4c0a-b024-4f3a-b741-5105940e7169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345756741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.1345756741
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.1544293529
Short name T514
Test name
Test status
Simulation time 489356387 ps
CPU time 11.38 seconds
Started Dec 31 12:36:44 PM PST 23
Finished Dec 31 12:37:12 PM PST 23
Peak memory 219108 kb
Host smart-811b5d7f-6c9a-4e2b-a422-e8e00ca76676
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544293529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.1544293529
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.3280253035
Short name T568
Test name
Test status
Simulation time 2001606057 ps
CPU time 13.34 seconds
Started Dec 31 12:36:29 PM PST 23
Finished Dec 31 12:36:58 PM PST 23
Peak memory 218000 kb
Host smart-97d8761b-a000-41f3-a3eb-03f733625695
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280253035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.3280253035
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.437706713
Short name T741
Test name
Test status
Simulation time 1327380562 ps
CPU time 6.84 seconds
Started Dec 31 12:36:40 PM PST 23
Finished Dec 31 12:37:05 PM PST 23
Peak memory 218004 kb
Host smart-4668bd2c-4a9c-4dd7-bde2-1a74586db969
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437706713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.437706713
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.1719671409
Short name T721
Test name
Test status
Simulation time 1532178236 ps
CPU time 9.72 seconds
Started Dec 31 12:36:33 PM PST 23
Finished Dec 31 12:36:59 PM PST 23
Peak memory 218100 kb
Host smart-25d49c4c-4514-4632-a32f-3ce4d3d4fd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719671409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.1719671409
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.750111289
Short name T953
Test name
Test status
Simulation time 29595236 ps
CPU time 1.57 seconds
Started Dec 31 12:36:54 PM PST 23
Finished Dec 31 12:37:10 PM PST 23
Peak memory 213368 kb
Host smart-b9554b0d-e623-4578-8fc0-ad5534762d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750111289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.750111289
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.1053365899
Short name T551
Test name
Test status
Simulation time 622154745 ps
CPU time 32.82 seconds
Started Dec 31 12:37:01 PM PST 23
Finished Dec 31 12:37:49 PM PST 23
Peak memory 250964 kb
Host smart-2d868573-d76c-4695-9205-848845b9fb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053365899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.1053365899
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.3353661628
Short name T725
Test name
Test status
Simulation time 129838734 ps
CPU time 4.08 seconds
Started Dec 31 12:36:36 PM PST 23
Finished Dec 31 12:36:56 PM PST 23
Peak memory 222304 kb
Host smart-9156dee6-3d91-465b-860d-e417912b5506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353661628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.3353661628
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.3119439798
Short name T924
Test name
Test status
Simulation time 15118557336 ps
CPU time 367.51 seconds
Started Dec 31 12:36:59 PM PST 23
Finished Dec 31 12:43:22 PM PST 23
Peak memory 283836 kb
Host smart-6fbbc8b1-3e9c-4e6e-b500-71d020dd15ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119439798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.3119439798
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.1902594043
Short name T499
Test name
Test status
Simulation time 38528131 ps
CPU time 0.78 seconds
Started Dec 31 12:37:33 PM PST 23
Finished Dec 31 12:37:39 PM PST 23
Peak memory 208088 kb
Host smart-fd0cb506-13f2-4ea1-8479-69bd3d796409
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902594043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.1902594043
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.2798831376
Short name T919
Test name
Test status
Simulation time 24594914 ps
CPU time 1.02 seconds
Started Dec 31 12:36:34 PM PST 23
Finished Dec 31 12:36:51 PM PST 23
Peak memory 209572 kb
Host smart-c4c77ac2-a7d9-4f2b-9af3-a4f2904c3e20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798831376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.2798831376
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.401658936
Short name T816
Test name
Test status
Simulation time 216447318 ps
CPU time 12.7 seconds
Started Dec 31 12:36:42 PM PST 23
Finished Dec 31 12:37:13 PM PST 23
Peak memory 218176 kb
Host smart-c1ee4611-2ae7-4290-b222-6d2f4a8c4fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401658936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.401658936
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.1553022199
Short name T4
Test name
Test status
Simulation time 126076086 ps
CPU time 3.87 seconds
Started Dec 31 12:37:01 PM PST 23
Finished Dec 31 12:37:21 PM PST 23
Peak memory 209548 kb
Host smart-cd177c51-4a83-4f74-a395-7b2a0b24906a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553022199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_a
ccess.1553022199
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.160983523
Short name T647
Test name
Test status
Simulation time 25488138 ps
CPU time 1.91 seconds
Started Dec 31 12:36:54 PM PST 23
Finished Dec 31 12:37:10 PM PST 23
Peak memory 218036 kb
Host smart-3b53b3ae-9c1e-4cc7-bf05-d0deaef6d2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160983523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.160983523
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.2315616029
Short name T615
Test name
Test status
Simulation time 2753373469 ps
CPU time 10.04 seconds
Started Dec 31 12:36:39 PM PST 23
Finished Dec 31 12:37:07 PM PST 23
Peak memory 218256 kb
Host smart-4b618948-0d84-45d3-ac4f-f2fea3ee64d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315616029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.2315616029
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.2885013634
Short name T333
Test name
Test status
Simulation time 380064605 ps
CPU time 12.74 seconds
Started Dec 31 12:36:56 PM PST 23
Finished Dec 31 12:37:24 PM PST 23
Peak memory 218000 kb
Host smart-04361c75-0120-4eed-ab1e-0a0e3bb8c4ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885013634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.2885013634
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.1837987434
Short name T63
Test name
Test status
Simulation time 559567633 ps
CPU time 10.36 seconds
Started Dec 31 12:36:32 PM PST 23
Finished Dec 31 12:36:58 PM PST 23
Peak memory 218128 kb
Host smart-e3c85821-365c-4808-ab0c-e7d4e2e21b78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837987434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
1837987434
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.2058819545
Short name T186
Test name
Test status
Simulation time 1162476903 ps
CPU time 8.72 seconds
Started Dec 31 12:36:53 PM PST 23
Finished Dec 31 12:37:16 PM PST 23
Peak memory 218060 kb
Host smart-20605310-8501-40eb-9c7d-9810315f6b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058819545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.2058819545
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.1726886530
Short name T72
Test name
Test status
Simulation time 42398332 ps
CPU time 2.32 seconds
Started Dec 31 12:36:38 PM PST 23
Finished Dec 31 12:36:57 PM PST 23
Peak memory 213744 kb
Host smart-4e861340-2feb-4e69-8c35-7a159132e7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726886530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.1726886530
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.294068708
Short name T968
Test name
Test status
Simulation time 226249180 ps
CPU time 19.16 seconds
Started Dec 31 12:36:56 PM PST 23
Finished Dec 31 12:37:30 PM PST 23
Peak memory 250920 kb
Host smart-8a08e813-9277-4a37-b44b-0c28d488873f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294068708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.294068708
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.2941309425
Short name T187
Test name
Test status
Simulation time 181613865 ps
CPU time 6.65 seconds
Started Dec 31 12:36:33 PM PST 23
Finished Dec 31 12:36:56 PM PST 23
Peak memory 250112 kb
Host smart-ec584f42-fdce-41ff-8a4f-0b969ca177fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941309425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.2941309425
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.2332815606
Short name T635
Test name
Test status
Simulation time 10067908447 ps
CPU time 170.28 seconds
Started Dec 31 12:36:54 PM PST 23
Finished Dec 31 12:39:59 PM PST 23
Peak memory 251116 kb
Host smart-7f8cb357-8b21-4a14-8010-ba0281f5ee91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332815606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.2332815606
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1716655422
Short name T758
Test name
Test status
Simulation time 11123186 ps
CPU time 1.05 seconds
Started Dec 31 12:36:34 PM PST 23
Finished Dec 31 12:36:51 PM PST 23
Peak memory 211280 kb
Host smart-c9a45308-d77b-4f9b-a14a-31810165a47d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716655422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.1716655422
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.1616448196
Short name T589
Test name
Test status
Simulation time 220927465 ps
CPU time 0.9 seconds
Started Dec 31 12:37:15 PM PST 23
Finished Dec 31 12:37:31 PM PST 23
Peak memory 208264 kb
Host smart-76501ea0-ae19-4bf9-a0ca-892e9d24b4f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616448196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.1616448196
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.1361119094
Short name T579
Test name
Test status
Simulation time 1615784111 ps
CPU time 13.72 seconds
Started Dec 31 12:36:39 PM PST 23
Finished Dec 31 12:37:09 PM PST 23
Peak memory 218084 kb
Host smart-052130b7-24f8-459e-a7c7-c8e0a937775f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361119094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.1361119094
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.1400880186
Short name T843
Test name
Test status
Simulation time 109152246 ps
CPU time 1.86 seconds
Started Dec 31 12:37:08 PM PST 23
Finished Dec 31 12:37:23 PM PST 23
Peak memory 209508 kb
Host smart-a017a2f0-4e3c-4c49-960b-808f931b1927
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400880186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_a
ccess.1400880186
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.3996736777
Short name T510
Test name
Test status
Simulation time 430430387 ps
CPU time 4.65 seconds
Started Dec 31 12:37:15 PM PST 23
Finished Dec 31 12:37:31 PM PST 23
Peak memory 218064 kb
Host smart-427020b0-a00a-4102-a970-cc95ebc93cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996736777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.3996736777
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.3146917625
Short name T481
Test name
Test status
Simulation time 1494189301 ps
CPU time 12.07 seconds
Started Dec 31 12:37:01 PM PST 23
Finished Dec 31 12:37:29 PM PST 23
Peak memory 218340 kb
Host smart-d59270d3-66e6-49d3-945b-c2eb5a1a661b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146917625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.3146917625
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.3975231497
Short name T366
Test name
Test status
Simulation time 589022777 ps
CPU time 16.72 seconds
Started Dec 31 12:36:29 PM PST 23
Finished Dec 31 12:37:01 PM PST 23
Peak memory 218008 kb
Host smart-d7ad7129-8ee6-4415-8b52-ef7a942f31c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975231497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.3975231497
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.3910217574
Short name T391
Test name
Test status
Simulation time 371415396 ps
CPU time 13.54 seconds
Started Dec 31 12:36:35 PM PST 23
Finished Dec 31 12:37:05 PM PST 23
Peak memory 218024 kb
Host smart-b0e3e2e8-de44-45b7-817f-1a3610d43e07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910217574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
3910217574
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.3345155708
Short name T57
Test name
Test status
Simulation time 558453329 ps
CPU time 6.13 seconds
Started Dec 31 12:36:58 PM PST 23
Finished Dec 31 12:37:20 PM PST 23
Peak memory 218072 kb
Host smart-98ccff01-ef1b-4492-8e4c-2fa9059150de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345155708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.3345155708
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.1537409960
Short name T486
Test name
Test status
Simulation time 56587744 ps
CPU time 1.71 seconds
Started Dec 31 12:36:38 PM PST 23
Finished Dec 31 12:36:57 PM PST 23
Peak memory 213312 kb
Host smart-cccf7b59-7f53-46ba-af61-b02d8fc0a53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537409960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.1537409960
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1813337440
Short name T928
Test name
Test status
Simulation time 571785856 ps
CPU time 27.97 seconds
Started Dec 31 12:36:42 PM PST 23
Finished Dec 31 12:37:27 PM PST 23
Peak memory 251000 kb
Host smart-0d36b73c-de1e-454b-a929-04fd2e1f595a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813337440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1813337440
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.2002442317
Short name T773
Test name
Test status
Simulation time 294625200 ps
CPU time 8.35 seconds
Started Dec 31 12:36:46 PM PST 23
Finished Dec 31 12:37:11 PM PST 23
Peak memory 251000 kb
Host smart-0859b0bf-973a-4301-a3ea-d2eb353de184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002442317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2002442317
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.2949221544
Short name T573
Test name
Test status
Simulation time 5117320210 ps
CPU time 153.94 seconds
Started Dec 31 12:36:40 PM PST 23
Finished Dec 31 12:39:31 PM PST 23
Peak memory 278924 kb
Host smart-7854d43d-71cb-4357-b508-7f639273e448
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949221544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.2949221544
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.4005704724
Short name T36
Test name
Test status
Simulation time 13984944 ps
CPU time 0.94 seconds
Started Dec 31 12:36:27 PM PST 23
Finished Dec 31 12:36:44 PM PST 23
Peak memory 208076 kb
Host smart-711eb1a4-a51a-461d-b51d-8a07ef0b38dd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005704724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.4005704724
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.3217868719
Short name T363
Test name
Test status
Simulation time 41729255 ps
CPU time 0.9 seconds
Started Dec 31 12:36:37 PM PST 23
Finished Dec 31 12:36:54 PM PST 23
Peak memory 209552 kb
Host smart-266698dd-f699-4ec0-a25b-284067c479c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217868719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.3217868719
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.3684978841
Short name T648
Test name
Test status
Simulation time 2546473746 ps
CPU time 14.36 seconds
Started Dec 31 12:37:04 PM PST 23
Finished Dec 31 12:37:33 PM PST 23
Peak memory 218132 kb
Host smart-b255d6bd-310f-4d37-a8b5-ddf905f009e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684978841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.3684978841
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.2945145605
Short name T827
Test name
Test status
Simulation time 1152962781 ps
CPU time 8.8 seconds
Started Dec 31 12:36:41 PM PST 23
Finished Dec 31 12:37:08 PM PST 23
Peak memory 209648 kb
Host smart-ef861151-0f60-4fdb-9e22-d9687e06489a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945145605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_a
ccess.2945145605
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.1771044939
Short name T849
Test name
Test status
Simulation time 239646250 ps
CPU time 2.46 seconds
Started Dec 31 12:36:45 PM PST 23
Finished Dec 31 12:37:04 PM PST 23
Peak memory 218088 kb
Host smart-5d03252e-66ad-400c-a1b6-18ab1e3f668c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771044939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.1771044939
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.61375236
Short name T858
Test name
Test status
Simulation time 422330442 ps
CPU time 14.56 seconds
Started Dec 31 12:36:39 PM PST 23
Finished Dec 31 12:37:11 PM PST 23
Peak memory 218472 kb
Host smart-81641a85-3b29-42a5-b760-2e9b3755b247
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61375236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.61375236
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.3346406999
Short name T908
Test name
Test status
Simulation time 233097755 ps
CPU time 7.61 seconds
Started Dec 31 12:37:02 PM PST 23
Finished Dec 31 12:37:25 PM PST 23
Peak memory 218020 kb
Host smart-261c5a00-f084-4ebe-8975-6ff521a7fdd7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346406999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.3346406999
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.1585696888
Short name T607
Test name
Test status
Simulation time 554862533 ps
CPU time 8.04 seconds
Started Dec 31 12:36:46 PM PST 23
Finished Dec 31 12:37:10 PM PST 23
Peak memory 218044 kb
Host smart-a45e2529-d3bf-4ad0-9ffc-7e3081e1aae9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585696888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
1585696888
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.2419185998
Short name T940
Test name
Test status
Simulation time 357214234 ps
CPU time 9.49 seconds
Started Dec 31 12:36:30 PM PST 23
Finished Dec 31 12:36:54 PM PST 23
Peak memory 218060 kb
Host smart-ac9fe145-9c8a-4093-a432-28622515c19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419185998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.2419185998
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.1565290456
Short name T669
Test name
Test status
Simulation time 43202697 ps
CPU time 1.13 seconds
Started Dec 31 12:36:53 PM PST 23
Finished Dec 31 12:37:09 PM PST 23
Peak memory 213020 kb
Host smart-eb29433a-e053-4e7f-9388-e268b2b2d4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565290456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.1565290456
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.773157640
Short name T13
Test name
Test status
Simulation time 226151829 ps
CPU time 22.16 seconds
Started Dec 31 12:36:57 PM PST 23
Finished Dec 31 12:37:34 PM PST 23
Peak memory 250992 kb
Host smart-54765169-9ba2-4871-9dcf-47d42882e9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773157640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.773157640
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.800967009
Short name T315
Test name
Test status
Simulation time 97609116 ps
CPU time 6.83 seconds
Started Dec 31 12:36:50 PM PST 23
Finished Dec 31 12:37:12 PM PST 23
Peak memory 251044 kb
Host smart-15a2a2c6-e70a-47b9-849e-6b542847feed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800967009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.800967009
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2759258921
Short name T337
Test name
Test status
Simulation time 216706627 ps
CPU time 0.85 seconds
Started Dec 31 12:36:29 PM PST 23
Finished Dec 31 12:36:45 PM PST 23
Peak memory 211360 kb
Host smart-4f4822d4-5ac0-471a-9b4b-c884a7c6ee95
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759258921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.2759258921
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3596669217
Short name T815
Test name
Test status
Simulation time 122706818 ps
CPU time 1.36 seconds
Started Dec 31 12:36:59 PM PST 23
Finished Dec 31 12:37:15 PM PST 23
Peak memory 209652 kb
Host smart-e508af54-11b7-4fb4-aeef-f0ee850133df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596669217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3596669217
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.375295621
Short name T483
Test name
Test status
Simulation time 1305553792 ps
CPU time 7.43 seconds
Started Dec 31 12:36:46 PM PST 23
Finished Dec 31 12:37:10 PM PST 23
Peak memory 209552 kb
Host smart-2773dc30-0600-4d0f-8491-3f3d4d8ec702
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375295621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_ac
cess.375295621
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.2057081261
Short name T779
Test name
Test status
Simulation time 51014919 ps
CPU time 2.77 seconds
Started Dec 31 12:36:36 PM PST 23
Finished Dec 31 12:36:55 PM PST 23
Peak memory 218048 kb
Host smart-90a80bc0-2243-43c4-a5fd-9d203bcaadfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057081261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.2057081261
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.2442296130
Short name T719
Test name
Test status
Simulation time 915734646 ps
CPU time 8.98 seconds
Started Dec 31 12:36:55 PM PST 23
Finished Dec 31 12:37:19 PM PST 23
Peak memory 218168 kb
Host smart-785b67c0-b6fa-44fc-afe8-9e3548504c6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442296130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.2442296130
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.1881977095
Short name T494
Test name
Test status
Simulation time 2922445765 ps
CPU time 16.71 seconds
Started Dec 31 12:36:49 PM PST 23
Finished Dec 31 12:37:22 PM PST 23
Peak memory 218076 kb
Host smart-f8ed113b-4a09-4c86-8ccb-8b69e24c3791
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881977095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.1881977095
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.3112379396
Short name T586
Test name
Test status
Simulation time 520183617 ps
CPU time 10.55 seconds
Started Dec 31 12:36:59 PM PST 23
Finished Dec 31 12:37:25 PM PST 23
Peak memory 218068 kb
Host smart-0e8342f4-49d4-4d5d-9bea-f2b9f2a54725
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112379396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
3112379396
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.440802080
Short name T56
Test name
Test status
Simulation time 433001677 ps
CPU time 6.82 seconds
Started Dec 31 12:37:08 PM PST 23
Finished Dec 31 12:37:28 PM PST 23
Peak memory 218084 kb
Host smart-a0412514-7910-4506-be1c-60b32215e59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440802080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.440802080
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.2911637994
Short name T84
Test name
Test status
Simulation time 132528116 ps
CPU time 1 seconds
Started Dec 31 12:36:45 PM PST 23
Finished Dec 31 12:37:03 PM PST 23
Peak memory 212488 kb
Host smart-56daf160-a13e-4229-b66a-f80ac1487bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911637994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.2911637994
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.1380705555
Short name T120
Test name
Test status
Simulation time 794546454 ps
CPU time 22.52 seconds
Started Dec 31 12:36:45 PM PST 23
Finished Dec 31 12:37:24 PM PST 23
Peak memory 250880 kb
Host smart-16dfcbce-39f5-4701-b4cc-90bca2df71eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380705555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.1380705555
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.3307640300
Short name T427
Test name
Test status
Simulation time 54708094 ps
CPU time 3.12 seconds
Started Dec 31 12:36:50 PM PST 23
Finished Dec 31 12:37:08 PM PST 23
Peak memory 221984 kb
Host smart-f1f91066-a10c-4e4c-86aa-7a71097f2a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307640300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.3307640300
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.2156024077
Short name T439
Test name
Test status
Simulation time 45950218386 ps
CPU time 147.67 seconds
Started Dec 31 12:36:48 PM PST 23
Finished Dec 31 12:39:31 PM PST 23
Peak memory 283888 kb
Host smart-432b0878-3e9e-4aef-96c3-091e8976477a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156024077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.2156024077
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1599428205
Short name T930
Test name
Test status
Simulation time 10825703 ps
CPU time 0.75 seconds
Started Dec 31 12:37:08 PM PST 23
Finished Dec 31 12:37:22 PM PST 23
Peak memory 207968 kb
Host smart-a8ced427-8d97-4e21-9d50-290a34da0ba7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599428205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.1599428205
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.530359962
Short name T727
Test name
Test status
Simulation time 47612122 ps
CPU time 0.81 seconds
Started Dec 31 12:36:45 PM PST 23
Finished Dec 31 12:37:03 PM PST 23
Peak memory 209408 kb
Host smart-a962c718-4c5c-4e2f-9710-9cb6a7f97e48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530359962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.530359962
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.2739124607
Short name T722
Test name
Test status
Simulation time 979500660 ps
CPU time 9.48 seconds
Started Dec 31 12:37:07 PM PST 23
Finished Dec 31 12:37:29 PM PST 23
Peak memory 218348 kb
Host smart-b793863a-bcf2-4b66-8f00-2c18af199e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739124607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.2739124607
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.2518076573
Short name T425
Test name
Test status
Simulation time 107596356 ps
CPU time 1.73 seconds
Started Dec 31 12:36:40 PM PST 23
Finished Dec 31 12:36:59 PM PST 23
Peak memory 209552 kb
Host smart-fc75f513-a853-4915-9cb6-37de64f71b93
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518076573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_a
ccess.2518076573
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.4130954893
Short name T508
Test name
Test status
Simulation time 220985016 ps
CPU time 3.02 seconds
Started Dec 31 12:36:38 PM PST 23
Finished Dec 31 12:36:58 PM PST 23
Peak memory 218292 kb
Host smart-c0c47d82-195f-4ec6-a4f9-ed8f1585c89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130954893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.4130954893
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.934989667
Short name T405
Test name
Test status
Simulation time 702711720 ps
CPU time 9.12 seconds
Started Dec 31 12:37:25 PM PST 23
Finished Dec 31 12:37:43 PM PST 23
Peak memory 218068 kb
Host smart-60356747-4170-4f99-9067-f811be9c6e56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934989667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.934989667
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.1999457812
Short name T663
Test name
Test status
Simulation time 398818774 ps
CPU time 13.7 seconds
Started Dec 31 12:36:49 PM PST 23
Finished Dec 31 12:37:18 PM PST 23
Peak memory 217976 kb
Host smart-91289252-64bc-44ff-a19b-c07b35f73b1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999457812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.1999457812
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.3837759961
Short name T740
Test name
Test status
Simulation time 420684622 ps
CPU time 9.12 seconds
Started Dec 31 12:36:44 PM PST 23
Finished Dec 31 12:37:10 PM PST 23
Peak memory 218004 kb
Host smart-b1089fec-ac5e-4116-b93c-819bab478624
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837759961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
3837759961
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.3665847443
Short name T652
Test name
Test status
Simulation time 603297276 ps
CPU time 11.19 seconds
Started Dec 31 12:36:37 PM PST 23
Finished Dec 31 12:37:04 PM PST 23
Peak memory 218044 kb
Host smart-67fa4c6e-1cf3-49af-8282-ff86124cd27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665847443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.3665847443
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.2835176993
Short name T531
Test name
Test status
Simulation time 34398840 ps
CPU time 2.28 seconds
Started Dec 31 12:37:04 PM PST 23
Finished Dec 31 12:37:21 PM PST 23
Peak memory 213500 kb
Host smart-94d7bc21-3fe1-41ae-874b-1540bbf49474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835176993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2835176993
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.4247344303
Short name T455
Test name
Test status
Simulation time 1078115910 ps
CPU time 28.57 seconds
Started Dec 31 12:36:58 PM PST 23
Finished Dec 31 12:37:42 PM PST 23
Peak memory 251012 kb
Host smart-4d90a56e-fe5f-4524-8c33-fc1e4bdc1906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247344303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.4247344303
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.697690886
Short name T823
Test name
Test status
Simulation time 117353126 ps
CPU time 3.48 seconds
Started Dec 31 12:36:54 PM PST 23
Finished Dec 31 12:37:12 PM PST 23
Peak memory 222120 kb
Host smart-fd94f7cb-1fcf-4c71-8e13-b004f67aeed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697690886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.697690886
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.3460755576
Short name T898
Test name
Test status
Simulation time 20183098454 ps
CPU time 317.53 seconds
Started Dec 31 12:37:19 PM PST 23
Finished Dec 31 12:42:48 PM PST 23
Peak memory 283860 kb
Host smart-9ca5f840-3fbb-4433-9406-c74a1b31041e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460755576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.3460755576
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.2137417716
Short name T723
Test name
Test status
Simulation time 16992442 ps
CPU time 1.16 seconds
Started Dec 31 12:36:55 PM PST 23
Finished Dec 31 12:37:10 PM PST 23
Peak memory 211348 kb
Host smart-23a1f96d-c98c-48c5-b03c-569bdc8c263b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137417716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.2137417716
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.2802293097
Short name T547
Test name
Test status
Simulation time 24765788 ps
CPU time 1.24 seconds
Started Dec 31 12:36:53 PM PST 23
Finished Dec 31 12:37:09 PM PST 23
Peak memory 209688 kb
Host smart-c2b0f7b8-001d-4bde-8857-c829f6da464b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802293097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.2802293097
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.945616794
Short name T434
Test name
Test status
Simulation time 2957695108 ps
CPU time 18.69 seconds
Started Dec 31 12:36:55 PM PST 23
Finished Dec 31 12:37:28 PM PST 23
Peak memory 218264 kb
Host smart-ffaaf7f5-3eb0-47bf-b399-32897929c2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945616794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.945616794
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.3304790793
Short name T975
Test name
Test status
Simulation time 1361065067 ps
CPU time 7.36 seconds
Started Dec 31 12:36:43 PM PST 23
Finished Dec 31 12:37:07 PM PST 23
Peak memory 209536 kb
Host smart-97fbca8f-b6a5-47bb-ae0d-7a49068b9955
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304790793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_a
ccess.3304790793
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.3612581528
Short name T805
Test name
Test status
Simulation time 186720496 ps
CPU time 2.79 seconds
Started Dec 31 12:36:55 PM PST 23
Finished Dec 31 12:37:12 PM PST 23
Peak memory 218016 kb
Host smart-4bdf0266-c5ba-4ff5-928f-b7e546e286b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612581528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3612581528
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.3127207173
Short name T388
Test name
Test status
Simulation time 232376812 ps
CPU time 11.86 seconds
Started Dec 31 12:37:02 PM PST 23
Finished Dec 31 12:37:29 PM PST 23
Peak memory 218124 kb
Host smart-b5f6d9d9-b7a0-4682-bfb5-ff7949cf352d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127207173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.3127207173
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.1514079385
Short name T518
Test name
Test status
Simulation time 1729474876 ps
CPU time 15.62 seconds
Started Dec 31 12:36:51 PM PST 23
Finished Dec 31 12:37:21 PM PST 23
Peak memory 217996 kb
Host smart-83f8be01-5ff6-4689-8096-ee7c59854dae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514079385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.1514079385
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3254760373
Short name T536
Test name
Test status
Simulation time 236700828 ps
CPU time 6.59 seconds
Started Dec 31 12:37:04 PM PST 23
Finished Dec 31 12:37:25 PM PST 23
Peak memory 217968 kb
Host smart-44957eb9-1d67-4947-abbd-952c1128a80b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254760373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
3254760373
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.2488931284
Short name T530
Test name
Test status
Simulation time 1636562144 ps
CPU time 10 seconds
Started Dec 31 12:36:59 PM PST 23
Finished Dec 31 12:37:25 PM PST 23
Peak memory 218060 kb
Host smart-5341778f-a129-4295-8621-a00635814809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488931284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2488931284
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.2626088412
Short name T492
Test name
Test status
Simulation time 129268524 ps
CPU time 1.99 seconds
Started Dec 31 12:36:50 PM PST 23
Finished Dec 31 12:37:07 PM PST 23
Peak memory 213668 kb
Host smart-3c55ecf0-6af5-4838-92db-86289d820888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626088412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.2626088412
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.2044195178
Short name T370
Test name
Test status
Simulation time 1196035200 ps
CPU time 30.97 seconds
Started Dec 31 12:36:43 PM PST 23
Finished Dec 31 12:37:31 PM PST 23
Peak memory 250992 kb
Host smart-faeb8454-c72e-42c1-95bd-0b10c2fc70c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044195178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.2044195178
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.1480397210
Short name T497
Test name
Test status
Simulation time 59152349 ps
CPU time 6.44 seconds
Started Dec 31 12:37:04 PM PST 23
Finished Dec 31 12:37:25 PM PST 23
Peak memory 246544 kb
Host smart-baad9ce0-1d8f-4305-92c3-7cb2a8968f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480397210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.1480397210
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.1571792622
Short name T943
Test name
Test status
Simulation time 1849517703 ps
CPU time 73.05 seconds
Started Dec 31 12:36:58 PM PST 23
Finished Dec 31 12:38:27 PM PST 23
Peak memory 250704 kb
Host smart-377b437f-eac5-4dae-b41b-aff93ba198c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571792622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.1571792622
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.3502876284
Short name T714
Test name
Test status
Simulation time 28321257505 ps
CPU time 785.98 seconds
Started Dec 31 12:36:49 PM PST 23
Finished Dec 31 12:50:10 PM PST 23
Peak memory 268800 kb
Host smart-87a6efdc-ffc2-4412-a5bb-4983347b0ee0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3502876284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.3502876284
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2492344363
Short name T911
Test name
Test status
Simulation time 25276014 ps
CPU time 0.86 seconds
Started Dec 31 12:36:32 PM PST 23
Finished Dec 31 12:36:48 PM PST 23
Peak memory 208228 kb
Host smart-548d1712-df76-41f8-812f-c0016afb5350
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492344363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.2492344363
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.955376161
Short name T782
Test name
Test status
Simulation time 39506614 ps
CPU time 0.83 seconds
Started Dec 31 12:37:03 PM PST 23
Finished Dec 31 12:37:19 PM PST 23
Peak memory 209396 kb
Host smart-c3dccf96-b4af-41c8-b465-c112ebe69750
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955376161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.955376161
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.127818220
Short name T692
Test name
Test status
Simulation time 959939051 ps
CPU time 10.2 seconds
Started Dec 31 12:37:01 PM PST 23
Finished Dec 31 12:37:26 PM PST 23
Peak memory 218124 kb
Host smart-5201e448-0aaf-472f-ab8f-3b6373dd662c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127818220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.127818220
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.2586278127
Short name T703
Test name
Test status
Simulation time 2868689896 ps
CPU time 17.5 seconds
Started Dec 31 12:36:57 PM PST 23
Finished Dec 31 12:37:30 PM PST 23
Peak memory 209644 kb
Host smart-30dc89c3-67a1-4e23-8f11-a66d382e5446
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586278127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_a
ccess.2586278127
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.1349938276
Short name T946
Test name
Test status
Simulation time 341089368 ps
CPU time 4.11 seconds
Started Dec 31 12:36:53 PM PST 23
Finished Dec 31 12:37:12 PM PST 23
Peak memory 218144 kb
Host smart-0ced95cf-de28-4305-b9e1-9ca89ee7ba00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349938276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.1349938276
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.3521867083
Short name T384
Test name
Test status
Simulation time 721513248 ps
CPU time 13.47 seconds
Started Dec 31 12:36:44 PM PST 23
Finished Dec 31 12:37:15 PM PST 23
Peak memory 219096 kb
Host smart-072beb8c-aba4-43da-ac0e-559d4861589d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521867083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.3521867083
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.108581994
Short name T529
Test name
Test status
Simulation time 2017954346 ps
CPU time 9.7 seconds
Started Dec 31 12:37:13 PM PST 23
Finished Dec 31 12:37:35 PM PST 23
Peak memory 217980 kb
Host smart-6138b6e1-6eae-459a-8f77-44f8d72a8cf0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108581994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_di
gest.108581994
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.1062642336
Short name T352
Test name
Test status
Simulation time 859087622 ps
CPU time 8.41 seconds
Started Dec 31 12:37:05 PM PST 23
Finished Dec 31 12:37:27 PM PST 23
Peak memory 218024 kb
Host smart-da5a99a9-6859-4827-a1ff-a6da0c70dad4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062642336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
1062642336
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.249517878
Short name T570
Test name
Test status
Simulation time 1065195720 ps
CPU time 11.4 seconds
Started Dec 31 12:37:00 PM PST 23
Finished Dec 31 12:37:26 PM PST 23
Peak memory 218076 kb
Host smart-7b89a551-59b4-48f4-aba3-9564ed5cf381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249517878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.249517878
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.2277687985
Short name T750
Test name
Test status
Simulation time 80769840 ps
CPU time 1.97 seconds
Started Dec 31 12:37:01 PM PST 23
Finished Dec 31 12:37:18 PM PST 23
Peak memory 213348 kb
Host smart-3efc5e2a-3473-4acb-8152-c5971988deba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277687985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.2277687985
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.3314569683
Short name T611
Test name
Test status
Simulation time 393330686 ps
CPU time 31.01 seconds
Started Dec 31 12:36:49 PM PST 23
Finished Dec 31 12:37:36 PM PST 23
Peak memory 251008 kb
Host smart-4c6502dc-2ffa-4efb-9470-71fe24b9d9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314569683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.3314569683
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.13215836
Short name T506
Test name
Test status
Simulation time 378211464 ps
CPU time 4.11 seconds
Started Dec 31 12:36:52 PM PST 23
Finished Dec 31 12:37:10 PM PST 23
Peak memory 222324 kb
Host smart-e5cad0ab-3bd6-44bf-bc06-3de721314401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13215836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.13215836
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.655606968
Short name T649
Test name
Test status
Simulation time 19325702567 ps
CPU time 72.04 seconds
Started Dec 31 12:37:09 PM PST 23
Finished Dec 31 12:38:34 PM PST 23
Peak memory 226488 kb
Host smart-fd64003f-0786-4aae-ba11-44607a37ca18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655606968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.655606968
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1219541093
Short name T414
Test name
Test status
Simulation time 12676655 ps
CPU time 0.77 seconds
Started Dec 31 12:37:03 PM PST 23
Finished Dec 31 12:37:19 PM PST 23
Peak memory 208092 kb
Host smart-5ae9a4ff-2647-418a-9b3e-fdbf2c78c6da
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219541093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.1219541093
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.465690681
Short name T426
Test name
Test status
Simulation time 14281842 ps
CPU time 0.82 seconds
Started Dec 31 12:35:41 PM PST 23
Finished Dec 31 12:35:45 PM PST 23
Peak memory 209424 kb
Host smart-821ce0a3-6ca7-4f58-88b0-8d772f5c6ff0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465690681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.465690681
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.2553060014
Short name T473
Test name
Test status
Simulation time 3325316729 ps
CPU time 9.09 seconds
Started Dec 31 12:35:53 PM PST 23
Finished Dec 31 12:36:15 PM PST 23
Peak memory 218356 kb
Host smart-46742248-0c69-4df0-aa43-29b459a0ac8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553060014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.2553060014
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.3497768118
Short name T596
Test name
Test status
Simulation time 342020759 ps
CPU time 2.72 seconds
Started Dec 31 12:35:47 PM PST 23
Finished Dec 31 12:36:02 PM PST 23
Peak memory 209532 kb
Host smart-5a9fda29-1720-4aa0-a5de-f0e402672d93
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497768118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_ac
cess.3497768118
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.2879587350
Short name T840
Test name
Test status
Simulation time 3081790989 ps
CPU time 25.37 seconds
Started Dec 31 12:36:01 PM PST 23
Finished Dec 31 12:36:44 PM PST 23
Peak memory 219232 kb
Host smart-fcf7704e-61fe-4891-90cf-9d2b696731c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879587350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.2879587350
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.3548190433
Short name T602
Test name
Test status
Simulation time 2502483211 ps
CPU time 14.78 seconds
Started Dec 31 12:35:32 PM PST 23
Finished Dec 31 12:35:48 PM PST 23
Peak memory 217828 kb
Host smart-1d221d70-ea22-48c2-8ca8-772329076222
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548190433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
priority.3548190433
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.1083380860
Short name T926
Test name
Test status
Simulation time 1073229961 ps
CPU time 7.48 seconds
Started Dec 31 12:35:54 PM PST 23
Finished Dec 31 12:36:16 PM PST 23
Peak memory 218080 kb
Host smart-59ec643d-8804-4d05-9847-08db41486b3e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083380860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.1083380860
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.396898142
Short name T314
Test name
Test status
Simulation time 1258599792 ps
CPU time 16.53 seconds
Started Dec 31 12:35:58 PM PST 23
Finished Dec 31 12:36:32 PM PST 23
Peak memory 213048 kb
Host smart-15d3992a-2b46-4298-8e64-59c3c1c6f1e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396898142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_regwen_during_op.396898142
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.2180655559
Short name T585
Test name
Test status
Simulation time 226141722 ps
CPU time 2.87 seconds
Started Dec 31 12:35:40 PM PST 23
Finished Dec 31 12:35:47 PM PST 23
Peak memory 212832 kb
Host smart-a8e16511-bfc9-4ea2-b6fb-588285b3b4a9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180655559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
2180655559
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3680313990
Short name T533
Test name
Test status
Simulation time 8045556034 ps
CPU time 44.84 seconds
Started Dec 31 12:35:50 PM PST 23
Finished Dec 31 12:36:45 PM PST 23
Peak memory 283768 kb
Host smart-0fac39eb-dbfd-4222-ba0b-d5158709ad28
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680313990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.3680313990
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.1033184316
Short name T535
Test name
Test status
Simulation time 841043237 ps
CPU time 10.03 seconds
Started Dec 31 12:36:06 PM PST 23
Finished Dec 31 12:36:32 PM PST 23
Peak memory 244928 kb
Host smart-a7c2b79d-c109-48a8-ba0b-a271d6f5bf4a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033184316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.1033184316
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.1527600487
Short name T639
Test name
Test status
Simulation time 140720980 ps
CPU time 3.51 seconds
Started Dec 31 12:35:37 PM PST 23
Finished Dec 31 12:35:42 PM PST 23
Peak memory 218072 kb
Host smart-7917457b-9c6a-4468-913a-94c552dee175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527600487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.1527600487
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.3275252450
Short name T438
Test name
Test status
Simulation time 296314750 ps
CPU time 10.95 seconds
Started Dec 31 12:35:55 PM PST 23
Finished Dec 31 12:36:21 PM PST 23
Peak memory 214160 kb
Host smart-bb3793d3-9fcb-41ab-9d9d-7cb0e7eb786f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275252450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.3275252450
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.2316657964
Short name T60
Test name
Test status
Simulation time 901785461 ps
CPU time 37.66 seconds
Started Dec 31 12:35:54 PM PST 23
Finished Dec 31 12:36:46 PM PST 23
Peak memory 281480 kb
Host smart-bbc6f4b2-db71-4010-8030-5f534922c17c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316657964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.2316657964
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.794587961
Short name T350
Test name
Test status
Simulation time 705764608 ps
CPU time 11.96 seconds
Started Dec 31 12:35:57 PM PST 23
Finished Dec 31 12:36:26 PM PST 23
Peak memory 219076 kb
Host smart-0273d0f2-ffdd-4797-b70d-e6eec2eee479
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794587961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.794587961
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.3006387766
Short name T871
Test name
Test status
Simulation time 1867476910 ps
CPU time 9.45 seconds
Started Dec 31 12:35:46 PM PST 23
Finished Dec 31 12:36:05 PM PST 23
Peak memory 218092 kb
Host smart-70be4e27-efe2-409b-8d7f-3c322370d508
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006387766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.3006387766
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.3229220271
Short name T553
Test name
Test status
Simulation time 352334592 ps
CPU time 8.59 seconds
Started Dec 31 12:36:08 PM PST 23
Finished Dec 31 12:36:32 PM PST 23
Peak memory 217980 kb
Host smart-3cfa1927-3618-46c8-bf8d-c60a41352611
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229220271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.3
229220271
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.4218707771
Short name T184
Test name
Test status
Simulation time 804653476 ps
CPU time 5.93 seconds
Started Dec 31 12:35:50 PM PST 23
Finished Dec 31 12:36:06 PM PST 23
Peak memory 218060 kb
Host smart-17e834b5-68f9-443f-abd3-627984e4e20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218707771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.4218707771
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3285149635
Short name T748
Test name
Test status
Simulation time 14588554 ps
CPU time 1.31 seconds
Started Dec 31 12:35:54 PM PST 23
Finished Dec 31 12:36:10 PM PST 23
Peak memory 213144 kb
Host smart-eedfe861-8960-4147-a0d4-71fa055f4504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285149635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3285149635
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.556364822
Short name T862
Test name
Test status
Simulation time 237685267 ps
CPU time 26.47 seconds
Started Dec 31 12:35:44 PM PST 23
Finished Dec 31 12:36:17 PM PST 23
Peak memory 250916 kb
Host smart-be9d3f99-58dc-45dc-abaa-55f47722a236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556364822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.556364822
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.4155954940
Short name T562
Test name
Test status
Simulation time 353054598 ps
CPU time 3.59 seconds
Started Dec 31 12:36:06 PM PST 23
Finished Dec 31 12:36:26 PM PST 23
Peak memory 222416 kb
Host smart-99dc6192-5f6b-4613-98c2-f212f6683ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155954940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.4155954940
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.210570027
Short name T466
Test name
Test status
Simulation time 5680647833 ps
CPU time 54.62 seconds
Started Dec 31 12:35:59 PM PST 23
Finished Dec 31 12:37:11 PM PST 23
Peak memory 250676 kb
Host smart-11d4ae94-5729-42e8-9921-69fb28a19ecc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210570027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.210570027
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.885010540
Short name T12
Test name
Test status
Simulation time 145037236 ps
CPU time 1.02 seconds
Started Dec 31 12:36:01 PM PST 23
Finished Dec 31 12:36:19 PM PST 23
Peak memory 212600 kb
Host smart-d1ac8c67-5ce4-4d26-bbb2-180bf1ea1db5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885010540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr
l_volatile_unlock_smoke.885010540
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.118119100
Short name T981
Test name
Test status
Simulation time 22213132 ps
CPU time 0.86 seconds
Started Dec 31 12:37:03 PM PST 23
Finished Dec 31 12:37:19 PM PST 23
Peak memory 209524 kb
Host smart-7dad97da-3290-418f-9a6a-32aba3942f0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118119100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.118119100
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.2331679876
Short name T552
Test name
Test status
Simulation time 2449904607 ps
CPU time 12.42 seconds
Started Dec 31 12:36:40 PM PST 23
Finished Dec 31 12:37:10 PM PST 23
Peak memory 218120 kb
Host smart-045a9622-f4b6-400f-bf0b-5a47056a463e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331679876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2331679876
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.1246288668
Short name T894
Test name
Test status
Simulation time 424598632 ps
CPU time 5.03 seconds
Started Dec 31 12:37:04 PM PST 23
Finished Dec 31 12:37:23 PM PST 23
Peak memory 209524 kb
Host smart-2360175e-0279-435d-ad8d-13d4c1c6ee19
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246288668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_a
ccess.1246288668
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.2491574854
Short name T507
Test name
Test status
Simulation time 345453366 ps
CPU time 2.95 seconds
Started Dec 31 12:36:53 PM PST 23
Finished Dec 31 12:37:10 PM PST 23
Peak memory 218168 kb
Host smart-1b78dd8c-8df4-4733-9bfd-a3976b49385a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491574854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.2491574854
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.1869049989
Short name T618
Test name
Test status
Simulation time 811761453 ps
CPU time 15.71 seconds
Started Dec 31 12:36:56 PM PST 23
Finished Dec 31 12:37:27 PM PST 23
Peak memory 219084 kb
Host smart-40ca26bb-2367-4af3-a2ec-7d0fde1a8caa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869049989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.1869049989
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2664219600
Short name T330
Test name
Test status
Simulation time 280455707 ps
CPU time 10.88 seconds
Started Dec 31 12:36:51 PM PST 23
Finished Dec 31 12:37:17 PM PST 23
Peak memory 217976 kb
Host smart-3c607bf3-2261-4ad3-a4cb-3495c6ae958d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664219600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.2664219600
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.1339754766
Short name T347
Test name
Test status
Simulation time 186893879 ps
CPU time 6.06 seconds
Started Dec 31 12:37:04 PM PST 23
Finished Dec 31 12:37:25 PM PST 23
Peak memory 217988 kb
Host smart-07fc66ab-d8d5-441d-a245-eaa26118cc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339754766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.1339754766
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.1718206842
Short name T500
Test name
Test status
Simulation time 389237653 ps
CPU time 2.53 seconds
Started Dec 31 12:37:19 PM PST 23
Finished Dec 31 12:37:32 PM PST 23
Peak memory 213556 kb
Host smart-463d693d-00a6-4f65-97ff-46a541af0a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718206842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.1718206842
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.444497722
Short name T312
Test name
Test status
Simulation time 388302331 ps
CPU time 18.34 seconds
Started Dec 31 12:36:46 PM PST 23
Finished Dec 31 12:37:21 PM PST 23
Peak memory 244156 kb
Host smart-1a10fa8e-b294-414e-833d-acdc183c7c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444497722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.444497722
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.839814150
Short name T464
Test name
Test status
Simulation time 514439312 ps
CPU time 3.05 seconds
Started Dec 31 12:37:03 PM PST 23
Finished Dec 31 12:37:21 PM PST 23
Peak memory 218068 kb
Host smart-19c74697-27a9-4c44-8e25-14bb96b86c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839814150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.839814150
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.4261564764
Short name T732
Test name
Test status
Simulation time 65353003343 ps
CPU time 76.13 seconds
Started Dec 31 12:37:09 PM PST 23
Finished Dec 31 12:38:38 PM PST 23
Peak memory 251760 kb
Host smart-2bdf1fe5-8793-42b4-8992-a17e491cc0e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261564764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.4261564764
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.4078502991
Short name T8
Test name
Test status
Simulation time 23340297 ps
CPU time 0.75 seconds
Started Dec 31 12:36:52 PM PST 23
Finished Dec 31 12:37:07 PM PST 23
Peak memory 207900 kb
Host smart-3dc2e8cb-0f05-4e3a-a467-1aabbf458746
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078502991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.4078502991
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.3497943759
Short name T31
Test name
Test status
Simulation time 121017883 ps
CPU time 1.1 seconds
Started Dec 31 12:36:40 PM PST 23
Finished Dec 31 12:36:58 PM PST 23
Peak memory 208352 kb
Host smart-4552109e-63f6-481e-86b4-f733eb0e0460
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497943759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.3497943759
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.1141860481
Short name T853
Test name
Test status
Simulation time 1426778047 ps
CPU time 9.62 seconds
Started Dec 31 12:37:09 PM PST 23
Finished Dec 31 12:37:32 PM PST 23
Peak memory 217992 kb
Host smart-6cd672cc-a231-480e-a783-b7437f370c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141860481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.1141860481
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.3416884229
Short name T5
Test name
Test status
Simulation time 108645524 ps
CPU time 1.84 seconds
Started Dec 31 12:36:43 PM PST 23
Finished Dec 31 12:37:03 PM PST 23
Peak memory 209488 kb
Host smart-cf368790-2ed9-4c96-ae28-254acc689c96
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416884229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_a
ccess.3416884229
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.2820276864
Short name T189
Test name
Test status
Simulation time 76836473 ps
CPU time 3.84 seconds
Started Dec 31 12:37:25 PM PST 23
Finished Dec 31 12:37:37 PM PST 23
Peak memory 218072 kb
Host smart-90077829-eac1-4bb9-b1d1-86937a5d56ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820276864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.2820276864
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.1340394394
Short name T524
Test name
Test status
Simulation time 2100393956 ps
CPU time 10.77 seconds
Started Dec 31 12:37:07 PM PST 23
Finished Dec 31 12:37:31 PM PST 23
Peak memory 219188 kb
Host smart-ac688120-1243-44dd-a32d-d117840e13d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340394394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.1340394394
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.2703502177
Short name T914
Test name
Test status
Simulation time 270476227 ps
CPU time 11.71 seconds
Started Dec 31 12:36:53 PM PST 23
Finished Dec 31 12:37:19 PM PST 23
Peak memory 218004 kb
Host smart-84fcfd8d-7d16-44d1-85e0-38fd74304fea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703502177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.2703502177
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.4243811900
Short name T731
Test name
Test status
Simulation time 339425143 ps
CPU time 9.07 seconds
Started Dec 31 12:36:51 PM PST 23
Finished Dec 31 12:37:15 PM PST 23
Peak memory 218132 kb
Host smart-e77a0c5f-25d6-41ed-ba27-b4c1690a0cce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243811900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
4243811900
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.259803226
Short name T724
Test name
Test status
Simulation time 319954347 ps
CPU time 9.2 seconds
Started Dec 31 12:36:59 PM PST 23
Finished Dec 31 12:37:23 PM PST 23
Peak memory 218012 kb
Host smart-29db80be-0c61-4b49-aaf3-94f50cefd808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259803226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.259803226
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.1922799794
Short name T339
Test name
Test status
Simulation time 80027540 ps
CPU time 2.67 seconds
Started Dec 31 12:36:52 PM PST 23
Finished Dec 31 12:37:09 PM PST 23
Peak memory 213408 kb
Host smart-cd99129f-361a-4cbf-9507-c21042ea517c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922799794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.1922799794
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.2535862144
Short name T321
Test name
Test status
Simulation time 1571967676 ps
CPU time 21.68 seconds
Started Dec 31 12:36:55 PM PST 23
Finished Dec 31 12:37:32 PM PST 23
Peak memory 251052 kb
Host smart-0f6f6d75-8218-4c64-a89a-4b7be95e5ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535862144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.2535862144
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.1192763860
Short name T711
Test name
Test status
Simulation time 322067413 ps
CPU time 3.42 seconds
Started Dec 31 12:36:52 PM PST 23
Finished Dec 31 12:37:10 PM PST 23
Peak memory 222272 kb
Host smart-a885ffff-a7c0-4023-8aa7-73d64037aad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192763860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.1192763860
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.1663498118
Short name T686
Test name
Test status
Simulation time 59228492369 ps
CPU time 315.11 seconds
Started Dec 31 12:37:06 PM PST 23
Finished Dec 31 12:42:34 PM PST 23
Peak memory 275732 kb
Host smart-f44c53c3-dedd-4cac-8640-b4a48caff860
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663498118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.1663498118
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.667917753
Short name T46
Test name
Test status
Simulation time 157731003 ps
CPU time 0.88 seconds
Started Dec 31 12:37:17 PM PST 23
Finished Dec 31 12:37:29 PM PST 23
Peak memory 211404 kb
Host smart-bcc2a87d-1f96-42bd-bc6e-dcf1d5a19261
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667917753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ct
rl_volatile_unlock_smoke.667917753
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.2662812716
Short name T885
Test name
Test status
Simulation time 62060839 ps
CPU time 0.94 seconds
Started Dec 31 12:37:04 PM PST 23
Finished Dec 31 12:37:19 PM PST 23
Peak memory 208248 kb
Host smart-7f8210f4-0b70-4bcc-9036-ddd37e554534
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662812716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.2662812716
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.3026577699
Short name T856
Test name
Test status
Simulation time 1157896692 ps
CPU time 9.38 seconds
Started Dec 31 12:36:48 PM PST 23
Finished Dec 31 12:37:13 PM PST 23
Peak memory 218056 kb
Host smart-01542441-f6f4-49ca-8c08-b72cdc1362fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026577699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.3026577699
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.822393434
Short name T685
Test name
Test status
Simulation time 2173023873 ps
CPU time 5.02 seconds
Started Dec 31 12:36:49 PM PST 23
Finished Dec 31 12:37:10 PM PST 23
Peak memory 209588 kb
Host smart-c4337b8e-f5b8-4e1b-9966-0c593cdb248e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822393434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_ac
cess.822393434
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.750481669
Short name T629
Test name
Test status
Simulation time 44188681 ps
CPU time 2.31 seconds
Started Dec 31 12:37:18 PM PST 23
Finished Dec 31 12:37:31 PM PST 23
Peak memory 218148 kb
Host smart-44830e76-8feb-47b7-9624-02b037de318f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750481669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.750481669
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.3370336443
Short name T341
Test name
Test status
Simulation time 403293596 ps
CPU time 10.22 seconds
Started Dec 31 12:37:15 PM PST 23
Finished Dec 31 12:37:40 PM PST 23
Peak memory 218168 kb
Host smart-d891735c-96d2-43aa-b518-4d5e55d0b3b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370336443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.3370336443
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.3652230298
Short name T701
Test name
Test status
Simulation time 1517470955 ps
CPU time 12.03 seconds
Started Dec 31 12:37:05 PM PST 23
Finished Dec 31 12:37:31 PM PST 23
Peak memory 218016 kb
Host smart-a7223565-4ef1-4248-986b-53d60edf1a25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652230298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.3652230298
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.4186250703
Short name T971
Test name
Test status
Simulation time 1274445835 ps
CPU time 9.76 seconds
Started Dec 31 12:37:21 PM PST 23
Finished Dec 31 12:37:41 PM PST 23
Peak memory 218088 kb
Host smart-f804e616-8027-4721-a0b4-de6850d7b2c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186250703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
4186250703
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.3720380058
Short name T451
Test name
Test status
Simulation time 400698000 ps
CPU time 10.5 seconds
Started Dec 31 12:36:43 PM PST 23
Finished Dec 31 12:37:11 PM PST 23
Peak memory 218140 kb
Host smart-3a4e9fc3-9867-4878-8367-4501556b0f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720380058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.3720380058
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.3948398304
Short name T64
Test name
Test status
Simulation time 19377948 ps
CPU time 1.33 seconds
Started Dec 31 12:36:52 PM PST 23
Finished Dec 31 12:37:08 PM PST 23
Peak memory 213156 kb
Host smart-1b8e9447-8cdf-4ded-abf3-2ec2f042a33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948398304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.3948398304
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.3540287636
Short name T556
Test name
Test status
Simulation time 339197439 ps
CPU time 21.69 seconds
Started Dec 31 12:36:45 PM PST 23
Finished Dec 31 12:37:23 PM PST 23
Peak memory 250980 kb
Host smart-9dc2306e-da65-4ca4-b2bb-47ca16c80fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540287636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3540287636
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3478626213
Short name T859
Test name
Test status
Simulation time 383671309 ps
CPU time 2.84 seconds
Started Dec 31 12:36:47 PM PST 23
Finished Dec 31 12:37:06 PM PST 23
Peak memory 222112 kb
Host smart-fc84f415-400f-46ce-8f34-fa88e086fcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478626213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3478626213
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.2604320057
Short name T851
Test name
Test status
Simulation time 20088727562 ps
CPU time 80.37 seconds
Started Dec 31 12:36:41 PM PST 23
Finished Dec 31 12:38:20 PM PST 23
Peak memory 226260 kb
Host smart-f83cff2d-6876-401f-a054-f59c2e831ecf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604320057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.2604320057
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.668444593
Short name T34
Test name
Test status
Simulation time 33463706 ps
CPU time 0.89 seconds
Started Dec 31 12:36:49 PM PST 23
Finished Dec 31 12:37:05 PM PST 23
Peak memory 211296 kb
Host smart-d965bd80-2e4e-4f3f-884f-6f9fb8af4734
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668444593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ct
rl_volatile_unlock_smoke.668444593
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.452610405
Short name T947
Test name
Test status
Simulation time 32164870 ps
CPU time 1.49 seconds
Started Dec 31 12:37:00 PM PST 23
Finished Dec 31 12:37:16 PM PST 23
Peak memory 209584 kb
Host smart-867ef7b9-ab58-47a1-bdf5-d5dc3ad48ebc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452610405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.452610405
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.2745966037
Short name T942
Test name
Test status
Simulation time 216862723 ps
CPU time 7.37 seconds
Started Dec 31 12:37:06 PM PST 23
Finished Dec 31 12:37:26 PM PST 23
Peak memory 218084 kb
Host smart-37426938-52bf-4d5b-9a00-2a8970d1edae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745966037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2745966037
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.2127587909
Short name T812
Test name
Test status
Simulation time 143880411 ps
CPU time 2.23 seconds
Started Dec 31 12:37:17 PM PST 23
Finished Dec 31 12:37:31 PM PST 23
Peak memory 209520 kb
Host smart-fb850a4e-b3de-470b-aca1-9eaf2a29b1bd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127587909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_a
ccess.2127587909
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.3703936997
Short name T897
Test name
Test status
Simulation time 480493342 ps
CPU time 3.47 seconds
Started Dec 31 12:36:52 PM PST 23
Finished Dec 31 12:37:10 PM PST 23
Peak memory 218020 kb
Host smart-c59be41a-a02c-4591-8767-9005d6521a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703936997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.3703936997
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.3141777941
Short name T880
Test name
Test status
Simulation time 320398146 ps
CPU time 12.24 seconds
Started Dec 31 12:37:03 PM PST 23
Finished Dec 31 12:37:30 PM PST 23
Peak memory 218088 kb
Host smart-4fd58d7a-b3d6-4984-8290-cfc7479a3f94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141777941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.3141777941
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.1227911659
Short name T541
Test name
Test status
Simulation time 1518210000 ps
CPU time 11.04 seconds
Started Dec 31 12:36:57 PM PST 23
Finished Dec 31 12:37:23 PM PST 23
Peak memory 218016 kb
Host smart-7029854b-ceee-43b3-be3d-533d8c7ad0fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227911659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.1227911659
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2884038529
Short name T702
Test name
Test status
Simulation time 229473459 ps
CPU time 6.35 seconds
Started Dec 31 12:36:49 PM PST 23
Finished Dec 31 12:37:11 PM PST 23
Peak memory 218108 kb
Host smart-d8a8164c-6383-4f04-9ddb-1cf2e8811c41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884038529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
2884038529
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.3499852564
Short name T123
Test name
Test status
Simulation time 193994669 ps
CPU time 9.93 seconds
Started Dec 31 12:36:49 PM PST 23
Finished Dec 31 12:37:14 PM PST 23
Peak memory 218424 kb
Host smart-f936eaf2-cdb8-4787-b344-314e4f8fcdd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499852564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.3499852564
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.3614609557
Short name T671
Test name
Test status
Simulation time 34273921 ps
CPU time 2.18 seconds
Started Dec 31 12:36:54 PM PST 23
Finished Dec 31 12:37:10 PM PST 23
Peak memory 214016 kb
Host smart-218ee9ca-5c6d-4014-ab76-bcefac883ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614609557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.3614609557
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.237227143
Short name T383
Test name
Test status
Simulation time 274010958 ps
CPU time 25.34 seconds
Started Dec 31 12:36:54 PM PST 23
Finished Dec 31 12:37:34 PM PST 23
Peak memory 251008 kb
Host smart-f9a6cb6c-5241-4912-b241-76b95f8f6715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237227143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.237227143
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2082425711
Short name T683
Test name
Test status
Simulation time 326514352 ps
CPU time 5.65 seconds
Started Dec 31 12:36:59 PM PST 23
Finished Dec 31 12:37:19 PM PST 23
Peak memory 246664 kb
Host smart-cb062717-9379-48dc-a51e-c6610fd4df8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082425711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2082425711
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.2213012757
Short name T387
Test name
Test status
Simulation time 477512415 ps
CPU time 5.95 seconds
Started Dec 31 12:37:11 PM PST 23
Finished Dec 31 12:37:29 PM PST 23
Peak memory 217044 kb
Host smart-daf9fac7-e118-4d23-9ffc-3183fa541fc8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213012757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.2213012757
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1746731912
Short name T624
Test name
Test status
Simulation time 12884188 ps
CPU time 1.1 seconds
Started Dec 31 12:37:20 PM PST 23
Finished Dec 31 12:37:32 PM PST 23
Peak memory 211424 kb
Host smart-358c60b5-e3b5-44e9-872d-668df2687616
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746731912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.1746731912
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.31160026
Short name T498
Test name
Test status
Simulation time 14798514 ps
CPU time 0.86 seconds
Started Dec 31 12:37:07 PM PST 23
Finished Dec 31 12:37:21 PM PST 23
Peak memory 209600 kb
Host smart-b9297f31-455f-42b9-84c6-b1095fab8a8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31160026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.31160026
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.796101691
Short name T595
Test name
Test status
Simulation time 376963148 ps
CPU time 17.03 seconds
Started Dec 31 12:36:55 PM PST 23
Finished Dec 31 12:37:27 PM PST 23
Peak memory 218084 kb
Host smart-1a31d4a5-7e25-41ae-a6cb-fdbe88d4fca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796101691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.796101691
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.1742452969
Short name T958
Test name
Test status
Simulation time 286679939 ps
CPU time 1.57 seconds
Started Dec 31 12:37:04 PM PST 23
Finished Dec 31 12:37:20 PM PST 23
Peak memory 209692 kb
Host smart-686f72f9-27c2-4f66-bb81-774103084ddd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742452969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_a
ccess.1742452969
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.214596105
Short name T674
Test name
Test status
Simulation time 115564905 ps
CPU time 1.73 seconds
Started Dec 31 12:36:47 PM PST 23
Finished Dec 31 12:37:04 PM PST 23
Peak memory 218032 kb
Host smart-fea23f0e-c645-402a-9f91-6092014c68b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214596105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.214596105
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.3523457368
Short name T432
Test name
Test status
Simulation time 1224776563 ps
CPU time 14.27 seconds
Started Dec 31 12:36:54 PM PST 23
Finished Dec 31 12:37:22 PM PST 23
Peak memory 219108 kb
Host smart-9b2903a5-81b7-4f5a-9333-e8d5669358e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523457368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.3523457368
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.1574114468
Short name T978
Test name
Test status
Simulation time 959728449 ps
CPU time 10.22 seconds
Started Dec 31 12:37:09 PM PST 23
Finished Dec 31 12:37:32 PM PST 23
Peak memory 217984 kb
Host smart-2f29e371-bb99-4cea-bceb-4bf0401e5c82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574114468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.1574114468
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.3145725492
Short name T836
Test name
Test status
Simulation time 488704659 ps
CPU time 8.19 seconds
Started Dec 31 12:37:09 PM PST 23
Finished Dec 31 12:37:30 PM PST 23
Peak memory 217992 kb
Host smart-c3d17e1c-f303-4605-901f-6e343d3325dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145725492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
3145725492
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.1151655043
Short name T784
Test name
Test status
Simulation time 452075184 ps
CPU time 8.98 seconds
Started Dec 31 12:36:58 PM PST 23
Finished Dec 31 12:37:22 PM PST 23
Peak memory 218040 kb
Host smart-c86f9b0f-def5-45a3-b4de-7f75b8282342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151655043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1151655043
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.2803435701
Short name T537
Test name
Test status
Simulation time 46915426 ps
CPU time 2.86 seconds
Started Dec 31 12:36:57 PM PST 23
Finished Dec 31 12:37:15 PM PST 23
Peak memory 214400 kb
Host smart-818251b7-fe9b-4b0a-8c1a-02c8f51c9bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803435701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.2803435701
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.1037385503
Short name T539
Test name
Test status
Simulation time 1048366816 ps
CPU time 24.39 seconds
Started Dec 31 12:37:01 PM PST 23
Finished Dec 31 12:37:41 PM PST 23
Peak memory 251032 kb
Host smart-552e5b9d-bc45-40eb-9887-326e16c89c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037385503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.1037385503
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.1746484739
Short name T847
Test name
Test status
Simulation time 329805636 ps
CPU time 4.37 seconds
Started Dec 31 12:37:13 PM PST 23
Finished Dec 31 12:37:33 PM PST 23
Peak memory 221900 kb
Host smart-91eceed3-382a-4d81-875f-1cd3beacec45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746484739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.1746484739
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.4021537179
Short name T516
Test name
Test status
Simulation time 13451747977 ps
CPU time 152.6 seconds
Started Dec 31 12:37:11 PM PST 23
Finished Dec 31 12:39:56 PM PST 23
Peak memory 251120 kb
Host smart-2b6f7aee-4877-4cdd-bfa2-dc22b8779e0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021537179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.4021537179
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3543864022
Short name T397
Test name
Test status
Simulation time 33029855 ps
CPU time 0.83 seconds
Started Dec 31 12:36:59 PM PST 23
Finished Dec 31 12:37:15 PM PST 23
Peak memory 208008 kb
Host smart-46809524-3f46-46ac-a671-b79092ab502c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543864022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.3543864022
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.3491924129
Short name T572
Test name
Test status
Simulation time 36642330 ps
CPU time 0.91 seconds
Started Dec 31 12:36:58 PM PST 23
Finished Dec 31 12:37:14 PM PST 23
Peak memory 209592 kb
Host smart-487dcb7d-d4a8-43e3-94dd-54733768bbed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491924129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.3491924129
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.2814993024
Short name T967
Test name
Test status
Simulation time 651026895 ps
CPU time 10.28 seconds
Started Dec 31 12:37:05 PM PST 23
Finished Dec 31 12:37:29 PM PST 23
Peak memory 218040 kb
Host smart-eeb3210c-1722-441d-a83e-1f56a919dac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814993024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.2814993024
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.4037068404
Short name T941
Test name
Test status
Simulation time 1538985537 ps
CPU time 3.25 seconds
Started Dec 31 12:36:46 PM PST 23
Finished Dec 31 12:37:06 PM PST 23
Peak memory 209612 kb
Host smart-74a66c93-3d23-48ea-85d8-f1168a6db816
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037068404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_a
ccess.4037068404
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.48923652
Short name T471
Test name
Test status
Simulation time 98705860 ps
CPU time 4.19 seconds
Started Dec 31 12:36:50 PM PST 23
Finished Dec 31 12:37:09 PM PST 23
Peak memory 218092 kb
Host smart-dfa8a7a8-c750-4ec4-859b-9ae8f0fe3cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48923652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.48923652
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.118163909
Short name T623
Test name
Test status
Simulation time 710350863 ps
CPU time 26.01 seconds
Started Dec 31 12:37:08 PM PST 23
Finished Dec 31 12:37:47 PM PST 23
Peak memory 218208 kb
Host smart-0f985b10-f3c5-412c-96e9-eecb747c42a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118163909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.118163909
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.1742940165
Short name T390
Test name
Test status
Simulation time 2346384594 ps
CPU time 14.25 seconds
Started Dec 31 12:37:08 PM PST 23
Finished Dec 31 12:37:36 PM PST 23
Peak memory 218112 kb
Host smart-4b050c3e-09a2-4a80-89f9-fac897fcdfa2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742940165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.1742940165
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.2519144175
Short name T637
Test name
Test status
Simulation time 1833767527 ps
CPU time 10.93 seconds
Started Dec 31 12:36:57 PM PST 23
Finished Dec 31 12:37:23 PM PST 23
Peak memory 218040 kb
Host smart-90254826-7c4b-49ff-9d93-7f8437fa1691
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519144175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
2519144175
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.1890062999
Short name T888
Test name
Test status
Simulation time 815807136 ps
CPU time 6.19 seconds
Started Dec 31 12:36:46 PM PST 23
Finished Dec 31 12:37:08 PM PST 23
Peak memory 218084 kb
Host smart-ae6afc50-e2a7-4643-9e56-c2fd308d705d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890062999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1890062999
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.55148497
Short name T528
Test name
Test status
Simulation time 616633806 ps
CPU time 4.93 seconds
Started Dec 31 12:37:06 PM PST 23
Finished Dec 31 12:37:25 PM PST 23
Peak memory 213688 kb
Host smart-a4fcb414-8a26-4506-af03-0c39b69d7b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55148497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.55148497
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.1568717836
Short name T796
Test name
Test status
Simulation time 259156993 ps
CPU time 21.03 seconds
Started Dec 31 12:37:03 PM PST 23
Finished Dec 31 12:37:39 PM PST 23
Peak memory 251048 kb
Host smart-2e57cc1d-bfe7-4f68-9787-0cd58f36a6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568717836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.1568717836
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.2050343743
Short name T603
Test name
Test status
Simulation time 278005636 ps
CPU time 6.17 seconds
Started Dec 31 12:36:52 PM PST 23
Finished Dec 31 12:37:12 PM PST 23
Peak memory 250456 kb
Host smart-9eb48c80-e38a-42ad-a642-d85d10af54b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050343743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2050343743
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.3510898180
Short name T837
Test name
Test status
Simulation time 37630228836 ps
CPU time 127.52 seconds
Started Dec 31 12:37:31 PM PST 23
Finished Dec 31 12:39:45 PM PST 23
Peak memory 255444 kb
Host smart-220c8758-30f1-4588-a591-f3af86c2730c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510898180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.3510898180
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.512189382
Short name T739
Test name
Test status
Simulation time 13279264 ps
CPU time 0.97 seconds
Started Dec 31 12:36:45 PM PST 23
Finished Dec 31 12:37:03 PM PST 23
Peak memory 208068 kb
Host smart-92165bb3-d022-42df-9287-914b76751e17
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512189382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ct
rl_volatile_unlock_smoke.512189382
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.3394864863
Short name T925
Test name
Test status
Simulation time 23874414 ps
CPU time 1.03 seconds
Started Dec 31 12:37:11 PM PST 23
Finished Dec 31 12:37:25 PM PST 23
Peak memory 208316 kb
Host smart-b68d9a2c-66e7-42c0-be84-e37811036563
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394864863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3394864863
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.3075974393
Short name T15
Test name
Test status
Simulation time 499141469 ps
CPU time 12.87 seconds
Started Dec 31 12:37:22 PM PST 23
Finished Dec 31 12:37:45 PM PST 23
Peak memory 218428 kb
Host smart-16e8761d-2bf7-4430-9feb-372e789c289f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075974393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.3075974393
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.3282547548
Short name T659
Test name
Test status
Simulation time 723592947 ps
CPU time 2.32 seconds
Started Dec 31 12:36:59 PM PST 23
Finished Dec 31 12:37:17 PM PST 23
Peak memory 209520 kb
Host smart-a5e786ba-313d-4b58-8328-6b4fcc4302f4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282547548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_a
ccess.3282547548
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.2834535037
Short name T375
Test name
Test status
Simulation time 104393095 ps
CPU time 2.84 seconds
Started Dec 31 12:36:56 PM PST 23
Finished Dec 31 12:37:14 PM PST 23
Peak memory 218068 kb
Host smart-966256f1-d049-4477-b406-dd4cab1faf85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834535037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.2834535037
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.1454311946
Short name T869
Test name
Test status
Simulation time 292235642 ps
CPU time 8.91 seconds
Started Dec 31 12:37:01 PM PST 23
Finished Dec 31 12:37:25 PM PST 23
Peak memory 218412 kb
Host smart-3c0e9db9-38a1-42dc-ac25-d77f832f1509
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454311946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.1454311946
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.2289149217
Short name T845
Test name
Test status
Simulation time 422891854 ps
CPU time 13.56 seconds
Started Dec 31 12:37:21 PM PST 23
Finished Dec 31 12:37:45 PM PST 23
Peak memory 218016 kb
Host smart-47356be7-5a48-48d9-93dc-a625c92ea1f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289149217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.2289149217
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.1768833563
Short name T327
Test name
Test status
Simulation time 464215331 ps
CPU time 14.59 seconds
Started Dec 31 12:36:51 PM PST 23
Finished Dec 31 12:37:20 PM PST 23
Peak memory 218008 kb
Host smart-70276249-4255-45e1-8a5b-8d4abd92f0cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768833563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
1768833563
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.1139087004
Short name T561
Test name
Test status
Simulation time 506915325 ps
CPU time 10.04 seconds
Started Dec 31 12:37:03 PM PST 23
Finished Dec 31 12:37:28 PM PST 23
Peak memory 218076 kb
Host smart-13448448-e494-4f96-9b1c-7af2c9fa7f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139087004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1139087004
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.1038337691
Short name T608
Test name
Test status
Simulation time 181885465 ps
CPU time 2.52 seconds
Started Dec 31 12:37:10 PM PST 23
Finished Dec 31 12:37:25 PM PST 23
Peak memory 213800 kb
Host smart-2257b127-e98e-49c3-a4ee-09034bd484dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038337691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1038337691
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.2622580558
Short name T761
Test name
Test status
Simulation time 1274068424 ps
CPU time 22.09 seconds
Started Dec 31 12:36:35 PM PST 23
Finished Dec 31 12:37:13 PM PST 23
Peak memory 251104 kb
Host smart-7f8aa8f5-bd66-4e82-8b90-c850bb46e88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622580558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.2622580558
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.1870892731
Short name T781
Test name
Test status
Simulation time 282921114 ps
CPU time 6.66 seconds
Started Dec 31 12:37:17 PM PST 23
Finished Dec 31 12:37:35 PM PST 23
Peak memory 250816 kb
Host smart-a2de7ec6-33a7-49a9-b6aa-0f7148e9ffcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870892731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.1870892731
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.257771545
Short name T161
Test name
Test status
Simulation time 38320972837 ps
CPU time 168.71 seconds
Started Dec 31 12:37:09 PM PST 23
Finished Dec 31 12:40:10 PM PST 23
Peak memory 251112 kb
Host smart-28711958-b839-4b9a-943c-a0729aef2ae7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257771545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.257771545
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.4031913916
Short name T457
Test name
Test status
Simulation time 45944852 ps
CPU time 0.98 seconds
Started Dec 31 12:37:49 PM PST 23
Finished Dec 31 12:37:51 PM PST 23
Peak memory 209656 kb
Host smart-852fa470-998e-4eae-a0ac-23f2e2db8b09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031913916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.4031913916
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.3668332788
Short name T948
Test name
Test status
Simulation time 288798558 ps
CPU time 8.53 seconds
Started Dec 31 12:37:35 PM PST 23
Finished Dec 31 12:37:47 PM PST 23
Peak memory 218080 kb
Host smart-4b64a5a5-b941-417f-abc4-351c3e5670a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668332788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.3668332788
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.408437063
Short name T436
Test name
Test status
Simulation time 1069476441 ps
CPU time 7.19 seconds
Started Dec 31 12:37:32 PM PST 23
Finished Dec 31 12:37:44 PM PST 23
Peak memory 209528 kb
Host smart-c6f69830-9347-4bad-9ad9-ac842688aa14
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408437063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_ac
cess.408437063
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.2589432664
Short name T757
Test name
Test status
Simulation time 431233433 ps
CPU time 2.81 seconds
Started Dec 31 12:36:59 PM PST 23
Finished Dec 31 12:37:17 PM PST 23
Peak memory 218088 kb
Host smart-0b1062dd-23e2-4a80-b29d-2cebb195d6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589432664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2589432664
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.550726904
Short name T335
Test name
Test status
Simulation time 641417658 ps
CPU time 11.47 seconds
Started Dec 31 12:37:09 PM PST 23
Finished Dec 31 12:37:33 PM PST 23
Peak memory 219052 kb
Host smart-1bdca2fe-1a7a-4faf-9aaa-ada5c9522adc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550726904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.550726904
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.4261694104
Short name T769
Test name
Test status
Simulation time 2663322822 ps
CPU time 11.52 seconds
Started Dec 31 12:37:16 PM PST 23
Finished Dec 31 12:37:39 PM PST 23
Peak memory 218104 kb
Host smart-de6401c7-3a1a-44b0-8f8b-016b5e691a1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261694104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.4261694104
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.2387299619
Short name T788
Test name
Test status
Simulation time 390196345 ps
CPU time 12.29 seconds
Started Dec 31 12:37:23 PM PST 23
Finished Dec 31 12:37:44 PM PST 23
Peak memory 218024 kb
Host smart-b4446566-ec58-4145-b94b-728aeab8b659
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387299619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
2387299619
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2754228005
Short name T520
Test name
Test status
Simulation time 55724361 ps
CPU time 2.13 seconds
Started Dec 31 12:37:13 PM PST 23
Finished Dec 31 12:37:27 PM PST 23
Peak memory 213696 kb
Host smart-873a3aea-1baf-4768-9b19-aa8bf46ff1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754228005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2754228005
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.3066443181
Short name T342
Test name
Test status
Simulation time 365671913 ps
CPU time 20.21 seconds
Started Dec 31 12:37:11 PM PST 23
Finished Dec 31 12:37:44 PM PST 23
Peak memory 251044 kb
Host smart-3ea7e68f-b2bf-4e3e-b35b-2ec6596f2c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066443181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3066443181
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.1084460688
Short name T720
Test name
Test status
Simulation time 95395617 ps
CPU time 8.67 seconds
Started Dec 31 12:37:03 PM PST 23
Finished Dec 31 12:37:26 PM PST 23
Peak memory 251072 kb
Host smart-9ade20e8-056d-476d-bff9-5ebce8429e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084460688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.1084460688
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.2705107389
Short name T83
Test name
Test status
Simulation time 14360391634 ps
CPU time 103.13 seconds
Started Dec 31 12:37:03 PM PST 23
Finished Dec 31 12:39:01 PM PST 23
Peak memory 250884 kb
Host smart-41653142-2c34-4213-98f4-7c72a220269c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705107389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.2705107389
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.1006254102
Short name T521
Test name
Test status
Simulation time 62358239943 ps
CPU time 424.49 seconds
Started Dec 31 12:37:15 PM PST 23
Finished Dec 31 12:44:31 PM PST 23
Peak memory 438636 kb
Host smart-00293a4e-d9d4-41f2-a5e6-697d8712158d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1006254102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.1006254102
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2001956286
Short name T980
Test name
Test status
Simulation time 27799980 ps
CPU time 0.87 seconds
Started Dec 31 12:36:55 PM PST 23
Finished Dec 31 12:37:11 PM PST 23
Peak memory 208008 kb
Host smart-379ae831-f761-421d-9a3f-dc0de9dbf461
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001956286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.2001956286
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.3139162018
Short name T704
Test name
Test status
Simulation time 30154926 ps
CPU time 0.84 seconds
Started Dec 31 12:37:15 PM PST 23
Finished Dec 31 12:37:27 PM PST 23
Peak memory 209580 kb
Host smart-da121a7c-ea3f-408c-99e4-8d3a7fbfd3f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139162018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.3139162018
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.4268879004
Short name T409
Test name
Test status
Simulation time 333320965 ps
CPU time 8.31 seconds
Started Dec 31 12:37:01 PM PST 23
Finished Dec 31 12:37:25 PM PST 23
Peak memory 218032 kb
Host smart-d3c7b8d1-6acc-42b9-8c98-7e878dd4c10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268879004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.4268879004
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.2676266386
Short name T437
Test name
Test status
Simulation time 244364313 ps
CPU time 1.4 seconds
Started Dec 31 12:37:27 PM PST 23
Finished Dec 31 12:37:37 PM PST 23
Peak memory 209536 kb
Host smart-34801d9f-887c-44d0-9e47-dcbae23403ce
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676266386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_a
ccess.2676266386
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.2979810867
Short name T118
Test name
Test status
Simulation time 38057829 ps
CPU time 2.43 seconds
Started Dec 31 12:37:06 PM PST 23
Finished Dec 31 12:37:21 PM PST 23
Peak memory 218084 kb
Host smart-84051728-c22d-4885-8e4a-5b6164b83556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979810867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.2979810867
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.973516672
Short name T569
Test name
Test status
Simulation time 243204131 ps
CPU time 7.8 seconds
Started Dec 31 12:37:08 PM PST 23
Finished Dec 31 12:37:29 PM PST 23
Peak memory 219076 kb
Host smart-8ec85f12-d59f-43d4-b1c1-df3648ddfb5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973516672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.973516672
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.610636806
Short name T415
Test name
Test status
Simulation time 2143576504 ps
CPU time 9.31 seconds
Started Dec 31 12:36:59 PM PST 23
Finished Dec 31 12:37:23 PM PST 23
Peak memory 218028 kb
Host smart-3c78dfa7-3ea2-43a4-a974-b3c6f6d6d926
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610636806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_di
gest.610636806
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.836008385
Short name T411
Test name
Test status
Simulation time 238896909 ps
CPU time 8.01 seconds
Started Dec 31 12:37:20 PM PST 23
Finished Dec 31 12:37:39 PM PST 23
Peak memory 218012 kb
Host smart-b3fa56c0-2197-4876-af98-abdbfdd53f9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836008385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.836008385
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.1235441368
Short name T627
Test name
Test status
Simulation time 360935902 ps
CPU time 12.39 seconds
Started Dec 31 12:37:02 PM PST 23
Finished Dec 31 12:37:29 PM PST 23
Peak memory 218020 kb
Host smart-4800e91f-a06c-46c6-82f6-0f114525011e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235441368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.1235441368
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.2807608343
Short name T75
Test name
Test status
Simulation time 145774562 ps
CPU time 2.51 seconds
Started Dec 31 12:37:01 PM PST 23
Finished Dec 31 12:37:19 PM PST 23
Peak memory 214000 kb
Host smart-4ec31041-2674-4eed-b304-223774d4ea61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807608343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.2807608343
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.3342793539
Short name T762
Test name
Test status
Simulation time 768752488 ps
CPU time 26.04 seconds
Started Dec 31 12:37:32 PM PST 23
Finished Dec 31 12:38:03 PM PST 23
Peak memory 250956 kb
Host smart-0b7be34c-2825-4d70-9368-f688fc6b1c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342793539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3342793539
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.540993223
Short name T359
Test name
Test status
Simulation time 229733884 ps
CPU time 3.33 seconds
Started Dec 31 12:37:08 PM PST 23
Finished Dec 31 12:37:24 PM PST 23
Peak memory 226472 kb
Host smart-429dc204-a5ee-4a50-80d3-e7c47bfb3996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540993223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.540993223
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.1383744315
Short name T656
Test name
Test status
Simulation time 11429672980 ps
CPU time 75.02 seconds
Started Dec 31 12:37:08 PM PST 23
Finished Dec 31 12:38:37 PM PST 23
Peak memory 282832 kb
Host smart-19f36872-c762-4df3-92b9-c4f960630ae1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383744315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.1383744315
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.1261685006
Short name T923
Test name
Test status
Simulation time 12039230 ps
CPU time 0.92 seconds
Started Dec 31 12:37:18 PM PST 23
Finished Dec 31 12:37:30 PM PST 23
Peak memory 208492 kb
Host smart-8d1959d8-8a38-4396-b48c-b539265cae3d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261685006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.1261685006
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.4119970694
Short name T899
Test name
Test status
Simulation time 26103314 ps
CPU time 0.98 seconds
Started Dec 31 12:37:07 PM PST 23
Finished Dec 31 12:37:21 PM PST 23
Peak memory 209624 kb
Host smart-90c8a39f-e8f6-49fe-8550-2f0f479d7fe2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119970694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.4119970694
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.2023427812
Short name T324
Test name
Test status
Simulation time 2298999638 ps
CPU time 16.06 seconds
Started Dec 31 12:37:15 PM PST 23
Finished Dec 31 12:37:42 PM PST 23
Peak memory 218108 kb
Host smart-6bbfb6b3-08b4-4728-9c50-eb033dcfa976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023427812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.2023427812
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.1318070667
Short name T545
Test name
Test status
Simulation time 129406321 ps
CPU time 2.97 seconds
Started Dec 31 12:37:13 PM PST 23
Finished Dec 31 12:37:28 PM PST 23
Peak memory 209496 kb
Host smart-b541512d-d96b-41fc-8608-38b95a8b7183
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318070667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_a
ccess.1318070667
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.398356910
Short name T495
Test name
Test status
Simulation time 40286503 ps
CPU time 1.99 seconds
Started Dec 31 12:37:35 PM PST 23
Finished Dec 31 12:37:41 PM PST 23
Peak memory 218072 kb
Host smart-913db486-a1e6-4bd1-8841-1440b6d2681d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398356910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.398356910
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.3445572104
Short name T340
Test name
Test status
Simulation time 302881468 ps
CPU time 12.05 seconds
Started Dec 31 12:37:05 PM PST 23
Finished Dec 31 12:37:31 PM PST 23
Peak memory 218064 kb
Host smart-dd7eb976-8d35-4412-837e-213aebc1004a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445572104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.3445572104
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1176940777
Short name T319
Test name
Test status
Simulation time 382930028 ps
CPU time 9.88 seconds
Started Dec 31 12:37:00 PM PST 23
Finished Dec 31 12:37:25 PM PST 23
Peak memory 218016 kb
Host smart-afb6fa2c-1f14-4d1c-9aa1-3b6bd336d4db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176940777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1176940777
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.3182952478
Short name T364
Test name
Test status
Simulation time 894525244 ps
CPU time 10.91 seconds
Started Dec 31 12:37:18 PM PST 23
Finished Dec 31 12:37:40 PM PST 23
Peak memory 217976 kb
Host smart-ae55c8f8-d039-4289-b735-6208c0065d59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182952478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
3182952478
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.3832097076
Short name T58
Test name
Test status
Simulation time 514175615 ps
CPU time 14.77 seconds
Started Dec 31 12:37:20 PM PST 23
Finished Dec 31 12:37:45 PM PST 23
Peak memory 218080 kb
Host smart-763a8249-abe0-43a6-ae9e-958c6577c4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832097076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3832097076
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.3709105525
Short name T830
Test name
Test status
Simulation time 85080554 ps
CPU time 5.78 seconds
Started Dec 31 12:37:16 PM PST 23
Finished Dec 31 12:37:33 PM PST 23
Peak memory 213984 kb
Host smart-aa8b7590-b21c-43cb-8607-e836ce3e7d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709105525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.3709105525
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.3698961996
Short name T89
Test name
Test status
Simulation time 575740191 ps
CPU time 30.48 seconds
Started Dec 31 12:37:01 PM PST 23
Finished Dec 31 12:37:47 PM PST 23
Peak memory 251224 kb
Host smart-d48546eb-b5b1-480e-a6de-77845b75d01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698961996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.3698961996
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.2505406231
Short name T690
Test name
Test status
Simulation time 279782169 ps
CPU time 6.63 seconds
Started Dec 31 12:37:00 PM PST 23
Finished Dec 31 12:37:21 PM PST 23
Peak memory 250320 kb
Host smart-37534e31-f4b2-4c8e-976d-6e77bcb67f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505406231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.2505406231
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.1850265059
Short name T379
Test name
Test status
Simulation time 30376592909 ps
CPU time 69.91 seconds
Started Dec 31 12:37:18 PM PST 23
Finished Dec 31 12:38:39 PM PST 23
Peak memory 271236 kb
Host smart-4ec0f67d-b355-46ba-b87f-5008a7aff872
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850265059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.1850265059
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1851852770
Short name T913
Test name
Test status
Simulation time 11600351 ps
CPU time 0.76 seconds
Started Dec 31 12:36:58 PM PST 23
Finished Dec 31 12:37:14 PM PST 23
Peak memory 208248 kb
Host smart-f5ee0695-ee19-4567-9dc2-34e521a89d38
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851852770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.1851852770
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.3464899592
Short name T77
Test name
Test status
Simulation time 60096112 ps
CPU time 0.83 seconds
Started Dec 31 12:36:06 PM PST 23
Finished Dec 31 12:36:23 PM PST 23
Peak memory 208232 kb
Host smart-59af6c0e-bd11-4267-8160-8e19c67c0d04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464899592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.3464899592
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2245509244
Short name T181
Test name
Test status
Simulation time 14519267 ps
CPU time 0.97 seconds
Started Dec 31 12:35:59 PM PST 23
Finished Dec 31 12:36:18 PM PST 23
Peak memory 209516 kb
Host smart-dabdf0f6-103c-4186-8823-8ede5d4ee994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245509244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2245509244
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.4032390350
Short name T638
Test name
Test status
Simulation time 607643808 ps
CPU time 12.92 seconds
Started Dec 31 12:36:07 PM PST 23
Finished Dec 31 12:36:36 PM PST 23
Peak memory 218036 kb
Host smart-daa79a37-11c0-4c28-b979-e188ecb057d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032390350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.4032390350
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.989226191
Short name T640
Test name
Test status
Simulation time 133052116 ps
CPU time 3.9 seconds
Started Dec 31 12:35:50 PM PST 23
Finished Dec 31 12:36:04 PM PST 23
Peak memory 209512 kb
Host smart-5b37db49-1ce6-4a25-870a-9dd23e88c947
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989226191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_acc
ess.989226191
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.375002912
Short name T18
Test name
Test status
Simulation time 2172109360 ps
CPU time 34.82 seconds
Started Dec 31 12:36:00 PM PST 23
Finished Dec 31 12:36:56 PM PST 23
Peak memory 218280 kb
Host smart-07897d89-f139-4ce9-857b-8c3566574772
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375002912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_err
ors.375002912
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.1424589249
Short name T767
Test name
Test status
Simulation time 2277753296 ps
CPU time 11.14 seconds
Started Dec 31 12:35:42 PM PST 23
Finished Dec 31 12:35:56 PM PST 23
Peak memory 217856 kb
Host smart-b3670b43-15ae-4fc7-b199-63331c4191a9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424589249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_
priority.1424589249
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.873618128
Short name T746
Test name
Test status
Simulation time 191884725 ps
CPU time 4.69 seconds
Started Dec 31 12:36:09 PM PST 23
Finished Dec 31 12:36:31 PM PST 23
Peak memory 218012 kb
Host smart-6ae937cc-cf3b-4d07-a66c-0a54748782df
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873618128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_
prog_failure.873618128
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.275540808
Short name T357
Test name
Test status
Simulation time 2870506896 ps
CPU time 18.22 seconds
Started Dec 31 12:36:05 PM PST 23
Finished Dec 31 12:36:40 PM PST 23
Peak memory 213448 kb
Host smart-e548845a-5f61-4b32-b4cf-4c2e9f94c68d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275540808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_regwen_during_op.275540808
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.410166255
Short name T884
Test name
Test status
Simulation time 342518581 ps
CPU time 5.28 seconds
Started Dec 31 12:35:58 PM PST 23
Finished Dec 31 12:36:21 PM PST 23
Peak memory 213344 kb
Host smart-98b07196-49e4-4bac-8427-d583f9639f62
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410166255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.410166255
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.1780877219
Short name T807
Test name
Test status
Simulation time 7453334952 ps
CPU time 64.65 seconds
Started Dec 31 12:36:01 PM PST 23
Finished Dec 31 12:37:22 PM PST 23
Peak memory 283716 kb
Host smart-715b6395-8f04-4913-bacb-ef5f4c0dc330
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780877219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.1780877219
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.287393814
Short name T190
Test name
Test status
Simulation time 1723092477 ps
CPU time 16.23 seconds
Started Dec 31 12:35:47 PM PST 23
Finished Dec 31 12:36:16 PM PST 23
Peak memory 245968 kb
Host smart-79739d38-c97c-4806-b8db-be1be8050ef9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287393814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_state_post_trans.287393814
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.975355149
Short name T546
Test name
Test status
Simulation time 123337539 ps
CPU time 2.33 seconds
Started Dec 31 12:36:00 PM PST 23
Finished Dec 31 12:36:20 PM PST 23
Peak memory 218036 kb
Host smart-297b0889-018d-4f8c-8ae5-76e3a94fc295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975355149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.975355149
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.3176306980
Short name T362
Test name
Test status
Simulation time 659190610 ps
CPU time 6.84 seconds
Started Dec 31 12:35:58 PM PST 23
Finished Dec 31 12:36:22 PM PST 23
Peak memory 214080 kb
Host smart-21c535d4-57fb-4465-a550-e3075ceb2085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176306980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.3176306980
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.1771100149
Short name T842
Test name
Test status
Simulation time 2907429228 ps
CPU time 19.2 seconds
Started Dec 31 12:36:08 PM PST 23
Finished Dec 31 12:36:44 PM PST 23
Peak memory 219116 kb
Host smart-6229fc79-732d-4476-aca3-2642a1dfd468
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771100149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.1771100149
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.4013448375
Short name T42
Test name
Test status
Simulation time 490898296 ps
CPU time 7.54 seconds
Started Dec 31 12:36:03 PM PST 23
Finished Dec 31 12:36:27 PM PST 23
Peak memory 218008 kb
Host smart-a255351f-dc22-4501-9733-4472c27d5443
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013448375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.4013448375
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3277870570
Short name T863
Test name
Test status
Simulation time 884073284 ps
CPU time 9.48 seconds
Started Dec 31 12:36:02 PM PST 23
Finished Dec 31 12:36:28 PM PST 23
Peak memory 218000 kb
Host smart-7efce613-d8ab-4bbc-9d61-38f8d117a507
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277870570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.3
277870570
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.3978225719
Short name T949
Test name
Test status
Simulation time 2391359031 ps
CPU time 12.7 seconds
Started Dec 31 12:35:42 PM PST 23
Finished Dec 31 12:35:58 PM PST 23
Peak memory 218088 kb
Host smart-9f565c45-0392-4ee5-b238-1282522542d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978225719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.3978225719
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.707277029
Short name T458
Test name
Test status
Simulation time 48929698 ps
CPU time 1.73 seconds
Started Dec 31 12:35:46 PM PST 23
Finished Dec 31 12:35:58 PM PST 23
Peak memory 213624 kb
Host smart-06ae30f5-fff0-40e3-96cb-b8cdc95892ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707277029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.707277029
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.3227581691
Short name T306
Test name
Test status
Simulation time 1026130123 ps
CPU time 22.13 seconds
Started Dec 31 12:35:54 PM PST 23
Finished Dec 31 12:36:31 PM PST 23
Peak memory 251020 kb
Host smart-b71282a2-2ddb-4670-8156-7d3fd1f7c43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227581691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.3227581691
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.1489350958
Short name T311
Test name
Test status
Simulation time 246410938 ps
CPU time 6.83 seconds
Started Dec 31 12:35:52 PM PST 23
Finished Dec 31 12:36:09 PM PST 23
Peak memory 250512 kb
Host smart-998f238d-cd30-4686-a2ea-d3074fc56efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489350958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.1489350958
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.2703285981
Short name T916
Test name
Test status
Simulation time 9230688716 ps
CPU time 150.3 seconds
Started Dec 31 12:36:01 PM PST 23
Finished Dec 31 12:38:57 PM PST 23
Peak memory 250968 kb
Host smart-86d8176b-ab17-4443-b25d-992f852dd20c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703285981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.2703285981
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.2098188175
Short name T122
Test name
Test status
Simulation time 15609374728 ps
CPU time 494.03 seconds
Started Dec 31 12:35:55 PM PST 23
Finished Dec 31 12:44:26 PM PST 23
Peak memory 447852 kb
Host smart-cfc9e33b-ac46-4a73-8d48-1889c719a89b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2098188175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.2098188175
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.91194445
Short name T713
Test name
Test status
Simulation time 48551951 ps
CPU time 0.7 seconds
Started Dec 31 12:35:50 PM PST 23
Finished Dec 31 12:36:01 PM PST 23
Peak memory 206460 kb
Host smart-16fe58b0-51ae-4c8f-b1e4-e4490064940e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91194445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_volatile_unlock_smoke.91194445
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.3931390022
Short name T102
Test name
Test status
Simulation time 57343668 ps
CPU time 0.88 seconds
Started Dec 31 12:36:04 PM PST 23
Finished Dec 31 12:36:21 PM PST 23
Peak memory 208248 kb
Host smart-c3203581-b4ab-4c3c-8dad-9ed9ceca67ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931390022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.3931390022
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.823328353
Short name T544
Test name
Test status
Simulation time 22185139 ps
CPU time 0.91 seconds
Started Dec 31 12:35:43 PM PST 23
Finished Dec 31 12:35:47 PM PST 23
Peak memory 209480 kb
Host smart-3671d7d1-f91d-4303-8900-7c9addfc9426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823328353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.823328353
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.591232056
Short name T395
Test name
Test status
Simulation time 3005961780 ps
CPU time 11.26 seconds
Started Dec 31 12:35:56 PM PST 23
Finished Dec 31 12:36:24 PM PST 23
Peak memory 218128 kb
Host smart-39808966-df4f-458b-9978-5ad3de2e1b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591232056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.591232056
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.107011377
Short name T772
Test name
Test status
Simulation time 3262674991 ps
CPU time 10.7 seconds
Started Dec 31 12:35:46 PM PST 23
Finished Dec 31 12:36:06 PM PST 23
Peak memory 209672 kb
Host smart-5dc058ac-5124-406f-b918-cd3e801f1db1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107011377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_acc
ess.107011377
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.984952634
Short name T983
Test name
Test status
Simulation time 1327614757 ps
CPU time 20.13 seconds
Started Dec 31 12:36:01 PM PST 23
Finished Dec 31 12:36:38 PM PST 23
Peak memory 218000 kb
Host smart-e6409945-a9e8-4e21-a237-724ebdaef95f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984952634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_err
ors.984952634
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.1347262991
Short name T373
Test name
Test status
Simulation time 113961218 ps
CPU time 3.67 seconds
Started Dec 31 12:35:59 PM PST 23
Finished Dec 31 12:36:20 PM PST 23
Peak memory 217804 kb
Host smart-1b436751-354b-4f6b-8ccb-3bbb81adca84
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347262991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
priority.1347262991
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.1599646456
Short name T689
Test name
Test status
Simulation time 6314190583 ps
CPU time 24.3 seconds
Started Dec 31 12:35:50 PM PST 23
Finished Dec 31 12:36:25 PM PST 23
Peak memory 219220 kb
Host smart-b059f304-3edd-413c-902b-1be1936e9bb1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599646456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.1599646456
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2425979801
Short name T797
Test name
Test status
Simulation time 1258469520 ps
CPU time 18.09 seconds
Started Dec 31 12:36:08 PM PST 23
Finished Dec 31 12:36:43 PM PST 23
Peak memory 213068 kb
Host smart-3750de6f-0fb1-40b8-b75b-997521c352a7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425979801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.2425979801
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.2394633138
Short name T747
Test name
Test status
Simulation time 1828235566 ps
CPU time 16.39 seconds
Started Dec 31 12:36:03 PM PST 23
Finished Dec 31 12:36:36 PM PST 23
Peak memory 213508 kb
Host smart-6a2710b5-ea8b-4ab7-bf7d-f3b6eb3ff796
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394633138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
2394633138
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.837815310
Short name T3
Test name
Test status
Simulation time 2436713465 ps
CPU time 54.39 seconds
Started Dec 31 12:36:06 PM PST 23
Finished Dec 31 12:37:17 PM PST 23
Peak memory 275592 kb
Host smart-bc86ae2c-c606-4746-9cc0-a5a3337a9620
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837815310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_state_failure.837815310
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.662177674
Short name T706
Test name
Test status
Simulation time 723298490 ps
CPU time 6.86 seconds
Started Dec 31 12:35:47 PM PST 23
Finished Dec 31 12:36:04 PM PST 23
Peak memory 222468 kb
Host smart-e35647e8-33c3-45f3-8386-15be8fff0698
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662177674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_state_post_trans.662177674
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.3303185198
Short name T412
Test name
Test status
Simulation time 364118248 ps
CPU time 3.52 seconds
Started Dec 31 12:36:06 PM PST 23
Finished Dec 31 12:36:25 PM PST 23
Peak memory 218132 kb
Host smart-fb0af248-5e8f-485d-a1f1-e03934881df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303185198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.3303185198
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.162743009
Short name T792
Test name
Test status
Simulation time 374600265 ps
CPU time 8.37 seconds
Started Dec 31 12:35:54 PM PST 23
Finished Dec 31 12:36:18 PM PST 23
Peak memory 214188 kb
Host smart-e19f83ab-30c6-462d-afa3-fe3bbdf095b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162743009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.162743009
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.4079883910
Short name T662
Test name
Test status
Simulation time 316816656 ps
CPU time 15.42 seconds
Started Dec 31 12:36:19 PM PST 23
Finished Dec 31 12:36:54 PM PST 23
Peak memory 219076 kb
Host smart-4dd3649e-e07d-4de6-84f6-13a8ead62f30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079883910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.4079883910
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.1164191530
Short name T957
Test name
Test status
Simulation time 345146364 ps
CPU time 13.24 seconds
Started Dec 31 12:36:08 PM PST 23
Finished Dec 31 12:36:39 PM PST 23
Peak memory 218012 kb
Host smart-460ddbc1-9623-4cf7-8833-34b5ee4637da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164191530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.1164191530
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.4210888245
Short name T821
Test name
Test status
Simulation time 2660216007 ps
CPU time 14.23 seconds
Started Dec 31 12:35:49 PM PST 23
Finished Dec 31 12:36:15 PM PST 23
Peak memory 218032 kb
Host smart-d04e2524-61c5-43fa-a17d-aa25fae769cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210888245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.4
210888245
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.1342364251
Short name T938
Test name
Test status
Simulation time 225962547 ps
CPU time 10.73 seconds
Started Dec 31 12:36:01 PM PST 23
Finished Dec 31 12:36:29 PM PST 23
Peak memory 218068 kb
Host smart-dc477f3d-d60b-43f4-8551-32352dcdd6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342364251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.1342364251
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.1329627567
Short name T889
Test name
Test status
Simulation time 126759728 ps
CPU time 3.69 seconds
Started Dec 31 12:36:01 PM PST 23
Finished Dec 31 12:36:22 PM PST 23
Peak memory 214232 kb
Host smart-7983f520-555f-48f4-9e5e-bc368875a99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329627567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.1329627567
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.1550766087
Short name T673
Test name
Test status
Simulation time 1804449715 ps
CPU time 22.93 seconds
Started Dec 31 12:35:50 PM PST 23
Finished Dec 31 12:36:24 PM PST 23
Peak memory 250976 kb
Host smart-a3f6226d-98e9-4f67-8f2e-251480296988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550766087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.1550766087
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.3146387153
Short name T336
Test name
Test status
Simulation time 90484996 ps
CPU time 9.67 seconds
Started Dec 31 12:35:57 PM PST 23
Finished Dec 31 12:36:23 PM PST 23
Peak memory 251032 kb
Host smart-ff763c89-80cb-4a8c-8f01-cea51f699de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146387153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.3146387153
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.812606889
Short name T80
Test name
Test status
Simulation time 9829147763 ps
CPU time 289.45 seconds
Started Dec 31 12:35:58 PM PST 23
Finished Dec 31 12:41:05 PM PST 23
Peak memory 283856 kb
Host smart-e9fa795e-f864-4927-9079-9ff7df3f4c7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812606889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.812606889
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.552698792
Short name T865
Test name
Test status
Simulation time 12881921 ps
CPU time 0.89 seconds
Started Dec 31 12:36:00 PM PST 23
Finished Dec 31 12:36:27 PM PST 23
Peak memory 208012 kb
Host smart-a0dbf923-ac31-46f8-ba95-f645056254b8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552698792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctr
l_volatile_unlock_smoke.552698792
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.1711539425
Short name T360
Test name
Test status
Simulation time 17136340 ps
CPU time 0.92 seconds
Started Dec 31 12:35:58 PM PST 23
Finished Dec 31 12:36:16 PM PST 23
Peak memory 208212 kb
Host smart-c67f7da1-0c1e-4bec-bb3d-d1b6719a260e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711539425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.1711539425
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.1102610016
Short name T304
Test name
Test status
Simulation time 29022635 ps
CPU time 0.83 seconds
Started Dec 31 12:35:56 PM PST 23
Finished Dec 31 12:36:14 PM PST 23
Peak memory 209516 kb
Host smart-a84b305d-1ebd-4d9c-acd0-1768be744b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102610016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.1102610016
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.426141199
Short name T613
Test name
Test status
Simulation time 1098186279 ps
CPU time 7.54 seconds
Started Dec 31 12:36:00 PM PST 23
Finished Dec 31 12:36:25 PM PST 23
Peak memory 218072 kb
Host smart-f898c251-ea1a-4373-83cb-b375c66e85a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426141199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.426141199
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.1867308654
Short name T468
Test name
Test status
Simulation time 542869335 ps
CPU time 5.8 seconds
Started Dec 31 12:35:51 PM PST 23
Finished Dec 31 12:36:07 PM PST 23
Peak memory 209568 kb
Host smart-5388e0bc-a5c4-419b-a34f-d796cff3c6b5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867308654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_ac
cess.1867308654
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.1097087472
Short name T666
Test name
Test status
Simulation time 2470707994 ps
CPU time 69.43 seconds
Started Dec 31 12:36:10 PM PST 23
Finished Dec 31 12:37:38 PM PST 23
Peak memory 219208 kb
Host smart-3855edf8-452b-4d7d-a1c7-c9195787fd2a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097087472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.1097087472
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.733370634
Short name T708
Test name
Test status
Simulation time 2132409483 ps
CPU time 13.09 seconds
Started Dec 31 12:36:04 PM PST 23
Finished Dec 31 12:36:33 PM PST 23
Peak memory 217748 kb
Host smart-1c138988-10d2-4dc9-bb8c-a445c319777e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733370634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jt
ag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_p
riority.733370634
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.4008465201
Short name T328
Test name
Test status
Simulation time 8517735996 ps
CPU time 11.71 seconds
Started Dec 31 12:36:13 PM PST 23
Finished Dec 31 12:36:45 PM PST 23
Peak memory 218052 kb
Host smart-bdf60d13-8389-4334-bd2f-c9a189d216f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008465201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.4008465201
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1286592759
Short name T854
Test name
Test status
Simulation time 5344717308 ps
CPU time 17.32 seconds
Started Dec 31 12:36:36 PM PST 23
Finished Dec 31 12:37:10 PM PST 23
Peak memory 213708 kb
Host smart-e9f70589-79f8-46ff-9a67-9be3923144f7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286592759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.1286592759
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.753621571
Short name T766
Test name
Test status
Simulation time 330855566 ps
CPU time 5.34 seconds
Started Dec 31 12:36:02 PM PST 23
Finished Dec 31 12:36:24 PM PST 23
Peak memory 213304 kb
Host smart-133e0557-d51c-491f-80ae-5b5019a2bf87
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753621571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.753621571
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.1146179797
Short name T308
Test name
Test status
Simulation time 11099929303 ps
CPU time 77.52 seconds
Started Dec 31 12:36:12 PM PST 23
Finished Dec 31 12:37:49 PM PST 23
Peak memory 267404 kb
Host smart-1893dab6-99f5-49a8-b3bb-32358d1487e3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146179797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.1146179797
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.3618812831
Short name T864
Test name
Test status
Simulation time 1380490886 ps
CPU time 12.41 seconds
Started Dec 31 12:36:08 PM PST 23
Finished Dec 31 12:36:36 PM PST 23
Peak memory 247112 kb
Host smart-03b44d0f-d99c-4c52-818e-9d5ff3c70882
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618812831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.3618812831
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.3369115067
Short name T650
Test name
Test status
Simulation time 137332139 ps
CPU time 3.95 seconds
Started Dec 31 12:36:05 PM PST 23
Finished Dec 31 12:36:26 PM PST 23
Peak memory 218028 kb
Host smart-38e446d8-00b6-4c84-a641-72bdb79a681e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369115067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.3369115067
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.457081119
Short name T726
Test name
Test status
Simulation time 391230450 ps
CPU time 24.9 seconds
Started Dec 31 12:36:11 PM PST 23
Finished Dec 31 12:36:55 PM PST 23
Peak memory 214176 kb
Host smart-c3b0acae-7708-4347-bc1d-b72b8c728d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457081119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.457081119
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.2337250512
Short name T931
Test name
Test status
Simulation time 1822661824 ps
CPU time 13.82 seconds
Started Dec 31 12:35:57 PM PST 23
Finished Dec 31 12:36:28 PM PST 23
Peak memory 219072 kb
Host smart-cc89d983-cd63-45a5-ba7c-507c1b58bfd0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337250512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.2337250512
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3418860697
Short name T376
Test name
Test status
Simulation time 987280402 ps
CPU time 12.22 seconds
Started Dec 31 12:36:27 PM PST 23
Finished Dec 31 12:36:55 PM PST 23
Peak memory 217980 kb
Host smart-87c0db42-a71c-4120-8d20-365e58e91d26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418860697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.3418860697
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.320403837
Short name T664
Test name
Test status
Simulation time 1916164609 ps
CPU time 9.56 seconds
Started Dec 31 12:36:16 PM PST 23
Finished Dec 31 12:36:47 PM PST 23
Peak memory 217976 kb
Host smart-c98d29c4-88cc-4d1a-8eed-0868093aa9d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320403837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.320403837
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.2310995818
Short name T413
Test name
Test status
Simulation time 59090364 ps
CPU time 2.16 seconds
Started Dec 31 12:35:54 PM PST 23
Finished Dec 31 12:36:11 PM PST 23
Peak memory 213736 kb
Host smart-8adf300f-2946-4623-974a-6dcb98b8415d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310995818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2310995818
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.2108929383
Short name T846
Test name
Test status
Simulation time 926839803 ps
CPU time 22.75 seconds
Started Dec 31 12:36:12 PM PST 23
Finished Dec 31 12:36:55 PM PST 23
Peak memory 251024 kb
Host smart-c6dd2b2a-506e-4cbe-9440-fabc2db869ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108929383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.2108929383
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.97117254
Short name T783
Test name
Test status
Simulation time 323978704 ps
CPU time 4.01 seconds
Started Dec 31 12:36:18 PM PST 23
Finished Dec 31 12:36:42 PM PST 23
Peak memory 223012 kb
Host smart-cdbb98a4-aeff-4420-af61-661dc19dff2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97117254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.97117254
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.3125226943
Short name T51
Test name
Test status
Simulation time 2715782311 ps
CPU time 65.78 seconds
Started Dec 31 12:35:49 PM PST 23
Finished Dec 31 12:37:06 PM PST 23
Peak memory 251128 kb
Host smart-f58274d8-94f7-44fd-98be-7ef88821350b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125226943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.3125226943
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3576326449
Short name T358
Test name
Test status
Simulation time 11954939 ps
CPU time 0.93 seconds
Started Dec 31 12:35:52 PM PST 23
Finished Dec 31 12:36:04 PM PST 23
Peak memory 211352 kb
Host smart-53f515c0-173a-479b-8dd5-16377259b5a2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576326449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.3576326449
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.1180660596
Short name T634
Test name
Test status
Simulation time 41017796 ps
CPU time 0.92 seconds
Started Dec 31 12:35:57 PM PST 23
Finished Dec 31 12:36:14 PM PST 23
Peak memory 209572 kb
Host smart-13c8aad8-e201-4daa-8309-0f0083a4b0da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180660596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1180660596
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.290173597
Short name T310
Test name
Test status
Simulation time 12163067 ps
CPU time 0.83 seconds
Started Dec 31 12:36:06 PM PST 23
Finished Dec 31 12:36:23 PM PST 23
Peak memory 209316 kb
Host smart-6d0bc7fd-3f7f-46f8-a9cc-86c1f9b64698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290173597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.290173597
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.2183600560
Short name T522
Test name
Test status
Simulation time 490322751 ps
CPU time 8.27 seconds
Started Dec 31 12:37:32 PM PST 23
Finished Dec 31 12:37:46 PM PST 23
Peak memory 217984 kb
Host smart-93a4f75f-190f-4efc-bb5b-9deb85d4b474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183600560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.2183600560
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.2496336756
Short name T684
Test name
Test status
Simulation time 237651225 ps
CPU time 2.3 seconds
Started Dec 31 12:37:36 PM PST 23
Finished Dec 31 12:37:41 PM PST 23
Peak memory 209468 kb
Host smart-e909c245-5763-491f-a936-e4544ab386d2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496336756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_ac
cess.2496336756
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.415426349
Short name T654
Test name
Test status
Simulation time 1798126993 ps
CPU time 24.02 seconds
Started Dec 31 12:35:58 PM PST 23
Finished Dec 31 12:36:40 PM PST 23
Peak memory 217984 kb
Host smart-a17eafb7-d8ee-4177-b86b-91d5b706bdad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415426349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_err
ors.415426349
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.1105380973
Short name T526
Test name
Test status
Simulation time 3025039738 ps
CPU time 12.94 seconds
Started Dec 31 12:36:02 PM PST 23
Finished Dec 31 12:36:43 PM PST 23
Peak memory 217876 kb
Host smart-f4deb180-9c6d-43a1-8fdd-e317581299e9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105380973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
priority.1105380973
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.798594172
Short name T626
Test name
Test status
Simulation time 526506273 ps
CPU time 4.53 seconds
Started Dec 31 12:35:51 PM PST 23
Finished Dec 31 12:36:06 PM PST 23
Peak memory 218100 kb
Host smart-0ff0a450-a2f3-4fef-8653-c56312a0f482
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798594172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
prog_failure.798594172
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2831107892
Short name T661
Test name
Test status
Simulation time 3525427080 ps
CPU time 18.52 seconds
Started Dec 31 12:36:11 PM PST 23
Finished Dec 31 12:36:49 PM PST 23
Peak memory 213204 kb
Host smart-f627bf16-9f02-4bfa-81c0-ae2243b882a6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831107892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.2831107892
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.73592113
Short name T71
Test name
Test status
Simulation time 1672170252 ps
CPU time 12.11 seconds
Started Dec 31 12:35:58 PM PST 23
Finished Dec 31 12:36:27 PM PST 23
Peak memory 213500 kb
Host smart-4cded116-b86e-461e-9009-2ef5ef287609
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73592113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.73592113
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.3096181080
Short name T386
Test name
Test status
Simulation time 17695087469 ps
CPU time 85.18 seconds
Started Dec 31 12:36:06 PM PST 23
Finished Dec 31 12:37:47 PM PST 23
Peak memory 274884 kb
Host smart-00016dab-944c-4bbd-929b-9a4004aba0e8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096181080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.3096181080
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.2468204246
Short name T883
Test name
Test status
Simulation time 1553243699 ps
CPU time 9.76 seconds
Started Dec 31 12:36:48 PM PST 23
Finished Dec 31 12:37:14 PM PST 23
Peak memory 248792 kb
Host smart-6e4b9837-47a5-4292-a84e-1e7f8c08e8a9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468204246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.2468204246
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.29765855
Short name T313
Test name
Test status
Simulation time 139405261 ps
CPU time 3.27 seconds
Started Dec 31 12:35:51 PM PST 23
Finished Dec 31 12:36:05 PM PST 23
Peak memory 218016 kb
Host smart-031086a2-9751-4aec-af84-999313ab0ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29765855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.29765855
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.3197426873
Short name T43
Test name
Test status
Simulation time 404009730 ps
CPU time 13.93 seconds
Started Dec 31 12:36:11 PM PST 23
Finished Dec 31 12:36:44 PM PST 23
Peak memory 214112 kb
Host smart-18ea7a32-643e-4b0d-b54d-518049856588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197426873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.3197426873
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.3196971036
Short name T348
Test name
Test status
Simulation time 323701155 ps
CPU time 9.71 seconds
Started Dec 31 12:35:48 PM PST 23
Finished Dec 31 12:36:10 PM PST 23
Peak memory 218056 kb
Host smart-e510725b-eb37-41f6-9371-9b15563f6db0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196971036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.3196971036
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.1822342007
Short name T322
Test name
Test status
Simulation time 305895412 ps
CPU time 8.9 seconds
Started Dec 31 12:36:09 PM PST 23
Finished Dec 31 12:36:36 PM PST 23
Peak memory 217980 kb
Host smart-bfecc52d-189f-44d0-a0ef-c5044fdf69c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822342007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.1822342007
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.202824085
Short name T838
Test name
Test status
Simulation time 329162573 ps
CPU time 7.57 seconds
Started Dec 31 12:36:10 PM PST 23
Finished Dec 31 12:36:35 PM PST 23
Peak memory 217976 kb
Host smart-b4818392-f5c2-411d-a910-f118ff30c8aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202824085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.202824085
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.3827883694
Short name T693
Test name
Test status
Simulation time 670802949 ps
CPU time 13.69 seconds
Started Dec 31 12:36:16 PM PST 23
Finished Dec 31 12:36:51 PM PST 23
Peak memory 218064 kb
Host smart-0e41132b-61f9-491a-b4c7-58e98582b95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827883694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.3827883694
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.1517479806
Short name T848
Test name
Test status
Simulation time 34633430 ps
CPU time 2.02 seconds
Started Dec 31 12:35:58 PM PST 23
Finished Dec 31 12:36:18 PM PST 23
Peak memory 213596 kb
Host smart-9dc7d583-05ee-483d-8f47-a496d0723160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517479806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.1517479806
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.369181577
Short name T646
Test name
Test status
Simulation time 680286980 ps
CPU time 37.43 seconds
Started Dec 31 12:36:08 PM PST 23
Finished Dec 31 12:37:03 PM PST 23
Peak memory 250976 kb
Host smart-26ac6207-1aa5-4d0e-bb91-c5a2229676c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369181577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.369181577
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.539105689
Short name T433
Test name
Test status
Simulation time 818073199 ps
CPU time 7 seconds
Started Dec 31 12:35:55 PM PST 23
Finished Dec 31 12:36:19 PM PST 23
Peak memory 246120 kb
Host smart-9b25cece-f8ff-4aad-9e9b-3d47ad529d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539105689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.539105689
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.1811090773
Short name T66
Test name
Test status
Simulation time 27841110863 ps
CPU time 121.38 seconds
Started Dec 31 12:36:16 PM PST 23
Finished Dec 31 12:38:38 PM PST 23
Peak memory 269980 kb
Host smart-c8e1efd8-1d01-45ac-bfee-d9119b27323a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811090773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.1811090773
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2313900191
Short name T326
Test name
Test status
Simulation time 11887610 ps
CPU time 0.7 seconds
Started Dec 31 12:36:05 PM PST 23
Finished Dec 31 12:36:22 PM PST 23
Peak memory 207488 kb
Host smart-ad260b39-7c20-4dfd-bd51-ad249175225e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313900191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.2313900191
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.736792199
Short name T487
Test name
Test status
Simulation time 20745631 ps
CPU time 1.17 seconds
Started Dec 31 12:36:17 PM PST 23
Finished Dec 31 12:36:39 PM PST 23
Peak memory 209536 kb
Host smart-ed935430-6531-4e2b-8f36-7fe19ce93b1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736792199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.736792199
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.2947929314
Short name T633
Test name
Test status
Simulation time 357969132 ps
CPU time 9.9 seconds
Started Dec 31 12:36:08 PM PST 23
Finished Dec 31 12:36:34 PM PST 23
Peak memory 218020 kb
Host smart-7ac2aa06-1344-4b23-95d0-dfee2caa8a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947929314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.2947929314
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.3241365645
Short name T735
Test name
Test status
Simulation time 845540304 ps
CPU time 6.3 seconds
Started Dec 31 12:36:16 PM PST 23
Finished Dec 31 12:36:46 PM PST 23
Peak memory 209524 kb
Host smart-75d482e3-b148-4c12-9d14-723f964cd8ba
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241365645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_ac
cess.3241365645
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.886652730
Short name T929
Test name
Test status
Simulation time 2781875124 ps
CPU time 30.3 seconds
Started Dec 31 12:35:49 PM PST 23
Finished Dec 31 12:36:31 PM PST 23
Peak memory 218068 kb
Host smart-9b289c41-720a-4db2-870d-813e4f8e629a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886652730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_err
ors.886652730
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.2158954740
Short name T950
Test name
Test status
Simulation time 161529270 ps
CPU time 2.6 seconds
Started Dec 31 12:35:56 PM PST 23
Finished Dec 31 12:36:15 PM PST 23
Peak memory 209584 kb
Host smart-c67f9196-d989-4fba-a0c2-514c0d08b1af
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158954740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_j
tag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_
priority.2158954740
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.842546636
Short name T467
Test name
Test status
Simulation time 2352981902 ps
CPU time 9.78 seconds
Started Dec 31 12:35:53 PM PST 23
Finished Dec 31 12:36:25 PM PST 23
Peak memory 218068 kb
Host smart-bc3bfd01-53b7-420f-acb2-3f1bb55acb42
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842546636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_
prog_failure.842546636
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3510258742
Short name T621
Test name
Test status
Simulation time 4680276160 ps
CPU time 15.16 seconds
Started Dec 31 12:37:28 PM PST 23
Finished Dec 31 12:37:51 PM PST 23
Peak memory 213472 kb
Host smart-8f318ad2-b33f-4a7a-82b9-9c7f0a0cde73
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510258742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.3510258742
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.3917026456
Short name T974
Test name
Test status
Simulation time 204841592 ps
CPU time 3.84 seconds
Started Dec 31 12:35:52 PM PST 23
Finished Dec 31 12:36:06 PM PST 23
Peak memory 213120 kb
Host smart-91c4a218-6b73-4397-bbc6-95acb4dc979f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917026456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
3917026456
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.2388049675
Short name T382
Test name
Test status
Simulation time 5943434240 ps
CPU time 43.86 seconds
Started Dec 31 12:35:54 PM PST 23
Finished Dec 31 12:36:53 PM PST 23
Peak memory 275596 kb
Host smart-24adc06a-20c8-494d-b127-76e08ce85454
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388049675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.2388049675
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.2848801608
Short name T418
Test name
Test status
Simulation time 720109447 ps
CPU time 10.29 seconds
Started Dec 31 12:36:00 PM PST 23
Finished Dec 31 12:36:27 PM PST 23
Peak memory 247332 kb
Host smart-f32cf6ee-6378-47a0-b9ef-56279206b135
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848801608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.2848801608
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.2717379148
Short name T554
Test name
Test status
Simulation time 839037701 ps
CPU time 2.98 seconds
Started Dec 31 12:35:48 PM PST 23
Finished Dec 31 12:36:03 PM PST 23
Peak memory 218060 kb
Host smart-671a0203-cd8d-4dbf-8d54-60d4715372df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717379148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.2717379148
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.1217848468
Short name T643
Test name
Test status
Simulation time 1047608166 ps
CPU time 7.88 seconds
Started Dec 31 12:35:55 PM PST 23
Finished Dec 31 12:36:19 PM PST 23
Peak memory 213912 kb
Host smart-71644f68-9e61-435a-bf5c-40a4f6098f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217848468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.1217848468
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.1634915950
Short name T403
Test name
Test status
Simulation time 1478487576 ps
CPU time 14.75 seconds
Started Dec 31 12:35:59 PM PST 23
Finished Dec 31 12:36:31 PM PST 23
Peak memory 219116 kb
Host smart-4d8118ed-ae6c-4ae4-9c05-8c4174fc8b16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634915950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1634915950
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.907237108
Short name T653
Test name
Test status
Simulation time 868236639 ps
CPU time 12.09 seconds
Started Dec 31 12:36:04 PM PST 23
Finished Dec 31 12:36:32 PM PST 23
Peak memory 217992 kb
Host smart-6a60407e-7eea-4fef-889a-30eba9f580b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907237108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_dig
est.907237108
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2330956601
Short name T961
Test name
Test status
Simulation time 1551262731 ps
CPU time 10.95 seconds
Started Dec 31 12:37:14 PM PST 23
Finished Dec 31 12:37:36 PM PST 23
Peak memory 217796 kb
Host smart-47e1483c-eca1-4be1-95bf-10482bfa13ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330956601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
330956601
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.4289482712
Short name T841
Test name
Test status
Simulation time 3583018422 ps
CPU time 7.43 seconds
Started Dec 31 12:35:51 PM PST 23
Finished Dec 31 12:36:09 PM PST 23
Peak memory 218100 kb
Host smart-4ba92895-96cb-4b28-a5fa-88ef9886e62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289482712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.4289482712
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.911345906
Short name T45
Test name
Test status
Simulation time 71120384 ps
CPU time 2.07 seconds
Started Dec 31 12:36:11 PM PST 23
Finished Dec 31 12:36:32 PM PST 23
Peak memory 213372 kb
Host smart-8036054f-4068-4243-bafd-cd281027172b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911345906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.911345906
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.3724037091
Short name T625
Test name
Test status
Simulation time 270864684 ps
CPU time 29.24 seconds
Started Dec 31 12:36:01 PM PST 23
Finished Dec 31 12:36:47 PM PST 23
Peak memory 251068 kb
Host smart-6284c134-4b0f-4f40-8aa8-6a49eaa62972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724037091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.3724037091
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.2763140925
Short name T951
Test name
Test status
Simulation time 266038958 ps
CPU time 6.42 seconds
Started Dec 31 12:35:57 PM PST 23
Finished Dec 31 12:36:24 PM PST 23
Peak memory 246152 kb
Host smart-4ae82562-d725-4f91-8a1d-5568fb0ec96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763140925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.2763140925
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.3718767996
Short name T820
Test name
Test status
Simulation time 4758717325 ps
CPU time 15.62 seconds
Started Dec 31 12:35:59 PM PST 23
Finished Dec 31 12:36:32 PM PST 23
Peak memory 217876 kb
Host smart-baf43946-a57d-4779-9d88-172485e6293a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718767996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.3718767996
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2390005564
Short name T891
Test name
Test status
Simulation time 13820502 ps
CPU time 1 seconds
Started Dec 31 12:36:19 PM PST 23
Finished Dec 31 12:36:40 PM PST 23
Peak memory 208060 kb
Host smart-29a45aaa-0bbe-49cf-9577-d943f1bb33d7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390005564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.2390005564
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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